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1/*
2 * Copyright (C) 2016 Atmel Corporation,
3 * Songjun Wu <songjun.wu@atmel.com>,
4 * Nicolas Ferre <nicolas.ferre@atmel.com>
5 * Copyright (C) 2017 Free Electrons,
6 * Quentin Schulz <quentin.schulz@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
14 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
15 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
16 * asked rate.
17 *
18 * Traits of FRAC clock:
19 * enable - clk_enable writes nd, fracr parameters and enables PLL
20 * rate - rate is adjustable.
21 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
22 * parent - fixed parent. No clk_set_parent support
23 *
24 * Traits of PMC clock:
25 * enable - clk_enable writes qdpmc, and enables PMC output
26 * rate - rate is adjustable.
27 * clk->rate = parent->rate / (qdpmc + 1)
28 * parent - fixed parent. No clk_set_parent support
29 *
30 * Traits of PAD clock:
31 * enable - clk_enable writes divisors and enables PAD output
32 * rate - rate is adjustable.
33 * clk->rate = parent->rate / (qdaudio * div))
34 * parent - fixed parent. No clk_set_parent support
35 *
36 */
37
38#include <linux/clk.h>
39#include <linux/clk-provider.h>
40#include <linux/clk/at91_pmc.h>
41#include <linux/of.h>
42#include <linux/mfd/syscon.h>
43#include <linux/regmap.h>
44#include <linux/slab.h>
45
46#include "pmc.h"
47
48#define AUDIO_PLL_DIV_FRAC BIT(22)
49#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
50 AT91_PMC_AUDIO_PLL_ND_OFFSET)
51
52#define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
53 AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \
54 (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
55 AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))
56
57#define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
58 AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
59
60#define AUDIO_PLL_FOUT_MIN 620000000UL
61#define AUDIO_PLL_FOUT_MAX 700000000UL
62
63struct clk_audio_frac {
64 struct clk_hw hw;
65 struct regmap *regmap;
66 u32 fracr;
67 u8 nd;
68};
69
70struct clk_audio_pad {
71 struct clk_hw hw;
72 struct regmap *regmap;
73 u8 qdaudio;
74 u8 div;
75};
76
77struct clk_audio_pmc {
78 struct clk_hw hw;
79 struct regmap *regmap;
80 u8 qdpmc;
81};
82
83#define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw)
84#define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw)
85#define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw)
86
87static int clk_audio_pll_frac_enable(struct clk_hw *hw)
88{
89 struct clk_audio_frac *frac = to_clk_audio_frac(hw);
90
91 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
92 AT91_PMC_AUDIO_PLL_RESETN, 0);
93 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
94 AT91_PMC_AUDIO_PLL_RESETN,
95 AT91_PMC_AUDIO_PLL_RESETN);
96 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1,
97 AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr);
98
99 /*
100 * reset and enable have to be done in 2 separated writes
101 * for AT91_PMC_AUDIO_PLL0
102 */
103 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
104 AT91_PMC_AUDIO_PLL_PLLEN |
105 AT91_PMC_AUDIO_PLL_ND_MASK,
106 AT91_PMC_AUDIO_PLL_PLLEN |
107 AT91_PMC_AUDIO_PLL_ND(frac->nd));
108
109 return 0;
110}
111
112static int clk_audio_pll_pad_enable(struct clk_hw *hw)
113{
114 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
115
116 regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
117 AT91_PMC_AUDIO_PLL_QDPAD_MASK,
118 AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));
119 regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
120 AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);
121
122 return 0;
123}
124
125static int clk_audio_pll_pmc_enable(struct clk_hw *hw)
126{
127 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
128
129 regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
130 AT91_PMC_AUDIO_PLL_PMCEN |
131 AT91_PMC_AUDIO_PLL_QDPMC_MASK,
132 AT91_PMC_AUDIO_PLL_PMCEN |
133 AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));
134 return 0;
135}
136
137static void clk_audio_pll_frac_disable(struct clk_hw *hw)
138{
139 struct clk_audio_frac *frac = to_clk_audio_frac(hw);
140
141 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
142 AT91_PMC_AUDIO_PLL_PLLEN, 0);
143 /* do it in 2 separated writes */
144 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
145 AT91_PMC_AUDIO_PLL_RESETN, 0);
146}
147
148static void clk_audio_pll_pad_disable(struct clk_hw *hw)
149{
150 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
151
152 regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
153 AT91_PMC_AUDIO_PLL_PADEN, 0);
154}
155
156static void clk_audio_pll_pmc_disable(struct clk_hw *hw)
157{
158 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
159
160 regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
161 AT91_PMC_AUDIO_PLL_PMCEN, 0);
162}
163
164static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
165 unsigned long nd, unsigned long fracr)
166{
167 unsigned long long fr = (unsigned long long)parent_rate * fracr;
168
169 pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
170
171 fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);
172
173 pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
174
175 return parent_rate * (nd + 1) + fr;
176}
177
178static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw,
179 unsigned long parent_rate)
180{
181 struct clk_audio_frac *frac = to_clk_audio_frac(hw);
182 unsigned long fout;
183
184 fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);
185
186 pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
187 fout, frac->nd, (unsigned long)frac->fracr);
188
189 return fout;
190}
191
192static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw,
193 unsigned long parent_rate)
194{
195 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
196 unsigned long apad_rate = 0;
197
198 if (apad_ck->qdaudio && apad_ck->div)
199 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);
200
201 pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
202 __func__, apad_rate, apad_ck->div, apad_ck->qdaudio);
203
204 return apad_rate;
205}
206
207static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw,
208 unsigned long parent_rate)
209{
210 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
211 unsigned long apmc_rate = 0;
212
213 apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
214
215 pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
216 apmc_rate, apmc_ck->qdpmc);
217
218 return apmc_rate;
219}
220
221static int clk_audio_pll_frac_compute_frac(unsigned long rate,
222 unsigned long parent_rate,
223 unsigned long *nd,
224 unsigned long *fracr)
225{
226 unsigned long long tmp, rem;
227
228 if (!rate)
229 return -EINVAL;
230
231 tmp = rate;
232 rem = do_div(tmp, parent_rate);
233 if (!tmp || tmp >= AUDIO_PLL_ND_MAX)
234 return -EINVAL;
235
236 *nd = tmp - 1;
237
238 tmp = rem * AUDIO_PLL_DIV_FRAC;
239 tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
240 if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
241 return -EINVAL;
242
243 /* we can cast here as we verified the bounds just above */
244 *fracr = (unsigned long)tmp;
245
246 return 0;
247}
248
249static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw,
250 struct clk_rate_request *req)
251{
252 unsigned long fracr, nd;
253 int ret;
254
255 pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__,
256 req->rate, req->best_parent_rate);
257
258 req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX);
259
260 req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN);
261 req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX);
262
263 ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate,
264 &nd, &fracr);
265 if (ret)
266 return ret;
267
268 req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr);
269
270 req->best_parent_hw = clk_hw_get_parent(hw);
271
272 pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n",
273 __func__, req->rate, nd, fracr);
274
275 return 0;
276}
277
278static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
279 unsigned long *parent_rate)
280{
281 struct clk_hw *pclk = clk_hw_get_parent(hw);
282 long best_rate = -EINVAL;
283 unsigned long best_parent_rate;
284 unsigned long tmp_qd;
285 u32 div;
286 long tmp_rate;
287 int tmp_diff;
288 int best_diff = -1;
289
290 pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
291 rate, *parent_rate);
292
293 /*
294 * Rate divisor is actually made of two different divisors, multiplied
295 * between themselves before dividing the rate.
296 * tmp_qd goes from 1 to 31 and div is either 2 or 3.
297 * In order to avoid testing twice the rate divisor (e.g. divisor 12 can
298 * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop
299 * for a rate divisor when div is 2 and tmp_qd is a multiple of 3.
300 * We cannot inverse it (condition div is 3 and tmp_qd is even) or we
301 * would miss some rate divisor that aren't reachable with div being 2
302 * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus
303 * tmp_qd is even so we skip it because we think div 2 could make this
304 * rate divisor which isn't possible since tmp_qd has to be <= 31).
305 */
306 for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
307 for (div = 2; div <= 3; div++) {
308 if (div == 2 && tmp_qd % 3 == 0)
309 continue;
310
311 best_parent_rate = clk_hw_round_rate(pclk,
312 rate * tmp_qd * div);
313 tmp_rate = best_parent_rate / (div * tmp_qd);
314 tmp_diff = abs(rate - tmp_rate);
315
316 if (best_diff < 0 || best_diff > tmp_diff) {
317 *parent_rate = best_parent_rate;
318 best_rate = tmp_rate;
319 best_diff = tmp_diff;
320 }
321 }
322
323 pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
324 __func__, best_rate, best_parent_rate);
325
326 return best_rate;
327}
328
329static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
330 unsigned long *parent_rate)
331{
332 struct clk_hw *pclk = clk_hw_get_parent(hw);
333 long best_rate = -EINVAL;
334 unsigned long best_parent_rate = 0;
335 u32 tmp_qd = 0, div;
336 long tmp_rate;
337 int tmp_diff;
338 int best_diff = -1;
339
340 pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
341 rate, *parent_rate);
342
343 if (!rate)
344 return 0;
345
346 best_parent_rate = clk_round_rate(pclk->clk, 1);
347 div = max(best_parent_rate / rate, 1UL);
348 for (; div <= AUDIO_PLL_QDPMC_MAX; div++) {
349 best_parent_rate = clk_round_rate(pclk->clk, rate * div);
350 tmp_rate = best_parent_rate / div;
351 tmp_diff = abs(rate - tmp_rate);
352
353 if (best_diff < 0 || best_diff > tmp_diff) {
354 *parent_rate = best_parent_rate;
355 best_rate = tmp_rate;
356 best_diff = tmp_diff;
357 tmp_qd = div;
358 if (!best_diff)
359 break; /* got exact match */
360 }
361 }
362
363 pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
364 __func__, best_rate, *parent_rate, tmp_qd - 1);
365
366 return best_rate;
367}
368
369static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate,
370 unsigned long parent_rate)
371{
372 struct clk_audio_frac *frac = to_clk_audio_frac(hw);
373 unsigned long fracr, nd;
374 int ret;
375
376 pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
377 parent_rate);
378
379 if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX)
380 return -EINVAL;
381
382 ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr);
383 if (ret)
384 return ret;
385
386 frac->nd = nd;
387 frac->fracr = fracr;
388
389 return 0;
390}
391
392static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate,
393 unsigned long parent_rate)
394{
395 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
396 u8 tmp_div;
397
398 pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
399 rate, parent_rate);
400
401 if (!rate)
402 return -EINVAL;
403
404 tmp_div = parent_rate / rate;
405 if (tmp_div % 3 == 0) {
406 apad_ck->qdaudio = tmp_div / 3;
407 apad_ck->div = 3;
408 } else {
409 apad_ck->qdaudio = tmp_div / 2;
410 apad_ck->div = 2;
411 }
412
413 return 0;
414}
415
416static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate,
417 unsigned long parent_rate)
418{
419 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
420
421 if (!rate)
422 return -EINVAL;
423
424 pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
425 rate, parent_rate);
426
427 apmc_ck->qdpmc = parent_rate / rate - 1;
428
429 return 0;
430}
431
432static const struct clk_ops audio_pll_frac_ops = {
433 .enable = clk_audio_pll_frac_enable,
434 .disable = clk_audio_pll_frac_disable,
435 .recalc_rate = clk_audio_pll_frac_recalc_rate,
436 .determine_rate = clk_audio_pll_frac_determine_rate,
437 .set_rate = clk_audio_pll_frac_set_rate,
438};
439
440static const struct clk_ops audio_pll_pad_ops = {
441 .enable = clk_audio_pll_pad_enable,
442 .disable = clk_audio_pll_pad_disable,
443 .recalc_rate = clk_audio_pll_pad_recalc_rate,
444 .round_rate = clk_audio_pll_pad_round_rate,
445 .set_rate = clk_audio_pll_pad_set_rate,
446};
447
448static const struct clk_ops audio_pll_pmc_ops = {
449 .enable = clk_audio_pll_pmc_enable,
450 .disable = clk_audio_pll_pmc_disable,
451 .recalc_rate = clk_audio_pll_pmc_recalc_rate,
452 .round_rate = clk_audio_pll_pmc_round_rate,
453 .set_rate = clk_audio_pll_pmc_set_rate,
454};
455
456struct clk_hw * __init
457at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
458 const char *parent_name)
459{
460 struct clk_audio_frac *frac_ck;
461 struct clk_init_data init = {};
462 int ret;
463
464 frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
465 if (!frac_ck)
466 return ERR_PTR(-ENOMEM);
467
468 init.name = name;
469 init.ops = &audio_pll_frac_ops;
470 init.parent_names = &parent_name;
471 init.num_parents = 1;
472 init.flags = CLK_SET_RATE_GATE;
473
474 frac_ck->hw.init = &init;
475 frac_ck->regmap = regmap;
476
477 ret = clk_hw_register(NULL, &frac_ck->hw);
478 if (ret) {
479 kfree(frac_ck);
480 return ERR_PTR(ret);
481 }
482
483 return &frac_ck->hw;
484}
485
486struct clk_hw * __init
487at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
488 const char *parent_name)
489{
490 struct clk_audio_pad *apad_ck;
491 struct clk_init_data init;
492 int ret;
493
494 apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
495 if (!apad_ck)
496 return ERR_PTR(-ENOMEM);
497
498 init.name = name;
499 init.ops = &audio_pll_pad_ops;
500 init.parent_names = &parent_name;
501 init.num_parents = 1;
502 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
503 CLK_SET_RATE_PARENT;
504
505 apad_ck->hw.init = &init;
506 apad_ck->regmap = regmap;
507
508 ret = clk_hw_register(NULL, &apad_ck->hw);
509 if (ret) {
510 kfree(apad_ck);
511 return ERR_PTR(ret);
512 }
513
514 return &apad_ck->hw;
515}
516
517struct clk_hw * __init
518at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
519 const char *parent_name)
520{
521 struct clk_audio_pmc *apmc_ck;
522 struct clk_init_data init;
523 int ret;
524
525 apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
526 if (!apmc_ck)
527 return ERR_PTR(-ENOMEM);
528
529 init.name = name;
530 init.ops = &audio_pll_pmc_ops;
531 init.parent_names = &parent_name;
532 init.num_parents = 1;
533 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
534 CLK_SET_RATE_PARENT;
535
536 apmc_ck->hw.init = &init;
537 apmc_ck->regmap = regmap;
538
539 ret = clk_hw_register(NULL, &apmc_ck->hw);
540 if (ret) {
541 kfree(apmc_ck);
542 return ERR_PTR(ret);
543 }
544
545 return &apmc_ck->hw;
546}
547

Warning: That file was not part of the compilation database. It may have many parsing errors.