1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Marvell PXA27x family clocks |
4 | * |
5 | * Copyright (C) 2014 Robert Jarzmik |
6 | * |
7 | * Heavily inspired from former arch/arm/mach-pxa/clock.c. |
8 | */ |
9 | #include <linux/clk-provider.h> |
10 | #include <linux/io.h> |
11 | #include <linux/clk.h> |
12 | #include <linux/clkdev.h> |
13 | #include <linux/of.h> |
14 | #include <linux/soc/pxa/smemc.h> |
15 | #include <linux/clk/pxa.h> |
16 | |
17 | #include <dt-bindings/clock/pxa-clock.h> |
18 | #include "clk-pxa.h" |
19 | #include "clk-pxa2xx.h" |
20 | |
21 | #define KHz 1000 |
22 | #define MHz (1000 * 1000) |
23 | |
24 | enum { |
25 | PXA_CORE_13Mhz = 0, |
26 | PXA_CORE_RUN, |
27 | PXA_CORE_TURBO, |
28 | }; |
29 | |
30 | enum { |
31 | PXA_BUS_13Mhz = 0, |
32 | PXA_BUS_RUN, |
33 | }; |
34 | |
35 | enum { |
36 | PXA_LCD_13Mhz = 0, |
37 | PXA_LCD_RUN, |
38 | }; |
39 | |
40 | enum { |
41 | PXA_MEM_13Mhz = 0, |
42 | PXA_MEM_SYSTEM_BUS, |
43 | PXA_MEM_RUN, |
44 | }; |
45 | |
46 | #define PXA27x_CLKCFG(B, HT, T) \ |
47 | (CLKCFG_FCS | \ |
48 | ((B) ? CLKCFG_FASTBUS : 0) | \ |
49 | ((HT) ? CLKCFG_HALFTURBO : 0) | \ |
50 | ((T) ? CLKCFG_TURBO : 0)) |
51 | #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) |
52 | |
53 | /* Define the refresh period in mSec for the SDRAM and the number of rows */ |
54 | #define SDRAM_TREF 64 /* standard 64ms SDRAM */ |
55 | |
56 | static void __iomem *clk_regs; |
57 | |
58 | static const char * const get_freq_khz[] = { |
59 | "core" , "run" , "cpll" , "memory" , |
60 | "system_bus" |
61 | }; |
62 | |
63 | static u32 mdrefr_dri(unsigned int freq_khz) |
64 | { |
65 | u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows(); |
66 | |
67 | return (interval - 31) / 32; |
68 | } |
69 | |
70 | /* |
71 | * Get the clock frequency as reflected by CCSR and the turbo flag. |
72 | * We assume these values have been applied via a fcs. |
73 | * If info is not 0 we also display the current settings. |
74 | */ |
75 | unsigned int pxa27x_get_clk_frequency_khz(int info) |
76 | { |
77 | struct clk *clk; |
78 | unsigned long clks[5]; |
79 | int i; |
80 | |
81 | for (i = 0; i < 5; i++) { |
82 | clk = clk_get(NULL, get_freq_khz[i]); |
83 | if (IS_ERR(clk)) { |
84 | clks[i] = 0; |
85 | } else { |
86 | clks[i] = clk_get_rate(clk); |
87 | clk_put(clk); |
88 | } |
89 | } |
90 | if (info) { |
91 | pr_info("Run Mode clock: %ld.%02ldMHz\n" , |
92 | clks[1] / 1000000, (clks[1] % 1000000) / 10000); |
93 | pr_info("Turbo Mode clock: %ld.%02ldMHz\n" , |
94 | clks[2] / 1000000, (clks[2] % 1000000) / 10000); |
95 | pr_info("Memory clock: %ld.%02ldMHz\n" , |
96 | clks[3] / 1000000, (clks[3] % 1000000) / 10000); |
97 | pr_info("System bus clock: %ld.%02ldMHz\n" , |
98 | clks[4] / 1000000, (clks[4] % 1000000) / 10000); |
99 | } |
100 | return (unsigned int)clks[0] / KHz; |
101 | } |
102 | |
103 | static bool pxa27x_is_ppll_disabled(void) |
104 | { |
105 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
106 | |
107 | return ccsr & (1 << CCCR_PPDIS_BIT); |
108 | } |
109 | |
110 | #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \ |
111 | bit, is_lp, flags) \ |
112 | PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \ |
113 | is_lp, CKEN, CKEN_ ## bit, flags) |
114 | #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ |
115 | PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \ |
116 | div_hp, bit, pxa27x_is_ppll_disabled, 0) |
117 | |
118 | PARENTS(pxa27x_pbus) = { "osc_13mhz" , "ppll_312mhz" }; |
119 | PARENTS(pxa27x_sbus) = { "system_bus" , "system_bus" }; |
120 | PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz" , "osc_32_768khz" }; |
121 | PARENTS(pxa27x_lcd_bus) = { "lcd_base" , "lcd_base" }; |
122 | PARENTS(pxa27x_membus) = { "lcd_base" , "lcd_base" }; |
123 | |
124 | #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ |
125 | PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ |
126 | CKEN, CKEN_ ## bit, 0) |
127 | #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ |
128 | PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ |
129 | CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) |
130 | |
131 | static struct desc_clk_cken pxa27x_clocks[] __initdata = { |
132 | PXA27X_PBUS_CKEN("pxa2xx-uart.0" , NULL, FFUART, 2, 42, 1), |
133 | PXA27X_PBUS_CKEN("pxa2xx-uart.1" , NULL, BTUART, 2, 42, 1), |
134 | PXA27X_PBUS_CKEN("pxa2xx-uart.2" , NULL, STUART, 2, 42, 1), |
135 | PXA27X_PBUS_CKEN("pxa2xx-i2s" , NULL, I2S, 2, 51, 0), |
136 | PXA27X_PBUS_CKEN("pxa2xx-i2c.0" , NULL, I2C, 2, 19, 0), |
137 | PXA27X_PBUS_CKEN("pxa27x-udc" , NULL, USB, 2, 13, 5), |
138 | PXA27X_PBUS_CKEN("pxa2xx-mci.0" , NULL, MMC, 2, 32, 0), |
139 | PXA27X_PBUS_CKEN("pxa2xx-ir" , "FICPCLK" , FICP, 2, 13, 0), |
140 | PXA27X_PBUS_CKEN("pxa27x-ohci" , NULL, USBHOST, 2, 13, 0), |
141 | PXA27X_PBUS_CKEN("pxa2xx-i2c.1" , NULL, PWRI2C, 1, 24, 0), |
142 | PXA27X_PBUS_CKEN("pxa27x-ssp.0" , NULL, SSP1, 1, 24, 0), |
143 | PXA27X_PBUS_CKEN("pxa27x-ssp.1" , NULL, SSP2, 1, 24, 0), |
144 | PXA27X_PBUS_CKEN("pxa27x-ssp.2" , NULL, SSP3, 1, 24, 0), |
145 | PXA27X_PBUS_CKEN("pxa27x-pwm.0" , NULL, PWM0, 1, 24, 0), |
146 | PXA27X_PBUS_CKEN("pxa27x-pwm.1" , NULL, PWM1, 1, 24, 0), |
147 | PXA27X_PBUS_CKEN(NULL, "MSLCLK" , MSL, 2, 13, 0), |
148 | PXA27X_PBUS_CKEN(NULL, "USIMCLK" , USIM, 2, 13, 0), |
149 | PXA27X_PBUS_CKEN(NULL, "MSTKCLK" , MEMSTK, 2, 32, 0), |
150 | PXA27X_PBUS_CKEN(NULL, "AC97CLK" , AC97, 1, 1, 0), |
151 | PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK" , AC97CONF, 1, 1, 0), |
152 | PXA27X_PBUS_CKEN(NULL, "OSTIMER0" , OSTIMER, 1, 96, 0), |
153 | |
154 | PXA27X_CKEN_1RATE("pxa27x-keypad" , NULL, KEYPAD, |
155 | pxa27x_32Mhz_bus_parents, 0), |
156 | PXA27X_CKEN_1RATE(NULL, "IMCLK" , IM, pxa27x_sbus_parents, 0), |
157 | PXA27X_CKEN_1RATE("pxa2xx-fb" , NULL, LCD, pxa27x_lcd_bus_parents, 0), |
158 | PXA27X_CKEN_1RATE("pxa27x-camera.0" , NULL, CAMERA, |
159 | pxa27x_lcd_bus_parents, 0), |
160 | PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia" , NULL, MEMC, |
161 | pxa27x_membus_parents, 0), |
162 | |
163 | }; |
164 | |
165 | /* |
166 | * PXA270 definitions |
167 | * |
168 | * For the PXA27x: |
169 | * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. |
170 | * |
171 | * A = 0 => memory controller clock from table 3-7, |
172 | * A = 1 => memory controller clock = system bus clock |
173 | * Run mode frequency = 13 MHz * L |
174 | * Turbo mode frequency = 13 MHz * L * N |
175 | * System bus frequency = 13 MHz * L / (B + 1) |
176 | * |
177 | * In CCCR: |
178 | * A = 1 |
179 | * L = 16 oscillator to run mode ratio |
180 | * 2N = 6 2 * (turbo mode to run mode ratio) |
181 | * |
182 | * In CCLKCFG: |
183 | * B = 1 Fast bus mode |
184 | * HT = 0 Half-Turbo mode |
185 | * T = 1 Turbo mode |
186 | * |
187 | * For now, just support some of the combinations in table 3-7 of |
188 | * PXA27x Processor Family Developer's Manual to simplify frequency |
189 | * change sequences. |
190 | */ |
191 | static struct pxa2xx_freq pxa27x_freqs[] = { |
192 | {104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) }, |
193 | {156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) }, |
194 | {208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) }, |
195 | {312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) }, |
196 | {416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) }, |
197 | {520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) }, |
198 | {624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) }, |
199 | }; |
200 | |
201 | static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw, |
202 | unsigned long parent_rate) |
203 | { |
204 | unsigned long clkcfg; |
205 | unsigned int t, ht; |
206 | unsigned int l, L, n2, N; |
207 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
208 | |
209 | asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); |
210 | t = clkcfg & (1 << 0); |
211 | ht = clkcfg & (1 << 2); |
212 | |
213 | l = ccsr & CCSR_L_MASK; |
214 | n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; |
215 | L = l * parent_rate; |
216 | N = (L * n2) / 2; |
217 | |
218 | return N; |
219 | } |
220 | |
221 | static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw, |
222 | struct clk_rate_request *req) |
223 | { |
224 | return pxa2xx_determine_rate(req, freqs: pxa27x_freqs, |
225 | ARRAY_SIZE(pxa27x_freqs)); |
226 | } |
227 | |
228 | static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate, |
229 | unsigned long parent_rate) |
230 | { |
231 | int i; |
232 | |
233 | pr_debug("%s(rate=%lu parent_rate=%lu)\n" , __func__, rate, parent_rate); |
234 | for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++) |
235 | if (pxa27x_freqs[i].cpll == rate) |
236 | break; |
237 | |
238 | if (i >= ARRAY_SIZE(pxa27x_freqs)) |
239 | return -EINVAL; |
240 | |
241 | pxa2xx_cpll_change(freq: &pxa27x_freqs[i], mdrefr_dri, cccr: clk_regs + CCCR); |
242 | return 0; |
243 | } |
244 | |
245 | PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" }; |
246 | RATE_OPS(clk_pxa27x_cpll, "cpll" ); |
247 | |
248 | static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw, |
249 | unsigned long parent_rate) |
250 | { |
251 | unsigned int l, osc_forced; |
252 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
253 | unsigned long cccr = readl(addr: clk_regs + CCCR); |
254 | |
255 | l = ccsr & CCSR_L_MASK; |
256 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
257 | if (osc_forced) { |
258 | if (cccr & (1 << CCCR_LCD_26_BIT)) |
259 | return parent_rate * 2; |
260 | else |
261 | return parent_rate; |
262 | } |
263 | |
264 | if (l <= 7) |
265 | return parent_rate; |
266 | if (l <= 16) |
267 | return parent_rate / 2; |
268 | return parent_rate / 4; |
269 | } |
270 | |
271 | static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw) |
272 | { |
273 | unsigned int osc_forced; |
274 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
275 | |
276 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
277 | if (osc_forced) |
278 | return PXA_LCD_13Mhz; |
279 | else |
280 | return PXA_LCD_RUN; |
281 | } |
282 | |
283 | PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz" , "run" }; |
284 | MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base" ); |
285 | |
286 | static void __init pxa27x_register_plls(void) |
287 | { |
288 | clk_register_fixed_rate(NULL, name: "osc_13mhz" , NULL, |
289 | CLK_GET_RATE_NOCACHE, |
290 | fixed_rate: 13 * MHz); |
291 | clkdev_pxa_register(CLK_OSC32k768, con_id: "osc_32_768khz" , NULL, |
292 | clk: clk_register_fixed_rate(NULL, name: "osc_32_768khz" , NULL, |
293 | CLK_GET_RATE_NOCACHE, |
294 | fixed_rate: 32768 * KHz)); |
295 | clk_register_fixed_rate(NULL, name: "clk_dummy" , NULL, flags: 0, fixed_rate: 0); |
296 | clk_register_fixed_factor(NULL, name: "ppll_312mhz" , parent_name: "osc_13mhz" , flags: 0, mult: 24, div: 1); |
297 | } |
298 | |
299 | static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw) |
300 | { |
301 | unsigned long clkcfg; |
302 | unsigned int t, ht, osc_forced; |
303 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
304 | |
305 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
306 | if (osc_forced) |
307 | return PXA_CORE_13Mhz; |
308 | |
309 | asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); |
310 | t = clkcfg & (1 << 0); |
311 | ht = clkcfg & (1 << 2); |
312 | |
313 | if (ht || t) |
314 | return PXA_CORE_TURBO; |
315 | return PXA_CORE_RUN; |
316 | } |
317 | |
318 | static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index) |
319 | { |
320 | if (index > PXA_CORE_TURBO) |
321 | return -EINVAL; |
322 | |
323 | pxa2xx_core_turbo_switch(on: index == PXA_CORE_TURBO); |
324 | |
325 | return 0; |
326 | } |
327 | |
328 | static int clk_pxa27x_core_determine_rate(struct clk_hw *hw, |
329 | struct clk_rate_request *req) |
330 | { |
331 | return __clk_mux_determine_rate(hw, req); |
332 | } |
333 | |
334 | PARENTS(clk_pxa27x_core) = { "osc_13mhz" , "run" , "cpll" }; |
335 | MUX_OPS(clk_pxa27x_core, "core" , CLK_SET_RATE_PARENT); |
336 | |
337 | static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw, |
338 | unsigned long parent_rate) |
339 | { |
340 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
341 | unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; |
342 | |
343 | return (parent_rate / n2) * 2; |
344 | } |
345 | PARENTS(clk_pxa27x_run) = { "cpll" }; |
346 | RATE_RO_OPS(clk_pxa27x_run, "run" ); |
347 | |
348 | static void __init pxa27x_register_core(void) |
349 | { |
350 | clkdev_pxa_register(CLK_NONE, con_id: "cpll" , NULL, |
351 | clk: clk_register_clk_pxa27x_cpll()); |
352 | clkdev_pxa_register(CLK_NONE, con_id: "run" , NULL, |
353 | clk: clk_register_clk_pxa27x_run()); |
354 | clkdev_pxa_register(CLK_CORE, con_id: "core" , NULL, |
355 | clk: clk_register_clk_pxa27x_core()); |
356 | } |
357 | |
358 | static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw, |
359 | unsigned long parent_rate) |
360 | { |
361 | unsigned long clkcfg; |
362 | unsigned int b, osc_forced; |
363 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
364 | |
365 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
366 | asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); |
367 | b = clkcfg & (1 << 3); |
368 | |
369 | if (osc_forced) |
370 | return parent_rate; |
371 | if (b) |
372 | return parent_rate; |
373 | else |
374 | return parent_rate / 2; |
375 | } |
376 | |
377 | static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw) |
378 | { |
379 | unsigned int osc_forced; |
380 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
381 | |
382 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
383 | if (osc_forced) |
384 | return PXA_BUS_13Mhz; |
385 | else |
386 | return PXA_BUS_RUN; |
387 | } |
388 | |
389 | PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz" , "run" }; |
390 | MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus" ); |
391 | |
392 | static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw, |
393 | unsigned long parent_rate) |
394 | { |
395 | unsigned int a, l, osc_forced; |
396 | unsigned long cccr = readl(addr: clk_regs + CCCR); |
397 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
398 | |
399 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
400 | a = cccr & (1 << CCCR_A_BIT); |
401 | l = ccsr & CCSR_L_MASK; |
402 | |
403 | if (osc_forced || a) |
404 | return parent_rate; |
405 | if (l <= 10) |
406 | return parent_rate; |
407 | if (l <= 20) |
408 | return parent_rate / 2; |
409 | return parent_rate / 4; |
410 | } |
411 | |
412 | static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw) |
413 | { |
414 | unsigned int osc_forced, a; |
415 | unsigned long cccr = readl(addr: clk_regs + CCCR); |
416 | unsigned long ccsr = readl(addr: clk_regs + CCSR); |
417 | |
418 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
419 | a = cccr & (1 << CCCR_A_BIT); |
420 | if (osc_forced) |
421 | return PXA_MEM_13Mhz; |
422 | if (a) |
423 | return PXA_MEM_SYSTEM_BUS; |
424 | else |
425 | return PXA_MEM_RUN; |
426 | } |
427 | |
428 | PARENTS(clk_pxa27x_memory) = { "osc_13mhz" , "system_bus" , "run" }; |
429 | MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory" ); |
430 | |
431 | #define DUMMY_CLK(_con_id, _dev_id, _parent) \ |
432 | { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } |
433 | struct dummy_clk { |
434 | const char *con_id; |
435 | const char *dev_id; |
436 | const char *parent; |
437 | }; |
438 | static struct dummy_clk dummy_clks[] __initdata = { |
439 | DUMMY_CLK(NULL, "pxa27x-gpio" , "osc_32_768khz" ), |
440 | DUMMY_CLK(NULL, "pxa-rtc" , "osc_32_768khz" ), |
441 | DUMMY_CLK(NULL, "sa1100-rtc" , "osc_32_768khz" ), |
442 | DUMMY_CLK("UARTCLK" , "pxa2xx-ir" , "STUART" ), |
443 | }; |
444 | |
445 | static void __init pxa27x_dummy_clocks_init(void) |
446 | { |
447 | struct clk *clk; |
448 | struct dummy_clk *d; |
449 | const char *name; |
450 | int i; |
451 | |
452 | for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { |
453 | d = &dummy_clks[i]; |
454 | name = d->dev_id ? d->dev_id : d->con_id; |
455 | clk = clk_register_fixed_factor(NULL, name, parent_name: d->parent, flags: 0, mult: 1, div: 1); |
456 | clk_register_clkdev(clk, d->con_id, d->dev_id); |
457 | } |
458 | } |
459 | |
460 | static void __init pxa27x_base_clocks_init(void) |
461 | { |
462 | pxa27x_register_plls(); |
463 | pxa27x_register_core(); |
464 | clkdev_pxa_register(CLK_NONE, con_id: "system_bus" , NULL, |
465 | clk: clk_register_clk_pxa27x_system_bus()); |
466 | clkdev_pxa_register(CLK_NONE, con_id: "memory" , NULL, |
467 | clk: clk_register_clk_pxa27x_memory()); |
468 | clk_register_clk_pxa27x_lcd_base(); |
469 | } |
470 | |
471 | int __init pxa27x_clocks_init(void __iomem *regs) |
472 | { |
473 | clk_regs = regs; |
474 | pxa27x_base_clocks_init(); |
475 | pxa27x_dummy_clocks_init(); |
476 | return clk_pxa_cken_init(clks: pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks), clk_regs: regs); |
477 | } |
478 | |
479 | static void __init pxa27x_dt_clocks_init(struct device_node *np) |
480 | { |
481 | pxa27x_clocks_init(ioremap(offset: 0x41300000ul, size: 0x10)); |
482 | clk_pxa_dt_common_init(np); |
483 | } |
484 | CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks" , pxa27x_dt_clocks_init); |
485 | |