1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * EDAC driver for Intel(R) Xeon(R) Skylake processors |
4 | * Copyright (c) 2016, Intel Corporation. |
5 | */ |
6 | |
7 | #include <linux/kernel.h> |
8 | #include <linux/processor.h> |
9 | #include <asm/cpu_device_id.h> |
10 | #include <asm/intel-family.h> |
11 | #include <asm/mce.h> |
12 | |
13 | #include "edac_module.h" |
14 | #include "skx_common.h" |
15 | |
16 | #define EDAC_MOD_STR "skx_edac" |
17 | |
18 | /* |
19 | * Debug macros |
20 | */ |
21 | #define skx_printk(level, fmt, arg...) \ |
22 | edac_printk(level, "skx", fmt, ##arg) |
23 | |
24 | #define skx_mc_printk(mci, level, fmt, arg...) \ |
25 | edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) |
26 | |
27 | static struct list_head *skx_edac_list; |
28 | |
29 | static u64 skx_tolm, skx_tohm; |
30 | static int skx_num_sockets; |
31 | static unsigned int nvdimm_count; |
32 | |
33 | #define MASK26 0x3FFFFFF /* Mask for 2^26 */ |
34 | #define MASK29 0x1FFFFFFF /* Mask for 2^29 */ |
35 | |
36 | static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx) |
37 | { |
38 | struct skx_dev *d; |
39 | |
40 | list_for_each_entry(d, skx_edac_list, list) { |
41 | if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number) |
42 | return d; |
43 | } |
44 | |
45 | return NULL; |
46 | } |
47 | |
48 | enum munittype { |
49 | CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD, |
50 | ERRCHAN0, ERRCHAN1, ERRCHAN2, |
51 | }; |
52 | |
53 | struct munit { |
54 | u16 did; |
55 | u16 devfn[SKX_NUM_IMC]; |
56 | u8 busidx; |
57 | u8 per_socket; |
58 | enum munittype mtype; |
59 | }; |
60 | |
61 | /* |
62 | * List of PCI device ids that we need together with some device |
63 | * number and function numbers to tell which memory controller the |
64 | * device belongs to. |
65 | */ |
66 | static const struct munit skx_all_munits[] = { |
67 | { 0x2054, { }, 1, 1, SAD_ALL }, |
68 | { 0x2055, { }, 1, 1, UTIL_ALL }, |
69 | { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 }, |
70 | { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 }, |
71 | { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 }, |
72 | { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 }, |
73 | { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 }, |
74 | { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 }, |
75 | { 0x208e, { }, 1, 0, SAD }, |
76 | { } |
77 | }; |
78 | |
79 | static int get_all_munits(const struct munit *m) |
80 | { |
81 | struct pci_dev *pdev, *prev; |
82 | struct skx_dev *d; |
83 | u32 reg; |
84 | int i = 0, ndev = 0; |
85 | |
86 | prev = NULL; |
87 | for (;;) { |
88 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, device: m->did, from: prev); |
89 | if (!pdev) |
90 | break; |
91 | ndev++; |
92 | if (m->per_socket == SKX_NUM_IMC) { |
93 | for (i = 0; i < SKX_NUM_IMC; i++) |
94 | if (m->devfn[i] == pdev->devfn) |
95 | break; |
96 | if (i == SKX_NUM_IMC) |
97 | goto fail; |
98 | } |
99 | d = get_skx_dev(bus: pdev->bus, idx: m->busidx); |
100 | if (!d) |
101 | goto fail; |
102 | |
103 | /* Be sure that the device is enabled */ |
104 | if (unlikely(pci_enable_device(pdev) < 0)) { |
105 | skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n" , |
106 | PCI_VENDOR_ID_INTEL, m->did); |
107 | goto fail; |
108 | } |
109 | |
110 | switch (m->mtype) { |
111 | case CHAN0: |
112 | case CHAN1: |
113 | case CHAN2: |
114 | pci_dev_get(dev: pdev); |
115 | d->imc[i].chan[m->mtype].cdev = pdev; |
116 | break; |
117 | case ERRCHAN0: |
118 | case ERRCHAN1: |
119 | case ERRCHAN2: |
120 | pci_dev_get(dev: pdev); |
121 | d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev; |
122 | break; |
123 | case SAD_ALL: |
124 | pci_dev_get(dev: pdev); |
125 | d->sad_all = pdev; |
126 | break; |
127 | case UTIL_ALL: |
128 | pci_dev_get(dev: pdev); |
129 | d->util_all = pdev; |
130 | break; |
131 | case SAD: |
132 | /* |
133 | * one of these devices per core, including cores |
134 | * that don't exist on this SKU. Ignore any that |
135 | * read a route table of zero, make sure all the |
136 | * non-zero values match. |
137 | */ |
138 | pci_read_config_dword(dev: pdev, where: 0xB4, val: ®); |
139 | if (reg != 0) { |
140 | if (d->mcroute == 0) { |
141 | d->mcroute = reg; |
142 | } else if (d->mcroute != reg) { |
143 | skx_printk(KERN_ERR, "mcroute mismatch\n" ); |
144 | goto fail; |
145 | } |
146 | } |
147 | ndev--; |
148 | break; |
149 | } |
150 | |
151 | prev = pdev; |
152 | } |
153 | |
154 | return ndev; |
155 | fail: |
156 | pci_dev_put(dev: pdev); |
157 | return -ENODEV; |
158 | } |
159 | |
160 | static struct res_config skx_cfg = { |
161 | .type = SKX, |
162 | .decs_did = 0x2016, |
163 | .busno_cfg_offset = 0xcc, |
164 | }; |
165 | |
166 | static const struct x86_cpu_id skx_cpuids[] = { |
167 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cfg), |
168 | { } |
169 | }; |
170 | MODULE_DEVICE_TABLE(x86cpu, skx_cpuids); |
171 | |
172 | static bool skx_check_ecc(u32 mcmtr) |
173 | { |
174 | return !!GET_BITFIELD(mcmtr, 2, 2); |
175 | } |
176 | |
177 | static int skx_get_dimm_config(struct mem_ctl_info *mci, struct res_config *cfg) |
178 | { |
179 | struct skx_pvt *pvt = mci->pvt_info; |
180 | u32 mtr, mcmtr, amap, mcddrtcfg; |
181 | struct skx_imc *imc = pvt->imc; |
182 | struct dimm_info *dimm; |
183 | int i, j; |
184 | int ndimms; |
185 | |
186 | /* Only the mcmtr on the first channel is effective */ |
187 | pci_read_config_dword(dev: imc->chan[0].cdev, where: 0x87c, val: &mcmtr); |
188 | |
189 | for (i = 0; i < SKX_NUM_CHANNELS; i++) { |
190 | ndimms = 0; |
191 | pci_read_config_dword(dev: imc->chan[i].cdev, where: 0x8C, val: &amap); |
192 | pci_read_config_dword(dev: imc->chan[i].cdev, where: 0x400, val: &mcddrtcfg); |
193 | for (j = 0; j < SKX_NUM_DIMMS; j++) { |
194 | dimm = edac_get_dimm(mci, layer0: i, layer1: j, layer2: 0); |
195 | pci_read_config_dword(dev: imc->chan[i].cdev, |
196 | where: 0x80 + 4 * j, val: &mtr); |
197 | if (IS_DIMM_PRESENT(mtr)) { |
198 | ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, chan: i, dimmno: j, cfg); |
199 | } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) { |
200 | ndimms += skx_get_nvdimm_info(dimm, imc, chan: i, dimmno: j, |
201 | EDAC_MOD_STR); |
202 | nvdimm_count++; |
203 | } |
204 | } |
205 | if (ndimms && !skx_check_ecc(mcmtr)) { |
206 | skx_printk(KERN_ERR, "ECC is disabled on imc %d\n" , imc->mc); |
207 | return -ENODEV; |
208 | } |
209 | } |
210 | |
211 | return 0; |
212 | } |
213 | |
214 | #define SKX_MAX_SAD 24 |
215 | |
216 | #define SKX_GET_SAD(d, i, reg) \ |
217 | pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg)) |
218 | #define SKX_GET_ILV(d, i, reg) \ |
219 | pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg)) |
220 | |
221 | #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31) |
222 | #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27) |
223 | #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26) |
224 | #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6) |
225 | #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4) |
226 | #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2) |
227 | #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0) |
228 | |
229 | #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0) |
230 | #define SKX_ILV_TARGET(tgt) ((tgt) & 7) |
231 | |
232 | static void skx_show_retry_rd_err_log(struct decoded_addr *res, |
233 | char *msg, int len, |
234 | bool scrub_err) |
235 | { |
236 | u32 log0, log1, log2, log3, log4; |
237 | u32 corr0, corr1, corr2, corr3; |
238 | struct pci_dev *edev; |
239 | int n; |
240 | |
241 | edev = res->dev->imc[res->imc].chan[res->channel].edev; |
242 | |
243 | pci_read_config_dword(dev: edev, where: 0x154, val: &log0); |
244 | pci_read_config_dword(dev: edev, where: 0x148, val: &log1); |
245 | pci_read_config_dword(dev: edev, where: 0x150, val: &log2); |
246 | pci_read_config_dword(dev: edev, where: 0x15c, val: &log3); |
247 | pci_read_config_dword(dev: edev, where: 0x114, val: &log4); |
248 | |
249 | n = snprintf(buf: msg, size: len, fmt: " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]" , |
250 | log0, log1, log2, log3, log4); |
251 | |
252 | pci_read_config_dword(dev: edev, where: 0x104, val: &corr0); |
253 | pci_read_config_dword(dev: edev, where: 0x108, val: &corr1); |
254 | pci_read_config_dword(dev: edev, where: 0x10c, val: &corr2); |
255 | pci_read_config_dword(dev: edev, where: 0x110, val: &corr3); |
256 | |
257 | if (len - n > 0) |
258 | snprintf(buf: msg + n, size: len - n, |
259 | fmt: " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]" , |
260 | corr0 & 0xffff, corr0 >> 16, |
261 | corr1 & 0xffff, corr1 >> 16, |
262 | corr2 & 0xffff, corr2 >> 16, |
263 | corr3 & 0xffff, corr3 >> 16); |
264 | } |
265 | |
266 | static bool skx_sad_decode(struct decoded_addr *res) |
267 | { |
268 | struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list); |
269 | u64 addr = res->addr; |
270 | int i, idx, tgt, lchan, shift; |
271 | u32 sad, ilv; |
272 | u64 limit, prev_limit; |
273 | int remote = 0; |
274 | |
275 | /* Simple sanity check for I/O space or out of range */ |
276 | if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) { |
277 | edac_dbg(0, "Address 0x%llx out of range\n" , addr); |
278 | return false; |
279 | } |
280 | |
281 | restart: |
282 | prev_limit = 0; |
283 | for (i = 0; i < SKX_MAX_SAD; i++) { |
284 | SKX_GET_SAD(d, i, sad); |
285 | limit = SKX_SAD_LIMIT(sad); |
286 | if (SKX_SAD_ENABLE(sad)) { |
287 | if (addr >= prev_limit && addr <= limit) |
288 | goto sad_found; |
289 | } |
290 | prev_limit = limit + 1; |
291 | } |
292 | edac_dbg(0, "No SAD entry for 0x%llx\n" , addr); |
293 | return false; |
294 | |
295 | sad_found: |
296 | SKX_GET_ILV(d, i, ilv); |
297 | |
298 | switch (SKX_SAD_INTERLEAVE(sad)) { |
299 | case 0: |
300 | idx = GET_BITFIELD(addr, 6, 8); |
301 | break; |
302 | case 1: |
303 | idx = GET_BITFIELD(addr, 8, 10); |
304 | break; |
305 | case 2: |
306 | idx = GET_BITFIELD(addr, 12, 14); |
307 | break; |
308 | case 3: |
309 | idx = GET_BITFIELD(addr, 30, 32); |
310 | break; |
311 | } |
312 | |
313 | tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3); |
314 | |
315 | /* If point to another node, find it and start over */ |
316 | if (SKX_ILV_REMOTE(tgt)) { |
317 | if (remote) { |
318 | edac_dbg(0, "Double remote!\n" ); |
319 | return false; |
320 | } |
321 | remote = 1; |
322 | list_for_each_entry(d, skx_edac_list, list) { |
323 | if (d->imc[0].src_id == SKX_ILV_TARGET(tgt)) |
324 | goto restart; |
325 | } |
326 | edac_dbg(0, "Can't find node %d\n" , SKX_ILV_TARGET(tgt)); |
327 | return false; |
328 | } |
329 | |
330 | if (SKX_SAD_MOD3(sad) == 0) { |
331 | lchan = SKX_ILV_TARGET(tgt); |
332 | } else { |
333 | switch (SKX_SAD_MOD3MODE(sad)) { |
334 | case 0: |
335 | shift = 6; |
336 | break; |
337 | case 1: |
338 | shift = 8; |
339 | break; |
340 | case 2: |
341 | shift = 12; |
342 | break; |
343 | default: |
344 | edac_dbg(0, "illegal mod3mode\n" ); |
345 | return false; |
346 | } |
347 | switch (SKX_SAD_MOD3ASMOD2(sad)) { |
348 | case 0: |
349 | lchan = (addr >> shift) % 3; |
350 | break; |
351 | case 1: |
352 | lchan = (addr >> shift) % 2; |
353 | break; |
354 | case 2: |
355 | lchan = (addr >> shift) % 2; |
356 | lchan = (lchan << 1) | !lchan; |
357 | break; |
358 | case 3: |
359 | lchan = ((addr >> shift) % 2) << 1; |
360 | break; |
361 | } |
362 | lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1); |
363 | } |
364 | |
365 | res->dev = d; |
366 | res->socket = d->imc[0].src_id; |
367 | res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2); |
368 | res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19); |
369 | |
370 | edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n" , |
371 | res->addr, res->socket, res->imc, res->channel); |
372 | return true; |
373 | } |
374 | |
375 | #define SKX_MAX_TAD 8 |
376 | |
377 | #define SKX_GET_TADBASE(d, mc, i, reg) \ |
378 | pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg)) |
379 | #define SKX_GET_TADWAYNESS(d, mc, i, reg) \ |
380 | pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg)) |
381 | #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \ |
382 | pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg)) |
383 | |
384 | #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26) |
385 | #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5) |
386 | #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7) |
387 | #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26) |
388 | #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26) |
389 | #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11)) |
390 | #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1) |
391 | |
392 | /* which bit used for both socket and channel interleave */ |
393 | static int skx_granularity[] = { 6, 8, 12, 30 }; |
394 | |
395 | static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits) |
396 | { |
397 | addr >>= shift; |
398 | addr /= ways; |
399 | addr <<= shift; |
400 | |
401 | return addr | (lowbits & ((1ull << shift) - 1)); |
402 | } |
403 | |
404 | static bool skx_tad_decode(struct decoded_addr *res) |
405 | { |
406 | int i; |
407 | u32 base, wayness, chnilvoffset; |
408 | int skt_interleave_bit, chn_interleave_bit; |
409 | u64 channel_addr; |
410 | |
411 | for (i = 0; i < SKX_MAX_TAD; i++) { |
412 | SKX_GET_TADBASE(res->dev, res->imc, i, base); |
413 | SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness); |
414 | if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness)) |
415 | goto tad_found; |
416 | } |
417 | edac_dbg(0, "No TAD entry for 0x%llx\n" , res->addr); |
418 | return false; |
419 | |
420 | tad_found: |
421 | res->sktways = SKX_TAD_SKTWAYS(wayness); |
422 | res->chanways = SKX_TAD_CHNWAYS(wayness); |
423 | skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)]; |
424 | chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)]; |
425 | |
426 | SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset); |
427 | channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset); |
428 | |
429 | if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) { |
430 | /* Must handle channel first, then socket */ |
431 | channel_addr = skx_do_interleave(addr: channel_addr, shift: chn_interleave_bit, |
432 | ways: res->chanways, lowbits: channel_addr); |
433 | channel_addr = skx_do_interleave(addr: channel_addr, shift: skt_interleave_bit, |
434 | ways: res->sktways, lowbits: channel_addr); |
435 | } else { |
436 | /* Handle socket then channel. Preserve low bits from original address */ |
437 | channel_addr = skx_do_interleave(addr: channel_addr, shift: skt_interleave_bit, |
438 | ways: res->sktways, lowbits: res->addr); |
439 | channel_addr = skx_do_interleave(addr: channel_addr, shift: chn_interleave_bit, |
440 | ways: res->chanways, lowbits: res->addr); |
441 | } |
442 | |
443 | res->chan_addr = channel_addr; |
444 | |
445 | edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n" , |
446 | res->addr, res->chan_addr, res->sktways, res->chanways); |
447 | return true; |
448 | } |
449 | |
450 | #define SKX_MAX_RIR 4 |
451 | |
452 | #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \ |
453 | pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ |
454 | 0x108 + 4 * (i), &(reg)) |
455 | #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \ |
456 | pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ |
457 | 0x120 + 16 * (idx) + 4 * (i), &(reg)) |
458 | |
459 | #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31) |
460 | #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29) |
461 | #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29)) |
462 | #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19) |
463 | #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26)) |
464 | |
465 | static bool skx_rir_decode(struct decoded_addr *res) |
466 | { |
467 | int i, idx, chan_rank; |
468 | int shift; |
469 | u32 rirway, rirlv; |
470 | u64 rank_addr, prev_limit = 0, limit; |
471 | |
472 | if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg) |
473 | shift = 6; |
474 | else |
475 | shift = 13; |
476 | |
477 | for (i = 0; i < SKX_MAX_RIR; i++) { |
478 | SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway); |
479 | limit = SKX_RIR_LIMIT(rirway); |
480 | if (SKX_RIR_VALID(rirway)) { |
481 | if (prev_limit <= res->chan_addr && |
482 | res->chan_addr <= limit) |
483 | goto rir_found; |
484 | } |
485 | prev_limit = limit; |
486 | } |
487 | edac_dbg(0, "No RIR entry for 0x%llx\n" , res->addr); |
488 | return false; |
489 | |
490 | rir_found: |
491 | rank_addr = res->chan_addr >> shift; |
492 | rank_addr /= SKX_RIR_WAYS(rirway); |
493 | rank_addr <<= shift; |
494 | rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0); |
495 | |
496 | res->rank_address = rank_addr; |
497 | idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway); |
498 | |
499 | SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv); |
500 | res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv); |
501 | chan_rank = SKX_RIR_CHAN_RANK(rirlv); |
502 | res->channel_rank = chan_rank; |
503 | res->dimm = chan_rank / 4; |
504 | res->rank = chan_rank % 4; |
505 | |
506 | edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n" , |
507 | res->addr, res->dimm, res->rank, |
508 | res->channel_rank, res->rank_address); |
509 | return true; |
510 | } |
511 | |
512 | static u8 skx_close_row[] = { |
513 | 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33, 34 |
514 | }; |
515 | |
516 | static u8 skx_close_column[] = { |
517 | 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 |
518 | }; |
519 | |
520 | static u8 skx_open_row[] = { |
521 | 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34 |
522 | }; |
523 | |
524 | static u8 skx_open_column[] = { |
525 | 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 |
526 | }; |
527 | |
528 | static u8 skx_open_fine_column[] = { |
529 | 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 |
530 | }; |
531 | |
532 | static int skx_bits(u64 addr, int nbits, u8 *bits) |
533 | { |
534 | int i, res = 0; |
535 | |
536 | for (i = 0; i < nbits; i++) |
537 | res |= ((addr >> bits[i]) & 1) << i; |
538 | return res; |
539 | } |
540 | |
541 | static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1) |
542 | { |
543 | int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1); |
544 | |
545 | if (do_xor) |
546 | ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1); |
547 | |
548 | return ret; |
549 | } |
550 | |
551 | static bool skx_mad_decode(struct decoded_addr *r) |
552 | { |
553 | struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm]; |
554 | int bg0 = dimm->fine_grain_bank ? 6 : 13; |
555 | |
556 | if (dimm->close_pg) { |
557 | r->row = skx_bits(addr: r->rank_address, nbits: dimm->rowbits, bits: skx_close_row); |
558 | r->column = skx_bits(addr: r->rank_address, nbits: dimm->colbits, bits: skx_close_column); |
559 | r->column |= 0x400; /* C10 is autoprecharge, always set */ |
560 | r->bank_address = skx_bank_bits(addr: r->rank_address, b0: 8, b1: 9, do_xor: dimm->bank_xor_enable, x0: 22, x1: 28); |
561 | r->bank_group = skx_bank_bits(addr: r->rank_address, b0: 6, b1: 7, do_xor: dimm->bank_xor_enable, x0: 20, x1: 21); |
562 | } else { |
563 | r->row = skx_bits(addr: r->rank_address, nbits: dimm->rowbits, bits: skx_open_row); |
564 | if (dimm->fine_grain_bank) |
565 | r->column = skx_bits(addr: r->rank_address, nbits: dimm->colbits, bits: skx_open_fine_column); |
566 | else |
567 | r->column = skx_bits(addr: r->rank_address, nbits: dimm->colbits, bits: skx_open_column); |
568 | r->bank_address = skx_bank_bits(addr: r->rank_address, b0: 18, b1: 19, do_xor: dimm->bank_xor_enable, x0: 22, x1: 23); |
569 | r->bank_group = skx_bank_bits(addr: r->rank_address, b0: bg0, b1: 17, do_xor: dimm->bank_xor_enable, x0: 20, x1: 21); |
570 | } |
571 | r->row &= (1u << dimm->rowbits) - 1; |
572 | |
573 | edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n" , |
574 | r->addr, r->row, r->column, r->bank_address, |
575 | r->bank_group); |
576 | return true; |
577 | } |
578 | |
579 | static bool skx_decode(struct decoded_addr *res) |
580 | { |
581 | return skx_sad_decode(res) && skx_tad_decode(res) && |
582 | skx_rir_decode(res) && skx_mad_decode(r: res); |
583 | } |
584 | |
585 | static struct notifier_block skx_mce_dec = { |
586 | .notifier_call = skx_mce_check_error, |
587 | .priority = MCE_PRIO_EDAC, |
588 | }; |
589 | |
590 | #ifdef CONFIG_EDAC_DEBUG |
591 | /* |
592 | * Debug feature. |
593 | * Exercise the address decode logic by writing an address to |
594 | * /sys/kernel/debug/edac/skx_test/addr. |
595 | */ |
596 | static struct dentry *skx_test; |
597 | |
598 | static int debugfs_u64_set(void *data, u64 val) |
599 | { |
600 | struct mce m; |
601 | |
602 | pr_warn_once("Fake error to 0x%llx injected via debugfs\n" , val); |
603 | |
604 | memset(&m, 0, sizeof(m)); |
605 | /* ADDRV + MemRd + Unknown channel */ |
606 | m.status = MCI_STATUS_ADDRV + 0x90; |
607 | /* One corrected error */ |
608 | m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT); |
609 | m.addr = val; |
610 | skx_mce_check_error(NULL, val: 0, data: &m); |
611 | |
612 | return 0; |
613 | } |
614 | DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n" ); |
615 | |
616 | static void setup_skx_debug(void) |
617 | { |
618 | skx_test = edac_debugfs_create_dir(dirname: "skx_test" ); |
619 | if (!skx_test) |
620 | return; |
621 | |
622 | if (!edac_debugfs_create_file(name: "addr" , mode: 0200, parent: skx_test, |
623 | NULL, fops: &fops_u64_wo)) { |
624 | debugfs_remove(dentry: skx_test); |
625 | skx_test = NULL; |
626 | } |
627 | } |
628 | |
629 | static void teardown_skx_debug(void) |
630 | { |
631 | debugfs_remove_recursive(dentry: skx_test); |
632 | } |
633 | #else |
634 | static inline void setup_skx_debug(void) {} |
635 | static inline void teardown_skx_debug(void) {} |
636 | #endif /*CONFIG_EDAC_DEBUG*/ |
637 | |
638 | /* |
639 | * skx_init: |
640 | * make sure we are running on the correct cpu model |
641 | * search for all the devices we need |
642 | * check which DIMMs are present. |
643 | */ |
644 | static int __init skx_init(void) |
645 | { |
646 | const struct x86_cpu_id *id; |
647 | struct res_config *cfg; |
648 | const struct munit *m; |
649 | const char *owner; |
650 | int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8}; |
651 | u8 mc = 0, src_id, node_id; |
652 | struct skx_dev *d; |
653 | |
654 | edac_dbg(2, "\n" ); |
655 | |
656 | if (ghes_get_devices()) |
657 | return -EBUSY; |
658 | |
659 | owner = edac_get_owner(); |
660 | if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) |
661 | return -EBUSY; |
662 | |
663 | if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) |
664 | return -ENODEV; |
665 | |
666 | id = x86_match_cpu(match: skx_cpuids); |
667 | if (!id) |
668 | return -ENODEV; |
669 | |
670 | cfg = (struct res_config *)id->driver_data; |
671 | |
672 | rc = skx_get_hi_lo(did: 0x2034, off, tolm: &skx_tolm, tohm: &skx_tohm); |
673 | if (rc) |
674 | return rc; |
675 | |
676 | rc = skx_get_all_bus_mappings(cfg, list: &skx_edac_list); |
677 | if (rc < 0) |
678 | goto fail; |
679 | if (rc == 0) { |
680 | edac_dbg(2, "No memory controllers found\n" ); |
681 | return -ENODEV; |
682 | } |
683 | skx_num_sockets = rc; |
684 | |
685 | for (m = skx_all_munits; m->did; m++) { |
686 | rc = get_all_munits(m); |
687 | if (rc < 0) |
688 | goto fail; |
689 | if (rc != m->per_socket * skx_num_sockets) { |
690 | edac_dbg(2, "Expected %d, got %d of 0x%x\n" , |
691 | m->per_socket * skx_num_sockets, rc, m->did); |
692 | rc = -ENODEV; |
693 | goto fail; |
694 | } |
695 | } |
696 | |
697 | list_for_each_entry(d, skx_edac_list, list) { |
698 | rc = skx_get_src_id(d, off: 0xf0, id: &src_id); |
699 | if (rc < 0) |
700 | goto fail; |
701 | rc = skx_get_node_id(d, id: &node_id); |
702 | if (rc < 0) |
703 | goto fail; |
704 | edac_dbg(2, "src_id=%d node_id=%d\n" , src_id, node_id); |
705 | for (i = 0; i < SKX_NUM_IMC; i++) { |
706 | d->imc[i].mc = mc++; |
707 | d->imc[i].lmc = i; |
708 | d->imc[i].src_id = src_id; |
709 | d->imc[i].node_id = node_id; |
710 | rc = skx_register_mci(imc: &d->imc[i], pdev: d->imc[i].chan[0].cdev, |
711 | ctl_name: "Skylake Socket" , EDAC_MOD_STR, |
712 | get_dimm_config: skx_get_dimm_config, cfg); |
713 | if (rc < 0) |
714 | goto fail; |
715 | } |
716 | } |
717 | |
718 | skx_set_decode(decode: skx_decode, show_retry_log: skx_show_retry_rd_err_log); |
719 | |
720 | if (nvdimm_count && skx_adxl_get() != -ENODEV) { |
721 | skx_set_decode(NULL, show_retry_log: skx_show_retry_rd_err_log); |
722 | } else { |
723 | if (nvdimm_count) |
724 | skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n" ); |
725 | skx_set_decode(decode: skx_decode, show_retry_log: skx_show_retry_rd_err_log); |
726 | } |
727 | |
728 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
729 | opstate_init(); |
730 | |
731 | setup_skx_debug(); |
732 | |
733 | mce_register_decode_chain(nb: &skx_mce_dec); |
734 | |
735 | return 0; |
736 | fail: |
737 | skx_remove(); |
738 | return rc; |
739 | } |
740 | |
741 | static void __exit skx_exit(void) |
742 | { |
743 | edac_dbg(2, "\n" ); |
744 | mce_unregister_decode_chain(nb: &skx_mce_dec); |
745 | teardown_skx_debug(); |
746 | if (nvdimm_count) |
747 | skx_adxl_put(); |
748 | skx_remove(); |
749 | } |
750 | |
751 | module_init(skx_init); |
752 | module_exit(skx_exit); |
753 | |
754 | module_param(edac_op_state, int, 0444); |
755 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI" ); |
756 | |
757 | MODULE_LICENSE("GPL v2" ); |
758 | MODULE_AUTHOR("Tony Luck" ); |
759 | MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors" ); |
760 | |