1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24#ifndef __AMDGPU_RING_H__
25#define __AMDGPU_RING_H__
26
27#include <drm/amdgpu_drm.h>
28#include <drm/gpu_scheduler.h>
29#include <drm/drm_print.h>
30
31/* max number of rings */
32#define AMDGPU_MAX_RINGS 23
33#define AMDGPU_MAX_GFX_RINGS 1
34#define AMDGPU_MAX_COMPUTE_RINGS 8
35#define AMDGPU_MAX_VCE_RINGS 3
36#define AMDGPU_MAX_UVD_ENC_RINGS 2
37
38/* some special values for the owner field */
39#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
40#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
41#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
42
43#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
44#define AMDGPU_FENCE_FLAG_INT (1 << 1)
45#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
46
47#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
48
49enum amdgpu_ring_type {
50 AMDGPU_RING_TYPE_GFX,
51 AMDGPU_RING_TYPE_COMPUTE,
52 AMDGPU_RING_TYPE_SDMA,
53 AMDGPU_RING_TYPE_UVD,
54 AMDGPU_RING_TYPE_VCE,
55 AMDGPU_RING_TYPE_KIQ,
56 AMDGPU_RING_TYPE_UVD_ENC,
57 AMDGPU_RING_TYPE_VCN_DEC,
58 AMDGPU_RING_TYPE_VCN_ENC,
59 AMDGPU_RING_TYPE_VCN_JPEG
60};
61
62struct amdgpu_device;
63struct amdgpu_ring;
64struct amdgpu_ib;
65struct amdgpu_cs_parser;
66struct amdgpu_job;
67
68/*
69 * Fences.
70 */
71struct amdgpu_fence_driver {
72 uint64_t gpu_addr;
73 volatile uint32_t *cpu_addr;
74 /* sync_seq is protected by ring emission lock */
75 uint32_t sync_seq;
76 atomic_t last_seq;
77 bool initialized;
78 struct amdgpu_irq_src *irq_src;
79 unsigned irq_type;
80 struct timer_list fallback_timer;
81 unsigned num_fences_mask;
82 spinlock_t lock;
83 struct dma_fence **fences;
84};
85
86int amdgpu_fence_driver_init(struct amdgpu_device *adev);
87void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
88void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
89
90int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
91 unsigned num_hw_submission);
92int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
93 struct amdgpu_irq_src *irq_src,
94 unsigned irq_type);
95void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
96void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
98 unsigned flags);
99int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
100bool amdgpu_fence_process(struct amdgpu_ring *ring);
101int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
102signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
103 uint32_t wait_seq,
104 signed long timeout);
105unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
106
107/*
108 * Rings.
109 */
110
111/* provided by hw blocks that expose a ring buffer for commands */
112struct amdgpu_ring_funcs {
113 enum amdgpu_ring_type type;
114 uint32_t align_mask;
115 u32 nop;
116 bool support_64bit_ptrs;
117 unsigned vmhub;
118 unsigned extra_dw;
119
120 /* ring read/write ptr handling */
121 u64 (*get_rptr)(struct amdgpu_ring *ring);
122 u64 (*get_wptr)(struct amdgpu_ring *ring);
123 void (*set_wptr)(struct amdgpu_ring *ring);
124 /* validating and patching of IBs */
125 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
126 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
127 /* constants to calculate how many DW are needed for an emit */
128 unsigned emit_frame_size;
129 unsigned emit_ib_size;
130 /* command emit functions */
131 void (*emit_ib)(struct amdgpu_ring *ring,
132 struct amdgpu_job *job,
133 struct amdgpu_ib *ib,
134 uint32_t flags);
135 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
136 uint64_t seq, unsigned flags);
137 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
138 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
139 uint64_t pd_addr);
140 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
141 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
142 uint32_t gds_base, uint32_t gds_size,
143 uint32_t gws_base, uint32_t gws_size,
144 uint32_t oa_base, uint32_t oa_size);
145 /* testing functions */
146 int (*test_ring)(struct amdgpu_ring *ring);
147 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
148 /* insert NOP packets */
149 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
150 void (*insert_start)(struct amdgpu_ring *ring);
151 void (*insert_end)(struct amdgpu_ring *ring);
152 /* pad the indirect buffer to the necessary number of dw */
153 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
154 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
155 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
156 /* note usage for clock and power gating */
157 void (*begin_use)(struct amdgpu_ring *ring);
158 void (*end_use)(struct amdgpu_ring *ring);
159 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
160 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
161 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
162 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
163 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
164 uint32_t val, uint32_t mask);
165 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
166 uint32_t reg0, uint32_t reg1,
167 uint32_t ref, uint32_t mask);
168 void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
169 /* priority functions */
170 void (*set_priority) (struct amdgpu_ring *ring,
171 enum drm_sched_priority priority);
172 /* Try to soft recover the ring to make the fence signal */
173 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
174};
175
176struct amdgpu_ring {
177 struct amdgpu_device *adev;
178 const struct amdgpu_ring_funcs *funcs;
179 struct amdgpu_fence_driver fence_drv;
180 struct drm_gpu_scheduler sched;
181
182 struct amdgpu_bo *ring_obj;
183 volatile uint32_t *ring;
184 unsigned rptr_offs;
185 u64 wptr;
186 u64 wptr_old;
187 unsigned ring_size;
188 unsigned max_dw;
189 int count_dw;
190 uint64_t gpu_addr;
191 uint64_t ptr_mask;
192 uint32_t buf_mask;
193 u32 idx;
194 u32 me;
195 u32 pipe;
196 u32 queue;
197 struct amdgpu_bo *mqd_obj;
198 uint64_t mqd_gpu_addr;
199 void *mqd_ptr;
200 uint64_t eop_gpu_addr;
201 u32 doorbell_index;
202 bool use_doorbell;
203 bool use_pollmem;
204 unsigned wptr_offs;
205 unsigned fence_offs;
206 uint64_t current_ctx;
207 char name[16];
208 unsigned cond_exe_offs;
209 u64 cond_exe_gpu_addr;
210 volatile u32 *cond_exe_cpu_addr;
211 unsigned vm_inv_eng;
212 struct dma_fence *vmid_wait;
213 bool has_compute_vm_bug;
214
215 atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX];
216 struct mutex priority_mutex;
217 /* protected by priority_mutex */
218 int priority;
219
220#if defined(CONFIG_DEBUG_FS)
221 struct dentry *ent;
222#endif
223};
224
225#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
226#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
227#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
228#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
229#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
230#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
231#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
232#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
233#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
234#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
235#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
236#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
237#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
238#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
239#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
240#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
241#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
242#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
243#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
244#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
245#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
246#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
247#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
248
249int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
250void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
251void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
252void amdgpu_ring_commit(struct amdgpu_ring *ring);
253void amdgpu_ring_undo(struct amdgpu_ring *ring);
254void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
255 enum drm_sched_priority priority);
256void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
257 enum drm_sched_priority priority);
258int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
259 unsigned ring_size, struct amdgpu_irq_src *irq_src,
260 unsigned irq_type);
261void amdgpu_ring_fini(struct amdgpu_ring *ring);
262void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
263 uint32_t reg0, uint32_t val0,
264 uint32_t reg1, uint32_t val1);
265bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
266 struct dma_fence *fence);
267
268static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
269{
270 int i = 0;
271 while (i <= ring->buf_mask)
272 ring->ring[i++] = ring->funcs->nop;
273
274}
275
276static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
277{
278 if (ring->count_dw <= 0)
279 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
280 ring->ring[ring->wptr++ & ring->buf_mask] = v;
281 ring->wptr &= ring->ptr_mask;
282 ring->count_dw--;
283}
284
285static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
286 void *src, int count_dw)
287{
288 unsigned occupied, chunk1, chunk2;
289 void *dst;
290
291 if (unlikely(ring->count_dw < count_dw))
292 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
293
294 occupied = ring->wptr & ring->buf_mask;
295 dst = (void *)&ring->ring[occupied];
296 chunk1 = ring->buf_mask + 1 - occupied;
297 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
298 chunk2 = count_dw - chunk1;
299 chunk1 <<= 2;
300 chunk2 <<= 2;
301
302 if (chunk1)
303 memcpy(dst, src, chunk1);
304
305 if (chunk2) {
306 src += chunk1;
307 dst = (void *)ring->ring;
308 memcpy(dst, src, chunk2);
309 }
310
311 ring->wptr += count_dw;
312 ring->wptr &= ring->ptr_mask;
313 ring->count_dw -= count_dw;
314}
315
316int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
317
318#endif
319