1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_BIOS_PARSER_TYPES_H__
27
28#define __DAL_BIOS_PARSER_TYPES_H__
29
30#include "dm_services.h"
31#include "include/signal_types.h"
32#include "include/grph_object_ctrl_defs.h"
33#include "include/gpio_types.h"
34#include "include/link_service_types.h"
35
36/* TODO: include signal_types.h and remove this enum */
37enum as_signal_type {
38 AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
39 AS_SIGNAL_TYPE_DVI,
40 AS_SIGNAL_TYPE_HDMI,
41 AS_SIGNAL_TYPE_LVDS,
42 AS_SIGNAL_TYPE_DISPLAY_PORT,
43 AS_SIGNAL_TYPE_GPU_PLL,
44 AS_SIGNAL_TYPE_XGMI,
45 AS_SIGNAL_TYPE_UNKNOWN
46};
47
48enum bp_result {
49 BP_RESULT_OK = 0, /* There was no error */
50 BP_RESULT_BADINPUT, /*Bad input parameter */
51 BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
52 BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
53 BP_RESULT_NORECORD, /* Record can't be found */
54 BP_RESULT_FAILURE
55};
56
57enum bp_encoder_control_action {
58 /* direct VBIOS translation! Just to simplify the translation */
59 ENCODER_CONTROL_DISABLE = 0,
60 ENCODER_CONTROL_ENABLE,
61 ENCODER_CONTROL_SETUP,
62 ENCODER_CONTROL_INIT
63};
64
65enum bp_transmitter_control_action {
66 /* direct VBIOS translation! Just to simplify the translation */
67 TRANSMITTER_CONTROL_DISABLE = 0,
68 TRANSMITTER_CONTROL_ENABLE,
69 TRANSMITTER_CONTROL_BACKLIGHT_OFF,
70 TRANSMITTER_CONTROL_BACKLIGHT_ON,
71 TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
72 TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
73 TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
74 TRANSMITTER_CONTROL_INIT,
75 TRANSMITTER_CONTROL_DEACTIVATE,
76 TRANSMITTER_CONTROL_ACTIAVATE,
77 TRANSMITTER_CONTROL_SETUP,
78 TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
79 /* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only
80 * (power up the panel)
81 */
82 TRANSMITTER_CONTROL_POWER_ON,
83 /* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only
84 * (power down the panel)
85 */
86 TRANSMITTER_CONTROL_POWER_OFF
87};
88
89enum bp_external_encoder_control_action {
90 EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
91 EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
92 EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
93 EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
94 EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
95 EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
96};
97
98enum bp_pipe_control_action {
99 ASIC_PIPE_DISABLE = 0,
100 ASIC_PIPE_ENABLE,
101 ASIC_PIPE_INIT
102};
103
104struct bp_encoder_control {
105 enum bp_encoder_control_action action;
106 enum engine_id engine_id;
107 enum transmitter transmitter;
108 enum signal_type signal;
109 enum dc_lane_count lanes_number;
110 enum dc_color_depth color_depth;
111 bool enable_dp_audio;
112 uint32_t pixel_clock; /* khz */
113};
114
115struct bp_external_encoder_control {
116 enum bp_external_encoder_control_action action;
117 enum engine_id engine_id;
118 enum dc_link_rate link_rate;
119 enum dc_lane_count lanes_number;
120 enum signal_type signal;
121 enum dc_color_depth color_depth;
122 bool coherent;
123 struct graphics_object_id encoder_id;
124 struct graphics_object_id connector_obj_id;
125 uint32_t pixel_clock; /* in KHz */
126};
127
128struct bp_crtc_source_select {
129 enum engine_id engine_id;
130 enum controller_id controller_id;
131 /* from GPU Tx aka asic_signal */
132 enum signal_type signal;
133 /* sink_signal may differ from asicSignal if Translator encoder */
134 enum signal_type sink_signal;
135 enum display_output_bit_depth display_output_bit_depth;
136 bool enable_dp_audio;
137};
138
139struct bp_transmitter_control {
140 enum bp_transmitter_control_action action;
141 enum engine_id engine_id;
142 enum transmitter transmitter; /* PhyId */
143 enum dc_lane_count lanes_number;
144 enum clock_source_id pll_id; /* needed for DCE 4.0 */
145 enum signal_type signal;
146 enum dc_color_depth color_depth; /* not used for DCE6.0 */
147 enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
148 struct graphics_object_id connector_obj_id;
149 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
150 * be pixel clock * deep_color_ratio (in KHz)
151 */
152 uint32_t pixel_clock;
153 uint32_t lane_select;
154 uint32_t lane_settings;
155 bool coherent;
156 bool multi_path;
157 bool single_pll_mode;
158};
159
160struct bp_hw_crtc_timing_parameters {
161 enum controller_id controller_id;
162 /* horizontal part */
163 uint32_t h_total;
164 uint32_t h_addressable;
165 uint32_t h_overscan_left;
166 uint32_t h_overscan_right;
167 uint32_t h_sync_start;
168 uint32_t h_sync_width;
169
170 /* vertical part */
171 uint32_t v_total;
172 uint32_t v_addressable;
173 uint32_t v_overscan_top;
174 uint32_t v_overscan_bottom;
175 uint32_t v_sync_start;
176 uint32_t v_sync_width;
177
178 struct timing_flags {
179 uint32_t INTERLACE:1;
180 uint32_t PIXEL_REPETITION:4;
181 uint32_t HSYNC_POSITIVE_POLARITY:1;
182 uint32_t VSYNC_POSITIVE_POLARITY:1;
183 uint32_t HORZ_COUNT_BY_TWO:1;
184 } flags;
185};
186
187struct bp_adjust_pixel_clock_parameters {
188 /* Input: Signal Type - to be converted to Encoder mode */
189 enum signal_type signal_type;
190 /* Input: Encoder object id */
191 struct graphics_object_id encoder_object_id;
192 /* Input: Pixel Clock (requested Pixel clock based on Video timing
193 * standard used) in KHz
194 */
195 uint32_t pixel_clock;
196 /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
197 uint32_t adjusted_pixel_clock;
198 /* Output: If non-zero, this refDiv value should be used to calculate
199 * other ppll params */
200 uint32_t reference_divider;
201 /* Output: If non-zero, this postDiv value should be used to calculate
202 * other ppll params */
203 uint32_t pixel_clock_post_divider;
204 /* Input: Enable spread spectrum */
205 bool ss_enable;
206};
207
208struct bp_pixel_clock_parameters {
209 enum controller_id controller_id; /* (Which CRTC uses this PLL) */
210 enum clock_source_id pll_id; /* Clock Source Id */
211 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
212 enum signal_type signal_type;
213 /* Adjusted Pixel Clock (after VBIOS exec table)
214 * that becomes Target Pixel Clock (100 Hz units) */
215 uint32_t target_pixel_clock_100hz;
216 /* Calculated Reference divider of Display PLL */
217 uint32_t reference_divider;
218 /* Calculated Feedback divider of Display PLL */
219 uint32_t feedback_divider;
220 /* Calculated Fractional Feedback divider of Display PLL */
221 uint32_t fractional_feedback_divider;
222 /* Calculated Pixel Clock Post divider of Display PLL */
223 uint32_t pixel_clock_post_divider;
224 struct graphics_object_id encoder_object_id; /* Encoder object id */
225 /* VBIOS returns a fixed display clock when DFS-bypass feature
226 * is enabled (KHz) */
227 uint32_t dfs_bypass_display_clock;
228 /* color depth to support HDMI deep color */
229 enum transmitter_color_depth color_depth;
230
231 struct program_pixel_clock_flags {
232 uint32_t FORCE_PROGRAMMING_OF_PLL:1;
233 /* Use Engine Clock as source for Display Clock when
234 * programming PLL */
235 uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
236 /* Use external reference clock (refDivSrc for PLL) */
237 uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
238 /* Use DFS bypass for Display clock. */
239 uint32_t SET_DISPCLK_DFS_BYPASS:1;
240 /* Force program PHY PLL only */
241 uint32_t PROGRAM_PHY_PLL_ONLY:1;
242 /* Support for YUV420 */
243 uint32_t SUPPORT_YUV_420:1;
244 /* Use XTALIN reference clock source */
245 uint32_t SET_XTALIN_REF_SRC:1;
246 /* Use GENLK reference clock source */
247 uint32_t SET_GENLOCK_REF_DIV_SRC:1;
248 } flags;
249};
250
251enum bp_dce_clock_type {
252 DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
253 DCECLOCK_TYPE_DPREFCLK = 1
254};
255
256/* DCE Clock Parameters structure for SetDceClock Exec command table */
257struct bp_set_dce_clock_parameters {
258 enum clock_source_id pll_id; /* Clock Source Id */
259 /* Display clock or DPREFCLK value */
260 uint32_t target_clock_frequency;
261 /* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */
262 enum bp_dce_clock_type clock_type;
263
264 struct set_dce_clock_flags {
265 uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
266 /* Use XTALIN reference clock source */
267 uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
268 /* Use PCIE reference clock source */
269 uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
270 /* Use GENLK reference clock source */
271 uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
272 } flags;
273};
274
275struct spread_spectrum_flags {
276 /* 1 = Center Spread; 0 = down spread */
277 uint32_t CENTER_SPREAD:1;
278 /* 1 = external; 0 = internal */
279 uint32_t EXTERNAL_SS:1;
280 /* 1 = delta-sigma type parameter; 0 = ver1 */
281 uint32_t DS_TYPE:1;
282};
283
284struct bp_spread_spectrum_parameters {
285 enum clock_source_id pll_id;
286 uint32_t percentage;
287 uint32_t ds_frac_amount;
288
289 union {
290 struct {
291 uint32_t step;
292 uint32_t delay;
293 uint32_t range; /* In Hz unit */
294 } ver1;
295 struct {
296 uint32_t feedback_amount;
297 uint32_t nfrac_amount;
298 uint32_t ds_frac_size;
299 } ds;
300 };
301
302 struct spread_spectrum_flags flags;
303};
304
305struct bp_encoder_cap_info {
306 uint32_t DP_HBR2_CAP:1;
307 uint32_t DP_HBR2_EN:1;
308 uint32_t DP_HBR3_EN:1;
309 uint32_t HDMI_6GB_EN:1;
310 uint32_t RESERVED:30;
311};
312
313#endif /*__DAL_BIOS_PARSER_TYPES_H__ */
314