1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
25 | */ |
26 | |
27 | #include <drm/drm_fixed.h> |
28 | #include <drm/drm_fourcc.h> |
29 | #include <drm/drm_framebuffer.h> |
30 | #include <drm/drm_modeset_helper_vtables.h> |
31 | #include <drm/drm_vblank.h> |
32 | #include <drm/radeon_drm.h> |
33 | |
34 | #include "atom.h" |
35 | #include "radeon.h" |
36 | |
37 | static void radeon_overscan_setup(struct drm_crtc *crtc, |
38 | struct drm_display_mode *mode) |
39 | { |
40 | struct drm_device *dev = crtc->dev; |
41 | struct radeon_device *rdev = dev->dev_private; |
42 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
43 | |
44 | WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); |
45 | WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); |
46 | WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); |
47 | } |
48 | |
49 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, |
50 | struct drm_display_mode *mode) |
51 | { |
52 | struct drm_device *dev = crtc->dev; |
53 | struct radeon_device *rdev = dev->dev_private; |
54 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
55 | int xres = mode->hdisplay; |
56 | int yres = mode->vdisplay; |
57 | bool hscale = true, vscale = true; |
58 | int hsync_wid; |
59 | int vsync_wid; |
60 | int hsync_start; |
61 | int blank_width; |
62 | u32 scale, inc, crtc_more_cntl; |
63 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; |
64 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; |
65 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; |
66 | struct drm_display_mode *native_mode = &radeon_crtc->native_mode; |
67 | |
68 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & |
69 | (RADEON_VERT_STRETCH_RESERVED | |
70 | RADEON_VERT_AUTO_RATIO_INC); |
71 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & |
72 | (RADEON_HORZ_FP_LOOP_STRETCH | |
73 | RADEON_HORZ_AUTO_RATIO_INC); |
74 | |
75 | crtc_more_cntl = 0; |
76 | if ((rdev->family == CHIP_RS100) || |
77 | (rdev->family == CHIP_RS200)) { |
78 | /* This is to workaround the asic bug for RMX, some versions |
79 | of BIOS dosen't have this register initialized correctly. */ |
80 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; |
81 | } |
82 | |
83 | |
84 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
85 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
86 | |
87 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
88 | if (!hsync_wid) |
89 | hsync_wid = 1; |
90 | hsync_start = mode->crtc_hsync_start - 8; |
91 | |
92 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) |
93 | | ((hsync_wid & 0x3f) << 16) |
94 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
95 | ? RADEON_CRTC_H_SYNC_POL |
96 | : 0)); |
97 | |
98 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
99 | | ((mode->crtc_vdisplay - 1) << 16)); |
100 | |
101 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
102 | if (!vsync_wid) |
103 | vsync_wid = 1; |
104 | |
105 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
106 | | ((vsync_wid & 0x1f) << 16) |
107 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
108 | ? RADEON_CRTC_V_SYNC_POL |
109 | : 0)); |
110 | |
111 | fp_horz_vert_active = 0; |
112 | |
113 | if (native_mode->hdisplay == 0 || |
114 | native_mode->vdisplay == 0) { |
115 | hscale = false; |
116 | vscale = false; |
117 | } else { |
118 | if (xres > native_mode->hdisplay) |
119 | xres = native_mode->hdisplay; |
120 | if (yres > native_mode->vdisplay) |
121 | yres = native_mode->vdisplay; |
122 | |
123 | if (xres == native_mode->hdisplay) |
124 | hscale = false; |
125 | if (yres == native_mode->vdisplay) |
126 | vscale = false; |
127 | } |
128 | |
129 | switch (radeon_crtc->rmx_type) { |
130 | case RMX_FULL: |
131 | case RMX_ASPECT: |
132 | if (!hscale) |
133 | fp_horz_stretch |= ((xres/8-1) << 16); |
134 | else { |
135 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; |
136 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) |
137 | / native_mode->hdisplay + 1; |
138 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | |
139 | RADEON_HORZ_STRETCH_BLEND | |
140 | RADEON_HORZ_STRETCH_ENABLE | |
141 | ((native_mode->hdisplay/8-1) << 16)); |
142 | } |
143 | |
144 | if (!vscale) |
145 | fp_vert_stretch |= ((yres-1) << 12); |
146 | else { |
147 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; |
148 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) |
149 | / native_mode->vdisplay + 1; |
150 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | |
151 | RADEON_VERT_STRETCH_ENABLE | |
152 | RADEON_VERT_STRETCH_BLEND | |
153 | ((native_mode->vdisplay-1) << 12)); |
154 | } |
155 | break; |
156 | case RMX_CENTER: |
157 | fp_horz_stretch |= ((xres/8-1) << 16); |
158 | fp_vert_stretch |= ((yres-1) << 12); |
159 | |
160 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | |
161 | RADEON_CRTC_AUTO_VERT_CENTER_EN); |
162 | |
163 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; |
164 | if (blank_width > 110) |
165 | blank_width = 110; |
166 | |
167 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) |
168 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
169 | |
170 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
171 | if (!hsync_wid) |
172 | hsync_wid = 1; |
173 | |
174 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) |
175 | | ((hsync_wid & 0x3f) << 16) |
176 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
177 | ? RADEON_CRTC_H_SYNC_POL |
178 | : 0)); |
179 | |
180 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) |
181 | | ((mode->crtc_vdisplay - 1) << 16)); |
182 | |
183 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
184 | if (!vsync_wid) |
185 | vsync_wid = 1; |
186 | |
187 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) |
188 | | ((vsync_wid & 0x1f) << 16) |
189 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
190 | ? RADEON_CRTC_V_SYNC_POL |
191 | : 0))); |
192 | |
193 | fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | |
194 | (((native_mode->hdisplay / 8) & 0x1ff) << 16)); |
195 | break; |
196 | case RMX_OFF: |
197 | default: |
198 | fp_horz_stretch |= ((xres/8-1) << 16); |
199 | fp_vert_stretch |= ((yres-1) << 12); |
200 | break; |
201 | } |
202 | |
203 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); |
204 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); |
205 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); |
206 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); |
207 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); |
208 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); |
209 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); |
210 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); |
211 | } |
212 | |
213 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
214 | { |
215 | struct radeon_device *rdev = dev->dev_private; |
216 | int i = 0; |
217 | |
218 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
219 | the cause yet, but this workaround will mask the problem for now. |
220 | Other chips usually will pass at the very first test, so the |
221 | workaround shouldn't have any effect on them. */ |
222 | for (i = 0; |
223 | (i < 10000 && |
224 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
225 | i++); |
226 | } |
227 | |
228 | static void radeon_pll_write_update(struct drm_device *dev) |
229 | { |
230 | struct radeon_device *rdev = dev->dev_private; |
231 | |
232 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
233 | |
234 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
235 | RADEON_PPLL_ATOMIC_UPDATE_W, |
236 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
237 | } |
238 | |
239 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
240 | { |
241 | struct radeon_device *rdev = dev->dev_private; |
242 | int i = 0; |
243 | |
244 | |
245 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
246 | the cause yet, but this workaround will mask the problem for now. |
247 | Other chips usually will pass at the very first test, so the |
248 | workaround shouldn't have any effect on them. */ |
249 | for (i = 0; |
250 | (i < 10000 && |
251 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
252 | i++); |
253 | } |
254 | |
255 | static void radeon_pll2_write_update(struct drm_device *dev) |
256 | { |
257 | struct radeon_device *rdev = dev->dev_private; |
258 | |
259 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
260 | |
261 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
262 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
263 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
264 | } |
265 | |
266 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
267 | uint16_t fb_div) |
268 | { |
269 | unsigned int vcoFreq; |
270 | |
271 | if (!ref_div) |
272 | return 1; |
273 | |
274 | vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; |
275 | |
276 | /* |
277 | * This is horribly crude: the VCO frequency range is divided into |
278 | * 3 parts, each part having a fixed PLL gain value. |
279 | */ |
280 | if (vcoFreq >= 30000) |
281 | /* |
282 | * [300..max] MHz : 7 |
283 | */ |
284 | return 7; |
285 | else if (vcoFreq >= 18000) |
286 | /* |
287 | * [180..300) MHz : 4 |
288 | */ |
289 | return 4; |
290 | else |
291 | /* |
292 | * [0..180) MHz : 1 |
293 | */ |
294 | return 1; |
295 | } |
296 | |
297 | static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
298 | { |
299 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
300 | struct drm_device *dev = crtc->dev; |
301 | struct radeon_device *rdev = dev->dev_private; |
302 | uint32_t crtc_ext_cntl = 0; |
303 | uint32_t mask; |
304 | |
305 | if (radeon_crtc->crtc_id) |
306 | mask = (RADEON_CRTC2_DISP_DIS | |
307 | RADEON_CRTC2_VSYNC_DIS | |
308 | RADEON_CRTC2_HSYNC_DIS | |
309 | RADEON_CRTC2_DISP_REQ_EN_B); |
310 | else |
311 | mask = (RADEON_CRTC_DISPLAY_DIS | |
312 | RADEON_CRTC_VSYNC_DIS | |
313 | RADEON_CRTC_HSYNC_DIS); |
314 | |
315 | /* |
316 | * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. |
317 | * Therefore it is set in the DAC DMPS function. |
318 | * This is different for GPU's with a single CRTC but a primary and a |
319 | * TV DAC: here it controls the single CRTC no matter where it is |
320 | * routed. Therefore we set it here. |
321 | */ |
322 | if (rdev->flags & RADEON_SINGLE_CRTC) |
323 | crtc_ext_cntl = RADEON_CRTC_CRT_ON; |
324 | |
325 | switch (mode) { |
326 | case DRM_MODE_DPMS_ON: |
327 | radeon_crtc->enabled = true; |
328 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
329 | radeon_pm_compute_clocks(rdev); |
330 | if (radeon_crtc->crtc_id) |
331 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); |
332 | else { |
333 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
334 | RADEON_CRTC_DISP_REQ_EN_B)); |
335 | WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); |
336 | } |
337 | if (dev->num_crtcs > radeon_crtc->crtc_id) |
338 | drm_crtc_vblank_on(crtc); |
339 | radeon_crtc_load_lut(crtc); |
340 | break; |
341 | case DRM_MODE_DPMS_STANDBY: |
342 | case DRM_MODE_DPMS_SUSPEND: |
343 | case DRM_MODE_DPMS_OFF: |
344 | if (dev->num_crtcs > radeon_crtc->crtc_id) |
345 | drm_crtc_vblank_off(crtc); |
346 | if (radeon_crtc->crtc_id) |
347 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); |
348 | else { |
349 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
350 | RADEON_CRTC_DISP_REQ_EN_B)); |
351 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); |
352 | } |
353 | radeon_crtc->enabled = false; |
354 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
355 | radeon_pm_compute_clocks(rdev); |
356 | break; |
357 | } |
358 | } |
359 | |
360 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
361 | struct drm_framebuffer *old_fb) |
362 | { |
363 | return radeon_crtc_do_set_base(crtc, fb: old_fb, x, y, atomic: 0); |
364 | } |
365 | |
366 | int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
367 | struct drm_framebuffer *fb, |
368 | int x, int y, enum mode_set_atomic state) |
369 | { |
370 | return radeon_crtc_do_set_base(crtc, fb, x, y, atomic: 1); |
371 | } |
372 | |
373 | int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
374 | struct drm_framebuffer *fb, |
375 | int x, int y, int atomic) |
376 | { |
377 | struct drm_device *dev = crtc->dev; |
378 | struct radeon_device *rdev = dev->dev_private; |
379 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
380 | struct drm_framebuffer *target_fb; |
381 | struct drm_gem_object *obj; |
382 | struct radeon_bo *rbo; |
383 | uint64_t base; |
384 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
385 | uint32_t crtc_pitch, pitch_pixels; |
386 | uint32_t tiling_flags; |
387 | int format; |
388 | uint32_t gen_cntl_reg, gen_cntl_val; |
389 | int r; |
390 | |
391 | DRM_DEBUG_KMS("\n" ); |
392 | /* no fb bound */ |
393 | if (!atomic && !crtc->primary->fb) { |
394 | DRM_DEBUG_KMS("No FB bound\n" ); |
395 | return 0; |
396 | } |
397 | |
398 | if (atomic) |
399 | target_fb = fb; |
400 | else |
401 | target_fb = crtc->primary->fb; |
402 | |
403 | switch (target_fb->format->cpp[0] * 8) { |
404 | case 8: |
405 | format = 2; |
406 | break; |
407 | case 15: /* 555 */ |
408 | format = 3; |
409 | break; |
410 | case 16: /* 565 */ |
411 | format = 4; |
412 | break; |
413 | case 24: /* RGB */ |
414 | format = 5; |
415 | break; |
416 | case 32: /* xRGB */ |
417 | format = 6; |
418 | break; |
419 | default: |
420 | return false; |
421 | } |
422 | |
423 | /* Pin framebuffer & get tilling informations */ |
424 | obj = target_fb->obj[0]; |
425 | rbo = gem_to_radeon_bo(obj); |
426 | retry: |
427 | r = radeon_bo_reserve(bo: rbo, no_intr: false); |
428 | if (unlikely(r != 0)) |
429 | return r; |
430 | /* Only 27 bit offset for legacy CRTC */ |
431 | r = radeon_bo_pin_restricted(bo: rbo, RADEON_GEM_DOMAIN_VRAM, max_offset: 1 << 27, |
432 | gpu_addr: &base); |
433 | if (unlikely(r != 0)) { |
434 | radeon_bo_unreserve(bo: rbo); |
435 | |
436 | /* On old GPU like RN50 with little vram pining can fails because |
437 | * current fb is taking all space needed. So instead of unpining |
438 | * the old buffer after pining the new one, first unpin old one |
439 | * and then retry pining new one. |
440 | * |
441 | * As only master can set mode only master can pin and it is |
442 | * unlikely the master client will race with itself especialy |
443 | * on those old gpu with single crtc. |
444 | * |
445 | * We don't shutdown the display controller because new buffer |
446 | * will end up in same spot. |
447 | */ |
448 | if (!atomic && fb && fb != crtc->primary->fb) { |
449 | struct radeon_bo *old_rbo; |
450 | unsigned long nsize, osize; |
451 | |
452 | old_rbo = gem_to_radeon_bo(fb->obj[0]); |
453 | osize = radeon_bo_size(bo: old_rbo); |
454 | nsize = radeon_bo_size(bo: rbo); |
455 | if (nsize <= osize && !radeon_bo_reserve(bo: old_rbo, no_intr: false)) { |
456 | radeon_bo_unpin(bo: old_rbo); |
457 | radeon_bo_unreserve(bo: old_rbo); |
458 | fb = NULL; |
459 | goto retry; |
460 | } |
461 | } |
462 | return -EINVAL; |
463 | } |
464 | radeon_bo_get_tiling_flags(bo: rbo, tiling_flags: &tiling_flags, NULL); |
465 | radeon_bo_unreserve(bo: rbo); |
466 | if (tiling_flags & RADEON_TILING_MICRO) |
467 | DRM_ERROR("trying to scanout microtiled buffer\n" ); |
468 | |
469 | /* if scanout was in GTT this really wouldn't work */ |
470 | /* crtc offset is from display base addr not FB location */ |
471 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; |
472 | |
473 | base -= radeon_crtc->legacy_display_base_addr; |
474 | |
475 | crtc_offset_cntl = 0; |
476 | |
477 | pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; |
478 | crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8, |
479 | target_fb->format->cpp[0] * 8 * 8); |
480 | crtc_pitch |= crtc_pitch << 16; |
481 | |
482 | crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; |
483 | if (tiling_flags & RADEON_TILING_MACRO) { |
484 | if (ASIC_IS_R300(rdev)) |
485 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
486 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
487 | R300_CRTC_MACRO_TILE_EN); |
488 | else |
489 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
490 | } else { |
491 | if (ASIC_IS_R300(rdev)) |
492 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
493 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
494 | R300_CRTC_MACRO_TILE_EN); |
495 | else |
496 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
497 | } |
498 | |
499 | if (tiling_flags & RADEON_TILING_MACRO) { |
500 | if (ASIC_IS_R300(rdev)) { |
501 | crtc_tile_x0_y0 = x | (y << 16); |
502 | base &= ~0x7ff; |
503 | } else { |
504 | int byteshift = target_fb->format->cpp[0] * 8 >> 4; |
505 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
506 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
507 | crtc_offset_cntl |= (y % 16); |
508 | } |
509 | } else { |
510 | int offset = y * pitch_pixels + x; |
511 | switch (target_fb->format->cpp[0] * 8) { |
512 | case 8: |
513 | offset *= 1; |
514 | break; |
515 | case 15: |
516 | case 16: |
517 | offset *= 2; |
518 | break; |
519 | case 24: |
520 | offset *= 3; |
521 | break; |
522 | case 32: |
523 | offset *= 4; |
524 | break; |
525 | default: |
526 | return false; |
527 | } |
528 | base += offset; |
529 | } |
530 | |
531 | base &= ~7; |
532 | |
533 | if (radeon_crtc->crtc_id == 1) |
534 | gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; |
535 | else |
536 | gen_cntl_reg = RADEON_CRTC_GEN_CNTL; |
537 | |
538 | gen_cntl_val = RREG32(gen_cntl_reg); |
539 | gen_cntl_val &= ~(0xf << 8); |
540 | gen_cntl_val |= (format << 8); |
541 | gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; |
542 | WREG32(gen_cntl_reg, gen_cntl_val); |
543 | |
544 | crtc_offset = (u32)base; |
545 | |
546 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
547 | |
548 | if (ASIC_IS_R300(rdev)) { |
549 | if (radeon_crtc->crtc_id) |
550 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
551 | else |
552 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
553 | } |
554 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
555 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
556 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
557 | |
558 | if (!atomic && fb && fb != crtc->primary->fb) { |
559 | rbo = gem_to_radeon_bo(fb->obj[0]); |
560 | r = radeon_bo_reserve(bo: rbo, no_intr: false); |
561 | if (unlikely(r != 0)) |
562 | return r; |
563 | radeon_bo_unpin(bo: rbo); |
564 | radeon_bo_unreserve(bo: rbo); |
565 | } |
566 | |
567 | /* Bytes per pixel may have changed */ |
568 | radeon_bandwidth_update(rdev); |
569 | |
570 | return 0; |
571 | } |
572 | |
573 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
574 | { |
575 | struct drm_device *dev = crtc->dev; |
576 | struct radeon_device *rdev = dev->dev_private; |
577 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
578 | const struct drm_framebuffer *fb = crtc->primary->fb; |
579 | struct drm_encoder *encoder; |
580 | int format; |
581 | int hsync_start; |
582 | int hsync_wid; |
583 | int vsync_wid; |
584 | uint32_t crtc_h_total_disp; |
585 | uint32_t crtc_h_sync_strt_wid; |
586 | uint32_t crtc_v_total_disp; |
587 | uint32_t crtc_v_sync_strt_wid; |
588 | bool is_tv = false; |
589 | |
590 | DRM_DEBUG_KMS("\n" ); |
591 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
592 | if (encoder->crtc == crtc) { |
593 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
594 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
595 | is_tv = true; |
596 | DRM_INFO("crtc %d is connected to a TV\n" , radeon_crtc->crtc_id); |
597 | break; |
598 | } |
599 | } |
600 | } |
601 | |
602 | switch (fb->format->cpp[0] * 8) { |
603 | case 8: |
604 | format = 2; |
605 | break; |
606 | case 15: /* 555 */ |
607 | format = 3; |
608 | break; |
609 | case 16: /* 565 */ |
610 | format = 4; |
611 | break; |
612 | case 24: /* RGB */ |
613 | format = 5; |
614 | break; |
615 | case 32: /* xRGB */ |
616 | format = 6; |
617 | break; |
618 | default: |
619 | return false; |
620 | } |
621 | |
622 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
623 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
624 | |
625 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
626 | if (!hsync_wid) |
627 | hsync_wid = 1; |
628 | hsync_start = mode->crtc_hsync_start - 8; |
629 | |
630 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
631 | | ((hsync_wid & 0x3f) << 16) |
632 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
633 | ? RADEON_CRTC_H_SYNC_POL |
634 | : 0)); |
635 | |
636 | /* This works for double scan mode. */ |
637 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
638 | | ((mode->crtc_vdisplay - 1) << 16)); |
639 | |
640 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
641 | if (!vsync_wid) |
642 | vsync_wid = 1; |
643 | |
644 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
645 | | ((vsync_wid & 0x1f) << 16) |
646 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
647 | ? RADEON_CRTC_V_SYNC_POL |
648 | : 0)); |
649 | |
650 | if (radeon_crtc->crtc_id) { |
651 | uint32_t crtc2_gen_cntl; |
652 | uint32_t disp2_merge_cntl; |
653 | |
654 | /* if TV DAC is enabled for another crtc and keep it enabled */ |
655 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; |
656 | crtc2_gen_cntl |= ((format << 8) |
657 | | RADEON_CRTC2_VSYNC_DIS |
658 | | RADEON_CRTC2_HSYNC_DIS |
659 | | RADEON_CRTC2_DISP_DIS |
660 | | RADEON_CRTC2_DISP_REQ_EN_B |
661 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
662 | ? RADEON_CRTC2_DBL_SCAN_EN |
663 | : 0) |
664 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
665 | ? RADEON_CRTC2_CSYNC_EN |
666 | : 0) |
667 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
668 | ? RADEON_CRTC2_INTERLACE_EN |
669 | : 0)); |
670 | |
671 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
672 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
673 | crtc2_gen_cntl |= RADEON_CRTC2_EN; |
674 | |
675 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
676 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
677 | |
678 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
679 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
680 | |
681 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); |
682 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); |
683 | } else { |
684 | uint32_t crtc_gen_cntl; |
685 | uint32_t crtc_ext_cntl; |
686 | uint32_t disp_merge_cntl; |
687 | |
688 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; |
689 | crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN |
690 | | (format << 8) |
691 | | RADEON_CRTC_DISP_REQ_EN_B |
692 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
693 | ? RADEON_CRTC_DBL_SCAN_EN |
694 | : 0) |
695 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
696 | ? RADEON_CRTC_CSYNC_EN |
697 | : 0) |
698 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
699 | ? RADEON_CRTC_INTERLACE_EN |
700 | : 0)); |
701 | |
702 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
703 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
704 | crtc_gen_cntl |= RADEON_CRTC_EN; |
705 | |
706 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
707 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
708 | RADEON_CRTC_VSYNC_DIS | |
709 | RADEON_CRTC_HSYNC_DIS | |
710 | RADEON_CRTC_DISPLAY_DIS); |
711 | |
712 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
713 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
714 | |
715 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
716 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
717 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
718 | } |
719 | |
720 | if (is_tv) |
721 | radeon_legacy_tv_adjust_crtc_reg(encoder, h_total_disp: &crtc_h_total_disp, |
722 | h_sync_strt_wid: &crtc_h_sync_strt_wid, v_total_disp: &crtc_v_total_disp, |
723 | v_sync_strt_wid: &crtc_v_sync_strt_wid); |
724 | |
725 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
726 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
727 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
728 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
729 | |
730 | return true; |
731 | } |
732 | |
733 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
734 | { |
735 | struct drm_device *dev = crtc->dev; |
736 | struct radeon_device *rdev = dev->dev_private; |
737 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
738 | struct drm_encoder *encoder; |
739 | uint32_t feedback_div = 0; |
740 | uint32_t frac_fb_div = 0; |
741 | uint32_t reference_div = 0; |
742 | uint32_t post_divider = 0; |
743 | uint32_t freq = 0; |
744 | uint8_t pll_gain; |
745 | bool use_bios_divs = false; |
746 | /* PLL registers */ |
747 | uint32_t pll_ref_div = 0; |
748 | uint32_t pll_fb_post_div = 0; |
749 | uint32_t htotal_cntl = 0; |
750 | bool is_tv = false; |
751 | struct radeon_pll *pll; |
752 | |
753 | struct { |
754 | int divider; |
755 | int bitvalue; |
756 | } *post_div, post_divs[] = { |
757 | /* From RAGE 128 VR/RAGE 128 GL Register |
758 | * Reference Manual (Technical Reference |
759 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
760 | * 3-17 (PLL_DIV_[3:0]). |
761 | */ |
762 | { 1, 0 }, /* VCLK_SRC */ |
763 | { 2, 1 }, /* VCLK_SRC/2 */ |
764 | { 4, 2 }, /* VCLK_SRC/4 */ |
765 | { 8, 3 }, /* VCLK_SRC/8 */ |
766 | { 3, 4 }, /* VCLK_SRC/3 */ |
767 | { 16, 5 }, /* VCLK_SRC/16 */ |
768 | { 6, 6 }, /* VCLK_SRC/6 */ |
769 | { 12, 7 }, /* VCLK_SRC/12 */ |
770 | { 0, 0 } |
771 | }; |
772 | |
773 | if (radeon_crtc->crtc_id) |
774 | pll = &rdev->clock.p2pll; |
775 | else |
776 | pll = &rdev->clock.p1pll; |
777 | |
778 | pll->flags = RADEON_PLL_LEGACY; |
779 | |
780 | if (mode->clock > 200000) /* range limits??? */ |
781 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
782 | else |
783 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
784 | |
785 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
786 | if (encoder->crtc == crtc) { |
787 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
788 | |
789 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
790 | is_tv = true; |
791 | break; |
792 | } |
793 | |
794 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
795 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
796 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
797 | if (!rdev->is_atom_bios) { |
798 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
799 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
800 | if (lvds) { |
801 | if (lvds->use_bios_dividers) { |
802 | pll_ref_div = lvds->panel_ref_divider; |
803 | pll_fb_post_div = (lvds->panel_fb_divider | |
804 | (lvds->panel_post_divider << 16)); |
805 | htotal_cntl = 0; |
806 | use_bios_divs = true; |
807 | } |
808 | } |
809 | } |
810 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
811 | } |
812 | } |
813 | } |
814 | |
815 | DRM_DEBUG_KMS("\n" ); |
816 | |
817 | if (!use_bios_divs) { |
818 | radeon_compute_pll_legacy(pll, freq: mode->clock, |
819 | dot_clock_p: &freq, fb_div_p: &feedback_div, frac_fb_div_p: &frac_fb_div, |
820 | ref_div_p: &reference_div, post_div_p: &post_divider); |
821 | |
822 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
823 | if (post_div->divider == post_divider) |
824 | break; |
825 | } |
826 | |
827 | if (!post_div->divider) |
828 | post_div = &post_divs[0]; |
829 | |
830 | DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n" , |
831 | (unsigned)freq, |
832 | feedback_div, |
833 | reference_div, |
834 | post_divider); |
835 | |
836 | pll_ref_div = reference_div; |
837 | #if defined(__powerpc__) && (0) /* TODO */ |
838 | /* apparently programming this otherwise causes a hang??? */ |
839 | if (info->MacModel == RADEON_MAC_IBOOK) |
840 | pll_fb_post_div = 0x000600ad; |
841 | else |
842 | #endif |
843 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
844 | |
845 | htotal_cntl = mode->htotal & 0x7; |
846 | |
847 | } |
848 | |
849 | pll_gain = radeon_compute_pll_gain(ref_freq: pll->reference_freq, |
850 | ref_div: pll_ref_div & 0x3ff, |
851 | fb_div: pll_fb_post_div & 0x7ff); |
852 | |
853 | if (radeon_crtc->crtc_id) { |
854 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
855 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
856 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
857 | |
858 | if (is_tv) { |
859 | radeon_legacy_tv_adjust_pll2(encoder, htotal2_cntl: &htotal_cntl, |
860 | p2pll_ref_div: &pll_ref_div, p2pll_div_0: &pll_fb_post_div, |
861 | pixclks_cntl: &pixclks_cntl); |
862 | } |
863 | |
864 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
865 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
866 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
867 | |
868 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
869 | RADEON_P2PLL_RESET |
870 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
871 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
872 | ~(RADEON_P2PLL_RESET |
873 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
874 | | RADEON_P2PLL_PVG_MASK)); |
875 | |
876 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
877 | pll_ref_div, |
878 | ~RADEON_P2PLL_REF_DIV_MASK); |
879 | |
880 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
881 | pll_fb_post_div, |
882 | ~RADEON_P2PLL_FB0_DIV_MASK); |
883 | |
884 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
885 | pll_fb_post_div, |
886 | ~RADEON_P2PLL_POST0_DIV_MASK); |
887 | |
888 | radeon_pll2_write_update(dev); |
889 | radeon_pll2_wait_for_read_update_complete(dev); |
890 | |
891 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
892 | |
893 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
894 | 0, |
895 | ~(RADEON_P2PLL_RESET |
896 | | RADEON_P2PLL_SLEEP |
897 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
898 | |
899 | DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n" , |
900 | (unsigned)pll_ref_div, |
901 | (unsigned)pll_fb_post_div, |
902 | (unsigned)htotal_cntl, |
903 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
904 | DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n" , |
905 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
906 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
907 | (unsigned)((pll_fb_post_div & |
908 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
909 | |
910 | mdelay(50); /* Let the clock to lock */ |
911 | |
912 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
913 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
914 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
915 | |
916 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
917 | } else { |
918 | uint32_t pixclks_cntl; |
919 | |
920 | |
921 | if (is_tv) { |
922 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
923 | radeon_legacy_tv_adjust_pll1(encoder, htotal_cntl: &htotal_cntl, ppll_ref_div: &pll_ref_div, |
924 | ppll_div_3: &pll_fb_post_div, pixclks_cntl: &pixclks_cntl); |
925 | } |
926 | |
927 | if (rdev->flags & RADEON_IS_MOBILITY) { |
928 | /* A temporal workaround for the occasional blanking on certain laptop panels. |
929 | This appears to related to the PLL divider registers (fail to lock?). |
930 | It occurs even when all dividers are the same with their old settings. |
931 | In this case we really don't need to fiddle with PLL registers. |
932 | By doing this we can avoid the blanking problem with some panels. |
933 | */ |
934 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
935 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
936 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
937 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
938 | RADEON_PLL_DIV_SEL, |
939 | ~(RADEON_PLL_DIV_SEL)); |
940 | r100_pll_errata_after_index(rdev); |
941 | return; |
942 | } |
943 | } |
944 | |
945 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
946 | RADEON_VCLK_SRC_SEL_CPUCLK, |
947 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
948 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
949 | RADEON_PPLL_RESET |
950 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
951 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
952 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
953 | ~(RADEON_PPLL_RESET |
954 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
955 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
956 | | RADEON_PPLL_PVG_MASK)); |
957 | |
958 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
959 | RADEON_PLL_DIV_SEL, |
960 | ~(RADEON_PLL_DIV_SEL)); |
961 | r100_pll_errata_after_index(rdev); |
962 | |
963 | if (ASIC_IS_R300(rdev) || |
964 | (rdev->family == CHIP_RS300) || |
965 | (rdev->family == CHIP_RS400) || |
966 | (rdev->family == CHIP_RS480)) { |
967 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
968 | /* When restoring console mode, use saved PPLL_REF_DIV |
969 | * setting. |
970 | */ |
971 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
972 | pll_ref_div, |
973 | 0); |
974 | } else { |
975 | /* R300 uses ref_div_acc field as real ref divider */ |
976 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
977 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
978 | ~R300_PPLL_REF_DIV_ACC_MASK); |
979 | } |
980 | } else |
981 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
982 | pll_ref_div, |
983 | ~RADEON_PPLL_REF_DIV_MASK); |
984 | |
985 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
986 | pll_fb_post_div, |
987 | ~RADEON_PPLL_FB3_DIV_MASK); |
988 | |
989 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
990 | pll_fb_post_div, |
991 | ~RADEON_PPLL_POST3_DIV_MASK); |
992 | |
993 | radeon_pll_write_update(dev); |
994 | radeon_pll_wait_for_read_update_complete(dev); |
995 | |
996 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
997 | |
998 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
999 | 0, |
1000 | ~(RADEON_PPLL_RESET |
1001 | | RADEON_PPLL_SLEEP |
1002 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
1003 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
1004 | |
1005 | DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n" , |
1006 | pll_ref_div, |
1007 | pll_fb_post_div, |
1008 | (unsigned)htotal_cntl, |
1009 | RREG32_PLL(RADEON_PPLL_CNTL)); |
1010 | DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n" , |
1011 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
1012 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
1013 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
1014 | |
1015 | mdelay(50); /* Let the clock to lock */ |
1016 | |
1017 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
1018 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
1019 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
1020 | |
1021 | if (is_tv) |
1022 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
1023 | } |
1024 | } |
1025 | |
1026 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
1027 | const struct drm_display_mode *mode, |
1028 | struct drm_display_mode *adjusted_mode) |
1029 | { |
1030 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1031 | return false; |
1032 | return true; |
1033 | } |
1034 | |
1035 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
1036 | struct drm_display_mode *mode, |
1037 | struct drm_display_mode *adjusted_mode, |
1038 | int x, int y, struct drm_framebuffer *old_fb) |
1039 | { |
1040 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1041 | |
1042 | /* TODO TV */ |
1043 | radeon_crtc_set_base(crtc, x, y, old_fb); |
1044 | radeon_set_crtc_timing(crtc, mode: adjusted_mode); |
1045 | radeon_set_pll(crtc, mode: adjusted_mode); |
1046 | radeon_overscan_setup(crtc, mode: adjusted_mode); |
1047 | if (radeon_crtc->crtc_id == 0) { |
1048 | radeon_legacy_rmx_mode_set(crtc, mode: adjusted_mode); |
1049 | } else { |
1050 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1051 | /* FIXME: only first crtc has rmx what should we |
1052 | * do ? |
1053 | */ |
1054 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n" ); |
1055 | } |
1056 | } |
1057 | radeon_cursor_reset(crtc); |
1058 | return 0; |
1059 | } |
1060 | |
1061 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
1062 | { |
1063 | struct drm_device *dev = crtc->dev; |
1064 | struct drm_crtc *crtci; |
1065 | |
1066 | /* |
1067 | * The hardware wedges sometimes if you reconfigure one CRTC |
1068 | * whilst another is running (see fdo bug #24611). |
1069 | */ |
1070 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) |
1071 | radeon_crtc_dpms(crtc: crtci, DRM_MODE_DPMS_OFF); |
1072 | } |
1073 | |
1074 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
1075 | { |
1076 | struct drm_device *dev = crtc->dev; |
1077 | struct drm_crtc *crtci; |
1078 | |
1079 | /* |
1080 | * Reenable the CRTCs that should be running. |
1081 | */ |
1082 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { |
1083 | if (crtci->enabled) |
1084 | radeon_crtc_dpms(crtc: crtci, DRM_MODE_DPMS_ON); |
1085 | } |
1086 | } |
1087 | |
1088 | static void radeon_crtc_disable(struct drm_crtc *crtc) |
1089 | { |
1090 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1091 | if (crtc->primary->fb) { |
1092 | int r; |
1093 | struct radeon_bo *rbo; |
1094 | |
1095 | rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); |
1096 | r = radeon_bo_reserve(bo: rbo, no_intr: false); |
1097 | if (unlikely(r)) |
1098 | DRM_ERROR("failed to reserve rbo before unpin\n" ); |
1099 | else { |
1100 | radeon_bo_unpin(bo: rbo); |
1101 | radeon_bo_unreserve(bo: rbo); |
1102 | } |
1103 | } |
1104 | } |
1105 | |
1106 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
1107 | .dpms = radeon_crtc_dpms, |
1108 | .mode_fixup = radeon_crtc_mode_fixup, |
1109 | .mode_set = radeon_crtc_mode_set, |
1110 | .mode_set_base = radeon_crtc_set_base, |
1111 | .mode_set_base_atomic = radeon_crtc_set_base_atomic, |
1112 | .prepare = radeon_crtc_prepare, |
1113 | .commit = radeon_crtc_commit, |
1114 | .disable = radeon_crtc_disable, |
1115 | .get_scanout_position = radeon_get_crtc_scanout_position, |
1116 | }; |
1117 | |
1118 | |
1119 | void radeon_legacy_init_crtc(struct drm_device *dev, |
1120 | struct radeon_crtc *radeon_crtc) |
1121 | { |
1122 | if (radeon_crtc->crtc_id == 1) |
1123 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
1124 | drm_crtc_helper_add(crtc: &radeon_crtc->base, funcs: &legacy_helper_funcs); |
1125 | } |
1126 | |