1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
2 | /************************************************************************** |
3 | * |
4 | * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the |
8 | * "Software"), to deal in the Software without restriction, including |
9 | * without limitation the rights to use, copy, modify, merge, publish, |
10 | * distribute, sub license, and/or sell copies of the Software, and to |
11 | * permit persons to whom the Software is furnished to do so, subject to |
12 | * the following conditions: |
13 | * |
14 | * The above copyright notice and this permission notice (including the |
15 | * next paragraph) shall be included in all copies or substantial portions |
16 | * of the Software. |
17 | * |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
25 | * |
26 | **************************************************************************/ |
27 | |
28 | |
29 | #include "vmwgfx_drv.h" |
30 | |
31 | #include "vmwgfx_bo.h" |
32 | #include "vmwgfx_binding.h" |
33 | #include "vmwgfx_devcaps.h" |
34 | #include "vmwgfx_mksstat.h" |
35 | #include "ttm_object.h" |
36 | |
37 | #include <drm/drm_aperture.h> |
38 | #include <drm/drm_drv.h> |
39 | #include <drm/drm_fbdev_generic.h> |
40 | #include <drm/drm_gem_ttm_helper.h> |
41 | #include <drm/drm_ioctl.h> |
42 | #include <drm/drm_module.h> |
43 | #include <drm/drm_sysfs.h> |
44 | #include <drm/ttm/ttm_range_manager.h> |
45 | #include <drm/ttm/ttm_placement.h> |
46 | #include <generated/utsrelease.h> |
47 | |
48 | #ifdef CONFIG_X86 |
49 | #include <asm/hypervisor.h> |
50 | #endif |
51 | #include <linux/cc_platform.h> |
52 | #include <linux/dma-mapping.h> |
53 | #include <linux/module.h> |
54 | #include <linux/pci.h> |
55 | #include <linux/version.h> |
56 | |
57 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" |
58 | |
59 | /* |
60 | * Fully encoded drm commands. Might move to vmw_drm.h |
61 | */ |
62 | |
63 | #define DRM_IOCTL_VMW_GET_PARAM \ |
64 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ |
65 | struct drm_vmw_getparam_arg) |
66 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ |
67 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ |
68 | union drm_vmw_alloc_dmabuf_arg) |
69 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ |
70 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ |
71 | struct drm_vmw_unref_dmabuf_arg) |
72 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ |
73 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ |
74 | struct drm_vmw_cursor_bypass_arg) |
75 | |
76 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ |
77 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ |
78 | struct drm_vmw_control_stream_arg) |
79 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ |
80 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ |
81 | struct drm_vmw_stream_arg) |
82 | #define DRM_IOCTL_VMW_UNREF_STREAM \ |
83 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ |
84 | struct drm_vmw_stream_arg) |
85 | |
86 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ |
87 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ |
88 | struct drm_vmw_context_arg) |
89 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ |
90 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ |
91 | struct drm_vmw_context_arg) |
92 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ |
93 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ |
94 | union drm_vmw_surface_create_arg) |
95 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ |
96 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ |
97 | struct drm_vmw_surface_arg) |
98 | #define DRM_IOCTL_VMW_REF_SURFACE \ |
99 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ |
100 | union drm_vmw_surface_reference_arg) |
101 | #define DRM_IOCTL_VMW_EXECBUF \ |
102 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ |
103 | struct drm_vmw_execbuf_arg) |
104 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
105 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ |
106 | struct drm_vmw_get_3d_cap_arg) |
107 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
108 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ |
109 | struct drm_vmw_fence_wait_arg) |
110 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
111 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ |
112 | struct drm_vmw_fence_signaled_arg) |
113 | #define DRM_IOCTL_VMW_FENCE_UNREF \ |
114 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ |
115 | struct drm_vmw_fence_arg) |
116 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
117 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ |
118 | struct drm_vmw_fence_event_arg) |
119 | #define DRM_IOCTL_VMW_PRESENT \ |
120 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ |
121 | struct drm_vmw_present_arg) |
122 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ |
123 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ |
124 | struct drm_vmw_present_readback_arg) |
125 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
126 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ |
127 | struct drm_vmw_update_layout_arg) |
128 | #define DRM_IOCTL_VMW_CREATE_SHADER \ |
129 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ |
130 | struct drm_vmw_shader_create_arg) |
131 | #define DRM_IOCTL_VMW_UNREF_SHADER \ |
132 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ |
133 | struct drm_vmw_shader_arg) |
134 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ |
135 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ |
136 | union drm_vmw_gb_surface_create_arg) |
137 | #define DRM_IOCTL_VMW_GB_SURFACE_REF \ |
138 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ |
139 | union drm_vmw_gb_surface_reference_arg) |
140 | #define DRM_IOCTL_VMW_SYNCCPU \ |
141 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ |
142 | struct drm_vmw_synccpu_arg) |
143 | #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ |
144 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ |
145 | struct drm_vmw_context_arg) |
146 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ |
147 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ |
148 | union drm_vmw_gb_surface_create_ext_arg) |
149 | #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ |
150 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ |
151 | union drm_vmw_gb_surface_reference_ext_arg) |
152 | #define DRM_IOCTL_VMW_MSG \ |
153 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ |
154 | struct drm_vmw_msg_arg) |
155 | #define DRM_IOCTL_VMW_MKSSTAT_RESET \ |
156 | DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) |
157 | #define DRM_IOCTL_VMW_MKSSTAT_ADD \ |
158 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ |
159 | struct drm_vmw_mksstat_add_arg) |
160 | #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ |
161 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ |
162 | struct drm_vmw_mksstat_remove_arg) |
163 | |
164 | /* |
165 | * Ioctl definitions. |
166 | */ |
167 | |
168 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
169 | DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, |
170 | DRM_RENDER_ALLOW), |
171 | DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, |
172 | DRM_RENDER_ALLOW), |
173 | DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, |
174 | DRM_RENDER_ALLOW), |
175 | DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, |
176 | vmw_kms_cursor_bypass_ioctl, |
177 | DRM_MASTER), |
178 | |
179 | DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
180 | DRM_MASTER), |
181 | DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
182 | DRM_MASTER), |
183 | DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
184 | DRM_MASTER), |
185 | |
186 | DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
187 | DRM_RENDER_ALLOW), |
188 | DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
189 | DRM_RENDER_ALLOW), |
190 | DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
191 | DRM_RENDER_ALLOW), |
192 | DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
193 | DRM_RENDER_ALLOW), |
194 | DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
195 | DRM_RENDER_ALLOW), |
196 | DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, |
197 | DRM_RENDER_ALLOW), |
198 | DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
199 | DRM_RENDER_ALLOW), |
200 | DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, |
201 | vmw_fence_obj_signaled_ioctl, |
202 | DRM_RENDER_ALLOW), |
203 | DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
204 | DRM_RENDER_ALLOW), |
205 | DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, |
206 | DRM_RENDER_ALLOW), |
207 | DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
208 | DRM_RENDER_ALLOW), |
209 | |
210 | /* these allow direct access to the framebuffers mark as master only */ |
211 | DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, |
212 | DRM_MASTER | DRM_AUTH), |
213 | DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, |
214 | vmw_present_readback_ioctl, |
215 | DRM_MASTER | DRM_AUTH), |
216 | /* |
217 | * The permissions of the below ioctl are overridden in |
218 | * vmw_generic_ioctl(). We require either |
219 | * DRM_MASTER or capable(CAP_SYS_ADMIN). |
220 | */ |
221 | DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, |
222 | vmw_kms_update_layout_ioctl, |
223 | DRM_RENDER_ALLOW), |
224 | DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, |
225 | vmw_shader_define_ioctl, |
226 | DRM_RENDER_ALLOW), |
227 | DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, |
228 | vmw_shader_destroy_ioctl, |
229 | DRM_RENDER_ALLOW), |
230 | DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, |
231 | vmw_gb_surface_define_ioctl, |
232 | DRM_RENDER_ALLOW), |
233 | DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, |
234 | vmw_gb_surface_reference_ioctl, |
235 | DRM_RENDER_ALLOW), |
236 | DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, |
237 | vmw_user_bo_synccpu_ioctl, |
238 | DRM_RENDER_ALLOW), |
239 | DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, |
240 | vmw_extended_context_define_ioctl, |
241 | DRM_RENDER_ALLOW), |
242 | DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, |
243 | vmw_gb_surface_define_ext_ioctl, |
244 | DRM_RENDER_ALLOW), |
245 | DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, |
246 | vmw_gb_surface_reference_ext_ioctl, |
247 | DRM_RENDER_ALLOW), |
248 | DRM_IOCTL_DEF_DRV(VMW_MSG, |
249 | vmw_msg_ioctl, |
250 | DRM_RENDER_ALLOW), |
251 | DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, |
252 | vmw_mksstat_reset_ioctl, |
253 | DRM_RENDER_ALLOW), |
254 | DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, |
255 | vmw_mksstat_add_ioctl, |
256 | DRM_RENDER_ALLOW), |
257 | DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, |
258 | vmw_mksstat_remove_ioctl, |
259 | DRM_RENDER_ALLOW), |
260 | }; |
261 | |
262 | static const struct pci_device_id vmw_pci_id_list[] = { |
263 | { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, |
264 | { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, |
265 | { } |
266 | }; |
267 | MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); |
268 | |
269 | static int vmw_restrict_iommu; |
270 | static int vmw_force_coherent; |
271 | static int vmw_restrict_dma_mask; |
272 | static int vmw_assume_16bpp; |
273 | |
274 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); |
275 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
276 | void *ptr); |
277 | |
278 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages" ); |
279 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); |
280 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages" ); |
281 | module_param_named(force_coherent, vmw_force_coherent, int, 0600); |
282 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU" ); |
283 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); |
284 | MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes" ); |
285 | module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); |
286 | |
287 | |
288 | struct bitmap_name { |
289 | uint32 value; |
290 | const char *name; |
291 | }; |
292 | |
293 | static const struct bitmap_name cap1_names[] = { |
294 | { SVGA_CAP_RECT_COPY, "rect copy" }, |
295 | { SVGA_CAP_CURSOR, "cursor" }, |
296 | { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, |
297 | { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, |
298 | { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, |
299 | { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, |
300 | { SVGA_CAP_3D, "3D" }, |
301 | { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, |
302 | { SVGA_CAP_MULTIMON, "multimon" }, |
303 | { SVGA_CAP_PITCHLOCK, "pitchlock" }, |
304 | { SVGA_CAP_IRQMASK, "irq mask" }, |
305 | { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, |
306 | { SVGA_CAP_GMR, "gmr" }, |
307 | { SVGA_CAP_TRACES, "traces" }, |
308 | { SVGA_CAP_GMR2, "gmr2" }, |
309 | { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, |
310 | { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, |
311 | { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, |
312 | { SVGA_CAP_GBOBJECTS, "gbobject" }, |
313 | { SVGA_CAP_DX, "dx" }, |
314 | { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, |
315 | { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, |
316 | { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, |
317 | }; |
318 | |
319 | |
320 | static const struct bitmap_name cap2_names[] = { |
321 | { SVGA_CAP2_GROW_OTABLE, "grow otable" }, |
322 | { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, |
323 | { SVGA_CAP2_DX2, "dx2" }, |
324 | { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, |
325 | { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, |
326 | { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, |
327 | { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, |
328 | { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, |
329 | { SVGA_CAP2_MSHINT, "mshint" }, |
330 | { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, |
331 | { SVGA_CAP2_DX3, "dx3" }, |
332 | { SVGA_CAP2_FRAME_TYPE, "frame type" }, |
333 | { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, |
334 | { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, |
335 | { SVGA_CAP2_EXTRA_REGS, "extra regs" }, |
336 | { SVGA_CAP2_LO_STAGING, "lo staging" }, |
337 | }; |
338 | |
339 | static void vmw_print_bitmap(struct drm_device *drm, |
340 | const char *prefix, uint32_t bitmap, |
341 | const struct bitmap_name *bnames, |
342 | uint32_t num_names) |
343 | { |
344 | char buf[512]; |
345 | uint32_t i; |
346 | uint32_t offset = 0; |
347 | for (i = 0; i < num_names; ++i) { |
348 | if ((bitmap & bnames[i].value) != 0) { |
349 | offset += snprintf(buf: buf + offset, |
350 | ARRAY_SIZE(buf) - offset, |
351 | fmt: "%s, " , bnames[i].name); |
352 | bitmap &= ~bnames[i].value; |
353 | } |
354 | } |
355 | |
356 | drm_info(drm, "%s: %s\n" , prefix, buf); |
357 | if (bitmap != 0) |
358 | drm_dbg(drm, "%s: unknown enums: %x\n" , prefix, bitmap); |
359 | } |
360 | |
361 | |
362 | static void vmw_print_sm_type(struct vmw_private *dev_priv) |
363 | { |
364 | static const char *names[] = { |
365 | [VMW_SM_LEGACY] = "Legacy" , |
366 | [VMW_SM_4] = "SM4" , |
367 | [VMW_SM_4_1] = "SM4_1" , |
368 | [VMW_SM_5] = "SM_5" , |
369 | [VMW_SM_5_1X] = "SM_5_1X" , |
370 | [VMW_SM_MAX] = "Invalid" |
371 | }; |
372 | BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); |
373 | drm_info(&dev_priv->drm, "Available shader model: %s.\n" , |
374 | names[dev_priv->sm_type]); |
375 | } |
376 | |
377 | /** |
378 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result |
379 | * |
380 | * @dev_priv: A device private structure. |
381 | * |
382 | * This function creates a small buffer object that holds the query |
383 | * result for dummy queries emitted as query barriers. |
384 | * The function will then map the first page and initialize a pending |
385 | * occlusion query result structure, Finally it will unmap the buffer. |
386 | * No interruptible waits are done within this function. |
387 | * |
388 | * Returns an error if bo creation or initialization fails. |
389 | */ |
390 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) |
391 | { |
392 | int ret; |
393 | struct vmw_bo *vbo; |
394 | struct ttm_bo_kmap_obj map; |
395 | volatile SVGA3dQueryResult *result; |
396 | bool dummy; |
397 | struct vmw_bo_params bo_params = { |
398 | .domain = VMW_BO_DOMAIN_SYS, |
399 | .busy_domain = VMW_BO_DOMAIN_SYS, |
400 | .bo_type = ttm_bo_type_kernel, |
401 | .size = PAGE_SIZE, |
402 | .pin = true |
403 | }; |
404 | |
405 | /* |
406 | * Create the vbo as pinned, so that a tryreserve will |
407 | * immediately succeed. This is because we're the only |
408 | * user of the bo currently. |
409 | */ |
410 | ret = vmw_bo_create(dev_priv, params: &bo_params, p_bo: &vbo); |
411 | if (unlikely(ret != 0)) |
412 | return ret; |
413 | |
414 | ret = ttm_bo_reserve(bo: &vbo->tbo, interruptible: false, no_wait: true, NULL); |
415 | BUG_ON(ret != 0); |
416 | vmw_bo_pin_reserved(bo: vbo, pin: true); |
417 | |
418 | ret = ttm_bo_kmap(bo: &vbo->tbo, start_page: 0, num_pages: 1, map: &map); |
419 | if (likely(ret == 0)) { |
420 | result = ttm_kmap_obj_virtual(map: &map, is_iomem: &dummy); |
421 | result->totalSize = sizeof(*result); |
422 | result->state = SVGA3D_QUERYSTATE_PENDING; |
423 | result->result32 = 0xff; |
424 | ttm_bo_kunmap(map: &map); |
425 | } |
426 | vmw_bo_pin_reserved(bo: vbo, pin: false); |
427 | ttm_bo_unreserve(bo: &vbo->tbo); |
428 | |
429 | if (unlikely(ret != 0)) { |
430 | DRM_ERROR("Dummy query buffer map failed.\n" ); |
431 | vmw_bo_unreference(buf: &vbo); |
432 | } else |
433 | dev_priv->dummy_query_bo = vbo; |
434 | |
435 | return ret; |
436 | } |
437 | |
438 | static int vmw_device_init(struct vmw_private *dev_priv) |
439 | { |
440 | bool uses_fb_traces = false; |
441 | |
442 | dev_priv->enable_state = vmw_read(dev_priv, offset: SVGA_REG_ENABLE); |
443 | dev_priv->config_done_state = vmw_read(dev_priv, offset: SVGA_REG_CONFIG_DONE); |
444 | dev_priv->traces_state = vmw_read(dev_priv, offset: SVGA_REG_TRACES); |
445 | |
446 | vmw_write(dev_priv, offset: SVGA_REG_ENABLE, value: SVGA_REG_ENABLE_ENABLE | |
447 | SVGA_REG_ENABLE_HIDE); |
448 | |
449 | uses_fb_traces = !vmw_cmd_supported(vmw: dev_priv) && |
450 | (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; |
451 | |
452 | vmw_write(dev_priv, offset: SVGA_REG_TRACES, value: uses_fb_traces); |
453 | dev_priv->fifo = vmw_fifo_create(dev_priv); |
454 | if (IS_ERR(ptr: dev_priv->fifo)) { |
455 | int err = PTR_ERR(ptr: dev_priv->fifo); |
456 | dev_priv->fifo = NULL; |
457 | return err; |
458 | } else if (!dev_priv->fifo) { |
459 | vmw_write(dev_priv, offset: SVGA_REG_CONFIG_DONE, value: 1); |
460 | } |
461 | |
462 | dev_priv->last_read_seqno = vmw_fence_read(dev_priv); |
463 | atomic_set(v: &dev_priv->marker_seq, i: dev_priv->last_read_seqno); |
464 | return 0; |
465 | } |
466 | |
467 | static void vmw_device_fini(struct vmw_private *vmw) |
468 | { |
469 | /* |
470 | * Legacy sync |
471 | */ |
472 | vmw_write(dev_priv: vmw, offset: SVGA_REG_SYNC, SVGA_SYNC_GENERIC); |
473 | while (vmw_read(dev_priv: vmw, offset: SVGA_REG_BUSY) != 0) |
474 | ; |
475 | |
476 | vmw->last_read_seqno = vmw_fence_read(dev_priv: vmw); |
477 | |
478 | vmw_write(dev_priv: vmw, offset: SVGA_REG_CONFIG_DONE, |
479 | value: vmw->config_done_state); |
480 | vmw_write(dev_priv: vmw, offset: SVGA_REG_ENABLE, |
481 | value: vmw->enable_state); |
482 | vmw_write(dev_priv: vmw, offset: SVGA_REG_TRACES, |
483 | value: vmw->traces_state); |
484 | |
485 | vmw_fifo_destroy(dev_priv: vmw); |
486 | } |
487 | |
488 | /** |
489 | * vmw_request_device_late - Perform late device setup |
490 | * |
491 | * @dev_priv: Pointer to device private. |
492 | * |
493 | * This function performs setup of otables and enables large command |
494 | * buffer submission. These tasks are split out to a separate function |
495 | * because it reverts vmw_release_device_early and is intended to be used |
496 | * by an error path in the hibernation code. |
497 | */ |
498 | static int vmw_request_device_late(struct vmw_private *dev_priv) |
499 | { |
500 | int ret; |
501 | |
502 | if (dev_priv->has_mob) { |
503 | ret = vmw_otables_setup(dev_priv); |
504 | if (unlikely(ret != 0)) { |
505 | DRM_ERROR("Unable to initialize " |
506 | "guest Memory OBjects.\n" ); |
507 | return ret; |
508 | } |
509 | } |
510 | |
511 | if (dev_priv->cman) { |
512 | ret = vmw_cmdbuf_set_pool_size(man: dev_priv->cman, size: 256*4096); |
513 | if (ret) { |
514 | struct vmw_cmdbuf_man *man = dev_priv->cman; |
515 | |
516 | dev_priv->cman = NULL; |
517 | vmw_cmdbuf_man_destroy(man); |
518 | } |
519 | } |
520 | |
521 | return 0; |
522 | } |
523 | |
524 | static int vmw_request_device(struct vmw_private *dev_priv) |
525 | { |
526 | int ret; |
527 | |
528 | ret = vmw_device_init(dev_priv); |
529 | if (unlikely(ret != 0)) { |
530 | DRM_ERROR("Unable to initialize the device.\n" ); |
531 | return ret; |
532 | } |
533 | vmw_fence_fifo_up(fman: dev_priv->fman); |
534 | dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); |
535 | if (IS_ERR(ptr: dev_priv->cman)) { |
536 | dev_priv->cman = NULL; |
537 | dev_priv->sm_type = VMW_SM_LEGACY; |
538 | } |
539 | |
540 | ret = vmw_request_device_late(dev_priv); |
541 | if (ret) |
542 | goto out_no_mob; |
543 | |
544 | ret = vmw_dummy_query_bo_create(dev_priv); |
545 | if (unlikely(ret != 0)) |
546 | goto out_no_query_bo; |
547 | |
548 | return 0; |
549 | |
550 | out_no_query_bo: |
551 | if (dev_priv->cman) |
552 | vmw_cmdbuf_remove_pool(man: dev_priv->cman); |
553 | if (dev_priv->has_mob) { |
554 | struct ttm_resource_manager *man; |
555 | |
556 | man = ttm_manager_type(bdev: &dev_priv->bdev, VMW_PL_MOB); |
557 | ttm_resource_manager_evict_all(bdev: &dev_priv->bdev, man); |
558 | vmw_otables_takedown(dev_priv); |
559 | } |
560 | if (dev_priv->cman) |
561 | vmw_cmdbuf_man_destroy(man: dev_priv->cman); |
562 | out_no_mob: |
563 | vmw_fence_fifo_down(fman: dev_priv->fman); |
564 | vmw_device_fini(vmw: dev_priv); |
565 | return ret; |
566 | } |
567 | |
568 | /** |
569 | * vmw_release_device_early - Early part of fifo takedown. |
570 | * |
571 | * @dev_priv: Pointer to device private struct. |
572 | * |
573 | * This is the first part of command submission takedown, to be called before |
574 | * buffer management is taken down. |
575 | */ |
576 | static void vmw_release_device_early(struct vmw_private *dev_priv) |
577 | { |
578 | /* |
579 | * Previous destructions should've released |
580 | * the pinned bo. |
581 | */ |
582 | |
583 | BUG_ON(dev_priv->pinned_bo != NULL); |
584 | |
585 | vmw_bo_unreference(buf: &dev_priv->dummy_query_bo); |
586 | if (dev_priv->cman) |
587 | vmw_cmdbuf_remove_pool(man: dev_priv->cman); |
588 | |
589 | if (dev_priv->has_mob) { |
590 | struct ttm_resource_manager *man; |
591 | |
592 | man = ttm_manager_type(bdev: &dev_priv->bdev, VMW_PL_MOB); |
593 | ttm_resource_manager_evict_all(bdev: &dev_priv->bdev, man); |
594 | vmw_otables_takedown(dev_priv); |
595 | } |
596 | } |
597 | |
598 | /** |
599 | * vmw_release_device_late - Late part of fifo takedown. |
600 | * |
601 | * @dev_priv: Pointer to device private struct. |
602 | * |
603 | * This is the last part of the command submission takedown, to be called when |
604 | * command submission is no longer needed. It may wait on pending fences. |
605 | */ |
606 | static void vmw_release_device_late(struct vmw_private *dev_priv) |
607 | { |
608 | vmw_fence_fifo_down(fman: dev_priv->fman); |
609 | if (dev_priv->cman) |
610 | vmw_cmdbuf_man_destroy(man: dev_priv->cman); |
611 | |
612 | vmw_device_fini(vmw: dev_priv); |
613 | } |
614 | |
615 | /* |
616 | * Sets the initial_[width|height] fields on the given vmw_private. |
617 | * |
618 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then |
619 | * clamping the value to fb_max_[width|height] fields and the |
620 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
621 | * If the values appear to be invalid, set them to |
622 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
623 | */ |
624 | static void vmw_get_initial_size(struct vmw_private *dev_priv) |
625 | { |
626 | uint32_t width; |
627 | uint32_t height; |
628 | |
629 | width = vmw_read(dev_priv, offset: SVGA_REG_WIDTH); |
630 | height = vmw_read(dev_priv, offset: SVGA_REG_HEIGHT); |
631 | |
632 | width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); |
633 | height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); |
634 | |
635 | if (width > dev_priv->fb_max_width || |
636 | height > dev_priv->fb_max_height) { |
637 | |
638 | /* |
639 | * This is a host error and shouldn't occur. |
640 | */ |
641 | |
642 | width = VMWGFX_MIN_INITIAL_WIDTH; |
643 | height = VMWGFX_MIN_INITIAL_HEIGHT; |
644 | } |
645 | |
646 | dev_priv->initial_width = width; |
647 | dev_priv->initial_height = height; |
648 | } |
649 | |
650 | /** |
651 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this |
652 | * system. |
653 | * |
654 | * @dev_priv: Pointer to a struct vmw_private |
655 | * |
656 | * This functions tries to determine what actions need to be taken by the |
657 | * driver to make system pages visible to the device. |
658 | * If this function decides that DMA is not possible, it returns -EINVAL. |
659 | * The driver may then try to disable features of the device that require |
660 | * DMA. |
661 | */ |
662 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) |
663 | { |
664 | static const char *names[vmw_dma_map_max] = { |
665 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages." , |
666 | [vmw_dma_map_populate] = "Caching DMA mappings." , |
667 | [vmw_dma_map_bind] = "Giving up DMA mappings early." }; |
668 | |
669 | /* |
670 | * When running with SEV we always want dma mappings, because |
671 | * otherwise ttm tt pool pages will bounce through swiotlb running |
672 | * out of available space. |
673 | */ |
674 | if (vmw_force_coherent || cc_platform_has(attr: CC_ATTR_MEM_ENCRYPT)) |
675 | dev_priv->map_mode = vmw_dma_alloc_coherent; |
676 | else if (vmw_restrict_iommu) |
677 | dev_priv->map_mode = vmw_dma_map_bind; |
678 | else |
679 | dev_priv->map_mode = vmw_dma_map_populate; |
680 | |
681 | drm_info(&dev_priv->drm, |
682 | "DMA map mode: %s\n" , names[dev_priv->map_mode]); |
683 | return 0; |
684 | } |
685 | |
686 | /** |
687 | * vmw_dma_masks - set required page- and dma masks |
688 | * |
689 | * @dev_priv: Pointer to struct drm-device |
690 | * |
691 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that |
692 | * restriction also for 64-bit systems. |
693 | */ |
694 | static int vmw_dma_masks(struct vmw_private *dev_priv) |
695 | { |
696 | struct drm_device *dev = &dev_priv->drm; |
697 | int ret = 0; |
698 | |
699 | ret = dma_set_mask_and_coherent(dev: dev->dev, DMA_BIT_MASK(64)); |
700 | if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { |
701 | drm_info(&dev_priv->drm, |
702 | "Restricting DMA addresses to 44 bits.\n" ); |
703 | return dma_set_mask_and_coherent(dev: dev->dev, DMA_BIT_MASK(44)); |
704 | } |
705 | |
706 | return ret; |
707 | } |
708 | |
709 | static int vmw_vram_manager_init(struct vmw_private *dev_priv) |
710 | { |
711 | int ret; |
712 | ret = ttm_range_man_init(bdev: &dev_priv->bdev, TTM_PL_VRAM, use_tt: false, |
713 | p_size: dev_priv->vram_size >> PAGE_SHIFT); |
714 | ttm_resource_manager_set_used(man: ttm_manager_type(bdev: &dev_priv->bdev, TTM_PL_VRAM), used: false); |
715 | return ret; |
716 | } |
717 | |
718 | static void vmw_vram_manager_fini(struct vmw_private *dev_priv) |
719 | { |
720 | ttm_range_man_fini(bdev: &dev_priv->bdev, TTM_PL_VRAM); |
721 | } |
722 | |
723 | static int vmw_setup_pci_resources(struct vmw_private *dev, |
724 | u32 pci_id) |
725 | { |
726 | resource_size_t rmmio_start; |
727 | resource_size_t rmmio_size; |
728 | resource_size_t fifo_start; |
729 | resource_size_t fifo_size; |
730 | int ret; |
731 | struct pci_dev *pdev = to_pci_dev(dev->drm.dev); |
732 | |
733 | pci_set_master(dev: pdev); |
734 | |
735 | ret = pci_request_regions(pdev, "vmwgfx probe" ); |
736 | if (ret) |
737 | return ret; |
738 | |
739 | dev->pci_id = pci_id; |
740 | if (pci_id == VMWGFX_PCI_ID_SVGA3) { |
741 | rmmio_start = pci_resource_start(pdev, 0); |
742 | rmmio_size = pci_resource_len(pdev, 0); |
743 | dev->vram_start = pci_resource_start(pdev, 2); |
744 | dev->vram_size = pci_resource_len(pdev, 2); |
745 | |
746 | drm_info(&dev->drm, |
747 | "Register MMIO at 0x%pa size is %llu kiB\n" , |
748 | &rmmio_start, (uint64_t)rmmio_size / 1024); |
749 | dev->rmmio = devm_ioremap(dev: dev->drm.dev, |
750 | offset: rmmio_start, |
751 | size: rmmio_size); |
752 | if (!dev->rmmio) { |
753 | drm_err(&dev->drm, |
754 | "Failed mapping registers mmio memory.\n" ); |
755 | pci_release_regions(pdev); |
756 | return -ENOMEM; |
757 | } |
758 | } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { |
759 | dev->io_start = pci_resource_start(pdev, 0); |
760 | dev->vram_start = pci_resource_start(pdev, 1); |
761 | dev->vram_size = pci_resource_len(pdev, 1); |
762 | fifo_start = pci_resource_start(pdev, 2); |
763 | fifo_size = pci_resource_len(pdev, 2); |
764 | |
765 | drm_info(&dev->drm, |
766 | "FIFO at %pa size is %llu kiB\n" , |
767 | &fifo_start, (uint64_t)fifo_size / 1024); |
768 | dev->fifo_mem = devm_memremap(dev: dev->drm.dev, |
769 | offset: fifo_start, |
770 | size: fifo_size, |
771 | flags: MEMREMAP_WB); |
772 | |
773 | if (IS_ERR(ptr: dev->fifo_mem)) { |
774 | drm_err(&dev->drm, |
775 | "Failed mapping FIFO memory.\n" ); |
776 | pci_release_regions(pdev); |
777 | return PTR_ERR(ptr: dev->fifo_mem); |
778 | } |
779 | } else { |
780 | pci_release_regions(pdev); |
781 | return -EINVAL; |
782 | } |
783 | |
784 | /* |
785 | * This is approximate size of the vram, the exact size will only |
786 | * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource |
787 | * size will be equal to or bigger than the size reported by |
788 | * SVGA_REG_VRAM_SIZE. |
789 | */ |
790 | drm_info(&dev->drm, |
791 | "VRAM at %pa size is %llu kiB\n" , |
792 | &dev->vram_start, (uint64_t)dev->vram_size / 1024); |
793 | |
794 | return 0; |
795 | } |
796 | |
797 | static int vmw_detect_version(struct vmw_private *dev) |
798 | { |
799 | uint32_t svga_id; |
800 | |
801 | vmw_write(dev_priv: dev, offset: SVGA_REG_ID, value: vmw_is_svga_v3(dev) ? |
802 | SVGA_ID_3 : SVGA_ID_2); |
803 | svga_id = vmw_read(dev_priv: dev, offset: SVGA_REG_ID); |
804 | if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { |
805 | drm_err(&dev->drm, |
806 | "Unsupported SVGA ID 0x%x on chipset 0x%x\n" , |
807 | svga_id, dev->pci_id); |
808 | return -ENOSYS; |
809 | } |
810 | BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); |
811 | drm_info(&dev->drm, |
812 | "Running on SVGA version %d.\n" , (svga_id & 0xff)); |
813 | return 0; |
814 | } |
815 | |
816 | static void vmw_write_driver_id(struct vmw_private *dev) |
817 | { |
818 | if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { |
819 | vmw_write(dev_priv: dev, offset: SVGA_REG_GUEST_DRIVER_ID, |
820 | value: SVGA_REG_GUEST_DRIVER_ID_LINUX); |
821 | |
822 | vmw_write(dev_priv: dev, offset: SVGA_REG_GUEST_DRIVER_VERSION1, |
823 | LINUX_VERSION_MAJOR << 24 | |
824 | LINUX_VERSION_PATCHLEVEL << 16 | |
825 | LINUX_VERSION_SUBLEVEL); |
826 | vmw_write(dev_priv: dev, offset: SVGA_REG_GUEST_DRIVER_VERSION2, |
827 | VMWGFX_DRIVER_MAJOR << 24 | |
828 | VMWGFX_DRIVER_MINOR << 16 | |
829 | VMWGFX_DRIVER_PATCHLEVEL); |
830 | vmw_write(dev_priv: dev, offset: SVGA_REG_GUEST_DRIVER_VERSION3, value: 0); |
831 | |
832 | vmw_write(dev_priv: dev, offset: SVGA_REG_GUEST_DRIVER_ID, |
833 | value: SVGA_REG_GUEST_DRIVER_ID_SUBMIT); |
834 | } |
835 | } |
836 | |
837 | static void vmw_sw_context_init(struct vmw_private *dev_priv) |
838 | { |
839 | struct vmw_sw_context *sw_context = &dev_priv->ctx; |
840 | |
841 | hash_init(sw_context->res_ht); |
842 | } |
843 | |
844 | static void vmw_sw_context_fini(struct vmw_private *dev_priv) |
845 | { |
846 | struct vmw_sw_context *sw_context = &dev_priv->ctx; |
847 | |
848 | vfree(addr: sw_context->cmd_bounce); |
849 | if (sw_context->staged_bindings) |
850 | vmw_binding_state_free(cbs: sw_context->staged_bindings); |
851 | } |
852 | |
853 | static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) |
854 | { |
855 | int ret; |
856 | enum vmw_res_type i; |
857 | bool refuse_dma = false; |
858 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
859 | |
860 | dev_priv->drm.dev_private = dev_priv; |
861 | |
862 | vmw_sw_context_init(dev_priv); |
863 | |
864 | mutex_init(&dev_priv->cmdbuf_mutex); |
865 | mutex_init(&dev_priv->binding_mutex); |
866 | spin_lock_init(&dev_priv->resource_lock); |
867 | spin_lock_init(&dev_priv->hw_lock); |
868 | spin_lock_init(&dev_priv->waiter_lock); |
869 | spin_lock_init(&dev_priv->cursor_lock); |
870 | |
871 | ret = vmw_setup_pci_resources(dev: dev_priv, pci_id); |
872 | if (ret) |
873 | return ret; |
874 | ret = vmw_detect_version(dev: dev_priv); |
875 | if (ret) |
876 | goto out_no_pci_or_version; |
877 | |
878 | |
879 | for (i = vmw_res_context; i < vmw_res_max; ++i) { |
880 | idr_init_base(idr: &dev_priv->res_idr[i], base: 1); |
881 | INIT_LIST_HEAD(list: &dev_priv->res_lru[i]); |
882 | } |
883 | |
884 | init_waitqueue_head(&dev_priv->fence_queue); |
885 | init_waitqueue_head(&dev_priv->fifo_queue); |
886 | dev_priv->fence_queue_waiters = 0; |
887 | dev_priv->fifo_queue_waiters = 0; |
888 | |
889 | dev_priv->used_memory_size = 0; |
890 | |
891 | dev_priv->assume_16bpp = !!vmw_assume_16bpp; |
892 | |
893 | dev_priv->capabilities = vmw_read(dev_priv, offset: SVGA_REG_CAPABILITIES); |
894 | vmw_print_bitmap(drm: &dev_priv->drm, prefix: "Capabilities" , |
895 | bitmap: dev_priv->capabilities, |
896 | bnames: cap1_names, ARRAY_SIZE(cap1_names)); |
897 | if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { |
898 | dev_priv->capabilities2 = vmw_read(dev_priv, offset: SVGA_REG_CAP2); |
899 | vmw_print_bitmap(drm: &dev_priv->drm, prefix: "Capabilities2" , |
900 | bitmap: dev_priv->capabilities2, |
901 | bnames: cap2_names, ARRAY_SIZE(cap2_names)); |
902 | } |
903 | |
904 | if (!vmwgfx_supported(vmw: dev_priv)) { |
905 | vmw_disable_backdoor(); |
906 | drm_err_once(&dev_priv->drm, |
907 | "vmwgfx seems to be running on an unsupported hypervisor." ); |
908 | drm_err_once(&dev_priv->drm, |
909 | "This configuration is likely broken." ); |
910 | drm_err_once(&dev_priv->drm, |
911 | "Please switch to a supported graphics device to avoid problems." ); |
912 | } |
913 | |
914 | ret = vmw_dma_select_mode(dev_priv); |
915 | if (unlikely(ret != 0)) { |
916 | drm_info(&dev_priv->drm, |
917 | "Restricting capabilities since DMA not available.\n" ); |
918 | refuse_dma = true; |
919 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) |
920 | drm_info(&dev_priv->drm, |
921 | "Disabling 3D acceleration.\n" ); |
922 | } |
923 | |
924 | dev_priv->vram_size = vmw_read(dev_priv, offset: SVGA_REG_VRAM_SIZE); |
925 | dev_priv->fifo_mem_size = vmw_read(dev_priv, offset: SVGA_REG_MEM_SIZE); |
926 | dev_priv->fb_max_width = vmw_read(dev_priv, offset: SVGA_REG_MAX_WIDTH); |
927 | dev_priv->fb_max_height = vmw_read(dev_priv, offset: SVGA_REG_MAX_HEIGHT); |
928 | |
929 | vmw_get_initial_size(dev_priv); |
930 | |
931 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
932 | dev_priv->max_gmr_ids = |
933 | vmw_read(dev_priv, offset: SVGA_REG_GMR_MAX_IDS); |
934 | dev_priv->max_gmr_pages = |
935 | vmw_read(dev_priv, offset: SVGA_REG_GMRS_MAX_PAGES); |
936 | dev_priv->memory_size = |
937 | vmw_read(dev_priv, offset: SVGA_REG_MEMORY_SIZE); |
938 | dev_priv->memory_size -= dev_priv->vram_size; |
939 | } else { |
940 | /* |
941 | * An arbitrary limit of 512MiB on surface |
942 | * memory. But all HWV8 hardware supports GMR2. |
943 | */ |
944 | dev_priv->memory_size = 512*1024*1024; |
945 | } |
946 | dev_priv->max_mob_pages = 0; |
947 | dev_priv->max_mob_size = 0; |
948 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
949 | uint64_t mem_size; |
950 | |
951 | if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) |
952 | mem_size = vmw_read(dev_priv, |
953 | offset: SVGA_REG_GBOBJECT_MEM_SIZE_KB); |
954 | else |
955 | mem_size = |
956 | vmw_read(dev_priv, |
957 | offset: SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); |
958 | |
959 | /* |
960 | * Workaround for low memory 2D VMs to compensate for the |
961 | * allocation taken by fbdev |
962 | */ |
963 | if (!(dev_priv->capabilities & SVGA_CAP_3D)) |
964 | mem_size *= 3; |
965 | |
966 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; |
967 | dev_priv->max_primary_mem = |
968 | vmw_read(dev_priv, offset: SVGA_REG_MAX_PRIMARY_MEM); |
969 | dev_priv->max_mob_size = |
970 | vmw_read(dev_priv, offset: SVGA_REG_MOB_MAX_SIZE); |
971 | dev_priv->stdu_max_width = |
972 | vmw_read(dev_priv, offset: SVGA_REG_SCREENTARGET_MAX_WIDTH); |
973 | dev_priv->stdu_max_height = |
974 | vmw_read(dev_priv, offset: SVGA_REG_SCREENTARGET_MAX_HEIGHT); |
975 | |
976 | vmw_write(dev_priv, offset: SVGA_REG_DEV_CAP, |
977 | SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); |
978 | dev_priv->texture_max_width = vmw_read(dev_priv, |
979 | offset: SVGA_REG_DEV_CAP); |
980 | vmw_write(dev_priv, offset: SVGA_REG_DEV_CAP, |
981 | SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); |
982 | dev_priv->texture_max_height = vmw_read(dev_priv, |
983 | offset: SVGA_REG_DEV_CAP); |
984 | } else { |
985 | dev_priv->texture_max_width = 8192; |
986 | dev_priv->texture_max_height = 8192; |
987 | dev_priv->max_primary_mem = dev_priv->vram_size; |
988 | } |
989 | drm_info(&dev_priv->drm, |
990 | "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n" , |
991 | (u64)dev_priv->vram_size / 1024, |
992 | (u64)dev_priv->fifo_mem_size / 1024, |
993 | dev_priv->memory_size / 1024); |
994 | |
995 | drm_info(&dev_priv->drm, |
996 | "MOB limits: max mob size = %u kB, max mob pages = %u\n" , |
997 | dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); |
998 | |
999 | ret = vmw_dma_masks(dev_priv); |
1000 | if (unlikely(ret != 0)) |
1001 | goto out_err0; |
1002 | |
1003 | dma_set_max_seg_size(dev: dev_priv->drm.dev, U32_MAX); |
1004 | |
1005 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
1006 | drm_info(&dev_priv->drm, |
1007 | "Max GMR ids is %u\n" , |
1008 | (unsigned)dev_priv->max_gmr_ids); |
1009 | drm_info(&dev_priv->drm, |
1010 | "Max number of GMR pages is %u\n" , |
1011 | (unsigned)dev_priv->max_gmr_pages); |
1012 | } |
1013 | drm_info(&dev_priv->drm, |
1014 | "Maximum display memory size is %llu kiB\n" , |
1015 | (uint64_t)dev_priv->max_primary_mem / 1024); |
1016 | |
1017 | /* Need mmio memory to check for fifo pitchlock cap. */ |
1018 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && |
1019 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && |
1020 | !vmw_fifo_have_pitchlock(dev_priv)) { |
1021 | ret = -ENOSYS; |
1022 | DRM_ERROR("Hardware has no pitchlock\n" ); |
1023 | goto out_err0; |
1024 | } |
1025 | |
1026 | dev_priv->tdev = ttm_object_device_init(ops: &vmw_prime_dmabuf_ops); |
1027 | |
1028 | if (unlikely(dev_priv->tdev == NULL)) { |
1029 | drm_err(&dev_priv->drm, |
1030 | "Unable to initialize TTM object management.\n" ); |
1031 | ret = -ENOMEM; |
1032 | goto out_err0; |
1033 | } |
1034 | |
1035 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
1036 | ret = vmw_irq_install(dev_priv); |
1037 | if (ret != 0) { |
1038 | drm_err(&dev_priv->drm, |
1039 | "Failed installing irq: %d\n" , ret); |
1040 | goto out_no_irq; |
1041 | } |
1042 | } |
1043 | |
1044 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
1045 | if (unlikely(dev_priv->fman == NULL)) { |
1046 | ret = -ENOMEM; |
1047 | goto out_no_fman; |
1048 | } |
1049 | |
1050 | ret = ttm_device_init(bdev: &dev_priv->bdev, funcs: &vmw_bo_driver, |
1051 | dev: dev_priv->drm.dev, |
1052 | mapping: dev_priv->drm.anon_inode->i_mapping, |
1053 | vma_manager: dev_priv->drm.vma_offset_manager, |
1054 | use_dma_alloc: dev_priv->map_mode == vmw_dma_alloc_coherent, |
1055 | use_dma32: false); |
1056 | if (unlikely(ret != 0)) { |
1057 | drm_err(&dev_priv->drm, |
1058 | "Failed initializing TTM buffer object driver.\n" ); |
1059 | goto out_no_bdev; |
1060 | } |
1061 | |
1062 | /* |
1063 | * Enable VRAM, but initially don't use it until SVGA is enabled and |
1064 | * unhidden. |
1065 | */ |
1066 | |
1067 | ret = vmw_vram_manager_init(dev_priv); |
1068 | if (unlikely(ret != 0)) { |
1069 | drm_err(&dev_priv->drm, |
1070 | "Failed initializing memory manager for VRAM.\n" ); |
1071 | goto out_no_vram; |
1072 | } |
1073 | |
1074 | ret = vmw_devcaps_create(vmw: dev_priv); |
1075 | if (unlikely(ret != 0)) { |
1076 | drm_err(&dev_priv->drm, |
1077 | "Failed initializing device caps.\n" ); |
1078 | goto out_no_vram; |
1079 | } |
1080 | |
1081 | /* |
1082 | * "Guest Memory Regions" is an aperture like feature with |
1083 | * one slot per bo. There is an upper limit of the number of |
1084 | * slots as well as the bo size. |
1085 | */ |
1086 | dev_priv->has_gmr = true; |
1087 | /* TODO: This is most likely not correct */ |
1088 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || |
1089 | refuse_dma || |
1090 | vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { |
1091 | drm_info(&dev_priv->drm, |
1092 | "No GMR memory available. " |
1093 | "Graphics memory resources are very limited.\n" ); |
1094 | dev_priv->has_gmr = false; |
1095 | } |
1096 | |
1097 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { |
1098 | dev_priv->has_mob = true; |
1099 | |
1100 | if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { |
1101 | drm_info(&dev_priv->drm, |
1102 | "No MOB memory available. " |
1103 | "3D will be disabled.\n" ); |
1104 | dev_priv->has_mob = false; |
1105 | } |
1106 | if (vmw_sys_man_init(dev_priv) != 0) { |
1107 | drm_info(&dev_priv->drm, |
1108 | "No MOB page table memory available. " |
1109 | "3D will be disabled.\n" ); |
1110 | dev_priv->has_mob = false; |
1111 | } |
1112 | } |
1113 | |
1114 | if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { |
1115 | if (vmw_devcap_get(vmw: dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) |
1116 | dev_priv->sm_type = VMW_SM_4; |
1117 | } |
1118 | |
1119 | /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ |
1120 | if (has_sm4_context(dev_priv) && |
1121 | (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { |
1122 | if (vmw_devcap_get(vmw: dev_priv, SVGA3D_DEVCAP_SM41)) |
1123 | dev_priv->sm_type = VMW_SM_4_1; |
1124 | if (has_sm4_1_context(dev_priv) && |
1125 | (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { |
1126 | if (vmw_devcap_get(vmw: dev_priv, SVGA3D_DEVCAP_SM5)) { |
1127 | dev_priv->sm_type = VMW_SM_5; |
1128 | if (vmw_devcap_get(vmw: dev_priv, SVGA3D_DEVCAP_GL43)) |
1129 | dev_priv->sm_type = VMW_SM_5_1X; |
1130 | } |
1131 | } |
1132 | } |
1133 | |
1134 | ret = vmw_kms_init(dev_priv); |
1135 | if (unlikely(ret != 0)) |
1136 | goto out_no_kms; |
1137 | vmw_overlay_init(dev_priv); |
1138 | |
1139 | ret = vmw_request_device(dev_priv); |
1140 | if (ret) |
1141 | goto out_no_fifo; |
1142 | |
1143 | vmw_print_sm_type(dev_priv); |
1144 | vmw_host_printf(fmt: "vmwgfx: Module Version: %d.%d.%d (kernel: %s)" , |
1145 | VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, |
1146 | VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); |
1147 | vmw_write_driver_id(dev: dev_priv); |
1148 | |
1149 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
1150 | register_pm_notifier(nb: &dev_priv->pm_nb); |
1151 | |
1152 | return 0; |
1153 | |
1154 | out_no_fifo: |
1155 | vmw_overlay_close(dev_priv); |
1156 | vmw_kms_close(dev_priv); |
1157 | out_no_kms: |
1158 | if (dev_priv->has_mob) { |
1159 | vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); |
1160 | vmw_sys_man_fini(dev_priv); |
1161 | } |
1162 | if (dev_priv->has_gmr) |
1163 | vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); |
1164 | vmw_devcaps_destroy(vmw: dev_priv); |
1165 | vmw_vram_manager_fini(dev_priv); |
1166 | out_no_vram: |
1167 | ttm_device_fini(bdev: &dev_priv->bdev); |
1168 | out_no_bdev: |
1169 | vmw_fence_manager_takedown(fman: dev_priv->fman); |
1170 | out_no_fman: |
1171 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
1172 | vmw_irq_uninstall(dev: &dev_priv->drm); |
1173 | out_no_irq: |
1174 | ttm_object_device_release(p_tdev: &dev_priv->tdev); |
1175 | out_err0: |
1176 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
1177 | idr_destroy(&dev_priv->res_idr[i]); |
1178 | |
1179 | if (dev_priv->ctx.staged_bindings) |
1180 | vmw_binding_state_free(cbs: dev_priv->ctx.staged_bindings); |
1181 | out_no_pci_or_version: |
1182 | pci_release_regions(pdev); |
1183 | return ret; |
1184 | } |
1185 | |
1186 | static void vmw_driver_unload(struct drm_device *dev) |
1187 | { |
1188 | struct vmw_private *dev_priv = vmw_priv(dev); |
1189 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1190 | enum vmw_res_type i; |
1191 | |
1192 | unregister_pm_notifier(nb: &dev_priv->pm_nb); |
1193 | |
1194 | vmw_sw_context_fini(dev_priv); |
1195 | vmw_fifo_resource_dec(dev_priv); |
1196 | |
1197 | vmw_svga_disable(dev_priv); |
1198 | |
1199 | vmw_kms_close(dev_priv); |
1200 | vmw_overlay_close(dev_priv); |
1201 | |
1202 | if (dev_priv->has_gmr) |
1203 | vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); |
1204 | |
1205 | vmw_release_device_early(dev_priv); |
1206 | if (dev_priv->has_mob) { |
1207 | vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); |
1208 | vmw_sys_man_fini(dev_priv); |
1209 | } |
1210 | vmw_devcaps_destroy(vmw: dev_priv); |
1211 | vmw_vram_manager_fini(dev_priv); |
1212 | ttm_device_fini(bdev: &dev_priv->bdev); |
1213 | vmw_release_device_late(dev_priv); |
1214 | vmw_fence_manager_takedown(fman: dev_priv->fman); |
1215 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
1216 | vmw_irq_uninstall(dev: &dev_priv->drm); |
1217 | |
1218 | ttm_object_device_release(p_tdev: &dev_priv->tdev); |
1219 | |
1220 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
1221 | idr_destroy(&dev_priv->res_idr[i]); |
1222 | |
1223 | vmw_mksstat_remove_all(dev_priv); |
1224 | |
1225 | pci_release_regions(pdev); |
1226 | } |
1227 | |
1228 | static void vmw_postclose(struct drm_device *dev, |
1229 | struct drm_file *file_priv) |
1230 | { |
1231 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); |
1232 | |
1233 | ttm_object_file_release(p_tfile: &vmw_fp->tfile); |
1234 | kfree(objp: vmw_fp); |
1235 | } |
1236 | |
1237 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
1238 | { |
1239 | struct vmw_private *dev_priv = vmw_priv(dev); |
1240 | struct vmw_fpriv *vmw_fp; |
1241 | int ret = -ENOMEM; |
1242 | |
1243 | vmw_fp = kzalloc(size: sizeof(*vmw_fp), GFP_KERNEL); |
1244 | if (unlikely(!vmw_fp)) |
1245 | return ret; |
1246 | |
1247 | vmw_fp->tfile = ttm_object_file_init(tdev: dev_priv->tdev); |
1248 | if (unlikely(vmw_fp->tfile == NULL)) |
1249 | goto out_no_tfile; |
1250 | |
1251 | file_priv->driver_priv = vmw_fp; |
1252 | |
1253 | return 0; |
1254 | |
1255 | out_no_tfile: |
1256 | kfree(objp: vmw_fp); |
1257 | return ret; |
1258 | } |
1259 | |
1260 | static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, |
1261 | unsigned long arg, |
1262 | long (*ioctl_func)(struct file *, unsigned int, |
1263 | unsigned long)) |
1264 | { |
1265 | struct drm_file *file_priv = filp->private_data; |
1266 | struct drm_device *dev = file_priv->minor->dev; |
1267 | unsigned int nr = DRM_IOCTL_NR(cmd); |
1268 | unsigned int flags; |
1269 | |
1270 | /* |
1271 | * Do extra checking on driver private ioctls. |
1272 | */ |
1273 | |
1274 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) |
1275 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { |
1276 | const struct drm_ioctl_desc *ioctl = |
1277 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
1278 | |
1279 | if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { |
1280 | return ioctl_func(filp, cmd, arg); |
1281 | } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { |
1282 | if (!drm_is_current_master(fpriv: file_priv) && |
1283 | !capable(CAP_SYS_ADMIN)) |
1284 | return -EACCES; |
1285 | } |
1286 | |
1287 | if (unlikely(ioctl->cmd != cmd)) |
1288 | goto out_io_encoding; |
1289 | |
1290 | flags = ioctl->flags; |
1291 | } else if (!drm_ioctl_flags(nr, flags: &flags)) |
1292 | return -EINVAL; |
1293 | |
1294 | return ioctl_func(filp, cmd, arg); |
1295 | |
1296 | out_io_encoding: |
1297 | DRM_ERROR("Invalid command format, ioctl %d\n" , |
1298 | nr - DRM_COMMAND_BASE); |
1299 | |
1300 | return -EINVAL; |
1301 | } |
1302 | |
1303 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, |
1304 | unsigned long arg) |
1305 | { |
1306 | return vmw_generic_ioctl(filp, cmd, arg, ioctl_func: &drm_ioctl); |
1307 | } |
1308 | |
1309 | #ifdef CONFIG_COMPAT |
1310 | static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, |
1311 | unsigned long arg) |
1312 | { |
1313 | return vmw_generic_ioctl(filp, cmd, arg, ioctl_func: &drm_compat_ioctl); |
1314 | } |
1315 | #endif |
1316 | |
1317 | static void vmw_master_set(struct drm_device *dev, |
1318 | struct drm_file *file_priv, |
1319 | bool from_open) |
1320 | { |
1321 | /* |
1322 | * Inform a new master that the layout may have changed while |
1323 | * it was gone. |
1324 | */ |
1325 | if (!from_open) |
1326 | drm_sysfs_hotplug_event(dev); |
1327 | } |
1328 | |
1329 | static void vmw_master_drop(struct drm_device *dev, |
1330 | struct drm_file *file_priv) |
1331 | { |
1332 | struct vmw_private *dev_priv = vmw_priv(dev); |
1333 | |
1334 | vmw_kms_legacy_hotspot_clear(dev_priv); |
1335 | } |
1336 | |
1337 | bool vmwgfx_supported(struct vmw_private *vmw) |
1338 | { |
1339 | #if defined(CONFIG_X86) |
1340 | return hypervisor_is_type(type: X86_HYPER_VMWARE); |
1341 | #elif defined(CONFIG_ARM64) |
1342 | /* |
1343 | * On aarch64 only svga3 is supported |
1344 | */ |
1345 | return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; |
1346 | #else |
1347 | drm_warn_once(&vmw->drm, |
1348 | "vmwgfx is running on an unknown architecture." ); |
1349 | return false; |
1350 | #endif |
1351 | } |
1352 | |
1353 | /** |
1354 | * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. |
1355 | * |
1356 | * @dev_priv: Pointer to device private struct. |
1357 | * Needs the reservation sem to be held in non-exclusive mode. |
1358 | */ |
1359 | static void __vmw_svga_enable(struct vmw_private *dev_priv) |
1360 | { |
1361 | struct ttm_resource_manager *man = ttm_manager_type(bdev: &dev_priv->bdev, TTM_PL_VRAM); |
1362 | |
1363 | if (!ttm_resource_manager_used(man)) { |
1364 | vmw_write(dev_priv, offset: SVGA_REG_ENABLE, value: SVGA_REG_ENABLE_ENABLE); |
1365 | ttm_resource_manager_set_used(man, used: true); |
1366 | } |
1367 | } |
1368 | |
1369 | /** |
1370 | * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. |
1371 | * |
1372 | * @dev_priv: Pointer to device private struct. |
1373 | */ |
1374 | void vmw_svga_enable(struct vmw_private *dev_priv) |
1375 | { |
1376 | __vmw_svga_enable(dev_priv); |
1377 | } |
1378 | |
1379 | /** |
1380 | * __vmw_svga_disable - Disable SVGA mode and use of VRAM. |
1381 | * |
1382 | * @dev_priv: Pointer to device private struct. |
1383 | * Needs the reservation sem to be held in exclusive mode. |
1384 | * Will not empty VRAM. VRAM must be emptied by caller. |
1385 | */ |
1386 | static void __vmw_svga_disable(struct vmw_private *dev_priv) |
1387 | { |
1388 | struct ttm_resource_manager *man = ttm_manager_type(bdev: &dev_priv->bdev, TTM_PL_VRAM); |
1389 | |
1390 | if (ttm_resource_manager_used(man)) { |
1391 | ttm_resource_manager_set_used(man, used: false); |
1392 | vmw_write(dev_priv, offset: SVGA_REG_ENABLE, |
1393 | value: SVGA_REG_ENABLE_HIDE | |
1394 | SVGA_REG_ENABLE_ENABLE); |
1395 | } |
1396 | } |
1397 | |
1398 | /** |
1399 | * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo |
1400 | * running. |
1401 | * |
1402 | * @dev_priv: Pointer to device private struct. |
1403 | * Will empty VRAM. |
1404 | */ |
1405 | void vmw_svga_disable(struct vmw_private *dev_priv) |
1406 | { |
1407 | struct ttm_resource_manager *man = ttm_manager_type(bdev: &dev_priv->bdev, TTM_PL_VRAM); |
1408 | /* |
1409 | * Disabling SVGA will turn off device modesetting capabilities, so |
1410 | * notify KMS about that so that it doesn't cache atomic state that |
1411 | * isn't valid anymore, for example crtcs turned on. |
1412 | * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), |
1413 | * but vmw_kms_lost_device() takes the reservation sem and thus we'll |
1414 | * end up with lock order reversal. Thus, a master may actually perform |
1415 | * a new modeset just after we call vmw_kms_lost_device() and race with |
1416 | * vmw_svga_disable(), but that should at worst cause atomic KMS state |
1417 | * to be inconsistent with the device, causing modesetting problems. |
1418 | * |
1419 | */ |
1420 | vmw_kms_lost_device(dev: &dev_priv->drm); |
1421 | if (ttm_resource_manager_used(man)) { |
1422 | if (ttm_resource_manager_evict_all(bdev: &dev_priv->bdev, man)) |
1423 | DRM_ERROR("Failed evicting VRAM buffers.\n" ); |
1424 | ttm_resource_manager_set_used(man, used: false); |
1425 | vmw_write(dev_priv, offset: SVGA_REG_ENABLE, |
1426 | value: SVGA_REG_ENABLE_HIDE | |
1427 | SVGA_REG_ENABLE_ENABLE); |
1428 | } |
1429 | } |
1430 | |
1431 | static void vmw_remove(struct pci_dev *pdev) |
1432 | { |
1433 | struct drm_device *dev = pci_get_drvdata(pdev); |
1434 | |
1435 | drm_dev_unregister(dev); |
1436 | vmw_driver_unload(dev); |
1437 | } |
1438 | |
1439 | static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) |
1440 | { |
1441 | struct drm_minor *minor = vmw->drm.primary; |
1442 | struct dentry *root = minor->debugfs_root; |
1443 | |
1444 | ttm_resource_manager_create_debugfs(man: ttm_manager_type(bdev: &vmw->bdev, TTM_PL_SYSTEM), |
1445 | parent: root, name: "system_ttm" ); |
1446 | ttm_resource_manager_create_debugfs(man: ttm_manager_type(bdev: &vmw->bdev, TTM_PL_VRAM), |
1447 | parent: root, name: "vram_ttm" ); |
1448 | if (vmw->has_gmr) |
1449 | ttm_resource_manager_create_debugfs(man: ttm_manager_type(bdev: &vmw->bdev, VMW_PL_GMR), |
1450 | parent: root, name: "gmr_ttm" ); |
1451 | if (vmw->has_mob) { |
1452 | ttm_resource_manager_create_debugfs(man: ttm_manager_type(bdev: &vmw->bdev, VMW_PL_MOB), |
1453 | parent: root, name: "mob_ttm" ); |
1454 | ttm_resource_manager_create_debugfs(man: ttm_manager_type(bdev: &vmw->bdev, VMW_PL_SYSTEM), |
1455 | parent: root, name: "system_mob_ttm" ); |
1456 | } |
1457 | } |
1458 | |
1459 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1460 | void *ptr) |
1461 | { |
1462 | struct vmw_private *dev_priv = |
1463 | container_of(nb, struct vmw_private, pm_nb); |
1464 | |
1465 | switch (val) { |
1466 | case PM_HIBERNATION_PREPARE: |
1467 | /* |
1468 | * Take the reservation sem in write mode, which will make sure |
1469 | * there are no other processes holding a buffer object |
1470 | * reservation, meaning we should be able to evict all buffer |
1471 | * objects if needed. |
1472 | * Once user-space processes have been frozen, we can release |
1473 | * the lock again. |
1474 | */ |
1475 | dev_priv->suspend_locked = true; |
1476 | break; |
1477 | case PM_POST_HIBERNATION: |
1478 | case PM_POST_RESTORE: |
1479 | if (READ_ONCE(dev_priv->suspend_locked)) { |
1480 | dev_priv->suspend_locked = false; |
1481 | } |
1482 | break; |
1483 | default: |
1484 | break; |
1485 | } |
1486 | return 0; |
1487 | } |
1488 | |
1489 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
1490 | { |
1491 | struct drm_device *dev = pci_get_drvdata(pdev); |
1492 | struct vmw_private *dev_priv = vmw_priv(dev); |
1493 | |
1494 | if (dev_priv->refuse_hibernation) |
1495 | return -EBUSY; |
1496 | |
1497 | pci_save_state(dev: pdev); |
1498 | pci_disable_device(dev: pdev); |
1499 | pci_set_power_state(dev: pdev, PCI_D3hot); |
1500 | return 0; |
1501 | } |
1502 | |
1503 | static int vmw_pci_resume(struct pci_dev *pdev) |
1504 | { |
1505 | pci_set_power_state(dev: pdev, PCI_D0); |
1506 | pci_restore_state(dev: pdev); |
1507 | return pci_enable_device(dev: pdev); |
1508 | } |
1509 | |
1510 | static int vmw_pm_suspend(struct device *kdev) |
1511 | { |
1512 | struct pci_dev *pdev = to_pci_dev(kdev); |
1513 | struct pm_message dummy; |
1514 | |
1515 | dummy.event = 0; |
1516 | |
1517 | return vmw_pci_suspend(pdev, state: dummy); |
1518 | } |
1519 | |
1520 | static int vmw_pm_resume(struct device *kdev) |
1521 | { |
1522 | struct pci_dev *pdev = to_pci_dev(kdev); |
1523 | |
1524 | return vmw_pci_resume(pdev); |
1525 | } |
1526 | |
1527 | static int vmw_pm_freeze(struct device *kdev) |
1528 | { |
1529 | struct pci_dev *pdev = to_pci_dev(kdev); |
1530 | struct drm_device *dev = pci_get_drvdata(pdev); |
1531 | struct vmw_private *dev_priv = vmw_priv(dev); |
1532 | struct ttm_operation_ctx ctx = { |
1533 | .interruptible = false, |
1534 | .no_wait_gpu = false |
1535 | }; |
1536 | int ret; |
1537 | |
1538 | /* |
1539 | * No user-space processes should be running now. |
1540 | */ |
1541 | ret = vmw_kms_suspend(dev: &dev_priv->drm); |
1542 | if (ret) { |
1543 | DRM_ERROR("Failed to freeze modesetting.\n" ); |
1544 | return ret; |
1545 | } |
1546 | |
1547 | vmw_execbuf_release_pinned_bo(dev_priv); |
1548 | vmw_resource_evict_all(dev_priv); |
1549 | vmw_release_device_early(dev_priv); |
1550 | while (ttm_device_swapout(bdev: &dev_priv->bdev, ctx: &ctx, GFP_KERNEL) > 0); |
1551 | vmw_fifo_resource_dec(dev_priv); |
1552 | if (atomic_read(v: &dev_priv->num_fifo_resources) != 0) { |
1553 | DRM_ERROR("Can't hibernate while 3D resources are active.\n" ); |
1554 | vmw_fifo_resource_inc(dev_priv); |
1555 | WARN_ON(vmw_request_device_late(dev_priv)); |
1556 | dev_priv->suspend_locked = false; |
1557 | if (dev_priv->suspend_state) |
1558 | vmw_kms_resume(dev); |
1559 | return -EBUSY; |
1560 | } |
1561 | |
1562 | vmw_fence_fifo_down(fman: dev_priv->fman); |
1563 | __vmw_svga_disable(dev_priv); |
1564 | |
1565 | vmw_release_device_late(dev_priv); |
1566 | return 0; |
1567 | } |
1568 | |
1569 | static int vmw_pm_restore(struct device *kdev) |
1570 | { |
1571 | struct pci_dev *pdev = to_pci_dev(kdev); |
1572 | struct drm_device *dev = pci_get_drvdata(pdev); |
1573 | struct vmw_private *dev_priv = vmw_priv(dev); |
1574 | int ret; |
1575 | |
1576 | vmw_detect_version(dev: dev_priv); |
1577 | |
1578 | vmw_fifo_resource_inc(dev_priv); |
1579 | |
1580 | ret = vmw_request_device(dev_priv); |
1581 | if (ret) |
1582 | return ret; |
1583 | |
1584 | __vmw_svga_enable(dev_priv); |
1585 | |
1586 | vmw_fence_fifo_up(fman: dev_priv->fman); |
1587 | dev_priv->suspend_locked = false; |
1588 | if (dev_priv->suspend_state) |
1589 | vmw_kms_resume(dev: &dev_priv->drm); |
1590 | |
1591 | return 0; |
1592 | } |
1593 | |
1594 | static const struct dev_pm_ops vmw_pm_ops = { |
1595 | .freeze = vmw_pm_freeze, |
1596 | .thaw = vmw_pm_restore, |
1597 | .restore = vmw_pm_restore, |
1598 | .suspend = vmw_pm_suspend, |
1599 | .resume = vmw_pm_resume, |
1600 | }; |
1601 | |
1602 | static const struct file_operations vmwgfx_driver_fops = { |
1603 | .owner = THIS_MODULE, |
1604 | .open = drm_open, |
1605 | .release = drm_release, |
1606 | .unlocked_ioctl = vmw_unlocked_ioctl, |
1607 | .mmap = drm_gem_mmap, |
1608 | .poll = drm_poll, |
1609 | .read = drm_read, |
1610 | #if defined(CONFIG_COMPAT) |
1611 | .compat_ioctl = vmw_compat_ioctl, |
1612 | #endif |
1613 | .llseek = noop_llseek, |
1614 | }; |
1615 | |
1616 | static const struct drm_driver driver = { |
1617 | .driver_features = |
1618 | DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, |
1619 | .ioctls = vmw_ioctls, |
1620 | .num_ioctls = ARRAY_SIZE(vmw_ioctls), |
1621 | .master_set = vmw_master_set, |
1622 | .master_drop = vmw_master_drop, |
1623 | .open = vmw_driver_open, |
1624 | .postclose = vmw_postclose, |
1625 | |
1626 | .dumb_create = vmw_dumb_create, |
1627 | .dumb_map_offset = drm_gem_ttm_dumb_map_offset, |
1628 | |
1629 | .prime_fd_to_handle = vmw_prime_fd_to_handle, |
1630 | .prime_handle_to_fd = vmw_prime_handle_to_fd, |
1631 | .gem_prime_import_sg_table = vmw_prime_import_sg_table, |
1632 | |
1633 | .fops = &vmwgfx_driver_fops, |
1634 | .name = VMWGFX_DRIVER_NAME, |
1635 | .desc = VMWGFX_DRIVER_DESC, |
1636 | .date = VMWGFX_DRIVER_DATE, |
1637 | .major = VMWGFX_DRIVER_MAJOR, |
1638 | .minor = VMWGFX_DRIVER_MINOR, |
1639 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL |
1640 | }; |
1641 | |
1642 | static struct pci_driver vmw_pci_driver = { |
1643 | .name = VMWGFX_DRIVER_NAME, |
1644 | .id_table = vmw_pci_id_list, |
1645 | .probe = vmw_probe, |
1646 | .remove = vmw_remove, |
1647 | .driver = { |
1648 | .pm = &vmw_pm_ops |
1649 | } |
1650 | }; |
1651 | |
1652 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1653 | { |
1654 | struct vmw_private *vmw; |
1655 | int ret; |
1656 | |
1657 | ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, req_driver: &driver); |
1658 | if (ret) |
1659 | goto out_error; |
1660 | |
1661 | ret = pcim_enable_device(pdev); |
1662 | if (ret) |
1663 | goto out_error; |
1664 | |
1665 | vmw = devm_drm_dev_alloc(&pdev->dev, &driver, |
1666 | struct vmw_private, drm); |
1667 | if (IS_ERR(ptr: vmw)) { |
1668 | ret = PTR_ERR(ptr: vmw); |
1669 | goto out_error; |
1670 | } |
1671 | |
1672 | pci_set_drvdata(pdev, data: &vmw->drm); |
1673 | |
1674 | ret = vmw_driver_load(dev_priv: vmw, pci_id: ent->device); |
1675 | if (ret) |
1676 | goto out_error; |
1677 | |
1678 | ret = drm_dev_register(dev: &vmw->drm, flags: 0); |
1679 | if (ret) |
1680 | goto out_unload; |
1681 | |
1682 | vmw_fifo_resource_inc(dev_priv: vmw); |
1683 | vmw_svga_enable(dev_priv: vmw); |
1684 | drm_fbdev_generic_setup(dev: &vmw->drm, preferred_bpp: 0); |
1685 | |
1686 | vmw_debugfs_gem_init(vdev: vmw); |
1687 | vmw_debugfs_resource_managers_init(vmw); |
1688 | |
1689 | return 0; |
1690 | out_unload: |
1691 | vmw_driver_unload(dev: &vmw->drm); |
1692 | out_error: |
1693 | return ret; |
1694 | } |
1695 | |
1696 | drm_module_pci_driver(vmw_pci_driver); |
1697 | |
1698 | MODULE_AUTHOR("VMware Inc. and others" ); |
1699 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device" ); |
1700 | MODULE_LICENSE("GPL and additional rights" ); |
1701 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1702 | __stringify(VMWGFX_DRIVER_MINOR) "." |
1703 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." |
1704 | "0" ); |
1705 | |