1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Driver for NAND MLC Controller in LPC32xx |
4 | * |
5 | * Author: Roland Stigge <stigge@antcom.de> |
6 | * |
7 | * Copyright © 2011 WORK Microwave GmbH |
8 | * Copyright © 2011, 2012 Roland Stigge |
9 | * |
10 | * NAND Flash Controller Operation: |
11 | * - Read: Auto Decode |
12 | * - Write: Auto Encode |
13 | * - Tested Page Sizes: 2048, 4096 |
14 | */ |
15 | |
16 | #include <linux/slab.h> |
17 | #include <linux/module.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/rawnand.h> |
21 | #include <linux/mtd/partitions.h> |
22 | #include <linux/clk.h> |
23 | #include <linux/err.h> |
24 | #include <linux/delay.h> |
25 | #include <linux/completion.h> |
26 | #include <linux/interrupt.h> |
27 | #include <linux/of.h> |
28 | #include <linux/gpio/consumer.h> |
29 | #include <linux/mtd/lpc32xx_mlc.h> |
30 | #include <linux/io.h> |
31 | #include <linux/mm.h> |
32 | #include <linux/dma-mapping.h> |
33 | #include <linux/dmaengine.h> |
34 | |
35 | #define DRV_NAME "lpc32xx_mlc" |
36 | |
37 | /********************************************************************** |
38 | * MLC NAND controller register offsets |
39 | **********************************************************************/ |
40 | |
41 | #define MLC_BUFF(x) (x + 0x00000) |
42 | #define MLC_DATA(x) (x + 0x08000) |
43 | #define MLC_CMD(x) (x + 0x10000) |
44 | #define MLC_ADDR(x) (x + 0x10004) |
45 | #define MLC_ECC_ENC_REG(x) (x + 0x10008) |
46 | #define MLC_ECC_DEC_REG(x) (x + 0x1000C) |
47 | #define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010) |
48 | #define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014) |
49 | #define MLC_RPR(x) (x + 0x10018) |
50 | #define MLC_WPR(x) (x + 0x1001C) |
51 | #define MLC_RUBP(x) (x + 0x10020) |
52 | #define MLC_ROBP(x) (x + 0x10024) |
53 | #define MLC_SW_WP_ADD_LOW(x) (x + 0x10028) |
54 | #define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C) |
55 | #define MLC_ICR(x) (x + 0x10030) |
56 | #define MLC_TIME_REG(x) (x + 0x10034) |
57 | #define MLC_IRQ_MR(x) (x + 0x10038) |
58 | #define MLC_IRQ_SR(x) (x + 0x1003C) |
59 | #define MLC_LOCK_PR(x) (x + 0x10044) |
60 | #define MLC_ISR(x) (x + 0x10048) |
61 | #define MLC_CEH(x) (x + 0x1004C) |
62 | |
63 | /********************************************************************** |
64 | * MLC_CMD bit definitions |
65 | **********************************************************************/ |
66 | #define MLCCMD_RESET 0xFF |
67 | |
68 | /********************************************************************** |
69 | * MLC_ICR bit definitions |
70 | **********************************************************************/ |
71 | #define MLCICR_WPROT (1 << 3) |
72 | #define MLCICR_LARGEBLOCK (1 << 2) |
73 | #define MLCICR_LONGADDR (1 << 1) |
74 | #define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */ |
75 | |
76 | /********************************************************************** |
77 | * MLC_TIME_REG bit definitions |
78 | **********************************************************************/ |
79 | #define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24) |
80 | #define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19) |
81 | #define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16) |
82 | #define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12) |
83 | #define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8) |
84 | #define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4) |
85 | #define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0) |
86 | |
87 | /********************************************************************** |
88 | * MLC_IRQ_MR and MLC_IRQ_SR bit definitions |
89 | **********************************************************************/ |
90 | #define MLCIRQ_NAND_READY (1 << 5) |
91 | #define MLCIRQ_CONTROLLER_READY (1 << 4) |
92 | #define MLCIRQ_DECODE_FAILURE (1 << 3) |
93 | #define MLCIRQ_DECODE_ERROR (1 << 2) |
94 | #define MLCIRQ_ECC_READY (1 << 1) |
95 | #define MLCIRQ_WRPROT_FAULT (1 << 0) |
96 | |
97 | /********************************************************************** |
98 | * MLC_LOCK_PR bit definitions |
99 | **********************************************************************/ |
100 | #define MLCLOCKPR_MAGIC 0xA25E |
101 | |
102 | /********************************************************************** |
103 | * MLC_ISR bit definitions |
104 | **********************************************************************/ |
105 | #define MLCISR_DECODER_FAILURE (1 << 6) |
106 | #define MLCISR_ERRORS ((1 << 4) | (1 << 5)) |
107 | #define MLCISR_ERRORS_DETECTED (1 << 3) |
108 | #define MLCISR_ECC_READY (1 << 2) |
109 | #define MLCISR_CONTROLLER_READY (1 << 1) |
110 | #define MLCISR_NAND_READY (1 << 0) |
111 | |
112 | /********************************************************************** |
113 | * MLC_CEH bit definitions |
114 | **********************************************************************/ |
115 | #define MLCCEH_NORMAL (1 << 0) |
116 | |
117 | struct lpc32xx_nand_cfg_mlc { |
118 | uint32_t tcea_delay; |
119 | uint32_t busy_delay; |
120 | uint32_t nand_ta; |
121 | uint32_t rd_high; |
122 | uint32_t rd_low; |
123 | uint32_t wr_high; |
124 | uint32_t wr_low; |
125 | struct mtd_partition *parts; |
126 | unsigned num_parts; |
127 | }; |
128 | |
129 | static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section, |
130 | struct mtd_oob_region *oobregion) |
131 | { |
132 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
133 | |
134 | if (section >= nand_chip->ecc.steps) |
135 | return -ERANGE; |
136 | |
137 | oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes; |
138 | oobregion->length = nand_chip->ecc.bytes; |
139 | |
140 | return 0; |
141 | } |
142 | |
143 | static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section, |
144 | struct mtd_oob_region *oobregion) |
145 | { |
146 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
147 | |
148 | if (section >= nand_chip->ecc.steps) |
149 | return -ERANGE; |
150 | |
151 | oobregion->offset = 16 * section; |
152 | oobregion->length = 16 - nand_chip->ecc.bytes; |
153 | |
154 | return 0; |
155 | } |
156 | |
157 | static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = { |
158 | .ecc = lpc32xx_ooblayout_ecc, |
159 | .free = lpc32xx_ooblayout_free, |
160 | }; |
161 | |
162 | static struct nand_bbt_descr lpc32xx_nand_bbt = { |
163 | .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | |
164 | NAND_BBT_WRITE, |
165 | .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 }, |
166 | }; |
167 | |
168 | static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = { |
169 | .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | |
170 | NAND_BBT_WRITE, |
171 | .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 }, |
172 | }; |
173 | |
174 | struct lpc32xx_nand_host { |
175 | struct platform_device *pdev; |
176 | struct nand_chip nand_chip; |
177 | struct lpc32xx_mlc_platform_data *pdata; |
178 | struct clk *clk; |
179 | struct gpio_desc *wp_gpio; |
180 | void __iomem *io_base; |
181 | int irq; |
182 | struct lpc32xx_nand_cfg_mlc *ncfg; |
183 | struct completion comp_nand; |
184 | struct completion comp_controller; |
185 | uint32_t llptr; |
186 | /* |
187 | * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer |
188 | */ |
189 | dma_addr_t oob_buf_phy; |
190 | /* |
191 | * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer |
192 | */ |
193 | uint8_t *oob_buf; |
194 | /* Physical address of DMA base address */ |
195 | dma_addr_t io_base_phy; |
196 | |
197 | struct completion comp_dma; |
198 | struct dma_chan *dma_chan; |
199 | struct dma_slave_config dma_slave_config; |
200 | struct scatterlist sgl; |
201 | uint8_t *dma_buf; |
202 | uint8_t *dummy_buf; |
203 | int mlcsubpages; /* number of 512bytes-subpages */ |
204 | }; |
205 | |
206 | /* |
207 | * Activate/Deactivate DMA Operation: |
208 | * |
209 | * Using the PL080 DMA Controller for transferring the 512 byte subpages |
210 | * instead of doing readl() / writel() in a loop slows it down significantly. |
211 | * Measurements via getnstimeofday() upon 512 byte subpage reads reveal: |
212 | * |
213 | * - readl() of 128 x 32 bits in a loop: ~20us |
214 | * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us |
215 | * - DMA read of 512 bytes (32 bit, no bursts): ~100us |
216 | * |
217 | * This applies to the transfer itself. In the DMA case: only the |
218 | * wait_for_completion() (DMA setup _not_ included). |
219 | * |
220 | * Note that the 512 bytes subpage transfer is done directly from/to a |
221 | * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a |
222 | * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND |
223 | * controller transferring data between its internal buffer to/from the NAND |
224 | * chip.) |
225 | * |
226 | * Therefore, using the PL080 DMA is disabled by default, for now. |
227 | * |
228 | */ |
229 | static int use_dma; |
230 | |
231 | static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) |
232 | { |
233 | uint32_t clkrate, tmp; |
234 | |
235 | /* Reset MLC controller */ |
236 | writel(MLCCMD_RESET, MLC_CMD(host->io_base)); |
237 | udelay(1000); |
238 | |
239 | /* Get base clock for MLC block */ |
240 | clkrate = clk_get_rate(clk: host->clk); |
241 | if (clkrate == 0) |
242 | clkrate = 104000000; |
243 | |
244 | /* Unlock MLC_ICR |
245 | * (among others, will be locked again automatically) */ |
246 | writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); |
247 | |
248 | /* Configure MLC Controller: Large Block, 5 Byte Address */ |
249 | tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR; |
250 | writel(val: tmp, MLC_ICR(host->io_base)); |
251 | |
252 | /* Unlock MLC_TIME_REG |
253 | * (among others, will be locked again automatically) */ |
254 | writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); |
255 | |
256 | /* Compute clock setup values, see LPC and NAND manual */ |
257 | tmp = 0; |
258 | tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1); |
259 | tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1); |
260 | tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1); |
261 | tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1); |
262 | tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low); |
263 | tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1); |
264 | tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low); |
265 | writel(val: tmp, MLC_TIME_REG(host->io_base)); |
266 | |
267 | /* Enable IRQ for CONTROLLER_READY and NAND_READY */ |
268 | writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY, |
269 | MLC_IRQ_MR(host->io_base)); |
270 | |
271 | /* Normal nCE operation: nCE controlled by controller */ |
272 | writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); |
273 | } |
274 | |
275 | /* |
276 | * Hardware specific access to control lines |
277 | */ |
278 | static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd, |
279 | unsigned int ctrl) |
280 | { |
281 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip: nand_chip); |
282 | |
283 | if (cmd != NAND_CMD_NONE) { |
284 | if (ctrl & NAND_CLE) |
285 | writel(val: cmd, MLC_CMD(host->io_base)); |
286 | else |
287 | writel(val: cmd, MLC_ADDR(host->io_base)); |
288 | } |
289 | } |
290 | |
291 | /* |
292 | * Read Device Ready (NAND device _and_ controller ready) |
293 | */ |
294 | static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip) |
295 | { |
296 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip: nand_chip); |
297 | |
298 | if ((readb(MLC_ISR(host->io_base)) & |
299 | (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) == |
300 | (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) |
301 | return 1; |
302 | |
303 | return 0; |
304 | } |
305 | |
306 | static irqreturn_t lpc3xxx_nand_irq(int irq, void *data) |
307 | { |
308 | struct lpc32xx_nand_host *host = data; |
309 | uint8_t sr; |
310 | |
311 | /* Clear interrupt flag by reading status */ |
312 | sr = readb(MLC_IRQ_SR(host->io_base)); |
313 | if (sr & MLCIRQ_NAND_READY) |
314 | complete(&host->comp_nand); |
315 | if (sr & MLCIRQ_CONTROLLER_READY) |
316 | complete(&host->comp_controller); |
317 | |
318 | return IRQ_HANDLED; |
319 | } |
320 | |
321 | static int lpc32xx_waitfunc_nand(struct nand_chip *chip) |
322 | { |
323 | struct mtd_info *mtd = nand_to_mtd(chip); |
324 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
325 | |
326 | if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY) |
327 | goto exit; |
328 | |
329 | wait_for_completion(&host->comp_nand); |
330 | |
331 | while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) { |
332 | /* Seems to be delayed sometimes by controller */ |
333 | dev_dbg(&mtd->dev, "Warning: NAND not ready.\n" ); |
334 | cpu_relax(); |
335 | } |
336 | |
337 | exit: |
338 | return NAND_STATUS_READY; |
339 | } |
340 | |
341 | static int lpc32xx_waitfunc_controller(struct nand_chip *chip) |
342 | { |
343 | struct mtd_info *mtd = nand_to_mtd(chip); |
344 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
345 | |
346 | if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY) |
347 | goto exit; |
348 | |
349 | wait_for_completion(&host->comp_controller); |
350 | |
351 | while (!(readb(MLC_ISR(host->io_base)) & |
352 | MLCISR_CONTROLLER_READY)) { |
353 | dev_dbg(&mtd->dev, "Warning: Controller not ready.\n" ); |
354 | cpu_relax(); |
355 | } |
356 | |
357 | exit: |
358 | return NAND_STATUS_READY; |
359 | } |
360 | |
361 | static int lpc32xx_waitfunc(struct nand_chip *chip) |
362 | { |
363 | lpc32xx_waitfunc_nand(chip); |
364 | lpc32xx_waitfunc_controller(chip); |
365 | |
366 | return NAND_STATUS_READY; |
367 | } |
368 | |
369 | /* |
370 | * Enable NAND write protect |
371 | */ |
372 | static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) |
373 | { |
374 | if (host->wp_gpio) |
375 | gpiod_set_value_cansleep(desc: host->wp_gpio, value: 1); |
376 | } |
377 | |
378 | /* |
379 | * Disable NAND write protect |
380 | */ |
381 | static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) |
382 | { |
383 | if (host->wp_gpio) |
384 | gpiod_set_value_cansleep(desc: host->wp_gpio, value: 0); |
385 | } |
386 | |
387 | static void lpc32xx_dma_complete_func(void *completion) |
388 | { |
389 | complete(completion); |
390 | } |
391 | |
392 | static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len, |
393 | enum dma_transfer_direction dir) |
394 | { |
395 | struct nand_chip *chip = mtd_to_nand(mtd); |
396 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
397 | struct dma_async_tx_descriptor *desc; |
398 | int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
399 | int res; |
400 | |
401 | sg_init_one(&host->sgl, mem, len); |
402 | |
403 | res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, |
404 | DMA_BIDIRECTIONAL); |
405 | if (res != 1) { |
406 | dev_err(mtd->dev.parent, "Failed to map sg list\n" ); |
407 | return -ENXIO; |
408 | } |
409 | desc = dmaengine_prep_slave_sg(chan: host->dma_chan, sgl: &host->sgl, sg_len: 1, dir, |
410 | flags); |
411 | if (!desc) { |
412 | dev_err(mtd->dev.parent, "Failed to prepare slave sg\n" ); |
413 | goto out1; |
414 | } |
415 | |
416 | init_completion(x: &host->comp_dma); |
417 | desc->callback = lpc32xx_dma_complete_func; |
418 | desc->callback_param = &host->comp_dma; |
419 | |
420 | dmaengine_submit(desc); |
421 | dma_async_issue_pending(chan: host->dma_chan); |
422 | |
423 | wait_for_completion_timeout(x: &host->comp_dma, timeout: msecs_to_jiffies(m: 1000)); |
424 | |
425 | dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, |
426 | DMA_BIDIRECTIONAL); |
427 | return 0; |
428 | out1: |
429 | dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, |
430 | DMA_BIDIRECTIONAL); |
431 | return -ENXIO; |
432 | } |
433 | |
434 | static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf, |
435 | int oob_required, int page) |
436 | { |
437 | struct mtd_info *mtd = nand_to_mtd(chip); |
438 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
439 | int i, j; |
440 | uint8_t *oobbuf = chip->oob_poi; |
441 | uint32_t mlc_isr; |
442 | int res; |
443 | uint8_t *dma_buf; |
444 | bool dma_mapped; |
445 | |
446 | if ((void *)buf <= high_memory) { |
447 | dma_buf = buf; |
448 | dma_mapped = true; |
449 | } else { |
450 | dma_buf = host->dma_buf; |
451 | dma_mapped = false; |
452 | } |
453 | |
454 | /* Writing Command and Address */ |
455 | nand_read_page_op(chip, page, offset_in_page: 0, NULL, len: 0); |
456 | |
457 | /* For all sub-pages */ |
458 | for (i = 0; i < host->mlcsubpages; i++) { |
459 | /* Start Auto Decode Command */ |
460 | writeb(val: 0x00, MLC_ECC_AUTO_DEC_REG(host->io_base)); |
461 | |
462 | /* Wait for Controller Ready */ |
463 | lpc32xx_waitfunc_controller(chip); |
464 | |
465 | /* Check ECC Error status */ |
466 | mlc_isr = readl(MLC_ISR(host->io_base)); |
467 | if (mlc_isr & MLCISR_DECODER_FAILURE) { |
468 | mtd->ecc_stats.failed++; |
469 | dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n" , __func__); |
470 | } else if (mlc_isr & MLCISR_ERRORS_DETECTED) { |
471 | mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1; |
472 | } |
473 | |
474 | /* Read 512 + 16 Bytes */ |
475 | if (use_dma) { |
476 | res = lpc32xx_xmit_dma(mtd, mem: dma_buf + i * 512, len: 512, |
477 | dir: DMA_DEV_TO_MEM); |
478 | if (res) |
479 | return res; |
480 | } else { |
481 | for (j = 0; j < (512 >> 2); j++) { |
482 | *((uint32_t *)(buf)) = |
483 | readl(MLC_BUFF(host->io_base)); |
484 | buf += 4; |
485 | } |
486 | } |
487 | for (j = 0; j < (16 >> 2); j++) { |
488 | *((uint32_t *)(oobbuf)) = |
489 | readl(MLC_BUFF(host->io_base)); |
490 | oobbuf += 4; |
491 | } |
492 | } |
493 | |
494 | if (use_dma && !dma_mapped) |
495 | memcpy(buf, dma_buf, mtd->writesize); |
496 | |
497 | return 0; |
498 | } |
499 | |
500 | static int lpc32xx_write_page_lowlevel(struct nand_chip *chip, |
501 | const uint8_t *buf, int oob_required, |
502 | int page) |
503 | { |
504 | struct mtd_info *mtd = nand_to_mtd(chip); |
505 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
506 | const uint8_t *oobbuf = chip->oob_poi; |
507 | uint8_t *dma_buf = (uint8_t *)buf; |
508 | int res; |
509 | int i, j; |
510 | |
511 | if (use_dma && (void *)buf >= high_memory) { |
512 | dma_buf = host->dma_buf; |
513 | memcpy(dma_buf, buf, mtd->writesize); |
514 | } |
515 | |
516 | nand_prog_page_begin_op(chip, page, offset_in_page: 0, NULL, len: 0); |
517 | |
518 | for (i = 0; i < host->mlcsubpages; i++) { |
519 | /* Start Encode */ |
520 | writeb(val: 0x00, MLC_ECC_ENC_REG(host->io_base)); |
521 | |
522 | /* Write 512 + 6 Bytes to Buffer */ |
523 | if (use_dma) { |
524 | res = lpc32xx_xmit_dma(mtd, mem: dma_buf + i * 512, len: 512, |
525 | dir: DMA_MEM_TO_DEV); |
526 | if (res) |
527 | return res; |
528 | } else { |
529 | for (j = 0; j < (512 >> 2); j++) { |
530 | writel(val: *((uint32_t *)(buf)), |
531 | MLC_BUFF(host->io_base)); |
532 | buf += 4; |
533 | } |
534 | } |
535 | writel(val: *((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base)); |
536 | oobbuf += 4; |
537 | writew(val: *((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base)); |
538 | oobbuf += 12; |
539 | |
540 | /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ |
541 | writeb(val: 0x00, MLC_ECC_AUTO_ENC_REG(host->io_base)); |
542 | |
543 | /* Wait for Controller Ready */ |
544 | lpc32xx_waitfunc_controller(chip); |
545 | } |
546 | |
547 | return nand_prog_page_end_op(chip); |
548 | } |
549 | |
550 | static int lpc32xx_read_oob(struct nand_chip *chip, int page) |
551 | { |
552 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
553 | |
554 | /* Read whole page - necessary with MLC controller! */ |
555 | lpc32xx_read_page(chip, buf: host->dummy_buf, oob_required: 1, page); |
556 | |
557 | return 0; |
558 | } |
559 | |
560 | static int lpc32xx_write_oob(struct nand_chip *chip, int page) |
561 | { |
562 | /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ |
563 | return 0; |
564 | } |
565 | |
566 | /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */ |
567 | static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode) |
568 | { |
569 | /* Always enabled! */ |
570 | } |
571 | |
572 | static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host) |
573 | { |
574 | struct mtd_info *mtd = nand_to_mtd(chip: &host->nand_chip); |
575 | dma_cap_mask_t mask; |
576 | |
577 | if (!host->pdata || !host->pdata->dma_filter) { |
578 | dev_err(mtd->dev.parent, "no DMA platform data\n" ); |
579 | return -ENOENT; |
580 | } |
581 | |
582 | dma_cap_zero(mask); |
583 | dma_cap_set(DMA_SLAVE, mask); |
584 | host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, |
585 | "nand-mlc" ); |
586 | if (!host->dma_chan) { |
587 | dev_err(mtd->dev.parent, "Failed to request DMA channel\n" ); |
588 | return -EBUSY; |
589 | } |
590 | |
591 | /* |
592 | * Set direction to a sensible value even if the dmaengine driver |
593 | * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x |
594 | * driver criticizes it as "alien transfer direction". |
595 | */ |
596 | host->dma_slave_config.direction = DMA_DEV_TO_MEM; |
597 | host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
598 | host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
599 | host->dma_slave_config.src_maxburst = 128; |
600 | host->dma_slave_config.dst_maxburst = 128; |
601 | /* DMA controller does flow control: */ |
602 | host->dma_slave_config.device_fc = false; |
603 | host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy); |
604 | host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy); |
605 | if (dmaengine_slave_config(chan: host->dma_chan, config: &host->dma_slave_config)) { |
606 | dev_err(mtd->dev.parent, "Failed to setup DMA slave\n" ); |
607 | goto out1; |
608 | } |
609 | |
610 | return 0; |
611 | out1: |
612 | dma_release_channel(chan: host->dma_chan); |
613 | return -ENXIO; |
614 | } |
615 | |
616 | static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev) |
617 | { |
618 | struct lpc32xx_nand_cfg_mlc *ncfg; |
619 | struct device_node *np = dev->of_node; |
620 | |
621 | ncfg = devm_kzalloc(dev, size: sizeof(*ncfg), GFP_KERNEL); |
622 | if (!ncfg) |
623 | return NULL; |
624 | |
625 | of_property_read_u32(np, propname: "nxp,tcea-delay" , out_value: &ncfg->tcea_delay); |
626 | of_property_read_u32(np, propname: "nxp,busy-delay" , out_value: &ncfg->busy_delay); |
627 | of_property_read_u32(np, propname: "nxp,nand-ta" , out_value: &ncfg->nand_ta); |
628 | of_property_read_u32(np, propname: "nxp,rd-high" , out_value: &ncfg->rd_high); |
629 | of_property_read_u32(np, propname: "nxp,rd-low" , out_value: &ncfg->rd_low); |
630 | of_property_read_u32(np, propname: "nxp,wr-high" , out_value: &ncfg->wr_high); |
631 | of_property_read_u32(np, propname: "nxp,wr-low" , out_value: &ncfg->wr_low); |
632 | |
633 | if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta || |
634 | !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high || |
635 | !ncfg->wr_low) { |
636 | dev_err(dev, "chip parameters not specified correctly\n" ); |
637 | return NULL; |
638 | } |
639 | |
640 | return ncfg; |
641 | } |
642 | |
643 | static int lpc32xx_nand_attach_chip(struct nand_chip *chip) |
644 | { |
645 | struct mtd_info *mtd = nand_to_mtd(chip); |
646 | struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
647 | struct device *dev = &host->pdev->dev; |
648 | |
649 | if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) |
650 | return 0; |
651 | |
652 | host->dma_buf = devm_kzalloc(dev, size: mtd->writesize, GFP_KERNEL); |
653 | if (!host->dma_buf) |
654 | return -ENOMEM; |
655 | |
656 | host->dummy_buf = devm_kzalloc(dev, size: mtd->writesize, GFP_KERNEL); |
657 | if (!host->dummy_buf) |
658 | return -ENOMEM; |
659 | |
660 | chip->ecc.size = 512; |
661 | chip->ecc.hwctl = lpc32xx_ecc_enable; |
662 | chip->ecc.read_page_raw = lpc32xx_read_page; |
663 | chip->ecc.read_page = lpc32xx_read_page; |
664 | chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel; |
665 | chip->ecc.write_page = lpc32xx_write_page_lowlevel; |
666 | chip->ecc.write_oob = lpc32xx_write_oob; |
667 | chip->ecc.read_oob = lpc32xx_read_oob; |
668 | chip->ecc.strength = 4; |
669 | chip->ecc.bytes = 10; |
670 | |
671 | mtd_set_ooblayout(mtd, ooblayout: &lpc32xx_ooblayout_ops); |
672 | host->mlcsubpages = mtd->writesize / 512; |
673 | |
674 | return 0; |
675 | } |
676 | |
677 | static const struct nand_controller_ops lpc32xx_nand_controller_ops = { |
678 | .attach_chip = lpc32xx_nand_attach_chip, |
679 | }; |
680 | |
681 | /* |
682 | * Probe for NAND controller |
683 | */ |
684 | static int lpc32xx_nand_probe(struct platform_device *pdev) |
685 | { |
686 | struct lpc32xx_nand_host *host; |
687 | struct mtd_info *mtd; |
688 | struct nand_chip *nand_chip; |
689 | struct resource *rc; |
690 | int res; |
691 | |
692 | /* Allocate memory for the device structure (and zero it) */ |
693 | host = devm_kzalloc(dev: &pdev->dev, size: sizeof(*host), GFP_KERNEL); |
694 | if (!host) |
695 | return -ENOMEM; |
696 | |
697 | host->pdev = pdev; |
698 | |
699 | host->io_base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &rc); |
700 | if (IS_ERR(ptr: host->io_base)) |
701 | return PTR_ERR(ptr: host->io_base); |
702 | |
703 | host->io_base_phy = rc->start; |
704 | |
705 | nand_chip = &host->nand_chip; |
706 | mtd = nand_to_mtd(chip: nand_chip); |
707 | if (pdev->dev.of_node) |
708 | host->ncfg = lpc32xx_parse_dt(dev: &pdev->dev); |
709 | if (!host->ncfg) { |
710 | dev_err(&pdev->dev, |
711 | "Missing or bad NAND config from device tree\n" ); |
712 | return -ENOENT; |
713 | } |
714 | |
715 | /* Start with WP disabled, if available */ |
716 | host->wp_gpio = gpiod_get_optional(dev: &pdev->dev, NULL, flags: GPIOD_OUT_LOW); |
717 | res = PTR_ERR_OR_ZERO(ptr: host->wp_gpio); |
718 | if (res) { |
719 | if (res != -EPROBE_DEFER) |
720 | dev_err(&pdev->dev, "WP GPIO is not available: %d\n" , |
721 | res); |
722 | return res; |
723 | } |
724 | |
725 | gpiod_set_consumer_name(desc: host->wp_gpio, name: "NAND WP" ); |
726 | |
727 | host->pdata = dev_get_platdata(dev: &pdev->dev); |
728 | |
729 | /* link the private data structures */ |
730 | nand_set_controller_data(chip: nand_chip, priv: host); |
731 | nand_set_flash_node(chip: nand_chip, np: pdev->dev.of_node); |
732 | mtd->dev.parent = &pdev->dev; |
733 | |
734 | /* Get NAND clock */ |
735 | host->clk = clk_get(dev: &pdev->dev, NULL); |
736 | if (IS_ERR(ptr: host->clk)) { |
737 | dev_err(&pdev->dev, "Clock initialization failure\n" ); |
738 | res = -ENOENT; |
739 | goto free_gpio; |
740 | } |
741 | res = clk_prepare_enable(clk: host->clk); |
742 | if (res) |
743 | goto put_clk; |
744 | |
745 | nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl; |
746 | nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready; |
747 | nand_chip->legacy.chip_delay = 25; /* us */ |
748 | nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base); |
749 | nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base); |
750 | |
751 | /* Init NAND controller */ |
752 | lpc32xx_nand_setup(host); |
753 | |
754 | platform_set_drvdata(pdev, data: host); |
755 | |
756 | /* Initialize function pointers */ |
757 | nand_chip->legacy.waitfunc = lpc32xx_waitfunc; |
758 | |
759 | nand_chip->options = NAND_NO_SUBPAGE_WRITE; |
760 | nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; |
761 | nand_chip->bbt_td = &lpc32xx_nand_bbt; |
762 | nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror; |
763 | |
764 | if (use_dma) { |
765 | res = lpc32xx_dma_setup(host); |
766 | if (res) { |
767 | res = -EIO; |
768 | goto unprepare_clk; |
769 | } |
770 | } |
771 | |
772 | /* initially clear interrupt status */ |
773 | readb(MLC_IRQ_SR(host->io_base)); |
774 | |
775 | init_completion(x: &host->comp_nand); |
776 | init_completion(x: &host->comp_controller); |
777 | |
778 | host->irq = platform_get_irq(pdev, 0); |
779 | if (host->irq < 0) { |
780 | res = -EINVAL; |
781 | goto release_dma_chan; |
782 | } |
783 | |
784 | if (request_irq(irq: host->irq, handler: &lpc3xxx_nand_irq, |
785 | IRQF_TRIGGER_HIGH, DRV_NAME, dev: host)) { |
786 | dev_err(&pdev->dev, "Error requesting NAND IRQ\n" ); |
787 | res = -ENXIO; |
788 | goto release_dma_chan; |
789 | } |
790 | |
791 | /* |
792 | * Scan to find existence of the device and get the type of NAND device: |
793 | * SMALL block or LARGE block. |
794 | */ |
795 | nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops; |
796 | res = nand_scan(chip: nand_chip, max_chips: 1); |
797 | if (res) |
798 | goto free_irq; |
799 | |
800 | mtd->name = DRV_NAME; |
801 | |
802 | res = mtd_device_register(mtd, host->ncfg->parts, |
803 | host->ncfg->num_parts); |
804 | if (res) |
805 | goto cleanup_nand; |
806 | |
807 | return 0; |
808 | |
809 | cleanup_nand: |
810 | nand_cleanup(chip: nand_chip); |
811 | free_irq: |
812 | free_irq(host->irq, host); |
813 | release_dma_chan: |
814 | if (use_dma) |
815 | dma_release_channel(chan: host->dma_chan); |
816 | unprepare_clk: |
817 | clk_disable_unprepare(clk: host->clk); |
818 | put_clk: |
819 | clk_put(clk: host->clk); |
820 | free_gpio: |
821 | lpc32xx_wp_enable(host); |
822 | gpiod_put(desc: host->wp_gpio); |
823 | |
824 | return res; |
825 | } |
826 | |
827 | /* |
828 | * Remove NAND device |
829 | */ |
830 | static void lpc32xx_nand_remove(struct platform_device *pdev) |
831 | { |
832 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
833 | struct nand_chip *chip = &host->nand_chip; |
834 | int ret; |
835 | |
836 | ret = mtd_device_unregister(master: nand_to_mtd(chip)); |
837 | WARN_ON(ret); |
838 | nand_cleanup(chip); |
839 | |
840 | free_irq(host->irq, host); |
841 | if (use_dma) |
842 | dma_release_channel(chan: host->dma_chan); |
843 | |
844 | clk_disable_unprepare(clk: host->clk); |
845 | clk_put(clk: host->clk); |
846 | |
847 | lpc32xx_wp_enable(host); |
848 | gpiod_put(desc: host->wp_gpio); |
849 | } |
850 | |
851 | static int lpc32xx_nand_resume(struct platform_device *pdev) |
852 | { |
853 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
854 | int ret; |
855 | |
856 | /* Re-enable NAND clock */ |
857 | ret = clk_prepare_enable(clk: host->clk); |
858 | if (ret) |
859 | return ret; |
860 | |
861 | /* Fresh init of NAND controller */ |
862 | lpc32xx_nand_setup(host); |
863 | |
864 | /* Disable write protect */ |
865 | lpc32xx_wp_disable(host); |
866 | |
867 | return 0; |
868 | } |
869 | |
870 | static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) |
871 | { |
872 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
873 | |
874 | /* Enable write protect for safety */ |
875 | lpc32xx_wp_enable(host); |
876 | |
877 | /* Disable clock */ |
878 | clk_disable_unprepare(clk: host->clk); |
879 | return 0; |
880 | } |
881 | |
882 | static const struct of_device_id lpc32xx_nand_match[] = { |
883 | { .compatible = "nxp,lpc3220-mlc" }, |
884 | { /* sentinel */ }, |
885 | }; |
886 | MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); |
887 | |
888 | static struct platform_driver lpc32xx_nand_driver = { |
889 | .probe = lpc32xx_nand_probe, |
890 | .remove_new = lpc32xx_nand_remove, |
891 | .resume = pm_ptr(lpc32xx_nand_resume), |
892 | .suspend = pm_ptr(lpc32xx_nand_suspend), |
893 | .driver = { |
894 | .name = DRV_NAME, |
895 | .of_match_table = lpc32xx_nand_match, |
896 | }, |
897 | }; |
898 | |
899 | module_platform_driver(lpc32xx_nand_driver); |
900 | |
901 | MODULE_LICENSE("GPL" ); |
902 | MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>" ); |
903 | MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller" ); |
904 | |