1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Marvell RVU Admin Function driver |
3 | * |
4 | * Copyright (C) 2018 Marvell. |
5 | * |
6 | */ |
7 | |
8 | #include <linux/bitfield.h> |
9 | #include <linux/module.h> |
10 | #include <linux/pci.h> |
11 | |
12 | #include "rvu_struct.h" |
13 | #include "rvu_reg.h" |
14 | #include "rvu.h" |
15 | #include "npc.h" |
16 | #include "cgx.h" |
17 | #include "npc_profile.h" |
18 | #include "rvu_npc_hash.h" |
19 | |
20 | #define RSVD_MCAM_ENTRIES_PER_PF 3 /* Broadcast, Promisc and AllMulticast */ |
21 | #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */ |
22 | |
23 | #define NPC_PARSE_RESULT_DMAC_OFFSET 8 |
24 | #define NPC_HW_TSTAMP_OFFSET 8ULL |
25 | #define NPC_KEX_CHAN_MASK 0xFFFULL |
26 | #define NPC_KEX_PF_FUNC_MASK 0xFFFFULL |
27 | |
28 | #define ALIGN_8B_CEIL(__a) (((__a) + 7) & (-8)) |
29 | |
30 | static const char def_pfl_name[] = "default" ; |
31 | |
32 | static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, |
33 | int blkaddr, u16 pcifunc); |
34 | static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, |
35 | u16 pcifunc); |
36 | |
37 | bool is_npc_intf_tx(u8 intf) |
38 | { |
39 | return !!(intf & 0x1); |
40 | } |
41 | |
42 | bool is_npc_intf_rx(u8 intf) |
43 | { |
44 | return !(intf & 0x1); |
45 | } |
46 | |
47 | bool is_npc_interface_valid(struct rvu *rvu, u8 intf) |
48 | { |
49 | struct rvu_hwinfo *hw = rvu->hw; |
50 | |
51 | return intf < hw->npc_intfs; |
52 | } |
53 | |
54 | int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena) |
55 | { |
56 | /* Due to a HW issue in these silicon versions, parse nibble enable |
57 | * configuration has to be identical for both Rx and Tx interfaces. |
58 | */ |
59 | if (is_rvu_96xx_B0(rvu)) |
60 | return nibble_ena; |
61 | return 0; |
62 | } |
63 | |
64 | void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) |
65 | { |
66 | int blkaddr; |
67 | u64 val = 0; |
68 | |
69 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
70 | if (blkaddr < 0) |
71 | return; |
72 | |
73 | /* Config CPI base for the PKIND */ |
74 | val = pkind | 1ULL << 62; |
75 | rvu_write64(rvu, block: blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); |
76 | } |
77 | |
78 | int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) |
79 | { |
80 | struct npc_pkind *pkind = &rvu->hw->pkind; |
81 | u32 map; |
82 | int i; |
83 | |
84 | for (i = 0; i < pkind->rsrc.max; i++) { |
85 | map = pkind->pfchan_map[i]; |
86 | if (((map >> 16) & 0x3F) == pf) |
87 | return i; |
88 | } |
89 | return -1; |
90 | } |
91 | |
92 | #define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20) |
93 | |
94 | int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable) |
95 | { |
96 | int pkind, blkaddr; |
97 | u64 val; |
98 | |
99 | pkind = rvu_npc_get_pkind(rvu, pf); |
100 | if (pkind < 0) { |
101 | dev_err(rvu->dev, "%s: pkind not mapped\n" , __func__); |
102 | return -EINVAL; |
103 | } |
104 | |
105 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc); |
106 | if (blkaddr < 0) { |
107 | dev_err(rvu->dev, "%s: NPC block not implemented\n" , __func__); |
108 | return -EINVAL; |
109 | } |
110 | |
111 | val = rvu_read64(rvu, block: blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); |
112 | val &= ~NPC_AF_ACTION0_PTR_ADVANCE; |
113 | /* If timestamp is enabled then configure NPC to shift 8 bytes */ |
114 | if (enable) |
115 | val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE, |
116 | NPC_HW_TSTAMP_OFFSET); |
117 | rvu_write64(rvu, block: blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); |
118 | |
119 | return 0; |
120 | } |
121 | |
122 | static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc, |
123 | int nixlf) |
124 | { |
125 | struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam); |
126 | struct rvu *rvu = hw->rvu; |
127 | int blkaddr = 0, max = 0; |
128 | struct rvu_block *block; |
129 | struct rvu_pfvf *pfvf; |
130 | |
131 | pfvf = rvu_get_pfvf(rvu, pcifunc); |
132 | /* Given a PF/VF and NIX LF number calculate the unicast mcam |
133 | * entry index based on the NIX block assigned to the PF/VF. |
134 | */ |
135 | blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); |
136 | while (blkaddr) { |
137 | if (pfvf->nix_blkaddr == blkaddr) |
138 | break; |
139 | block = &rvu->hw->block[blkaddr]; |
140 | max += block->lf.max; |
141 | blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); |
142 | } |
143 | |
144 | return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF; |
145 | } |
146 | |
147 | int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, |
148 | u16 pcifunc, int nixlf, int type) |
149 | { |
150 | int pf = rvu_get_pf(pcifunc); |
151 | int index; |
152 | |
153 | /* Check if this is for a PF */ |
154 | if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) { |
155 | /* Reserved entries exclude PF0 */ |
156 | pf--; |
157 | index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF); |
158 | /* Broadcast address matching entry should be first so |
159 | * that the packet can be replicated to all VFs. |
160 | */ |
161 | if (type == NIXLF_BCAST_ENTRY) |
162 | return index; |
163 | else if (type == NIXLF_ALLMULTI_ENTRY) |
164 | return index + 1; |
165 | else if (type == NIXLF_PROMISC_ENTRY) |
166 | return index + 2; |
167 | } |
168 | |
169 | return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf); |
170 | } |
171 | |
172 | int npc_get_bank(struct npc_mcam *mcam, int index) |
173 | { |
174 | int bank = index / mcam->banksize; |
175 | |
176 | /* 0,1 & 2,3 banks are combined for this keysize */ |
177 | if (mcam->keysize == NPC_MCAM_KEY_X2) |
178 | return bank ? 2 : 0; |
179 | |
180 | return bank; |
181 | } |
182 | |
183 | bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, |
184 | int blkaddr, int index) |
185 | { |
186 | int bank = npc_get_bank(mcam, index); |
187 | u64 cfg; |
188 | |
189 | index &= (mcam->banksize - 1); |
190 | cfg = rvu_read64(rvu, block: blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); |
191 | return (cfg & 1); |
192 | } |
193 | |
194 | void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, |
195 | int blkaddr, int index, bool enable) |
196 | { |
197 | int bank = npc_get_bank(mcam, index); |
198 | int actbank = bank; |
199 | |
200 | index &= (mcam->banksize - 1); |
201 | for (; bank < (actbank + mcam->banks_per_entry); bank++) { |
202 | rvu_write64(rvu, block: blkaddr, |
203 | NPC_AF_MCAMEX_BANKX_CFG(index, bank), |
204 | val: enable ? 1 : 0); |
205 | } |
206 | } |
207 | |
208 | static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, |
209 | int blkaddr, int index) |
210 | { |
211 | int bank = npc_get_bank(mcam, index); |
212 | int actbank = bank; |
213 | |
214 | index &= (mcam->banksize - 1); |
215 | for (; bank < (actbank + mcam->banks_per_entry); bank++) { |
216 | rvu_write64(rvu, block: blkaddr, |
217 | NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), val: 0); |
218 | rvu_write64(rvu, block: blkaddr, |
219 | NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), val: 0); |
220 | |
221 | rvu_write64(rvu, block: blkaddr, |
222 | NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), val: 0); |
223 | rvu_write64(rvu, block: blkaddr, |
224 | NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), val: 0); |
225 | |
226 | rvu_write64(rvu, block: blkaddr, |
227 | NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), val: 0); |
228 | rvu_write64(rvu, block: blkaddr, |
229 | NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), val: 0); |
230 | } |
231 | } |
232 | |
233 | static void npc_get_keyword(struct mcam_entry *entry, int idx, |
234 | u64 *cam0, u64 *cam1) |
235 | { |
236 | u64 kw_mask = 0x00; |
237 | |
238 | #define CAM_MASK(n) (BIT_ULL(n) - 1) |
239 | |
240 | /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and |
241 | * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1. |
242 | * |
243 | * Also, only 48 bits of BANKX_CAMX_W1 are valid. |
244 | */ |
245 | switch (idx) { |
246 | case 0: |
247 | /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */ |
248 | *cam1 = entry->kw[0]; |
249 | kw_mask = entry->kw_mask[0]; |
250 | break; |
251 | case 1: |
252 | /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */ |
253 | *cam1 = entry->kw[1] & CAM_MASK(48); |
254 | kw_mask = entry->kw_mask[1] & CAM_MASK(48); |
255 | break; |
256 | case 2: |
257 | /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48> |
258 | * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0> |
259 | */ |
260 | *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16); |
261 | *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16); |
262 | kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16); |
263 | kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16); |
264 | break; |
265 | case 3: |
266 | /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48> |
267 | * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0> |
268 | */ |
269 | *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16); |
270 | *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16); |
271 | kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16); |
272 | kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16); |
273 | break; |
274 | case 4: |
275 | /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32> |
276 | * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0> |
277 | */ |
278 | *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32); |
279 | *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32); |
280 | kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32); |
281 | kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32); |
282 | break; |
283 | case 5: |
284 | /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32> |
285 | * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0> |
286 | */ |
287 | *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32); |
288 | *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32); |
289 | kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32); |
290 | kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32); |
291 | break; |
292 | case 6: |
293 | /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16> |
294 | * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0> |
295 | */ |
296 | *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48); |
297 | *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48); |
298 | kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48); |
299 | kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48); |
300 | break; |
301 | case 7: |
302 | /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */ |
303 | *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48); |
304 | kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48); |
305 | break; |
306 | } |
307 | |
308 | *cam1 &= kw_mask; |
309 | *cam0 = ~*cam1 & kw_mask; |
310 | } |
311 | |
312 | static void npc_fill_entryword(struct mcam_entry *entry, int idx, |
313 | u64 cam0, u64 cam1) |
314 | { |
315 | /* Similar to npc_get_keyword, but fills mcam_entry structure from |
316 | * CAM registers. |
317 | */ |
318 | switch (idx) { |
319 | case 0: |
320 | entry->kw[0] = cam1; |
321 | entry->kw_mask[0] = cam1 ^ cam0; |
322 | break; |
323 | case 1: |
324 | entry->kw[1] = cam1; |
325 | entry->kw_mask[1] = cam1 ^ cam0; |
326 | break; |
327 | case 2: |
328 | entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48; |
329 | entry->kw[2] = (cam1 >> 16) & CAM_MASK(48); |
330 | entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; |
331 | entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48); |
332 | break; |
333 | case 3: |
334 | entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48; |
335 | entry->kw[3] = (cam1 >> 16) & CAM_MASK(32); |
336 | entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; |
337 | entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32); |
338 | break; |
339 | case 4: |
340 | entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32; |
341 | entry->kw[4] = (cam1 >> 32) & CAM_MASK(32); |
342 | entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; |
343 | entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32); |
344 | break; |
345 | case 5: |
346 | entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32; |
347 | entry->kw[5] = (cam1 >> 32) & CAM_MASK(16); |
348 | entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; |
349 | entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16); |
350 | break; |
351 | case 6: |
352 | entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16; |
353 | entry->kw[6] = (cam1 >> 48) & CAM_MASK(16); |
354 | entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; |
355 | entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16); |
356 | break; |
357 | case 7: |
358 | entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16; |
359 | entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; |
360 | break; |
361 | } |
362 | } |
363 | |
364 | static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam, |
365 | int blkaddr, u16 pf_func) |
366 | { |
367 | int bank, nixlf, index; |
368 | |
369 | /* get ucast entry rule entry index */ |
370 | if (nix_get_nixlf(rvu, pcifunc: pf_func, nixlf: &nixlf, NULL)) { |
371 | dev_err(rvu->dev, "%s: nixlf not attached to pcifunc:0x%x\n" , |
372 | __func__, pf_func); |
373 | /* Action 0 is drop */ |
374 | return 0; |
375 | } |
376 | |
377 | index = npc_get_nixlf_mcam_index(mcam, pcifunc: pf_func, nixlf, |
378 | NIXLF_UCAST_ENTRY); |
379 | bank = npc_get_bank(mcam, index); |
380 | index &= (mcam->banksize - 1); |
381 | |
382 | return rvu_read64(rvu, block: blkaddr, |
383 | NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); |
384 | } |
385 | |
386 | static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam, |
387 | int blkaddr, int index, struct mcam_entry *entry, |
388 | bool *enable) |
389 | { |
390 | struct rvu_npc_mcam_rule *rule; |
391 | u16 owner, target_func; |
392 | struct rvu_pfvf *pfvf; |
393 | u64 rx_action; |
394 | |
395 | owner = mcam->entry2pfvf_map[index]; |
396 | target_func = (entry->action >> 4) & 0xffff; |
397 | /* do nothing when target is LBK/PF or owner is not PF */ |
398 | if (is_pffunc_af(pcifunc: owner) || is_lbk_vf(rvu, pcifunc: target_func) || |
399 | (owner & RVU_PFVF_FUNC_MASK) || |
400 | !(target_func & RVU_PFVF_FUNC_MASK)) |
401 | return; |
402 | |
403 | /* save entry2target_pffunc */ |
404 | pfvf = rvu_get_pfvf(rvu, pcifunc: target_func); |
405 | mcam->entry2target_pffunc[index] = target_func; |
406 | |
407 | /* don't enable rule when nixlf not attached or initialized */ |
408 | if (!(is_nixlf_attached(rvu, pcifunc: target_func) && |
409 | test_bit(NIXLF_INITIALIZED, &pfvf->flags))) |
410 | *enable = false; |
411 | |
412 | /* fix up not needed for the rules added by user(ntuple filters) */ |
413 | list_for_each_entry(rule, &mcam->mcam_rules, list) { |
414 | if (rule->entry == index) |
415 | return; |
416 | } |
417 | |
418 | /* AF modifies given action iff PF/VF has requested for it */ |
419 | if ((entry->action & 0xFULL) != NIX_RX_ACTION_DEFAULT) |
420 | return; |
421 | |
422 | /* copy VF default entry action to the VF mcam entry */ |
423 | rx_action = npc_get_default_entry_action(rvu, mcam, blkaddr, |
424 | pf_func: target_func); |
425 | if (rx_action) |
426 | entry->action = rx_action; |
427 | } |
428 | |
429 | static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, |
430 | int blkaddr, int index, u8 intf, |
431 | struct mcam_entry *entry, bool enable) |
432 | { |
433 | int bank = npc_get_bank(mcam, index); |
434 | int kw = 0, actbank, actindex; |
435 | u8 tx_intf_mask = ~intf & 0x3; |
436 | u8 tx_intf = intf; |
437 | u64 cam0, cam1; |
438 | |
439 | actbank = bank; /* Save bank id, to set action later on */ |
440 | actindex = index; |
441 | index &= (mcam->banksize - 1); |
442 | |
443 | /* Disable before mcam entry update */ |
444 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: actindex, enable: false); |
445 | |
446 | /* Clear mcam entry to avoid writes being suppressed by NPC */ |
447 | npc_clear_mcam_entry(rvu, mcam, blkaddr, index: actindex); |
448 | |
449 | /* CAM1 takes the comparison value and |
450 | * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'. |
451 | * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0 |
452 | * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1 |
453 | * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare. |
454 | */ |
455 | for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) { |
456 | /* Interface should be set in all banks */ |
457 | if (is_npc_intf_tx(intf)) { |
458 | /* Last bit must be set and rest don't care |
459 | * for TX interfaces |
460 | */ |
461 | tx_intf_mask = 0x1; |
462 | tx_intf = intf & tx_intf_mask; |
463 | tx_intf_mask = ~tx_intf & tx_intf_mask; |
464 | } |
465 | |
466 | rvu_write64(rvu, block: blkaddr, |
467 | NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), |
468 | val: tx_intf); |
469 | rvu_write64(rvu, block: blkaddr, |
470 | NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), |
471 | val: tx_intf_mask); |
472 | |
473 | /* Set the match key */ |
474 | npc_get_keyword(entry, idx: kw, cam0: &cam0, cam1: &cam1); |
475 | rvu_write64(rvu, block: blkaddr, |
476 | NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), val: cam1); |
477 | rvu_write64(rvu, block: blkaddr, |
478 | NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), val: cam0); |
479 | |
480 | npc_get_keyword(entry, idx: kw + 1, cam0: &cam0, cam1: &cam1); |
481 | rvu_write64(rvu, block: blkaddr, |
482 | NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), val: cam1); |
483 | rvu_write64(rvu, block: blkaddr, |
484 | NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), val: cam0); |
485 | } |
486 | |
487 | /* PF installing VF rule */ |
488 | if (is_npc_intf_rx(intf) && actindex < mcam->bmap_entries) |
489 | npc_fixup_vf_rule(rvu, mcam, blkaddr, index: actindex, entry, enable: &enable); |
490 | |
491 | /* Set 'action' */ |
492 | rvu_write64(rvu, block: blkaddr, |
493 | NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), val: entry->action); |
494 | |
495 | /* Set TAG 'action' */ |
496 | rvu_write64(rvu, block: blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), |
497 | val: entry->vtag_action); |
498 | |
499 | /* Enable the entry */ |
500 | if (enable) |
501 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: actindex, enable: true); |
502 | } |
503 | |
504 | void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, |
505 | int blkaddr, u16 src, |
506 | struct mcam_entry *entry, u8 *intf, u8 *ena) |
507 | { |
508 | int sbank = npc_get_bank(mcam, index: src); |
509 | int bank, kw = 0; |
510 | u64 cam0, cam1; |
511 | |
512 | src &= (mcam->banksize - 1); |
513 | bank = sbank; |
514 | |
515 | for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) { |
516 | cam1 = rvu_read64(rvu, block: blkaddr, |
517 | NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1)); |
518 | cam0 = rvu_read64(rvu, block: blkaddr, |
519 | NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0)); |
520 | npc_fill_entryword(entry, idx: kw, cam0, cam1); |
521 | |
522 | cam1 = rvu_read64(rvu, block: blkaddr, |
523 | NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1)); |
524 | cam0 = rvu_read64(rvu, block: blkaddr, |
525 | NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0)); |
526 | npc_fill_entryword(entry, idx: kw + 1, cam0, cam1); |
527 | } |
528 | |
529 | entry->action = rvu_read64(rvu, block: blkaddr, |
530 | NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); |
531 | entry->vtag_action = |
532 | rvu_read64(rvu, block: blkaddr, |
533 | NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); |
534 | *intf = rvu_read64(rvu, block: blkaddr, |
535 | NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3; |
536 | *ena = rvu_read64(rvu, block: blkaddr, |
537 | NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1; |
538 | } |
539 | |
540 | static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, |
541 | int blkaddr, u16 src, u16 dest) |
542 | { |
543 | int dbank = npc_get_bank(mcam, index: dest); |
544 | int sbank = npc_get_bank(mcam, index: src); |
545 | u64 cfg, sreg, dreg; |
546 | int bank, i; |
547 | |
548 | src &= (mcam->banksize - 1); |
549 | dest &= (mcam->banksize - 1); |
550 | |
551 | /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */ |
552 | for (bank = 0; bank < mcam->banks_per_entry; bank++) { |
553 | sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0); |
554 | dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0); |
555 | for (i = 0; i < 6; i++) { |
556 | cfg = rvu_read64(rvu, block: blkaddr, offset: sreg + (i * 8)); |
557 | rvu_write64(rvu, block: blkaddr, offset: dreg + (i * 8), val: cfg); |
558 | } |
559 | } |
560 | |
561 | /* Copy action */ |
562 | cfg = rvu_read64(rvu, block: blkaddr, |
563 | NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); |
564 | rvu_write64(rvu, block: blkaddr, |
565 | NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), val: cfg); |
566 | |
567 | /* Copy TAG action */ |
568 | cfg = rvu_read64(rvu, block: blkaddr, |
569 | NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); |
570 | rvu_write64(rvu, block: blkaddr, |
571 | NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), val: cfg); |
572 | |
573 | /* Enable or disable */ |
574 | cfg = rvu_read64(rvu, block: blkaddr, |
575 | NPC_AF_MCAMEX_BANKX_CFG(src, sbank)); |
576 | rvu_write64(rvu, block: blkaddr, |
577 | NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), val: cfg); |
578 | } |
579 | |
580 | u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, |
581 | int blkaddr, int index) |
582 | { |
583 | int bank = npc_get_bank(mcam, index); |
584 | |
585 | index &= (mcam->banksize - 1); |
586 | return rvu_read64(rvu, block: blkaddr, |
587 | NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); |
588 | } |
589 | |
590 | void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, |
591 | int blkaddr, int index, u64 cfg) |
592 | { |
593 | int bank = npc_get_bank(mcam, index); |
594 | |
595 | index &= (mcam->banksize - 1); |
596 | return rvu_write64(rvu, block: blkaddr, |
597 | NPC_AF_MCAMEX_BANKX_ACTION(index, bank), val: cfg); |
598 | } |
599 | |
600 | void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, |
601 | int nixlf, u64 chan, u8 *mac_addr) |
602 | { |
603 | struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); |
604 | struct npc_install_flow_req req = { 0 }; |
605 | struct npc_install_flow_rsp rsp = { 0 }; |
606 | struct npc_mcam *mcam = &rvu->hw->mcam; |
607 | struct nix_rx_action action = { 0 }; |
608 | int blkaddr, index; |
609 | |
610 | /* AF's and SDP VFs work in promiscuous mode */ |
611 | if (is_lbk_vf(rvu, pcifunc) || is_sdp_vf(rvu, pcifunc)) |
612 | return; |
613 | |
614 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
615 | if (blkaddr < 0) |
616 | return; |
617 | |
618 | /* Ucast rule should not be installed if DMAC |
619 | * extraction is not supported by the profile. |
620 | */ |
621 | if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), intf: pfvf->nix_rx_intf)) |
622 | return; |
623 | |
624 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
625 | nixlf, NIXLF_UCAST_ENTRY); |
626 | |
627 | /* Don't change the action if entry is already enabled |
628 | * Otherwise RSS action may get overwritten. |
629 | */ |
630 | if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { |
631 | *(u64 *)&action = npc_get_mcam_action(rvu, mcam, |
632 | blkaddr, index); |
633 | } else { |
634 | action.op = NIX_RX_ACTIONOP_UCAST; |
635 | action.pf_func = pcifunc; |
636 | } |
637 | |
638 | req.default_rule = 1; |
639 | ether_addr_copy(dst: req.packet.dmac, src: mac_addr); |
640 | eth_broadcast_addr(addr: (u8 *)&req.mask.dmac); |
641 | req.features = BIT_ULL(NPC_DMAC); |
642 | req.channel = chan; |
643 | req.chan_mask = 0xFFFU; |
644 | req.intf = pfvf->nix_rx_intf; |
645 | req.op = action.op; |
646 | req.hdr.pcifunc = 0; /* AF is requester */ |
647 | req.vf = action.pf_func; |
648 | req.index = action.index; |
649 | req.match_id = action.match_id; |
650 | req.flow_key_alg = action.flow_key_alg; |
651 | |
652 | rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); |
653 | } |
654 | |
655 | void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, |
656 | int nixlf, u64 chan, u8 chan_cnt) |
657 | { |
658 | struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); |
659 | struct npc_install_flow_req req = { 0 }; |
660 | struct npc_install_flow_rsp rsp = { 0 }; |
661 | struct npc_mcam *mcam = &rvu->hw->mcam; |
662 | struct rvu_hwinfo *hw = rvu->hw; |
663 | int blkaddr, ucast_idx, index; |
664 | struct nix_rx_action action = { 0 }; |
665 | u64 relaxed_mask; |
666 | u8 flow_key_alg; |
667 | |
668 | if (!hw->cap.nix_rx_multicast && is_cgx_vf(rvu, pcifunc)) |
669 | return; |
670 | |
671 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
672 | if (blkaddr < 0) |
673 | return; |
674 | |
675 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
676 | nixlf, NIXLF_PROMISC_ENTRY); |
677 | |
678 | if (is_cgx_vf(rvu, pcifunc)) |
679 | index = npc_get_nixlf_mcam_index(mcam, |
680 | pcifunc: pcifunc & ~RVU_PFVF_FUNC_MASK, |
681 | nixlf, NIXLF_PROMISC_ENTRY); |
682 | |
683 | /* If the corresponding PF's ucast action is RSS, |
684 | * use the same action for promisc also |
685 | */ |
686 | ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, |
687 | nixlf, NIXLF_UCAST_ENTRY); |
688 | if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index: ucast_idx)) |
689 | *(u64 *)&action = npc_get_mcam_action(rvu, mcam, |
690 | blkaddr, index: ucast_idx); |
691 | |
692 | if (action.op != NIX_RX_ACTIONOP_RSS) { |
693 | *(u64 *)&action = 0; |
694 | action.op = NIX_RX_ACTIONOP_UCAST; |
695 | } |
696 | |
697 | flow_key_alg = action.flow_key_alg; |
698 | |
699 | /* RX_ACTION set to MCAST for CGX PF's */ |
700 | if (hw->cap.nix_rx_multicast && pfvf->use_mce_list && |
701 | is_pf_cgxmapped(rvu, pf: rvu_get_pf(pcifunc))) { |
702 | *(u64 *)&action = 0; |
703 | action.op = NIX_RX_ACTIONOP_MCAST; |
704 | pfvf = rvu_get_pfvf(rvu, pcifunc: pcifunc & ~RVU_PFVF_FUNC_MASK); |
705 | action.index = pfvf->promisc_mce_idx; |
706 | } |
707 | |
708 | /* For cn10k the upper two bits of the channel number are |
709 | * cpt channel number. with masking out these bits in the |
710 | * mcam entry, same entry used for NIX will allow packets |
711 | * received from cpt for parsing. |
712 | */ |
713 | if (!is_rvu_otx2(rvu)) { |
714 | req.chan_mask = NIX_CHAN_CPT_X2P_MASK; |
715 | } else { |
716 | req.chan_mask = 0xFFFU; |
717 | } |
718 | |
719 | if (chan_cnt > 1) { |
720 | if (!is_power_of_2(n: chan_cnt)) { |
721 | dev_err(rvu->dev, |
722 | "%s: channel count more than 1, must be power of 2\n" , __func__); |
723 | return; |
724 | } |
725 | relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1, |
726 | ilog2(chan_cnt)); |
727 | req.chan_mask &= relaxed_mask; |
728 | } |
729 | |
730 | req.channel = chan; |
731 | req.intf = pfvf->nix_rx_intf; |
732 | req.entry = index; |
733 | req.op = action.op; |
734 | req.hdr.pcifunc = 0; /* AF is requester */ |
735 | req.vf = pcifunc; |
736 | req.index = action.index; |
737 | req.match_id = action.match_id; |
738 | req.flow_key_alg = flow_key_alg; |
739 | |
740 | rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); |
741 | } |
742 | |
743 | void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, |
744 | int nixlf, bool enable) |
745 | { |
746 | struct npc_mcam *mcam = &rvu->hw->mcam; |
747 | int blkaddr, index; |
748 | |
749 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
750 | if (blkaddr < 0) |
751 | return; |
752 | |
753 | /* Get 'pcifunc' of PF device */ |
754 | pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; |
755 | |
756 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
757 | nixlf, NIXLF_PROMISC_ENTRY); |
758 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); |
759 | } |
760 | |
761 | void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, |
762 | int nixlf, u64 chan) |
763 | { |
764 | struct rvu_pfvf *pfvf; |
765 | struct npc_install_flow_req req = { 0 }; |
766 | struct npc_install_flow_rsp rsp = { 0 }; |
767 | struct npc_mcam *mcam = &rvu->hw->mcam; |
768 | struct rvu_hwinfo *hw = rvu->hw; |
769 | int blkaddr, index; |
770 | |
771 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
772 | if (blkaddr < 0) |
773 | return; |
774 | |
775 | /* Skip LBK VFs */ |
776 | if (is_lbk_vf(rvu, pcifunc)) |
777 | return; |
778 | |
779 | /* If pkt replication is not supported, |
780 | * then only PF is allowed to add a bcast match entry. |
781 | */ |
782 | if (!hw->cap.nix_rx_multicast && is_vf(pcifunc)) |
783 | return; |
784 | |
785 | /* Get 'pcifunc' of PF device */ |
786 | pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; |
787 | pfvf = rvu_get_pfvf(rvu, pcifunc); |
788 | |
789 | /* Bcast rule should not be installed if both DMAC |
790 | * and LXMB extraction is not supported by the profile. |
791 | */ |
792 | if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), intf: pfvf->nix_rx_intf) && |
793 | !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), intf: pfvf->nix_rx_intf)) |
794 | return; |
795 | |
796 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
797 | nixlf, NIXLF_BCAST_ENTRY); |
798 | |
799 | if (!hw->cap.nix_rx_multicast) { |
800 | /* Early silicon doesn't support pkt replication, |
801 | * so install entry with UCAST action, so that PF |
802 | * receives all broadcast packets. |
803 | */ |
804 | req.op = NIX_RX_ACTIONOP_UCAST; |
805 | } else { |
806 | req.op = NIX_RX_ACTIONOP_MCAST; |
807 | req.index = pfvf->bcast_mce_idx; |
808 | } |
809 | |
810 | eth_broadcast_addr(addr: (u8 *)&req.packet.dmac); |
811 | eth_broadcast_addr(addr: (u8 *)&req.mask.dmac); |
812 | req.features = BIT_ULL(NPC_DMAC); |
813 | req.channel = chan; |
814 | req.chan_mask = 0xFFFU; |
815 | req.intf = pfvf->nix_rx_intf; |
816 | req.entry = index; |
817 | req.hdr.pcifunc = 0; /* AF is requester */ |
818 | req.vf = pcifunc; |
819 | |
820 | rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); |
821 | } |
822 | |
823 | void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, |
824 | bool enable) |
825 | { |
826 | struct npc_mcam *mcam = &rvu->hw->mcam; |
827 | int blkaddr, index; |
828 | |
829 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
830 | if (blkaddr < 0) |
831 | return; |
832 | |
833 | /* Get 'pcifunc' of PF device */ |
834 | pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; |
835 | |
836 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, |
837 | NIXLF_BCAST_ENTRY); |
838 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); |
839 | } |
840 | |
841 | void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, |
842 | u64 chan) |
843 | { |
844 | struct npc_install_flow_req req = { 0 }; |
845 | struct npc_install_flow_rsp rsp = { 0 }; |
846 | struct npc_mcam *mcam = &rvu->hw->mcam; |
847 | struct rvu_hwinfo *hw = rvu->hw; |
848 | int blkaddr, ucast_idx, index; |
849 | u8 mac_addr[ETH_ALEN] = { 0 }; |
850 | struct nix_rx_action action = { 0 }; |
851 | struct rvu_pfvf *pfvf; |
852 | u8 flow_key_alg; |
853 | u16 vf_func; |
854 | |
855 | /* Only CGX PF/VF can add allmulticast entry */ |
856 | if (is_lbk_vf(rvu, pcifunc) && is_sdp_vf(rvu, pcifunc)) |
857 | return; |
858 | |
859 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
860 | if (blkaddr < 0) |
861 | return; |
862 | |
863 | /* Get 'pcifunc' of PF device */ |
864 | vf_func = pcifunc & RVU_PFVF_FUNC_MASK; |
865 | pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; |
866 | pfvf = rvu_get_pfvf(rvu, pcifunc); |
867 | |
868 | /* Mcast rule should not be installed if both DMAC |
869 | * and LXMB extraction is not supported by the profile. |
870 | */ |
871 | if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), intf: pfvf->nix_rx_intf) && |
872 | !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), intf: pfvf->nix_rx_intf)) |
873 | return; |
874 | |
875 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
876 | nixlf, NIXLF_ALLMULTI_ENTRY); |
877 | |
878 | /* If the corresponding PF's ucast action is RSS, |
879 | * use the same action for multicast entry also |
880 | */ |
881 | ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, |
882 | nixlf, NIXLF_UCAST_ENTRY); |
883 | if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index: ucast_idx)) |
884 | *(u64 *)&action = npc_get_mcam_action(rvu, mcam, |
885 | blkaddr, index: ucast_idx); |
886 | |
887 | flow_key_alg = action.flow_key_alg; |
888 | if (action.op != NIX_RX_ACTIONOP_RSS) { |
889 | *(u64 *)&action = 0; |
890 | action.op = NIX_RX_ACTIONOP_UCAST; |
891 | action.pf_func = pcifunc; |
892 | } |
893 | |
894 | /* RX_ACTION set to MCAST for CGX PF's */ |
895 | if (hw->cap.nix_rx_multicast && pfvf->use_mce_list) { |
896 | *(u64 *)&action = 0; |
897 | action.op = NIX_RX_ACTIONOP_MCAST; |
898 | action.index = pfvf->mcast_mce_idx; |
899 | } |
900 | |
901 | mac_addr[0] = 0x01; /* LSB bit of 1st byte in DMAC */ |
902 | ether_addr_copy(dst: req.packet.dmac, src: mac_addr); |
903 | ether_addr_copy(dst: req.mask.dmac, src: mac_addr); |
904 | req.features = BIT_ULL(NPC_DMAC); |
905 | |
906 | /* For cn10k the upper two bits of the channel number are |
907 | * cpt channel number. with masking out these bits in the |
908 | * mcam entry, same entry used for NIX will allow packets |
909 | * received from cpt for parsing. |
910 | */ |
911 | if (!is_rvu_otx2(rvu)) |
912 | req.chan_mask = NIX_CHAN_CPT_X2P_MASK; |
913 | else |
914 | req.chan_mask = 0xFFFU; |
915 | |
916 | req.channel = chan; |
917 | req.intf = pfvf->nix_rx_intf; |
918 | req.entry = index; |
919 | req.op = action.op; |
920 | req.hdr.pcifunc = 0; /* AF is requester */ |
921 | req.vf = pcifunc | vf_func; |
922 | req.index = action.index; |
923 | req.match_id = action.match_id; |
924 | req.flow_key_alg = flow_key_alg; |
925 | |
926 | rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); |
927 | } |
928 | |
929 | void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, |
930 | bool enable) |
931 | { |
932 | struct npc_mcam *mcam = &rvu->hw->mcam; |
933 | int blkaddr, index; |
934 | |
935 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
936 | if (blkaddr < 0) |
937 | return; |
938 | |
939 | /* Get 'pcifunc' of PF device */ |
940 | pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; |
941 | |
942 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, |
943 | NIXLF_ALLMULTI_ENTRY); |
944 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); |
945 | } |
946 | |
947 | static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam, |
948 | int blkaddr, u16 pcifunc, u64 rx_action) |
949 | { |
950 | int actindex, index, bank, entry; |
951 | struct rvu_npc_mcam_rule *rule; |
952 | bool enable, update; |
953 | |
954 | if (!(pcifunc & RVU_PFVF_FUNC_MASK)) |
955 | return; |
956 | |
957 | mutex_lock(&mcam->lock); |
958 | for (index = 0; index < mcam->bmap_entries; index++) { |
959 | if (mcam->entry2target_pffunc[index] == pcifunc) { |
960 | update = true; |
961 | /* update not needed for the rules added via ntuple filters */ |
962 | list_for_each_entry(rule, &mcam->mcam_rules, list) { |
963 | if (rule->entry == index) |
964 | update = false; |
965 | } |
966 | if (!update) |
967 | continue; |
968 | bank = npc_get_bank(mcam, index); |
969 | actindex = index; |
970 | entry = index & (mcam->banksize - 1); |
971 | |
972 | /* read vf flow entry enable status */ |
973 | enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, |
974 | index: actindex); |
975 | /* disable before mcam entry update */ |
976 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: actindex, |
977 | enable: false); |
978 | /* update 'action' */ |
979 | rvu_write64(rvu, block: blkaddr, |
980 | NPC_AF_MCAMEX_BANKX_ACTION(entry, bank), |
981 | val: rx_action); |
982 | if (enable) |
983 | npc_enable_mcam_entry(rvu, mcam, blkaddr, |
984 | index: actindex, enable: true); |
985 | } |
986 | } |
987 | mutex_unlock(lock: &mcam->lock); |
988 | } |
989 | |
990 | static void npc_update_rx_action_with_alg_idx(struct rvu *rvu, struct nix_rx_action action, |
991 | struct rvu_pfvf *pfvf, int mcam_index, int blkaddr, |
992 | int alg_idx) |
993 | |
994 | { |
995 | struct npc_mcam *mcam = &rvu->hw->mcam; |
996 | struct rvu_hwinfo *hw = rvu->hw; |
997 | int bank, ; |
998 | |
999 | if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, index: mcam_index)) |
1000 | return; |
1001 | |
1002 | op_rss = (!hw->cap.nix_rx_multicast || !pfvf->use_mce_list); |
1003 | |
1004 | bank = npc_get_bank(mcam, index: mcam_index); |
1005 | mcam_index &= (mcam->banksize - 1); |
1006 | |
1007 | /* If Rx action is MCAST update only RSS algorithm index */ |
1008 | if (!op_rss) { |
1009 | *(u64 *)&action = rvu_read64(rvu, block: blkaddr, |
1010 | NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank)); |
1011 | |
1012 | action.flow_key_alg = alg_idx; |
1013 | } |
1014 | rvu_write64(rvu, block: blkaddr, |
1015 | NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank), val: *(u64 *)&action); |
1016 | } |
1017 | |
1018 | void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, |
1019 | int group, int alg_idx, int mcam_index) |
1020 | { |
1021 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1022 | struct nix_rx_action action; |
1023 | int blkaddr, index, bank; |
1024 | struct rvu_pfvf *pfvf; |
1025 | |
1026 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
1027 | if (blkaddr < 0) |
1028 | return; |
1029 | |
1030 | /* Check if this is for reserved default entry */ |
1031 | if (mcam_index < 0) { |
1032 | if (group != DEFAULT_RSS_CONTEXT_GROUP) |
1033 | return; |
1034 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
1035 | nixlf, NIXLF_UCAST_ENTRY); |
1036 | } else { |
1037 | /* TODO: validate this mcam index */ |
1038 | index = mcam_index; |
1039 | } |
1040 | |
1041 | if (index >= mcam->total_entries) |
1042 | return; |
1043 | |
1044 | bank = npc_get_bank(mcam, index); |
1045 | index &= (mcam->banksize - 1); |
1046 | |
1047 | *(u64 *)&action = rvu_read64(rvu, block: blkaddr, |
1048 | NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); |
1049 | /* Ignore if no action was set earlier */ |
1050 | if (!*(u64 *)&action) |
1051 | return; |
1052 | |
1053 | action.op = NIX_RX_ACTIONOP_RSS; |
1054 | action.pf_func = pcifunc; |
1055 | action.index = group; |
1056 | action.flow_key_alg = alg_idx; |
1057 | |
1058 | rvu_write64(rvu, block: blkaddr, |
1059 | NPC_AF_MCAMEX_BANKX_ACTION(index, bank), val: *(u64 *)&action); |
1060 | |
1061 | /* update the VF flow rule action with the VF default entry action */ |
1062 | if (mcam_index < 0) |
1063 | npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc, |
1064 | rx_action: *(u64 *)&action); |
1065 | |
1066 | /* update the action change in default rule */ |
1067 | pfvf = rvu_get_pfvf(rvu, pcifunc); |
1068 | if (pfvf->def_ucast_rule) |
1069 | pfvf->def_ucast_rule->rx_action = action; |
1070 | |
1071 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
1072 | nixlf, NIXLF_PROMISC_ENTRY); |
1073 | |
1074 | /* If PF's promiscuous entry is enabled, |
1075 | * Set RSS action for that entry as well |
1076 | */ |
1077 | npc_update_rx_action_with_alg_idx(rvu, action, pfvf, mcam_index: index, blkaddr, |
1078 | alg_idx); |
1079 | |
1080 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
1081 | nixlf, NIXLF_ALLMULTI_ENTRY); |
1082 | /* If PF's allmulti entry is enabled, |
1083 | * Set RSS action for that entry as well |
1084 | */ |
1085 | npc_update_rx_action_with_alg_idx(rvu, action, pfvf, mcam_index: index, blkaddr, |
1086 | alg_idx); |
1087 | } |
1088 | |
1089 | void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, |
1090 | int nixlf, int type, bool enable) |
1091 | { |
1092 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1093 | struct rvu_hwinfo *hw = rvu->hw; |
1094 | struct nix_mce_list *mce_list; |
1095 | int index, blkaddr, mce_idx; |
1096 | struct rvu_pfvf *pfvf; |
1097 | |
1098 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
1099 | if (blkaddr < 0) |
1100 | return; |
1101 | |
1102 | index = npc_get_nixlf_mcam_index(mcam, pcifunc: pcifunc & ~RVU_PFVF_FUNC_MASK, |
1103 | nixlf, type); |
1104 | |
1105 | /* disable MCAM entry when packet replication is not supported by hw */ |
1106 | if (!hw->cap.nix_rx_multicast && !is_vf(pcifunc)) { |
1107 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); |
1108 | return; |
1109 | } |
1110 | |
1111 | /* return incase mce list is not enabled */ |
1112 | pfvf = rvu_get_pfvf(rvu, pcifunc: pcifunc & ~RVU_PFVF_FUNC_MASK); |
1113 | if (hw->cap.nix_rx_multicast && is_vf(pcifunc) && |
1114 | type != NIXLF_BCAST_ENTRY && !pfvf->use_mce_list) |
1115 | return; |
1116 | |
1117 | nix_get_mce_list(rvu, pcifunc, type, mce_list: &mce_list, mce_idx: &mce_idx); |
1118 | |
1119 | nix_update_mce_list(rvu, pcifunc, mce_list, |
1120 | mce_idx, mcam_index: index, add: enable); |
1121 | if (enable) |
1122 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); |
1123 | } |
1124 | |
1125 | static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc, |
1126 | int nixlf, bool enable) |
1127 | { |
1128 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1129 | int index, blkaddr; |
1130 | |
1131 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
1132 | if (blkaddr < 0) |
1133 | return; |
1134 | |
1135 | /* Ucast MCAM match entry of this PF/VF */ |
1136 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, |
1137 | nixlf, NIXLF_UCAST_ENTRY); |
1138 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); |
1139 | |
1140 | /* Nothing to do for VFs, on platforms where pkt replication |
1141 | * is not supported |
1142 | */ |
1143 | if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast) |
1144 | return; |
1145 | |
1146 | /* add/delete pf_func to broadcast MCE list */ |
1147 | npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, |
1148 | NIXLF_BCAST_ENTRY, enable); |
1149 | } |
1150 | |
1151 | void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) |
1152 | { |
1153 | if (nixlf < 0) |
1154 | return; |
1155 | |
1156 | npc_enadis_default_entries(rvu, pcifunc, nixlf, enable: false); |
1157 | |
1158 | /* Delete multicast and promisc MCAM entries */ |
1159 | npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, |
1160 | NIXLF_ALLMULTI_ENTRY, enable: false); |
1161 | npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, |
1162 | NIXLF_PROMISC_ENTRY, enable: false); |
1163 | } |
1164 | |
1165 | bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable) |
1166 | { |
1167 | int blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
1168 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1169 | struct rvu_npc_mcam_rule *rule, *tmp; |
1170 | |
1171 | mutex_lock(&mcam->lock); |
1172 | |
1173 | list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { |
1174 | if (rule->intf != intf) |
1175 | continue; |
1176 | |
1177 | if (rule->entry != entry) |
1178 | continue; |
1179 | |
1180 | rule->enable = enable; |
1181 | mutex_unlock(lock: &mcam->lock); |
1182 | |
1183 | npc_enable_mcam_entry(rvu, mcam, blkaddr, |
1184 | index: entry, enable); |
1185 | |
1186 | return true; |
1187 | } |
1188 | |
1189 | mutex_unlock(lock: &mcam->lock); |
1190 | return false; |
1191 | } |
1192 | |
1193 | void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) |
1194 | { |
1195 | if (nixlf < 0) |
1196 | return; |
1197 | |
1198 | /* Enables only broadcast match entry. Promisc/Allmulti are enabled |
1199 | * in set_rx_mode mbox handler. |
1200 | */ |
1201 | npc_enadis_default_entries(rvu, pcifunc, nixlf, enable: true); |
1202 | } |
1203 | |
1204 | void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) |
1205 | { |
1206 | struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); |
1207 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1208 | struct rvu_npc_mcam_rule *rule, *tmp; |
1209 | int blkaddr; |
1210 | |
1211 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
1212 | if (blkaddr < 0) |
1213 | return; |
1214 | |
1215 | mutex_lock(&mcam->lock); |
1216 | |
1217 | /* Disable MCAM entries directing traffic to this 'pcifunc' */ |
1218 | list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { |
1219 | if (is_npc_intf_rx(intf: rule->intf) && |
1220 | rule->rx_action.pf_func == pcifunc && |
1221 | rule->rx_action.op != NIX_RX_ACTIONOP_MCAST) { |
1222 | npc_enable_mcam_entry(rvu, mcam, blkaddr, |
1223 | index: rule->entry, enable: false); |
1224 | rule->enable = false; |
1225 | /* Indicate that default rule is disabled */ |
1226 | if (rule->default_rule) { |
1227 | pfvf->def_ucast_rule = NULL; |
1228 | list_del(entry: &rule->list); |
1229 | kfree(objp: rule); |
1230 | } |
1231 | } |
1232 | } |
1233 | |
1234 | mutex_unlock(lock: &mcam->lock); |
1235 | |
1236 | npc_mcam_disable_flows(rvu, target: pcifunc); |
1237 | |
1238 | rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); |
1239 | } |
1240 | |
1241 | void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) |
1242 | { |
1243 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1244 | struct rvu_npc_mcam_rule *rule, *tmp; |
1245 | int blkaddr; |
1246 | |
1247 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
1248 | if (blkaddr < 0) |
1249 | return; |
1250 | |
1251 | mutex_lock(&mcam->lock); |
1252 | |
1253 | /* Free all MCAM entries owned by this 'pcifunc' */ |
1254 | npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); |
1255 | |
1256 | /* Free all MCAM counters owned by this 'pcifunc' */ |
1257 | npc_mcam_free_all_counters(rvu, mcam, pcifunc); |
1258 | |
1259 | /* Delete MCAM entries owned by this 'pcifunc' */ |
1260 | list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { |
1261 | if (rule->owner == pcifunc && !rule->default_rule) { |
1262 | list_del(entry: &rule->list); |
1263 | kfree(objp: rule); |
1264 | } |
1265 | } |
1266 | |
1267 | mutex_unlock(lock: &mcam->lock); |
1268 | |
1269 | rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); |
1270 | } |
1271 | |
1272 | static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr, |
1273 | struct npc_mcam_kex *mkex, u8 intf) |
1274 | { |
1275 | int lid, lt, ld, fl; |
1276 | |
1277 | if (is_npc_intf_tx(intf)) |
1278 | return; |
1279 | |
1280 | rvu_write64(rvu, block: blkaddr, NPC_AF_INTFX_KEX_CFG(intf), |
1281 | val: mkex->keyx_cfg[NIX_INTF_RX]); |
1282 | |
1283 | /* Program LDATA */ |
1284 | for (lid = 0; lid < NPC_MAX_LID; lid++) { |
1285 | for (lt = 0; lt < NPC_MAX_LT; lt++) { |
1286 | for (ld = 0; ld < NPC_MAX_LD; ld++) |
1287 | SET_KEX_LD(intf, lid, lt, ld, |
1288 | mkex->intf_lid_lt_ld[NIX_INTF_RX] |
1289 | [lid][lt][ld]); |
1290 | } |
1291 | } |
1292 | /* Program LFLAGS */ |
1293 | for (ld = 0; ld < NPC_MAX_LD; ld++) { |
1294 | for (fl = 0; fl < NPC_MAX_LFL; fl++) |
1295 | SET_KEX_LDFLAGS(intf, ld, fl, |
1296 | mkex->intf_ld_flags[NIX_INTF_RX] |
1297 | [ld][fl]); |
1298 | } |
1299 | } |
1300 | |
1301 | static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr, |
1302 | struct npc_mcam_kex *mkex, u8 intf) |
1303 | { |
1304 | int lid, lt, ld, fl; |
1305 | |
1306 | if (is_npc_intf_rx(intf)) |
1307 | return; |
1308 | |
1309 | rvu_write64(rvu, block: blkaddr, NPC_AF_INTFX_KEX_CFG(intf), |
1310 | val: mkex->keyx_cfg[NIX_INTF_TX]); |
1311 | |
1312 | /* Program LDATA */ |
1313 | for (lid = 0; lid < NPC_MAX_LID; lid++) { |
1314 | for (lt = 0; lt < NPC_MAX_LT; lt++) { |
1315 | for (ld = 0; ld < NPC_MAX_LD; ld++) |
1316 | SET_KEX_LD(intf, lid, lt, ld, |
1317 | mkex->intf_lid_lt_ld[NIX_INTF_TX] |
1318 | [lid][lt][ld]); |
1319 | } |
1320 | } |
1321 | /* Program LFLAGS */ |
1322 | for (ld = 0; ld < NPC_MAX_LD; ld++) { |
1323 | for (fl = 0; fl < NPC_MAX_LFL; fl++) |
1324 | SET_KEX_LDFLAGS(intf, ld, fl, |
1325 | mkex->intf_ld_flags[NIX_INTF_TX] |
1326 | [ld][fl]); |
1327 | } |
1328 | } |
1329 | |
1330 | static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, |
1331 | struct npc_mcam_kex *mkex) |
1332 | { |
1333 | struct rvu_hwinfo *hw = rvu->hw; |
1334 | u8 intf; |
1335 | int ld; |
1336 | |
1337 | for (ld = 0; ld < NPC_MAX_LD; ld++) |
1338 | rvu_write64(rvu, block: blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld), |
1339 | val: mkex->kex_ld_flags[ld]); |
1340 | |
1341 | for (intf = 0; intf < hw->npc_intfs; intf++) { |
1342 | npc_program_mkex_rx(rvu, blkaddr, mkex, intf); |
1343 | npc_program_mkex_tx(rvu, blkaddr, mkex, intf); |
1344 | } |
1345 | |
1346 | /* Programme mkex hash profile */ |
1347 | npc_program_mkex_hash(rvu, blkaddr); |
1348 | } |
1349 | |
1350 | static int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr, |
1351 | u64 *size) |
1352 | { |
1353 | u64 prfl_addr, prfl_sz; |
1354 | |
1355 | if (!rvu->fwdata) |
1356 | return -EINVAL; |
1357 | |
1358 | prfl_addr = rvu->fwdata->mcam_addr; |
1359 | prfl_sz = rvu->fwdata->mcam_sz; |
1360 | |
1361 | if (!prfl_addr || !prfl_sz) |
1362 | return -EINVAL; |
1363 | |
1364 | *prfl_img_addr = ioremap_wc(offset: prfl_addr, size: prfl_sz); |
1365 | if (!(*prfl_img_addr)) |
1366 | return -ENOMEM; |
1367 | |
1368 | *size = prfl_sz; |
1369 | |
1370 | return 0; |
1371 | } |
1372 | |
1373 | /* strtoull of "mkexprof" with base:36 */ |
1374 | #define MKEX_END_SIGN 0xdeadbeef |
1375 | |
1376 | static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr, |
1377 | const char *mkex_profile) |
1378 | { |
1379 | struct device *dev = &rvu->pdev->dev; |
1380 | struct npc_mcam_kex *mcam_kex; |
1381 | void __iomem *mkex_prfl_addr = NULL; |
1382 | u64 prfl_sz; |
1383 | int ret; |
1384 | |
1385 | /* If user not selected mkex profile */ |
1386 | if (rvu->kpu_fwdata_sz || |
1387 | !strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN)) |
1388 | goto program_mkex; |
1389 | |
1390 | /* Setting up the mapping for mkex profile image */ |
1391 | ret = npc_fwdb_prfl_img_map(rvu, prfl_img_addr: &mkex_prfl_addr, size: &prfl_sz); |
1392 | if (ret < 0) |
1393 | goto program_mkex; |
1394 | |
1395 | mcam_kex = (struct npc_mcam_kex __force *)mkex_prfl_addr; |
1396 | |
1397 | while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) { |
1398 | /* Compare with mkex mod_param name string */ |
1399 | if (mcam_kex->mkex_sign == MKEX_SIGN && |
1400 | !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) { |
1401 | /* Due to an errata (35786) in A0/B0 pass silicon, |
1402 | * parse nibble enable configuration has to be |
1403 | * identical for both Rx and Tx interfaces. |
1404 | */ |
1405 | if (!is_rvu_96xx_B0(rvu) || |
1406 | mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX]) |
1407 | rvu->kpu.mkex = mcam_kex; |
1408 | goto program_mkex; |
1409 | } |
1410 | |
1411 | mcam_kex++; |
1412 | prfl_sz -= sizeof(struct npc_mcam_kex); |
1413 | } |
1414 | dev_warn(dev, "Failed to load requested profile: %s\n" , mkex_profile); |
1415 | |
1416 | program_mkex: |
1417 | dev_info(rvu->dev, "Using %s mkex profile\n" , rvu->kpu.mkex->name); |
1418 | /* Program selected mkex profile */ |
1419 | npc_program_mkex_profile(rvu, blkaddr, mkex: rvu->kpu.mkex); |
1420 | if (mkex_prfl_addr) |
1421 | iounmap(addr: mkex_prfl_addr); |
1422 | } |
1423 | |
1424 | static void npc_config_kpuaction(struct rvu *rvu, int blkaddr, |
1425 | const struct npc_kpu_profile_action *kpuaction, |
1426 | int kpu, int entry, bool pkind) |
1427 | { |
1428 | struct npc_kpu_action0 action0 = {0}; |
1429 | struct npc_kpu_action1 action1 = {0}; |
1430 | u64 reg; |
1431 | |
1432 | action1.errlev = kpuaction->errlev; |
1433 | action1.errcode = kpuaction->errcode; |
1434 | action1.dp0_offset = kpuaction->dp0_offset; |
1435 | action1.dp1_offset = kpuaction->dp1_offset; |
1436 | action1.dp2_offset = kpuaction->dp2_offset; |
1437 | |
1438 | if (pkind) |
1439 | reg = NPC_AF_PKINDX_ACTION1(entry); |
1440 | else |
1441 | reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry); |
1442 | |
1443 | rvu_write64(rvu, block: blkaddr, offset: reg, val: *(u64 *)&action1); |
1444 | |
1445 | action0.byp_count = kpuaction->bypass_count; |
1446 | action0.capture_ena = kpuaction->cap_ena; |
1447 | action0.parse_done = kpuaction->parse_done; |
1448 | action0.next_state = kpuaction->next_state; |
1449 | action0.capture_lid = kpuaction->lid; |
1450 | action0.capture_ltype = kpuaction->ltype; |
1451 | action0.capture_flags = kpuaction->flags; |
1452 | action0.ptr_advance = kpuaction->ptr_advance; |
1453 | action0.var_len_offset = kpuaction->offset; |
1454 | action0.var_len_mask = kpuaction->mask; |
1455 | action0.var_len_right = kpuaction->right; |
1456 | action0.var_len_shift = kpuaction->shift; |
1457 | |
1458 | if (pkind) |
1459 | reg = NPC_AF_PKINDX_ACTION0(entry); |
1460 | else |
1461 | reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry); |
1462 | |
1463 | rvu_write64(rvu, block: blkaddr, offset: reg, val: *(u64 *)&action0); |
1464 | } |
1465 | |
1466 | static void npc_config_kpucam(struct rvu *rvu, int blkaddr, |
1467 | const struct npc_kpu_profile_cam *kpucam, |
1468 | int kpu, int entry) |
1469 | { |
1470 | struct npc_kpu_cam cam0 = {0}; |
1471 | struct npc_kpu_cam cam1 = {0}; |
1472 | |
1473 | cam1.state = kpucam->state & kpucam->state_mask; |
1474 | cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask; |
1475 | cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask; |
1476 | cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask; |
1477 | |
1478 | cam0.state = ~kpucam->state & kpucam->state_mask; |
1479 | cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask; |
1480 | cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask; |
1481 | cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask; |
1482 | |
1483 | rvu_write64(rvu, block: blkaddr, |
1484 | NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), val: *(u64 *)&cam0); |
1485 | rvu_write64(rvu, block: blkaddr, |
1486 | NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), val: *(u64 *)&cam1); |
1487 | } |
1488 | |
1489 | static inline u64 enable_mask(int count) |
1490 | { |
1491 | return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL)); |
1492 | } |
1493 | |
1494 | static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, |
1495 | const struct npc_kpu_profile *profile) |
1496 | { |
1497 | int entry, num_entries, max_entries; |
1498 | u64 entry_mask; |
1499 | |
1500 | if (profile->cam_entries != profile->action_entries) { |
1501 | dev_err(rvu->dev, |
1502 | "KPU%d: CAM and action entries [%d != %d] not equal\n" , |
1503 | kpu, profile->cam_entries, profile->action_entries); |
1504 | } |
1505 | |
1506 | max_entries = rvu->hw->npc_kpu_entries; |
1507 | |
1508 | /* Program CAM match entries for previous KPU extracted data */ |
1509 | num_entries = min_t(int, profile->cam_entries, max_entries); |
1510 | for (entry = 0; entry < num_entries; entry++) |
1511 | npc_config_kpucam(rvu, blkaddr, |
1512 | kpucam: &profile->cam[entry], kpu, entry); |
1513 | |
1514 | /* Program this KPU's actions */ |
1515 | num_entries = min_t(int, profile->action_entries, max_entries); |
1516 | for (entry = 0; entry < num_entries; entry++) |
1517 | npc_config_kpuaction(rvu, blkaddr, kpuaction: &profile->action[entry], |
1518 | kpu, entry, pkind: false); |
1519 | |
1520 | /* Enable all programmed entries */ |
1521 | num_entries = min_t(int, profile->action_entries, profile->cam_entries); |
1522 | entry_mask = enable_mask(count: num_entries); |
1523 | /* Disable first KPU_MAX_CST_ENT entries for built-in profile */ |
1524 | if (!rvu->kpu.custom) |
1525 | entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0); |
1526 | rvu_write64(rvu, block: blkaddr, |
1527 | NPC_AF_KPUX_ENTRY_DISX(kpu, 0), val: entry_mask); |
1528 | if (num_entries > 64) { |
1529 | rvu_write64(rvu, block: blkaddr, |
1530 | NPC_AF_KPUX_ENTRY_DISX(kpu, 1), |
1531 | val: enable_mask(count: num_entries - 64)); |
1532 | } |
1533 | |
1534 | /* Enable this KPU */ |
1535 | rvu_write64(rvu, block: blkaddr, NPC_AF_KPUX_CFG(kpu), val: 0x01); |
1536 | } |
1537 | |
1538 | static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile) |
1539 | { |
1540 | profile->custom = 0; |
1541 | profile->name = def_pfl_name; |
1542 | profile->version = NPC_KPU_PROFILE_VER; |
1543 | profile->ikpu = ikpu_action_entries; |
1544 | profile->pkinds = ARRAY_SIZE(ikpu_action_entries); |
1545 | profile->kpu = npc_kpu_profiles; |
1546 | profile->kpus = ARRAY_SIZE(npc_kpu_profiles); |
1547 | profile->lt_def = &npc_lt_defaults; |
1548 | profile->mkex = &npc_mkex_default; |
1549 | profile->mkex_hash = &npc_mkex_hash_default; |
1550 | |
1551 | return 0; |
1552 | } |
1553 | |
1554 | static int npc_apply_custom_kpu(struct rvu *rvu, |
1555 | struct npc_kpu_profile_adapter *profile) |
1556 | { |
1557 | size_t hdr_sz = sizeof(struct npc_kpu_profile_fwdata), offset = 0; |
1558 | struct npc_kpu_profile_fwdata *fw = rvu->kpu_fwdata; |
1559 | struct npc_kpu_profile_action *action; |
1560 | struct npc_kpu_profile_cam *cam; |
1561 | struct npc_kpu_fwdata *fw_kpu; |
1562 | int entries; |
1563 | u16 kpu, entry; |
1564 | |
1565 | if (rvu->kpu_fwdata_sz < hdr_sz) { |
1566 | dev_warn(rvu->dev, "Invalid KPU profile size\n" ); |
1567 | return -EINVAL; |
1568 | } |
1569 | if (le64_to_cpu(fw->signature) != KPU_SIGN) { |
1570 | dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n" , |
1571 | fw->signature); |
1572 | return -EINVAL; |
1573 | } |
1574 | /* Verify if the using known profile structure */ |
1575 | if (NPC_KPU_VER_MAJ(profile->version) > |
1576 | NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)) { |
1577 | dev_warn(rvu->dev, "Not supported Major version: %d > %d\n" , |
1578 | NPC_KPU_VER_MAJ(profile->version), |
1579 | NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)); |
1580 | return -EINVAL; |
1581 | } |
1582 | /* Verify if profile is aligned with the required kernel changes */ |
1583 | if (NPC_KPU_VER_MIN(profile->version) < |
1584 | NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER)) { |
1585 | dev_warn(rvu->dev, |
1586 | "Invalid KPU profile version: %d.%d.%d expected version <= %d.%d.%d\n" , |
1587 | NPC_KPU_VER_MAJ(profile->version), |
1588 | NPC_KPU_VER_MIN(profile->version), |
1589 | NPC_KPU_VER_PATCH(profile->version), |
1590 | NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER), |
1591 | NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER), |
1592 | NPC_KPU_VER_PATCH(NPC_KPU_PROFILE_VER)); |
1593 | return -EINVAL; |
1594 | } |
1595 | /* Verify if profile fits the HW */ |
1596 | if (fw->kpus > profile->kpus) { |
1597 | dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n" , fw->kpus, |
1598 | profile->kpus); |
1599 | return -EINVAL; |
1600 | } |
1601 | |
1602 | profile->custom = 1; |
1603 | profile->name = fw->name; |
1604 | profile->version = le64_to_cpu(fw->version); |
1605 | profile->mkex = &fw->mkex; |
1606 | profile->lt_def = &fw->lt_def; |
1607 | |
1608 | for (kpu = 0; kpu < fw->kpus; kpu++) { |
1609 | fw_kpu = (struct npc_kpu_fwdata *)(fw->data + offset); |
1610 | if (fw_kpu->entries > KPU_MAX_CST_ENT) |
1611 | dev_warn(rvu->dev, |
1612 | "Too many custom entries on KPU%d: %d > %d\n" , |
1613 | kpu, fw_kpu->entries, KPU_MAX_CST_ENT); |
1614 | entries = min(fw_kpu->entries, KPU_MAX_CST_ENT); |
1615 | cam = (struct npc_kpu_profile_cam *)fw_kpu->data; |
1616 | offset += sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); |
1617 | action = (struct npc_kpu_profile_action *)(fw->data + offset); |
1618 | offset += fw_kpu->entries * sizeof(*action); |
1619 | if (rvu->kpu_fwdata_sz < hdr_sz + offset) { |
1620 | dev_warn(rvu->dev, |
1621 | "Profile size mismatch on KPU%i parsing.\n" , |
1622 | kpu + 1); |
1623 | return -EINVAL; |
1624 | } |
1625 | for (entry = 0; entry < entries; entry++) { |
1626 | profile->kpu[kpu].cam[entry] = cam[entry]; |
1627 | profile->kpu[kpu].action[entry] = action[entry]; |
1628 | } |
1629 | } |
1630 | |
1631 | return 0; |
1632 | } |
1633 | |
1634 | static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr, |
1635 | u64 prfl_sz, const char *kpu_profile) |
1636 | { |
1637 | struct npc_kpu_profile_fwdata *kpu_data = NULL; |
1638 | int rc = -EINVAL; |
1639 | |
1640 | kpu_data = (struct npc_kpu_profile_fwdata __force *)prfl_addr; |
1641 | if (le64_to_cpu(kpu_data->signature) == KPU_SIGN && |
1642 | !strncmp(kpu_data->name, kpu_profile, KPU_NAME_LEN)) { |
1643 | dev_info(rvu->dev, "Loading KPU profile from firmware db: %s\n" , |
1644 | kpu_profile); |
1645 | rvu->kpu_fwdata = kpu_data; |
1646 | rvu->kpu_fwdata_sz = prfl_sz; |
1647 | rvu->kpu_prfl_addr = prfl_addr; |
1648 | rc = 0; |
1649 | } |
1650 | |
1651 | return rc; |
1652 | } |
1653 | |
1654 | static int npc_fwdb_detect_load_prfl_img(struct rvu *rvu, uint64_t prfl_sz, |
1655 | const char *kpu_profile) |
1656 | { |
1657 | struct npc_coalesced_kpu_prfl *img_data = NULL; |
1658 | int i = 0, rc = -EINVAL; |
1659 | void __iomem *kpu_prfl_addr; |
1660 | u32 offset; |
1661 | |
1662 | img_data = (struct npc_coalesced_kpu_prfl __force *)rvu->kpu_prfl_addr; |
1663 | if (le64_to_cpu(img_data->signature) == KPU_SIGN && |
1664 | !strncmp(img_data->name, kpu_profile, KPU_NAME_LEN)) { |
1665 | /* Loaded profile is a single KPU profile. */ |
1666 | rc = npc_load_kpu_prfl_img(rvu, prfl_addr: rvu->kpu_prfl_addr, |
1667 | prfl_sz, kpu_profile); |
1668 | goto done; |
1669 | } |
1670 | |
1671 | /* Loaded profile is coalesced image, offset of first KPU profile.*/ |
1672 | offset = offsetof(struct npc_coalesced_kpu_prfl, prfl_sz) + |
1673 | (img_data->num_prfl * sizeof(uint16_t)); |
1674 | /* Check if mapped image is coalesced image. */ |
1675 | while (i < img_data->num_prfl) { |
1676 | /* Profile image offsets are rounded up to next 8 multiple.*/ |
1677 | offset = ALIGN_8B_CEIL(offset); |
1678 | kpu_prfl_addr = (void __iomem *)((uintptr_t)rvu->kpu_prfl_addr + |
1679 | offset); |
1680 | rc = npc_load_kpu_prfl_img(rvu, prfl_addr: kpu_prfl_addr, |
1681 | prfl_sz: img_data->prfl_sz[i], kpu_profile); |
1682 | if (!rc) |
1683 | break; |
1684 | /* Calculating offset of profile image based on profile size.*/ |
1685 | offset += img_data->prfl_sz[i]; |
1686 | i++; |
1687 | } |
1688 | done: |
1689 | return rc; |
1690 | } |
1691 | |
1692 | static int npc_load_kpu_profile_fwdb(struct rvu *rvu, const char *kpu_profile) |
1693 | { |
1694 | int ret = -EINVAL; |
1695 | u64 prfl_sz; |
1696 | |
1697 | /* Setting up the mapping for NPC profile image */ |
1698 | ret = npc_fwdb_prfl_img_map(rvu, prfl_img_addr: &rvu->kpu_prfl_addr, size: &prfl_sz); |
1699 | if (ret < 0) |
1700 | goto done; |
1701 | |
1702 | /* Detect if profile is coalesced or single KPU profile and load */ |
1703 | ret = npc_fwdb_detect_load_prfl_img(rvu, prfl_sz, kpu_profile); |
1704 | if (ret == 0) |
1705 | goto done; |
1706 | |
1707 | /* Cleaning up if KPU profile image from fwdata is not valid. */ |
1708 | if (rvu->kpu_prfl_addr) { |
1709 | iounmap(addr: rvu->kpu_prfl_addr); |
1710 | rvu->kpu_prfl_addr = NULL; |
1711 | rvu->kpu_fwdata_sz = 0; |
1712 | rvu->kpu_fwdata = NULL; |
1713 | } |
1714 | |
1715 | done: |
1716 | return ret; |
1717 | } |
1718 | |
1719 | static void npc_load_kpu_profile(struct rvu *rvu) |
1720 | { |
1721 | struct npc_kpu_profile_adapter *profile = &rvu->kpu; |
1722 | const char *kpu_profile = rvu->kpu_pfl_name; |
1723 | const struct firmware *fw = NULL; |
1724 | bool retry_fwdb = false; |
1725 | |
1726 | /* If user not specified profile customization */ |
1727 | if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN)) |
1728 | goto revert_to_default; |
1729 | /* First prepare default KPU, then we'll customize top entries. */ |
1730 | npc_prepare_default_kpu(profile); |
1731 | |
1732 | /* Order of preceedence for load loading NPC profile (high to low) |
1733 | * Firmware binary in filesystem. |
1734 | * Firmware database method. |
1735 | * Default KPU profile. |
1736 | */ |
1737 | if (!request_firmware_direct(fw: &fw, name: kpu_profile, device: rvu->dev)) { |
1738 | dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n" , |
1739 | kpu_profile); |
1740 | rvu->kpu_fwdata = kzalloc(size: fw->size, GFP_KERNEL); |
1741 | if (rvu->kpu_fwdata) { |
1742 | memcpy(rvu->kpu_fwdata, fw->data, fw->size); |
1743 | rvu->kpu_fwdata_sz = fw->size; |
1744 | } |
1745 | release_firmware(fw); |
1746 | retry_fwdb = true; |
1747 | goto program_kpu; |
1748 | } |
1749 | |
1750 | load_image_fwdb: |
1751 | /* Loading the KPU profile using firmware database */ |
1752 | if (npc_load_kpu_profile_fwdb(rvu, kpu_profile)) |
1753 | goto revert_to_default; |
1754 | |
1755 | program_kpu: |
1756 | /* Apply profile customization if firmware was loaded. */ |
1757 | if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) { |
1758 | /* If image from firmware filesystem fails to load or invalid |
1759 | * retry with firmware database method. |
1760 | */ |
1761 | if (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) { |
1762 | /* Loading image from firmware database failed. */ |
1763 | if (rvu->kpu_prfl_addr) { |
1764 | iounmap(addr: rvu->kpu_prfl_addr); |
1765 | rvu->kpu_prfl_addr = NULL; |
1766 | } else { |
1767 | kfree(objp: rvu->kpu_fwdata); |
1768 | } |
1769 | rvu->kpu_fwdata = NULL; |
1770 | rvu->kpu_fwdata_sz = 0; |
1771 | if (retry_fwdb) { |
1772 | retry_fwdb = false; |
1773 | goto load_image_fwdb; |
1774 | } |
1775 | } |
1776 | |
1777 | dev_warn(rvu->dev, |
1778 | "Can't load KPU profile %s. Using default.\n" , |
1779 | kpu_profile); |
1780 | kfree(objp: rvu->kpu_fwdata); |
1781 | rvu->kpu_fwdata = NULL; |
1782 | goto revert_to_default; |
1783 | } |
1784 | |
1785 | dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n" , |
1786 | profile->name, NPC_KPU_VER_MAJ(profile->version), |
1787 | NPC_KPU_VER_MIN(profile->version), |
1788 | NPC_KPU_VER_PATCH(profile->version)); |
1789 | |
1790 | return; |
1791 | |
1792 | revert_to_default: |
1793 | npc_prepare_default_kpu(profile); |
1794 | } |
1795 | |
1796 | static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) |
1797 | { |
1798 | struct rvu_hwinfo *hw = rvu->hw; |
1799 | int num_pkinds, num_kpus, idx; |
1800 | |
1801 | /* Disable all KPUs and their entries */ |
1802 | for (idx = 0; idx < hw->npc_kpus; idx++) { |
1803 | rvu_write64(rvu, block: blkaddr, |
1804 | NPC_AF_KPUX_ENTRY_DISX(idx, 0), val: ~0ULL); |
1805 | rvu_write64(rvu, block: blkaddr, |
1806 | NPC_AF_KPUX_ENTRY_DISX(idx, 1), val: ~0ULL); |
1807 | rvu_write64(rvu, block: blkaddr, NPC_AF_KPUX_CFG(idx), val: 0x00); |
1808 | } |
1809 | |
1810 | /* Load and customize KPU profile. */ |
1811 | npc_load_kpu_profile(rvu); |
1812 | |
1813 | /* First program IKPU profile i.e PKIND configs. |
1814 | * Check HW max count to avoid configuring junk or |
1815 | * writing to unsupported CSR addresses. |
1816 | */ |
1817 | num_pkinds = rvu->kpu.pkinds; |
1818 | num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds); |
1819 | |
1820 | for (idx = 0; idx < num_pkinds; idx++) |
1821 | npc_config_kpuaction(rvu, blkaddr, kpuaction: &rvu->kpu.ikpu[idx], kpu: 0, entry: idx, pkind: true); |
1822 | |
1823 | /* Program KPU CAM and Action profiles */ |
1824 | num_kpus = rvu->kpu.kpus; |
1825 | num_kpus = min_t(int, hw->npc_kpus, num_kpus); |
1826 | |
1827 | for (idx = 0; idx < num_kpus; idx++) |
1828 | npc_program_kpu_profile(rvu, blkaddr, kpu: idx, profile: &rvu->kpu.kpu[idx]); |
1829 | } |
1830 | |
1831 | void npc_mcam_rsrcs_deinit(struct rvu *rvu) |
1832 | { |
1833 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1834 | |
1835 | bitmap_free(bitmap: mcam->bmap); |
1836 | bitmap_free(bitmap: mcam->bmap_reverse); |
1837 | kfree(objp: mcam->entry2pfvf_map); |
1838 | kfree(objp: mcam->cntr2pfvf_map); |
1839 | kfree(objp: mcam->entry2cntr_map); |
1840 | kfree(objp: mcam->cntr_refcnt); |
1841 | kfree(objp: mcam->entry2target_pffunc); |
1842 | kfree(objp: mcam->counters.bmap); |
1843 | } |
1844 | |
1845 | int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr) |
1846 | { |
1847 | int nixlf_count = rvu_get_nixlf_count(rvu); |
1848 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1849 | int rsvd, err; |
1850 | u16 index; |
1851 | int cntr; |
1852 | u64 cfg; |
1853 | |
1854 | /* Actual number of MCAM entries vary by entry size */ |
1855 | cfg = (rvu_read64(rvu, block: blkaddr, |
1856 | NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07; |
1857 | mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize; |
1858 | mcam->keysize = cfg; |
1859 | |
1860 | /* Number of banks combined per MCAM entry */ |
1861 | if (cfg == NPC_MCAM_KEY_X4) |
1862 | mcam->banks_per_entry = 4; |
1863 | else if (cfg == NPC_MCAM_KEY_X2) |
1864 | mcam->banks_per_entry = 2; |
1865 | else |
1866 | mcam->banks_per_entry = 1; |
1867 | |
1868 | /* Reserve one MCAM entry for each of the NIX LF to |
1869 | * guarantee space to install default matching DMAC rule. |
1870 | * Also reserve 2 MCAM entries for each PF for default |
1871 | * channel based matching or 'bcast & promisc' matching to |
1872 | * support BCAST and PROMISC modes of operation for PFs. |
1873 | * PF0 is excluded. |
1874 | */ |
1875 | rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) + |
1876 | ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF); |
1877 | if (mcam->total_entries <= rsvd) { |
1878 | dev_warn(rvu->dev, |
1879 | "Insufficient NPC MCAM size %d for pkt I/O, exiting\n" , |
1880 | mcam->total_entries); |
1881 | return -ENOMEM; |
1882 | } |
1883 | |
1884 | mcam->bmap_entries = mcam->total_entries - rsvd; |
1885 | mcam->nixlf_offset = mcam->bmap_entries; |
1886 | mcam->pf_offset = mcam->nixlf_offset + nixlf_count; |
1887 | |
1888 | /* Allocate bitmaps for managing MCAM entries */ |
1889 | mcam->bmap = bitmap_zalloc(nbits: mcam->bmap_entries, GFP_KERNEL); |
1890 | if (!mcam->bmap) |
1891 | return -ENOMEM; |
1892 | |
1893 | mcam->bmap_reverse = bitmap_zalloc(nbits: mcam->bmap_entries, GFP_KERNEL); |
1894 | if (!mcam->bmap_reverse) |
1895 | goto free_bmap; |
1896 | |
1897 | mcam->bmap_fcnt = mcam->bmap_entries; |
1898 | |
1899 | /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ |
1900 | mcam->entry2pfvf_map = kcalloc(n: mcam->bmap_entries, size: sizeof(u16), |
1901 | GFP_KERNEL); |
1902 | |
1903 | if (!mcam->entry2pfvf_map) |
1904 | goto free_bmap_reverse; |
1905 | |
1906 | /* Reserve 1/8th of MCAM entries at the bottom for low priority |
1907 | * allocations and another 1/8th at the top for high priority |
1908 | * allocations. |
1909 | */ |
1910 | mcam->lprio_count = mcam->bmap_entries / 8; |
1911 | if (mcam->lprio_count > BITS_PER_LONG) |
1912 | mcam->lprio_count = round_down(mcam->lprio_count, |
1913 | BITS_PER_LONG); |
1914 | mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count; |
1915 | mcam->hprio_count = mcam->lprio_count; |
1916 | mcam->hprio_end = mcam->hprio_count; |
1917 | |
1918 | /* Allocate bitmap for managing MCAM counters and memory |
1919 | * for saving counter to RVU PFFUNC allocation mapping. |
1920 | */ |
1921 | err = rvu_alloc_bitmap(rsrc: &mcam->counters); |
1922 | if (err) |
1923 | goto free_entry_map; |
1924 | |
1925 | mcam->cntr2pfvf_map = kcalloc(n: mcam->counters.max, size: sizeof(u16), |
1926 | GFP_KERNEL); |
1927 | if (!mcam->cntr2pfvf_map) |
1928 | goto free_cntr_bmap; |
1929 | |
1930 | /* Alloc memory for MCAM entry to counter mapping and for tracking |
1931 | * counter's reference count. |
1932 | */ |
1933 | mcam->entry2cntr_map = kcalloc(n: mcam->bmap_entries, size: sizeof(u16), |
1934 | GFP_KERNEL); |
1935 | if (!mcam->entry2cntr_map) |
1936 | goto free_cntr_map; |
1937 | |
1938 | mcam->cntr_refcnt = kcalloc(n: mcam->counters.max, size: sizeof(u16), |
1939 | GFP_KERNEL); |
1940 | if (!mcam->cntr_refcnt) |
1941 | goto free_entry_cntr_map; |
1942 | |
1943 | /* Alloc memory for saving target device of mcam rule */ |
1944 | mcam->entry2target_pffunc = kmalloc_array(n: mcam->total_entries, |
1945 | size: sizeof(u16), GFP_KERNEL); |
1946 | if (!mcam->entry2target_pffunc) |
1947 | goto free_cntr_refcnt; |
1948 | |
1949 | for (index = 0; index < mcam->bmap_entries; index++) { |
1950 | mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; |
1951 | mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; |
1952 | } |
1953 | |
1954 | for (cntr = 0; cntr < mcam->counters.max; cntr++) |
1955 | mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; |
1956 | |
1957 | mutex_init(&mcam->lock); |
1958 | |
1959 | return 0; |
1960 | |
1961 | free_cntr_refcnt: |
1962 | kfree(objp: mcam->cntr_refcnt); |
1963 | free_entry_cntr_map: |
1964 | kfree(objp: mcam->entry2cntr_map); |
1965 | free_cntr_map: |
1966 | kfree(objp: mcam->cntr2pfvf_map); |
1967 | free_cntr_bmap: |
1968 | kfree(objp: mcam->counters.bmap); |
1969 | free_entry_map: |
1970 | kfree(objp: mcam->entry2pfvf_map); |
1971 | free_bmap_reverse: |
1972 | bitmap_free(bitmap: mcam->bmap_reverse); |
1973 | free_bmap: |
1974 | bitmap_free(bitmap: mcam->bmap); |
1975 | |
1976 | return -ENOMEM; |
1977 | } |
1978 | |
1979 | static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr) |
1980 | { |
1981 | struct npc_pkind *pkind = &rvu->hw->pkind; |
1982 | struct npc_mcam *mcam = &rvu->hw->mcam; |
1983 | struct rvu_hwinfo *hw = rvu->hw; |
1984 | u64 npc_const, npc_const1; |
1985 | u64 npc_const2 = 0; |
1986 | |
1987 | npc_const = rvu_read64(rvu, block: blkaddr, NPC_AF_CONST); |
1988 | npc_const1 = rvu_read64(rvu, block: blkaddr, NPC_AF_CONST1); |
1989 | if (npc_const1 & BIT_ULL(63)) |
1990 | npc_const2 = rvu_read64(rvu, block: blkaddr, NPC_AF_CONST2); |
1991 | |
1992 | pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT; |
1993 | hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL; |
1994 | hw->npc_kpu_entries = npc_const1 & 0xFFFULL; |
1995 | hw->npc_kpus = (npc_const >> 8) & 0x1FULL; |
1996 | hw->npc_intfs = npc_const & 0xFULL; |
1997 | hw->npc_counters = (npc_const >> 48) & 0xFFFFULL; |
1998 | |
1999 | mcam->banks = (npc_const >> 44) & 0xFULL; |
2000 | mcam->banksize = (npc_const >> 28) & 0xFFFFULL; |
2001 | hw->npc_stat_ena = BIT_ULL(9); |
2002 | /* Extended set */ |
2003 | if (npc_const2) { |
2004 | hw->npc_ext_set = true; |
2005 | /* 96xx supports only match_stats and npc_counters |
2006 | * reflected in NPC_AF_CONST reg. |
2007 | * STAT_SEL and ENA are at [0:8] and 9 bit positions. |
2008 | * 98xx has both match_stat and ext and npc_counter |
2009 | * reflected in NPC_AF_CONST2 |
2010 | * STAT_SEL_EXT added at [12:14] bit position. |
2011 | * cn10k supports only ext and hence npc_counters in |
2012 | * NPC_AF_CONST is 0 and npc_counters reflected in NPC_AF_CONST2. |
2013 | * STAT_SEL bitpos incremented from [0:8] to [0:11] and ENA bit moved to 63 |
2014 | */ |
2015 | if (!hw->npc_counters) |
2016 | hw->npc_stat_ena = BIT_ULL(63); |
2017 | hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL; |
2018 | mcam->banksize = npc_const2 & 0xFFFFULL; |
2019 | } |
2020 | |
2021 | mcam->counters.max = hw->npc_counters; |
2022 | } |
2023 | |
2024 | static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr) |
2025 | { |
2026 | struct npc_mcam_kex *mkex = rvu->kpu.mkex; |
2027 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2028 | struct rvu_hwinfo *hw = rvu->hw; |
2029 | u64 nibble_ena, rx_kex, tx_kex; |
2030 | u8 intf; |
2031 | |
2032 | /* Reserve last counter for MCAM RX miss action which is set to |
2033 | * drop packet. This way we will know how many pkts didn't match |
2034 | * any MCAM entry. |
2035 | */ |
2036 | mcam->counters.max--; |
2037 | mcam->rx_miss_act_cntr = mcam->counters.max; |
2038 | |
2039 | rx_kex = mkex->keyx_cfg[NIX_INTF_RX]; |
2040 | tx_kex = mkex->keyx_cfg[NIX_INTF_TX]; |
2041 | nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex); |
2042 | |
2043 | nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena); |
2044 | if (nibble_ena) { |
2045 | tx_kex &= ~NPC_PARSE_NIBBLE; |
2046 | tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena); |
2047 | mkex->keyx_cfg[NIX_INTF_TX] = tx_kex; |
2048 | } |
2049 | |
2050 | /* Configure RX interfaces */ |
2051 | for (intf = 0; intf < hw->npc_intfs; intf++) { |
2052 | if (is_npc_intf_tx(intf)) |
2053 | continue; |
2054 | |
2055 | /* Set RX MCAM search key size. LA..LE (ltype only) + Channel */ |
2056 | rvu_write64(rvu, block: blkaddr, NPC_AF_INTFX_KEX_CFG(intf), |
2057 | val: rx_kex); |
2058 | |
2059 | /* If MCAM lookup doesn't result in a match, drop the received |
2060 | * packet. And map this action to a counter to count dropped |
2061 | * packets. |
2062 | */ |
2063 | rvu_write64(rvu, block: blkaddr, |
2064 | NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP); |
2065 | |
2066 | /* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9] |
2067 | * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0] |
2068 | */ |
2069 | rvu_write64(rvu, block: blkaddr, |
2070 | NPC_AF_INTFX_MISS_STAT_ACT(intf), |
2071 | val: ((mcam->rx_miss_act_cntr >> 9) << 12) | |
2072 | hw->npc_stat_ena | mcam->rx_miss_act_cntr); |
2073 | } |
2074 | |
2075 | /* Configure TX interfaces */ |
2076 | for (intf = 0; intf < hw->npc_intfs; intf++) { |
2077 | if (is_npc_intf_rx(intf)) |
2078 | continue; |
2079 | |
2080 | /* Extract Ltypes LID_LA to LID_LE */ |
2081 | rvu_write64(rvu, block: blkaddr, NPC_AF_INTFX_KEX_CFG(intf), |
2082 | val: tx_kex); |
2083 | |
2084 | /* Set TX miss action to UCAST_DEFAULT i.e |
2085 | * transmit the packet on NIX LF SQ's default channel. |
2086 | */ |
2087 | rvu_write64(rvu, block: blkaddr, |
2088 | NPC_AF_INTFX_MISS_ACT(intf), |
2089 | NIX_TX_ACTIONOP_UCAST_DEFAULT); |
2090 | } |
2091 | } |
2092 | |
2093 | int rvu_npc_init(struct rvu *rvu) |
2094 | { |
2095 | struct npc_kpu_profile_adapter *kpu = &rvu->kpu; |
2096 | struct npc_pkind *pkind = &rvu->hw->pkind; |
2097 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2098 | int blkaddr, entry, bank, err; |
2099 | |
2100 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2101 | if (blkaddr < 0) { |
2102 | dev_err(rvu->dev, "%s: NPC block not implemented\n" , __func__); |
2103 | return -ENODEV; |
2104 | } |
2105 | |
2106 | rvu_npc_hw_init(rvu, blkaddr); |
2107 | |
2108 | /* First disable all MCAM entries, to stop traffic towards NIXLFs */ |
2109 | for (bank = 0; bank < mcam->banks; bank++) { |
2110 | for (entry = 0; entry < mcam->banksize; entry++) |
2111 | rvu_write64(rvu, block: blkaddr, |
2112 | NPC_AF_MCAMEX_BANKX_CFG(entry, bank), val: 0); |
2113 | } |
2114 | |
2115 | err = rvu_alloc_bitmap(rsrc: &pkind->rsrc); |
2116 | if (err) |
2117 | return err; |
2118 | /* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0', |
2119 | * no need to configure PKIND for all LBKs separately. |
2120 | */ |
2121 | rvu_alloc_rsrc(rsrc: &pkind->rsrc); |
2122 | |
2123 | /* Allocate mem for pkind to PF and channel mapping info */ |
2124 | pkind->pfchan_map = devm_kcalloc(dev: rvu->dev, n: pkind->rsrc.max, |
2125 | size: sizeof(u32), GFP_KERNEL); |
2126 | if (!pkind->pfchan_map) |
2127 | return -ENOMEM; |
2128 | |
2129 | /* Configure KPU profile */ |
2130 | npc_parser_profile_init(rvu, blkaddr); |
2131 | |
2132 | /* Config Outer L2, IPv4's NPC layer info */ |
2133 | rvu_write64(rvu, block: blkaddr, NPC_AF_PCK_DEF_OL2, |
2134 | val: (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) | |
2135 | kpu->lt_def->pck_ol2.ltype_mask); |
2136 | rvu_write64(rvu, block: blkaddr, NPC_AF_PCK_DEF_OIP4, |
2137 | val: (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) | |
2138 | kpu->lt_def->pck_oip4.ltype_mask); |
2139 | |
2140 | /* Config Inner IPV4 NPC layer info */ |
2141 | rvu_write64(rvu, block: blkaddr, NPC_AF_PCK_DEF_IIP4, |
2142 | val: (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) | |
2143 | kpu->lt_def->pck_iip4.ltype_mask); |
2144 | |
2145 | /* Enable below for Rx pkts. |
2146 | * - Outer IPv4 header checksum validation. |
2147 | * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B]. |
2148 | * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M]. |
2149 | * - Inner IPv4 header checksum validation. |
2150 | * - Set non zero checksum error code value |
2151 | */ |
2152 | rvu_write64(rvu, block: blkaddr, NPC_AF_PCK_CFG, |
2153 | val: rvu_read64(rvu, block: blkaddr, NPC_AF_PCK_CFG) | |
2154 | ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) | |
2155 | BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1)); |
2156 | |
2157 | rvu_npc_setup_interfaces(rvu, blkaddr); |
2158 | |
2159 | npc_config_secret_key(rvu, blkaddr); |
2160 | /* Configure MKEX profile */ |
2161 | npc_load_mkex_profile(rvu, blkaddr, mkex_profile: rvu->mkex_pfl_name); |
2162 | |
2163 | err = npc_mcam_rsrcs_init(rvu, blkaddr); |
2164 | if (err) |
2165 | return err; |
2166 | |
2167 | err = npc_flow_steering_init(rvu, blkaddr); |
2168 | if (err) { |
2169 | dev_err(rvu->dev, |
2170 | "Incorrect mkex profile loaded using default mkex\n" ); |
2171 | npc_load_mkex_profile(rvu, blkaddr, mkex_profile: def_pfl_name); |
2172 | } |
2173 | |
2174 | return 0; |
2175 | } |
2176 | |
2177 | void rvu_npc_freemem(struct rvu *rvu) |
2178 | { |
2179 | struct npc_pkind *pkind = &rvu->hw->pkind; |
2180 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2181 | |
2182 | kfree(objp: pkind->rsrc.bmap); |
2183 | npc_mcam_rsrcs_deinit(rvu); |
2184 | kfree(objp: mcam->counters.bmap); |
2185 | if (rvu->kpu_prfl_addr) |
2186 | iounmap(addr: rvu->kpu_prfl_addr); |
2187 | else |
2188 | kfree(objp: rvu->kpu_fwdata); |
2189 | mutex_destroy(lock: &mcam->lock); |
2190 | } |
2191 | |
2192 | void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, |
2193 | int blkaddr, int *alloc_cnt, |
2194 | int *enable_cnt) |
2195 | { |
2196 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2197 | int entry; |
2198 | |
2199 | *alloc_cnt = 0; |
2200 | *enable_cnt = 0; |
2201 | |
2202 | for (entry = 0; entry < mcam->bmap_entries; entry++) { |
2203 | if (mcam->entry2pfvf_map[entry] == pcifunc) { |
2204 | (*alloc_cnt)++; |
2205 | if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index: entry)) |
2206 | (*enable_cnt)++; |
2207 | } |
2208 | } |
2209 | } |
2210 | |
2211 | void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, |
2212 | int blkaddr, int *alloc_cnt, |
2213 | int *enable_cnt) |
2214 | { |
2215 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2216 | int cntr; |
2217 | |
2218 | *alloc_cnt = 0; |
2219 | *enable_cnt = 0; |
2220 | |
2221 | for (cntr = 0; cntr < mcam->counters.max; cntr++) { |
2222 | if (mcam->cntr2pfvf_map[cntr] == pcifunc) { |
2223 | (*alloc_cnt)++; |
2224 | if (mcam->cntr_refcnt[cntr]) |
2225 | (*enable_cnt)++; |
2226 | } |
2227 | } |
2228 | } |
2229 | |
2230 | static int npc_mcam_verify_entry(struct npc_mcam *mcam, |
2231 | u16 pcifunc, int entry) |
2232 | { |
2233 | /* verify AF installed entries */ |
2234 | if (is_pffunc_af(pcifunc)) |
2235 | return 0; |
2236 | /* Verify if entry is valid and if it is indeed |
2237 | * allocated to the requesting PFFUNC. |
2238 | */ |
2239 | if (entry >= mcam->bmap_entries) |
2240 | return NPC_MCAM_INVALID_REQ; |
2241 | |
2242 | if (pcifunc != mcam->entry2pfvf_map[entry]) |
2243 | return NPC_MCAM_PERM_DENIED; |
2244 | |
2245 | return 0; |
2246 | } |
2247 | |
2248 | static int npc_mcam_verify_counter(struct npc_mcam *mcam, |
2249 | u16 pcifunc, int cntr) |
2250 | { |
2251 | /* Verify if counter is valid and if it is indeed |
2252 | * allocated to the requesting PFFUNC. |
2253 | */ |
2254 | if (cntr >= mcam->counters.max) |
2255 | return NPC_MCAM_INVALID_REQ; |
2256 | |
2257 | if (pcifunc != mcam->cntr2pfvf_map[cntr]) |
2258 | return NPC_MCAM_PERM_DENIED; |
2259 | |
2260 | return 0; |
2261 | } |
2262 | |
2263 | static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam, |
2264 | int blkaddr, u16 entry, u16 cntr) |
2265 | { |
2266 | u16 index = entry & (mcam->banksize - 1); |
2267 | u32 bank = npc_get_bank(mcam, index: entry); |
2268 | struct rvu_hwinfo *hw = rvu->hw; |
2269 | |
2270 | /* Set mapping and increment counter's refcnt */ |
2271 | mcam->entry2cntr_map[entry] = cntr; |
2272 | mcam->cntr_refcnt[cntr]++; |
2273 | /* Enable stats */ |
2274 | rvu_write64(rvu, block: blkaddr, |
2275 | NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), |
2276 | val: ((cntr >> 9) << 12) | hw->npc_stat_ena | cntr); |
2277 | } |
2278 | |
2279 | static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu, |
2280 | struct npc_mcam *mcam, |
2281 | int blkaddr, u16 entry, u16 cntr) |
2282 | { |
2283 | u16 index = entry & (mcam->banksize - 1); |
2284 | u32 bank = npc_get_bank(mcam, index: entry); |
2285 | |
2286 | /* Remove mapping and reduce counter's refcnt */ |
2287 | mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP; |
2288 | mcam->cntr_refcnt[cntr]--; |
2289 | /* Disable stats */ |
2290 | rvu_write64(rvu, block: blkaddr, |
2291 | NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), val: 0x00); |
2292 | } |
2293 | |
2294 | /* Sets MCAM entry in bitmap as used. Update |
2295 | * reverse bitmap too. Should be called with |
2296 | * 'mcam->lock' held. |
2297 | */ |
2298 | static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index) |
2299 | { |
2300 | u16 entry, rentry; |
2301 | |
2302 | entry = index; |
2303 | rentry = mcam->bmap_entries - index - 1; |
2304 | |
2305 | __set_bit(entry, mcam->bmap); |
2306 | __set_bit(rentry, mcam->bmap_reverse); |
2307 | mcam->bmap_fcnt--; |
2308 | } |
2309 | |
2310 | /* Sets MCAM entry in bitmap as free. Update |
2311 | * reverse bitmap too. Should be called with |
2312 | * 'mcam->lock' held. |
2313 | */ |
2314 | static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index) |
2315 | { |
2316 | u16 entry, rentry; |
2317 | |
2318 | entry = index; |
2319 | rentry = mcam->bmap_entries - index - 1; |
2320 | |
2321 | __clear_bit(entry, mcam->bmap); |
2322 | __clear_bit(rentry, mcam->bmap_reverse); |
2323 | mcam->bmap_fcnt++; |
2324 | } |
2325 | |
2326 | static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, |
2327 | int blkaddr, u16 pcifunc) |
2328 | { |
2329 | u16 index, cntr; |
2330 | |
2331 | /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ |
2332 | for (index = 0; index < mcam->bmap_entries; index++) { |
2333 | if (mcam->entry2pfvf_map[index] == pcifunc) { |
2334 | mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; |
2335 | /* Free the entry in bitmap */ |
2336 | npc_mcam_clear_bit(mcam, index); |
2337 | /* Disable the entry */ |
2338 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable: false); |
2339 | |
2340 | /* Update entry2counter mapping */ |
2341 | cntr = mcam->entry2cntr_map[index]; |
2342 | if (cntr != NPC_MCAM_INVALID_MAP) |
2343 | npc_unmap_mcam_entry_and_cntr(rvu, mcam, |
2344 | blkaddr, entry: index, |
2345 | cntr); |
2346 | mcam->entry2target_pffunc[index] = 0x0; |
2347 | } |
2348 | } |
2349 | } |
2350 | |
2351 | static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, |
2352 | u16 pcifunc) |
2353 | { |
2354 | u16 cntr; |
2355 | |
2356 | /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */ |
2357 | for (cntr = 0; cntr < mcam->counters.max; cntr++) { |
2358 | if (mcam->cntr2pfvf_map[cntr] == pcifunc) { |
2359 | mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; |
2360 | mcam->cntr_refcnt[cntr] = 0; |
2361 | rvu_free_rsrc(rsrc: &mcam->counters, id: cntr); |
2362 | /* This API is expected to be called after freeing |
2363 | * MCAM entries, which inturn will remove |
2364 | * 'entry to counter' mapping. |
2365 | * No need to do it again. |
2366 | */ |
2367 | } |
2368 | } |
2369 | } |
2370 | |
2371 | /* Find area of contiguous free entries of size 'nr'. |
2372 | * If not found return max contiguous free entries available. |
2373 | */ |
2374 | static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start, |
2375 | u16 nr, u16 *max_area) |
2376 | { |
2377 | u16 max_area_start = 0; |
2378 | u16 index, next, end; |
2379 | |
2380 | *max_area = 0; |
2381 | |
2382 | again: |
2383 | index = find_next_zero_bit(addr: map, size, offset: start); |
2384 | if (index >= size) |
2385 | return max_area_start; |
2386 | |
2387 | end = ((index + nr) >= size) ? size : index + nr; |
2388 | next = find_next_bit(addr: map, size: end, offset: index); |
2389 | if (*max_area < (next - index)) { |
2390 | *max_area = next - index; |
2391 | max_area_start = index; |
2392 | } |
2393 | |
2394 | if (next < end) { |
2395 | start = next + 1; |
2396 | goto again; |
2397 | } |
2398 | |
2399 | return max_area_start; |
2400 | } |
2401 | |
2402 | /* Find number of free MCAM entries available |
2403 | * within range i.e in between 'start' and 'end'. |
2404 | */ |
2405 | static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end) |
2406 | { |
2407 | u16 index, next; |
2408 | u16 fcnt = 0; |
2409 | |
2410 | again: |
2411 | if (start >= end) |
2412 | return fcnt; |
2413 | |
2414 | index = find_next_zero_bit(addr: map, size: end, offset: start); |
2415 | if (index >= end) |
2416 | return fcnt; |
2417 | |
2418 | next = find_next_bit(addr: map, size: end, offset: index); |
2419 | if (next <= end) { |
2420 | fcnt += next - index; |
2421 | start = next + 1; |
2422 | goto again; |
2423 | } |
2424 | |
2425 | fcnt += end - index; |
2426 | return fcnt; |
2427 | } |
2428 | |
2429 | static void |
2430 | npc_get_mcam_search_range_priority(struct npc_mcam *mcam, |
2431 | struct npc_mcam_alloc_entry_req *req, |
2432 | u16 *start, u16 *end, bool *reverse) |
2433 | { |
2434 | u16 fcnt; |
2435 | |
2436 | if (req->priority == NPC_MCAM_HIGHER_PRIO) |
2437 | goto hprio; |
2438 | |
2439 | /* For a low priority entry allocation |
2440 | * - If reference entry is not in hprio zone then |
2441 | * search range: ref_entry to end. |
2442 | * - If reference entry is in hprio zone and if |
2443 | * request can be accomodated in non-hprio zone then |
2444 | * search range: 'start of middle zone' to 'end' |
2445 | * - else search in reverse, so that less number of hprio |
2446 | * zone entries are allocated. |
2447 | */ |
2448 | |
2449 | *reverse = false; |
2450 | *start = req->ref_entry + 1; |
2451 | *end = mcam->bmap_entries; |
2452 | |
2453 | if (req->ref_entry >= mcam->hprio_end) |
2454 | return; |
2455 | |
2456 | fcnt = npc_mcam_get_free_count(map: mcam->bmap, |
2457 | start: mcam->hprio_end, end: mcam->bmap_entries); |
2458 | if (fcnt > req->count) |
2459 | *start = mcam->hprio_end; |
2460 | else |
2461 | *reverse = true; |
2462 | return; |
2463 | |
2464 | hprio: |
2465 | /* For a high priority entry allocation, search is always |
2466 | * in reverse to preserve hprio zone entries. |
2467 | * - If reference entry is not in lprio zone then |
2468 | * search range: 0 to ref_entry. |
2469 | * - If reference entry is in lprio zone and if |
2470 | * request can be accomodated in middle zone then |
2471 | * search range: 'hprio_end' to 'lprio_start' |
2472 | */ |
2473 | |
2474 | *reverse = true; |
2475 | *start = 0; |
2476 | *end = req->ref_entry; |
2477 | |
2478 | if (req->ref_entry <= mcam->lprio_start) |
2479 | return; |
2480 | |
2481 | fcnt = npc_mcam_get_free_count(map: mcam->bmap, |
2482 | start: mcam->hprio_end, end: mcam->lprio_start); |
2483 | if (fcnt < req->count) |
2484 | return; |
2485 | *start = mcam->hprio_end; |
2486 | *end = mcam->lprio_start; |
2487 | } |
2488 | |
2489 | static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc, |
2490 | struct npc_mcam_alloc_entry_req *req, |
2491 | struct npc_mcam_alloc_entry_rsp *rsp) |
2492 | { |
2493 | u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; |
2494 | u16 fcnt, hp_fcnt, lp_fcnt; |
2495 | u16 start, end, index; |
2496 | int entry, next_start; |
2497 | bool reverse = false; |
2498 | unsigned long *bmap; |
2499 | u16 max_contig; |
2500 | |
2501 | mutex_lock(&mcam->lock); |
2502 | |
2503 | /* Check if there are any free entries */ |
2504 | if (!mcam->bmap_fcnt) { |
2505 | mutex_unlock(lock: &mcam->lock); |
2506 | return NPC_MCAM_ALLOC_FAILED; |
2507 | } |
2508 | |
2509 | /* MCAM entries are divided into high priority, middle and |
2510 | * low priority zones. Idea is to not allocate top and lower |
2511 | * most entries as much as possible, this is to increase |
2512 | * probability of honouring priority allocation requests. |
2513 | * |
2514 | * Two bitmaps are used for mcam entry management, |
2515 | * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'. |
2516 | * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'. |
2517 | * |
2518 | * Reverse bitmap is used to allocate entries |
2519 | * - when a higher priority entry is requested |
2520 | * - when available free entries are less. |
2521 | * Lower priority ones out of avaialble free entries are always |
2522 | * chosen when 'high vs low' question arises. |
2523 | */ |
2524 | |
2525 | /* Get the search range for priority allocation request */ |
2526 | if (req->priority) { |
2527 | npc_get_mcam_search_range_priority(mcam, req, |
2528 | start: &start, end: &end, reverse: &reverse); |
2529 | goto alloc; |
2530 | } |
2531 | |
2532 | /* For a VF base MCAM match rule is set by its PF. And all the |
2533 | * further MCAM rules installed by VF on its own are |
2534 | * concatenated with the base rule set by its PF. Hence PF entries |
2535 | * should be at lower priority compared to VF entries. Otherwise |
2536 | * base rule is hit always and rules installed by VF will be of |
2537 | * no use. Hence if the request is from PF and NOT a priority |
2538 | * allocation request then allocate low priority entries. |
2539 | */ |
2540 | if (!(pcifunc & RVU_PFVF_FUNC_MASK)) |
2541 | goto lprio_alloc; |
2542 | |
2543 | /* Find out the search range for non-priority allocation request |
2544 | * |
2545 | * Get MCAM free entry count in middle zone. |
2546 | */ |
2547 | lp_fcnt = npc_mcam_get_free_count(map: mcam->bmap, |
2548 | start: mcam->lprio_start, |
2549 | end: mcam->bmap_entries); |
2550 | hp_fcnt = npc_mcam_get_free_count(map: mcam->bmap, start: 0, end: mcam->hprio_end); |
2551 | fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt; |
2552 | |
2553 | /* Check if request can be accomodated in the middle zone */ |
2554 | if (fcnt > req->count) { |
2555 | start = mcam->hprio_end; |
2556 | end = mcam->lprio_start; |
2557 | } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) { |
2558 | /* Expand search zone from half of hprio zone to |
2559 | * half of lprio zone. |
2560 | */ |
2561 | start = mcam->hprio_end / 2; |
2562 | end = mcam->bmap_entries - (mcam->lprio_count / 2); |
2563 | reverse = true; |
2564 | } else { |
2565 | /* Not enough free entries, search all entries in reverse, |
2566 | * so that low priority ones will get used up. |
2567 | */ |
2568 | lprio_alloc: |
2569 | reverse = true; |
2570 | start = 0; |
2571 | end = mcam->bmap_entries; |
2572 | } |
2573 | |
2574 | alloc: |
2575 | if (reverse) { |
2576 | bmap = mcam->bmap_reverse; |
2577 | start = mcam->bmap_entries - start; |
2578 | end = mcam->bmap_entries - end; |
2579 | swap(start, end); |
2580 | } else { |
2581 | bmap = mcam->bmap; |
2582 | } |
2583 | |
2584 | if (req->contig) { |
2585 | /* Allocate requested number of contiguous entries, if |
2586 | * unsuccessful find max contiguous entries available. |
2587 | */ |
2588 | index = npc_mcam_find_zero_area(map: bmap, size: end, start, |
2589 | nr: req->count, max_area: &max_contig); |
2590 | rsp->count = max_contig; |
2591 | if (reverse) |
2592 | rsp->entry = mcam->bmap_entries - index - max_contig; |
2593 | else |
2594 | rsp->entry = index; |
2595 | } else { |
2596 | /* Allocate requested number of non-contiguous entries, |
2597 | * if unsuccessful allocate as many as possible. |
2598 | */ |
2599 | rsp->count = 0; |
2600 | next_start = start; |
2601 | for (entry = 0; entry < req->count; entry++) { |
2602 | index = find_next_zero_bit(addr: bmap, size: end, offset: next_start); |
2603 | if (index >= end) |
2604 | break; |
2605 | |
2606 | next_start = start + (index - start) + 1; |
2607 | |
2608 | /* Save the entry's index */ |
2609 | if (reverse) |
2610 | index = mcam->bmap_entries - index - 1; |
2611 | entry_list[entry] = index; |
2612 | rsp->count++; |
2613 | } |
2614 | } |
2615 | |
2616 | /* If allocating requested no of entries is unsucessful, |
2617 | * expand the search range to full bitmap length and retry. |
2618 | */ |
2619 | if (!req->priority && (rsp->count < req->count) && |
2620 | ((end - start) != mcam->bmap_entries)) { |
2621 | reverse = true; |
2622 | start = 0; |
2623 | end = mcam->bmap_entries; |
2624 | goto alloc; |
2625 | } |
2626 | |
2627 | /* For priority entry allocation requests, if allocation is |
2628 | * failed then expand search to max possible range and retry. |
2629 | */ |
2630 | if (req->priority && rsp->count < req->count) { |
2631 | if (req->priority == NPC_MCAM_LOWER_PRIO && |
2632 | (start != (req->ref_entry + 1))) { |
2633 | start = req->ref_entry + 1; |
2634 | end = mcam->bmap_entries; |
2635 | reverse = false; |
2636 | goto alloc; |
2637 | } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) && |
2638 | ((end - start) != req->ref_entry)) { |
2639 | start = 0; |
2640 | end = req->ref_entry; |
2641 | reverse = true; |
2642 | goto alloc; |
2643 | } |
2644 | } |
2645 | |
2646 | /* Copy MCAM entry indices into mbox response entry_list. |
2647 | * Requester always expects indices in ascending order, so |
2648 | * reverse the list if reverse bitmap is used for allocation. |
2649 | */ |
2650 | if (!req->contig && rsp->count) { |
2651 | index = 0; |
2652 | for (entry = rsp->count - 1; entry >= 0; entry--) { |
2653 | if (reverse) |
2654 | rsp->entry_list[index++] = entry_list[entry]; |
2655 | else |
2656 | rsp->entry_list[entry] = entry_list[entry]; |
2657 | } |
2658 | } |
2659 | |
2660 | /* Mark the allocated entries as used and set nixlf mapping */ |
2661 | for (entry = 0; entry < rsp->count; entry++) { |
2662 | index = req->contig ? |
2663 | (rsp->entry + entry) : rsp->entry_list[entry]; |
2664 | npc_mcam_set_bit(mcam, index); |
2665 | mcam->entry2pfvf_map[index] = pcifunc; |
2666 | mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; |
2667 | } |
2668 | |
2669 | /* Update available free count in mbox response */ |
2670 | rsp->free_count = mcam->bmap_fcnt; |
2671 | |
2672 | mutex_unlock(lock: &mcam->lock); |
2673 | return 0; |
2674 | } |
2675 | |
2676 | /* Marks bitmaps to reserved the mcam slot */ |
2677 | void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx) |
2678 | { |
2679 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2680 | |
2681 | npc_mcam_set_bit(mcam, index: entry_idx); |
2682 | } |
2683 | |
2684 | int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, |
2685 | struct npc_mcam_alloc_entry_req *req, |
2686 | struct npc_mcam_alloc_entry_rsp *rsp) |
2687 | { |
2688 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2689 | u16 pcifunc = req->hdr.pcifunc; |
2690 | int blkaddr; |
2691 | |
2692 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2693 | if (blkaddr < 0) |
2694 | return NPC_MCAM_INVALID_REQ; |
2695 | |
2696 | rsp->entry = NPC_MCAM_ENTRY_INVALID; |
2697 | rsp->free_count = 0; |
2698 | |
2699 | /* Check if ref_entry is greater that the range |
2700 | * then set it to max value. |
2701 | */ |
2702 | if (req->ref_entry > mcam->bmap_entries) |
2703 | req->ref_entry = mcam->bmap_entries; |
2704 | |
2705 | /* ref_entry can't be '0' if requested priority is high. |
2706 | * Can't be last entry if requested priority is low. |
2707 | */ |
2708 | if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) || |
2709 | ((req->ref_entry == mcam->bmap_entries) && |
2710 | req->priority == NPC_MCAM_LOWER_PRIO)) |
2711 | return NPC_MCAM_INVALID_REQ; |
2712 | |
2713 | /* Since list of allocated indices needs to be sent to requester, |
2714 | * max number of non-contiguous entries per mbox msg is limited. |
2715 | */ |
2716 | if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) { |
2717 | dev_err(rvu->dev, |
2718 | "%s: %d Non-contiguous MCAM entries requested is more than max (%d) allowed\n" , |
2719 | __func__, req->count, NPC_MAX_NONCONTIG_ENTRIES); |
2720 | return NPC_MCAM_INVALID_REQ; |
2721 | } |
2722 | |
2723 | /* Alloc request from PFFUNC with no NIXLF attached should be denied */ |
2724 | if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) |
2725 | return NPC_MCAM_ALLOC_DENIED; |
2726 | |
2727 | return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp); |
2728 | } |
2729 | |
2730 | int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, |
2731 | struct npc_mcam_free_entry_req *req, |
2732 | struct msg_rsp *rsp) |
2733 | { |
2734 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2735 | u16 pcifunc = req->hdr.pcifunc; |
2736 | int blkaddr, rc = 0; |
2737 | u16 cntr; |
2738 | |
2739 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2740 | if (blkaddr < 0) |
2741 | return NPC_MCAM_INVALID_REQ; |
2742 | |
2743 | /* Free request from PFFUNC with no NIXLF attached, ignore */ |
2744 | if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) |
2745 | return NPC_MCAM_INVALID_REQ; |
2746 | |
2747 | mutex_lock(&mcam->lock); |
2748 | |
2749 | if (req->all) |
2750 | goto free_all; |
2751 | |
2752 | rc = npc_mcam_verify_entry(mcam, pcifunc, entry: req->entry); |
2753 | if (rc) |
2754 | goto exit; |
2755 | |
2756 | mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP; |
2757 | mcam->entry2target_pffunc[req->entry] = 0x0; |
2758 | npc_mcam_clear_bit(mcam, index: req->entry); |
2759 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: req->entry, enable: false); |
2760 | |
2761 | /* Update entry2counter mapping */ |
2762 | cntr = mcam->entry2cntr_map[req->entry]; |
2763 | if (cntr != NPC_MCAM_INVALID_MAP) |
2764 | npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, |
2765 | entry: req->entry, cntr); |
2766 | |
2767 | goto exit; |
2768 | |
2769 | free_all: |
2770 | /* Free up all entries allocated to requesting PFFUNC */ |
2771 | npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); |
2772 | exit: |
2773 | mutex_unlock(lock: &mcam->lock); |
2774 | return rc; |
2775 | } |
2776 | |
2777 | int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu, |
2778 | struct npc_mcam_read_entry_req *req, |
2779 | struct npc_mcam_read_entry_rsp *rsp) |
2780 | { |
2781 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2782 | u16 pcifunc = req->hdr.pcifunc; |
2783 | int blkaddr, rc; |
2784 | |
2785 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2786 | if (blkaddr < 0) |
2787 | return NPC_MCAM_INVALID_REQ; |
2788 | |
2789 | mutex_lock(&mcam->lock); |
2790 | rc = npc_mcam_verify_entry(mcam, pcifunc, entry: req->entry); |
2791 | if (!rc) { |
2792 | npc_read_mcam_entry(rvu, mcam, blkaddr, src: req->entry, |
2793 | entry: &rsp->entry_data, |
2794 | intf: &rsp->intf, ena: &rsp->enable); |
2795 | } |
2796 | |
2797 | mutex_unlock(lock: &mcam->lock); |
2798 | return rc; |
2799 | } |
2800 | |
2801 | int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, |
2802 | struct npc_mcam_write_entry_req *req, |
2803 | struct msg_rsp *rsp) |
2804 | { |
2805 | struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc: req->hdr.pcifunc); |
2806 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2807 | u16 pcifunc = req->hdr.pcifunc; |
2808 | int blkaddr, rc; |
2809 | u8 nix_intf; |
2810 | |
2811 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2812 | if (blkaddr < 0) |
2813 | return NPC_MCAM_INVALID_REQ; |
2814 | |
2815 | mutex_lock(&mcam->lock); |
2816 | rc = npc_mcam_verify_entry(mcam, pcifunc, entry: req->entry); |
2817 | if (rc) |
2818 | goto exit; |
2819 | |
2820 | if (req->set_cntr && |
2821 | npc_mcam_verify_counter(mcam, pcifunc, cntr: req->cntr)) { |
2822 | rc = NPC_MCAM_INVALID_REQ; |
2823 | goto exit; |
2824 | } |
2825 | |
2826 | if (!is_npc_interface_valid(rvu, intf: req->intf)) { |
2827 | rc = NPC_MCAM_INVALID_REQ; |
2828 | goto exit; |
2829 | } |
2830 | |
2831 | if (is_npc_intf_tx(intf: req->intf)) |
2832 | nix_intf = pfvf->nix_tx_intf; |
2833 | else |
2834 | nix_intf = pfvf->nix_rx_intf; |
2835 | |
2836 | /* For AF installed rules, the nix_intf should be set to target NIX */ |
2837 | if (is_pffunc_af(pcifunc: req->hdr.pcifunc)) |
2838 | nix_intf = req->intf; |
2839 | |
2840 | npc_config_mcam_entry(rvu, mcam, blkaddr, index: req->entry, intf: nix_intf, |
2841 | entry: &req->entry_data, enable: req->enable_entry); |
2842 | |
2843 | if (req->set_cntr) |
2844 | npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, |
2845 | entry: req->entry, cntr: req->cntr); |
2846 | |
2847 | rc = 0; |
2848 | exit: |
2849 | mutex_unlock(lock: &mcam->lock); |
2850 | return rc; |
2851 | } |
2852 | |
2853 | int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, |
2854 | struct npc_mcam_ena_dis_entry_req *req, |
2855 | struct msg_rsp *rsp) |
2856 | { |
2857 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2858 | u16 pcifunc = req->hdr.pcifunc; |
2859 | int blkaddr, rc; |
2860 | |
2861 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2862 | if (blkaddr < 0) |
2863 | return NPC_MCAM_INVALID_REQ; |
2864 | |
2865 | mutex_lock(&mcam->lock); |
2866 | rc = npc_mcam_verify_entry(mcam, pcifunc, entry: req->entry); |
2867 | mutex_unlock(lock: &mcam->lock); |
2868 | if (rc) |
2869 | return rc; |
2870 | |
2871 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: req->entry, enable: true); |
2872 | |
2873 | return 0; |
2874 | } |
2875 | |
2876 | int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, |
2877 | struct npc_mcam_ena_dis_entry_req *req, |
2878 | struct msg_rsp *rsp) |
2879 | { |
2880 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2881 | u16 pcifunc = req->hdr.pcifunc; |
2882 | int blkaddr, rc; |
2883 | |
2884 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2885 | if (blkaddr < 0) |
2886 | return NPC_MCAM_INVALID_REQ; |
2887 | |
2888 | mutex_lock(&mcam->lock); |
2889 | rc = npc_mcam_verify_entry(mcam, pcifunc, entry: req->entry); |
2890 | mutex_unlock(lock: &mcam->lock); |
2891 | if (rc) |
2892 | return rc; |
2893 | |
2894 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: req->entry, enable: false); |
2895 | |
2896 | return 0; |
2897 | } |
2898 | |
2899 | int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, |
2900 | struct npc_mcam_shift_entry_req *req, |
2901 | struct npc_mcam_shift_entry_rsp *rsp) |
2902 | { |
2903 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2904 | u16 pcifunc = req->hdr.pcifunc; |
2905 | u16 old_entry, new_entry; |
2906 | int blkaddr, rc = 0; |
2907 | u16 index, cntr; |
2908 | |
2909 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2910 | if (blkaddr < 0) |
2911 | return NPC_MCAM_INVALID_REQ; |
2912 | |
2913 | if (req->shift_count > NPC_MCAM_MAX_SHIFTS) |
2914 | return NPC_MCAM_INVALID_REQ; |
2915 | |
2916 | mutex_lock(&mcam->lock); |
2917 | for (index = 0; index < req->shift_count; index++) { |
2918 | old_entry = req->curr_entry[index]; |
2919 | new_entry = req->new_entry[index]; |
2920 | |
2921 | /* Check if both old and new entries are valid and |
2922 | * does belong to this PFFUNC or not. |
2923 | */ |
2924 | rc = npc_mcam_verify_entry(mcam, pcifunc, entry: old_entry); |
2925 | if (rc) |
2926 | break; |
2927 | |
2928 | rc = npc_mcam_verify_entry(mcam, pcifunc, entry: new_entry); |
2929 | if (rc) |
2930 | break; |
2931 | |
2932 | /* new_entry should not have a counter mapped */ |
2933 | if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) { |
2934 | rc = NPC_MCAM_PERM_DENIED; |
2935 | break; |
2936 | } |
2937 | |
2938 | /* Disable the new_entry */ |
2939 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: new_entry, enable: false); |
2940 | |
2941 | /* Copy rule from old entry to new entry */ |
2942 | npc_copy_mcam_entry(rvu, mcam, blkaddr, src: old_entry, dest: new_entry); |
2943 | |
2944 | /* Copy counter mapping, if any */ |
2945 | cntr = mcam->entry2cntr_map[old_entry]; |
2946 | if (cntr != NPC_MCAM_INVALID_MAP) { |
2947 | npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, |
2948 | entry: old_entry, cntr); |
2949 | npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, |
2950 | entry: new_entry, cntr); |
2951 | } |
2952 | |
2953 | /* Enable new_entry and disable old_entry */ |
2954 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: new_entry, enable: true); |
2955 | npc_enable_mcam_entry(rvu, mcam, blkaddr, index: old_entry, enable: false); |
2956 | } |
2957 | |
2958 | /* If shift has failed then report the failed index */ |
2959 | if (index != req->shift_count) { |
2960 | rc = NPC_MCAM_PERM_DENIED; |
2961 | rsp->failed_entry_idx = index; |
2962 | } |
2963 | |
2964 | mutex_unlock(lock: &mcam->lock); |
2965 | return rc; |
2966 | } |
2967 | |
2968 | int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, |
2969 | struct npc_mcam_alloc_counter_req *req, |
2970 | struct npc_mcam_alloc_counter_rsp *rsp) |
2971 | { |
2972 | struct npc_mcam *mcam = &rvu->hw->mcam; |
2973 | u16 pcifunc = req->hdr.pcifunc; |
2974 | u16 max_contig, cntr; |
2975 | int blkaddr, index; |
2976 | |
2977 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
2978 | if (blkaddr < 0) |
2979 | return NPC_MCAM_INVALID_REQ; |
2980 | |
2981 | /* If the request is from a PFFUNC with no NIXLF attached, ignore */ |
2982 | if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) |
2983 | return NPC_MCAM_INVALID_REQ; |
2984 | |
2985 | /* Since list of allocated counter IDs needs to be sent to requester, |
2986 | * max number of non-contiguous counters per mbox msg is limited. |
2987 | */ |
2988 | if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) |
2989 | return NPC_MCAM_INVALID_REQ; |
2990 | |
2991 | mutex_lock(&mcam->lock); |
2992 | |
2993 | /* Check if unused counters are available or not */ |
2994 | if (!rvu_rsrc_free_count(rsrc: &mcam->counters)) { |
2995 | mutex_unlock(lock: &mcam->lock); |
2996 | return NPC_MCAM_ALLOC_FAILED; |
2997 | } |
2998 | |
2999 | rsp->count = 0; |
3000 | |
3001 | if (req->contig) { |
3002 | /* Allocate requested number of contiguous counters, if |
3003 | * unsuccessful find max contiguous entries available. |
3004 | */ |
3005 | index = npc_mcam_find_zero_area(map: mcam->counters.bmap, |
3006 | size: mcam->counters.max, start: 0, |
3007 | nr: req->count, max_area: &max_contig); |
3008 | rsp->count = max_contig; |
3009 | rsp->cntr = index; |
3010 | for (cntr = index; cntr < (index + max_contig); cntr++) { |
3011 | __set_bit(cntr, mcam->counters.bmap); |
3012 | mcam->cntr2pfvf_map[cntr] = pcifunc; |
3013 | } |
3014 | } else { |
3015 | /* Allocate requested number of non-contiguous counters, |
3016 | * if unsuccessful allocate as many as possible. |
3017 | */ |
3018 | for (cntr = 0; cntr < req->count; cntr++) { |
3019 | index = rvu_alloc_rsrc(rsrc: &mcam->counters); |
3020 | if (index < 0) |
3021 | break; |
3022 | rsp->cntr_list[cntr] = index; |
3023 | rsp->count++; |
3024 | mcam->cntr2pfvf_map[index] = pcifunc; |
3025 | } |
3026 | } |
3027 | |
3028 | mutex_unlock(lock: &mcam->lock); |
3029 | return 0; |
3030 | } |
3031 | |
3032 | int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, |
3033 | struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) |
3034 | { |
3035 | struct npc_mcam *mcam = &rvu->hw->mcam; |
3036 | u16 index, entry = 0; |
3037 | int blkaddr, err; |
3038 | |
3039 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
3040 | if (blkaddr < 0) |
3041 | return NPC_MCAM_INVALID_REQ; |
3042 | |
3043 | mutex_lock(&mcam->lock); |
3044 | err = npc_mcam_verify_counter(mcam, pcifunc: req->hdr.pcifunc, cntr: req->cntr); |
3045 | if (err) { |
3046 | mutex_unlock(lock: &mcam->lock); |
3047 | return err; |
3048 | } |
3049 | |
3050 | /* Mark counter as free/unused */ |
3051 | mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP; |
3052 | rvu_free_rsrc(rsrc: &mcam->counters, id: req->cntr); |
3053 | |
3054 | /* Disable all MCAM entry's stats which are using this counter */ |
3055 | while (entry < mcam->bmap_entries) { |
3056 | if (!mcam->cntr_refcnt[req->cntr]) |
3057 | break; |
3058 | |
3059 | index = find_next_bit(addr: mcam->bmap, size: mcam->bmap_entries, offset: entry); |
3060 | if (index >= mcam->bmap_entries) |
3061 | break; |
3062 | entry = index + 1; |
3063 | if (mcam->entry2cntr_map[index] != req->cntr) |
3064 | continue; |
3065 | |
3066 | npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, |
3067 | entry: index, cntr: req->cntr); |
3068 | } |
3069 | |
3070 | mutex_unlock(lock: &mcam->lock); |
3071 | return 0; |
3072 | } |
3073 | |
3074 | int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, |
3075 | struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp) |
3076 | { |
3077 | struct npc_mcam *mcam = &rvu->hw->mcam; |
3078 | u16 index, entry = 0; |
3079 | int blkaddr, rc; |
3080 | |
3081 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
3082 | if (blkaddr < 0) |
3083 | return NPC_MCAM_INVALID_REQ; |
3084 | |
3085 | mutex_lock(&mcam->lock); |
3086 | rc = npc_mcam_verify_counter(mcam, pcifunc: req->hdr.pcifunc, cntr: req->cntr); |
3087 | if (rc) |
3088 | goto exit; |
3089 | |
3090 | /* Unmap the MCAM entry and counter */ |
3091 | if (!req->all) { |
3092 | rc = npc_mcam_verify_entry(mcam, pcifunc: req->hdr.pcifunc, entry: req->entry); |
3093 | if (rc) |
3094 | goto exit; |
3095 | npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, |
3096 | entry: req->entry, cntr: req->cntr); |
3097 | goto exit; |
3098 | } |
3099 | |
3100 | /* Disable all MCAM entry's stats which are using this counter */ |
3101 | while (entry < mcam->bmap_entries) { |
3102 | if (!mcam->cntr_refcnt[req->cntr]) |
3103 | break; |
3104 | |
3105 | index = find_next_bit(addr: mcam->bmap, size: mcam->bmap_entries, offset: entry); |
3106 | if (index >= mcam->bmap_entries) |
3107 | break; |
3108 | entry = index + 1; |
3109 | |
3110 | if (mcam->entry2cntr_map[index] != req->cntr) |
3111 | continue; |
3112 | |
3113 | npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, |
3114 | entry: index, cntr: req->cntr); |
3115 | } |
3116 | exit: |
3117 | mutex_unlock(lock: &mcam->lock); |
3118 | return rc; |
3119 | } |
3120 | |
3121 | int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, |
3122 | struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) |
3123 | { |
3124 | struct npc_mcam *mcam = &rvu->hw->mcam; |
3125 | int blkaddr, err; |
3126 | |
3127 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
3128 | if (blkaddr < 0) |
3129 | return NPC_MCAM_INVALID_REQ; |
3130 | |
3131 | mutex_lock(&mcam->lock); |
3132 | err = npc_mcam_verify_counter(mcam, pcifunc: req->hdr.pcifunc, cntr: req->cntr); |
3133 | mutex_unlock(lock: &mcam->lock); |
3134 | if (err) |
3135 | return err; |
3136 | |
3137 | rvu_write64(rvu, block: blkaddr, NPC_AF_MATCH_STATX(req->cntr), val: 0x00); |
3138 | |
3139 | return 0; |
3140 | } |
3141 | |
3142 | int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, |
3143 | struct npc_mcam_oper_counter_req *req, |
3144 | struct npc_mcam_oper_counter_rsp *rsp) |
3145 | { |
3146 | struct npc_mcam *mcam = &rvu->hw->mcam; |
3147 | int blkaddr, err; |
3148 | |
3149 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
3150 | if (blkaddr < 0) |
3151 | return NPC_MCAM_INVALID_REQ; |
3152 | |
3153 | mutex_lock(&mcam->lock); |
3154 | err = npc_mcam_verify_counter(mcam, pcifunc: req->hdr.pcifunc, cntr: req->cntr); |
3155 | mutex_unlock(lock: &mcam->lock); |
3156 | if (err) |
3157 | return err; |
3158 | |
3159 | rsp->stat = rvu_read64(rvu, block: blkaddr, NPC_AF_MATCH_STATX(req->cntr)); |
3160 | rsp->stat &= BIT_ULL(48) - 1; |
3161 | |
3162 | return 0; |
3163 | } |
3164 | |
3165 | int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, |
3166 | struct npc_mcam_alloc_and_write_entry_req *req, |
3167 | struct npc_mcam_alloc_and_write_entry_rsp *rsp) |
3168 | { |
3169 | struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc: req->hdr.pcifunc); |
3170 | struct npc_mcam_alloc_counter_req cntr_req; |
3171 | struct npc_mcam_alloc_counter_rsp cntr_rsp; |
3172 | struct npc_mcam_alloc_entry_req entry_req; |
3173 | struct npc_mcam_alloc_entry_rsp entry_rsp; |
3174 | struct npc_mcam *mcam = &rvu->hw->mcam; |
3175 | u16 entry = NPC_MCAM_ENTRY_INVALID; |
3176 | u16 cntr = NPC_MCAM_ENTRY_INVALID; |
3177 | int blkaddr, rc; |
3178 | u8 nix_intf; |
3179 | |
3180 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
3181 | if (blkaddr < 0) |
3182 | return NPC_MCAM_INVALID_REQ; |
3183 | |
3184 | if (!is_npc_interface_valid(rvu, intf: req->intf)) |
3185 | return NPC_MCAM_INVALID_REQ; |
3186 | |
3187 | /* Try to allocate a MCAM entry */ |
3188 | entry_req.hdr.pcifunc = req->hdr.pcifunc; |
3189 | entry_req.contig = true; |
3190 | entry_req.priority = req->priority; |
3191 | entry_req.ref_entry = req->ref_entry; |
3192 | entry_req.count = 1; |
3193 | |
3194 | rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, |
3195 | req: &entry_req, rsp: &entry_rsp); |
3196 | if (rc) |
3197 | return rc; |
3198 | |
3199 | if (!entry_rsp.count) |
3200 | return NPC_MCAM_ALLOC_FAILED; |
3201 | |
3202 | entry = entry_rsp.entry; |
3203 | |
3204 | if (!req->alloc_cntr) |
3205 | goto write_entry; |
3206 | |
3207 | /* Now allocate counter */ |
3208 | cntr_req.hdr.pcifunc = req->hdr.pcifunc; |
3209 | cntr_req.contig = true; |
3210 | cntr_req.count = 1; |
3211 | |
3212 | rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, req: &cntr_req, rsp: &cntr_rsp); |
3213 | if (rc) { |
3214 | /* Free allocated MCAM entry */ |
3215 | mutex_lock(&mcam->lock); |
3216 | mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP; |
3217 | npc_mcam_clear_bit(mcam, index: entry); |
3218 | mutex_unlock(lock: &mcam->lock); |
3219 | return rc; |
3220 | } |
3221 | |
3222 | cntr = cntr_rsp.cntr; |
3223 | |
3224 | write_entry: |
3225 | mutex_lock(&mcam->lock); |
3226 | |
3227 | if (is_npc_intf_tx(intf: req->intf)) |
3228 | nix_intf = pfvf->nix_tx_intf; |
3229 | else |
3230 | nix_intf = pfvf->nix_rx_intf; |
3231 | |
3232 | npc_config_mcam_entry(rvu, mcam, blkaddr, index: entry, intf: nix_intf, |
3233 | entry: &req->entry_data, enable: req->enable_entry); |
3234 | |
3235 | if (req->alloc_cntr) |
3236 | npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr); |
3237 | mutex_unlock(lock: &mcam->lock); |
3238 | |
3239 | rsp->entry = entry; |
3240 | rsp->cntr = cntr; |
3241 | |
3242 | return 0; |
3243 | } |
3244 | |
3245 | #define GET_KEX_CFG(intf) \ |
3246 | rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) |
3247 | |
3248 | #define GET_KEX_FLAGS(ld) \ |
3249 | rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld)) |
3250 | |
3251 | #define GET_KEX_LD(intf, lid, lt, ld) \ |
3252 | rvu_read64(rvu, BLKADDR_NPC, \ |
3253 | NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)) |
3254 | |
3255 | #define GET_KEX_LDFLAGS(intf, ld, fl) \ |
3256 | rvu_read64(rvu, BLKADDR_NPC, \ |
3257 | NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl)) |
3258 | |
3259 | int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, |
3260 | struct npc_get_kex_cfg_rsp *rsp) |
3261 | { |
3262 | int lid, lt, ld, fl; |
3263 | |
3264 | rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX); |
3265 | rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX); |
3266 | for (lid = 0; lid < NPC_MAX_LID; lid++) { |
3267 | for (lt = 0; lt < NPC_MAX_LT; lt++) { |
3268 | for (ld = 0; ld < NPC_MAX_LD; ld++) { |
3269 | rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] = |
3270 | GET_KEX_LD(NIX_INTF_RX, lid, lt, ld); |
3271 | rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] = |
3272 | GET_KEX_LD(NIX_INTF_TX, lid, lt, ld); |
3273 | } |
3274 | } |
3275 | } |
3276 | for (ld = 0; ld < NPC_MAX_LD; ld++) |
3277 | rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld); |
3278 | |
3279 | for (ld = 0; ld < NPC_MAX_LD; ld++) { |
3280 | for (fl = 0; fl < NPC_MAX_LFL; fl++) { |
3281 | rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] = |
3282 | GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl); |
3283 | rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] = |
3284 | GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl); |
3285 | } |
3286 | } |
3287 | memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN); |
3288 | return 0; |
3289 | } |
3290 | |
3291 | static int |
3292 | npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind, |
3293 | u8 var_len_off, u8 var_len_off_mask, u8 shift_dir) |
3294 | { |
3295 | struct npc_kpu_action0 *act0; |
3296 | u8 shift_count = 0; |
3297 | int blkaddr; |
3298 | u64 val; |
3299 | |
3300 | if (!var_len_off_mask) |
3301 | return -EINVAL; |
3302 | |
3303 | if (var_len_off_mask != 0xff) { |
3304 | if (shift_dir) |
3305 | shift_count = __ffs(var_len_off_mask); |
3306 | else |
3307 | shift_count = (8 - __fls(word: var_len_off_mask)); |
3308 | } |
3309 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc); |
3310 | if (blkaddr < 0) { |
3311 | dev_err(rvu->dev, "%s: NPC block not implemented\n" , __func__); |
3312 | return -EINVAL; |
3313 | } |
3314 | val = rvu_read64(rvu, block: blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); |
3315 | act0 = (struct npc_kpu_action0 *)&val; |
3316 | act0->var_len_shift = shift_count; |
3317 | act0->var_len_right = shift_dir; |
3318 | act0->var_len_mask = var_len_off_mask; |
3319 | act0->var_len_offset = var_len_off; |
3320 | rvu_write64(rvu, block: blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); |
3321 | return 0; |
3322 | } |
3323 | |
3324 | int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, |
3325 | u64 pkind, u8 var_len_off, u8 var_len_off_mask, |
3326 | u8 shift_dir) |
3327 | |
3328 | { |
3329 | struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); |
3330 | int blkaddr, nixlf, rc, intf_mode; |
3331 | int pf = rvu_get_pf(pcifunc); |
3332 | u64 rxpkind, txpkind; |
3333 | u8 cgx_id, lmac_id; |
3334 | |
3335 | /* use default pkind to disable edsa/higig */ |
3336 | rxpkind = rvu_npc_get_pkind(rvu, pf); |
3337 | txpkind = NPC_TX_DEF_PKIND; |
3338 | intf_mode = NPC_INTF_MODE_DEF; |
3339 | |
3340 | if (mode & OTX2_PRIV_FLAGS_CUSTOM) { |
3341 | if (pkind == NPC_RX_CUSTOM_PRE_L2_PKIND) { |
3342 | rc = npc_set_var_len_offset_pkind(rvu, pcifunc, pkind, |
3343 | var_len_off, |
3344 | var_len_off_mask, |
3345 | shift_dir); |
3346 | if (rc) |
3347 | return rc; |
3348 | } |
3349 | rxpkind = pkind; |
3350 | txpkind = pkind; |
3351 | } |
3352 | |
3353 | if (dir & PKIND_RX) { |
3354 | /* rx pkind set req valid only for cgx mapped PFs */ |
3355 | if (!is_cgx_config_permitted(rvu, pcifunc)) |
3356 | return 0; |
3357 | rvu_get_cgx_lmac_id(map: rvu->pf2cgxlmac_map[pf], cgx_id: &cgx_id, lmac_id: &lmac_id); |
3358 | |
3359 | rc = cgx_set_pkind(cgxd: rvu_cgx_pdata(cgx_id, rvu), lmac_id, |
3360 | pkind: rxpkind); |
3361 | if (rc) |
3362 | return rc; |
3363 | } |
3364 | |
3365 | if (dir & PKIND_TX) { |
3366 | /* Tx pkind set request valid if PCIFUNC has NIXLF attached */ |
3367 | rc = nix_get_nixlf(rvu, pcifunc, nixlf: &nixlf, nix_blkaddr: &blkaddr); |
3368 | if (rc) |
3369 | return rc; |
3370 | |
3371 | rvu_write64(rvu, block: blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), |
3372 | val: txpkind); |
3373 | } |
3374 | |
3375 | pfvf->intf_mode = intf_mode; |
3376 | return 0; |
3377 | } |
3378 | |
3379 | int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req, |
3380 | struct msg_rsp *rsp) |
3381 | { |
3382 | return rvu_npc_set_parse_mode(rvu, pcifunc: req->hdr.pcifunc, mode: req->mode, |
3383 | dir: req->dir, pkind: req->pkind, var_len_off: req->var_len_off, |
3384 | var_len_off_mask: req->var_len_off_mask, shift_dir: req->shift_dir); |
3385 | } |
3386 | |
3387 | int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu, |
3388 | struct msg_req *req, |
3389 | struct npc_mcam_read_base_rule_rsp *rsp) |
3390 | { |
3391 | struct npc_mcam *mcam = &rvu->hw->mcam; |
3392 | int index, blkaddr, nixlf, rc = 0; |
3393 | u16 pcifunc = req->hdr.pcifunc; |
3394 | struct rvu_pfvf *pfvf; |
3395 | u8 intf, enable; |
3396 | |
3397 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
3398 | if (blkaddr < 0) |
3399 | return NPC_MCAM_INVALID_REQ; |
3400 | |
3401 | /* Return the channel number in case of PF */ |
3402 | if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { |
3403 | pfvf = rvu_get_pfvf(rvu, pcifunc); |
3404 | rsp->entry.kw[0] = pfvf->rx_chan_base; |
3405 | rsp->entry.kw_mask[0] = 0xFFFULL; |
3406 | goto out; |
3407 | } |
3408 | |
3409 | /* Find the pkt steering rule installed by PF to this VF */ |
3410 | mutex_lock(&mcam->lock); |
3411 | for (index = 0; index < mcam->bmap_entries; index++) { |
3412 | if (mcam->entry2target_pffunc[index] == pcifunc) |
3413 | goto read_entry; |
3414 | } |
3415 | |
3416 | rc = nix_get_nixlf(rvu, pcifunc, nixlf: &nixlf, NULL); |
3417 | if (rc < 0) { |
3418 | mutex_unlock(lock: &mcam->lock); |
3419 | goto out; |
3420 | } |
3421 | /* Read the default ucast entry if there is no pkt steering rule */ |
3422 | index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, |
3423 | NIXLF_UCAST_ENTRY); |
3424 | read_entry: |
3425 | /* Read the mcam entry */ |
3426 | npc_read_mcam_entry(rvu, mcam, blkaddr, src: index, entry: &rsp->entry, intf: &intf, |
3427 | ena: &enable); |
3428 | mutex_unlock(lock: &mcam->lock); |
3429 | out: |
3430 | return rc; |
3431 | } |
3432 | |
3433 | int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu, |
3434 | struct npc_mcam_get_stats_req *req, |
3435 | struct npc_mcam_get_stats_rsp *rsp) |
3436 | { |
3437 | struct npc_mcam *mcam = &rvu->hw->mcam; |
3438 | u16 index, cntr; |
3439 | int blkaddr; |
3440 | u64 regval; |
3441 | u32 bank; |
3442 | |
3443 | blkaddr = rvu_get_blkaddr(rvu, blktype: BLKTYPE_NPC, pcifunc: 0); |
3444 | if (blkaddr < 0) |
3445 | return NPC_MCAM_INVALID_REQ; |
3446 | |
3447 | mutex_lock(&mcam->lock); |
3448 | |
3449 | index = req->entry & (mcam->banksize - 1); |
3450 | bank = npc_get_bank(mcam, index: req->entry); |
3451 | |
3452 | /* read MCAM entry STAT_ACT register */ |
3453 | regval = rvu_read64(rvu, block: blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank)); |
3454 | |
3455 | if (!(regval & rvu->hw->npc_stat_ena)) { |
3456 | rsp->stat_ena = 0; |
3457 | mutex_unlock(lock: &mcam->lock); |
3458 | return 0; |
3459 | } |
3460 | |
3461 | cntr = regval & 0x1FF; |
3462 | |
3463 | rsp->stat_ena = 1; |
3464 | rsp->stat = rvu_read64(rvu, block: blkaddr, NPC_AF_MATCH_STATX(cntr)); |
3465 | rsp->stat &= BIT_ULL(48) - 1; |
3466 | |
3467 | mutex_unlock(lock: &mcam->lock); |
3468 | |
3469 | return 0; |
3470 | } |
3471 | |