1/*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <net/tc_act/tc_gact.h>
34#include <linux/mlx5/fs.h>
35#include <net/vxlan.h>
36#include <net/geneve.h>
37#include <linux/bpf.h>
38#include <linux/debugfs.h>
39#include <linux/if_bridge.h>
40#include <linux/filter.h>
41#include <net/page_pool/types.h>
42#include <net/pkt_sched.h>
43#include <net/xdp_sock_drv.h>
44#include "eswitch.h"
45#include "en.h"
46#include "en/txrx.h"
47#include "en_tc.h"
48#include "en_rep.h"
49#include "en_accel/ipsec.h"
50#include "en_accel/macsec.h"
51#include "en_accel/en_accel.h"
52#include "en_accel/ktls.h"
53#include "lib/vxlan.h"
54#include "lib/clock.h"
55#include "en/port.h"
56#include "en/xdp.h"
57#include "lib/eq.h"
58#include "en/monitor_stats.h"
59#include "en/health.h"
60#include "en/params.h"
61#include "en/xsk/pool.h"
62#include "en/xsk/setup.h"
63#include "en/xsk/rx.h"
64#include "en/xsk/tx.h"
65#include "en/hv_vhca_stats.h"
66#include "en/devlink.h"
67#include "lib/mlx5.h"
68#include "en/ptp.h"
69#include "en/htb.h"
70#include "qos.h"
71#include "en/trap.h"
72#include "lib/devcom.h"
73
74bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
75 enum mlx5e_mpwrq_umr_mode umr_mode)
76{
77 u16 umr_wqebbs, max_wqebbs;
78 bool striding_rq_umr;
79
80 striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
81 MLX5_CAP_ETH(mdev, reg_umr_sq);
82 if (!striding_rq_umr)
83 return false;
84
85 umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode);
86 max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
87 /* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is
88 * calculated from mlx5e_get_max_sq_aligned_wqebbs.
89 */
90 if (WARN_ON(umr_wqebbs > max_wqebbs))
91 return false;
92
93 return true;
94}
95
96void mlx5e_update_carrier(struct mlx5e_priv *priv)
97{
98 struct mlx5_core_dev *mdev = priv->mdev;
99 u8 port_state;
100 bool up;
101
102 port_state = mlx5_query_vport_state(mdev,
103 opmod: MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
104 vport: 0);
105
106 up = port_state == VPORT_STATE_UP;
107 if (up == netif_carrier_ok(dev: priv->netdev))
108 netif_carrier_event(dev: priv->netdev);
109 if (up) {
110 netdev_info(dev: priv->netdev, format: "Link up\n");
111 netif_carrier_on(dev: priv->netdev);
112 } else {
113 netdev_info(dev: priv->netdev, format: "Link down\n");
114 netif_carrier_off(dev: priv->netdev);
115 }
116}
117
118static void mlx5e_update_carrier_work(struct work_struct *work)
119{
120 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
121 update_carrier_work);
122
123 mutex_lock(&priv->state_lock);
124 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
125 if (priv->profile->update_carrier)
126 priv->profile->update_carrier(priv);
127 mutex_unlock(lock: &priv->state_lock);
128}
129
130static void mlx5e_update_stats_work(struct work_struct *work)
131{
132 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
133 update_stats_work);
134
135 mutex_lock(&priv->state_lock);
136 priv->profile->update_stats(priv);
137 mutex_unlock(lock: &priv->state_lock);
138}
139
140void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
141{
142 if (!priv->profile->update_stats)
143 return;
144
145 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
146 return;
147
148 queue_work(wq: priv->wq, work: &priv->update_stats_work);
149}
150
151static int async_event(struct notifier_block *nb, unsigned long event, void *data)
152{
153 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
154 struct mlx5_eqe *eqe = data;
155
156 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
157 return NOTIFY_DONE;
158
159 switch (eqe->sub_type) {
160 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
161 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
162 queue_work(wq: priv->wq, work: &priv->update_carrier_work);
163 break;
164 default:
165 return NOTIFY_DONE;
166 }
167
168 return NOTIFY_OK;
169}
170
171static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
172{
173 priv->events_nb.notifier_call = async_event;
174 mlx5_notifier_register(dev: priv->mdev, nb: &priv->events_nb);
175}
176
177static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
178{
179 mlx5_notifier_unregister(dev: priv->mdev, nb: &priv->events_nb);
180}
181
182static int mlx5e_devcom_event_mpv(int event, void *my_data, void *event_data)
183{
184 struct mlx5e_priv *slave_priv = my_data;
185
186 switch (event) {
187 case MPV_DEVCOM_MASTER_UP:
188 mlx5_devcom_comp_set_ready(devcom: slave_priv->devcom, ready: true);
189 break;
190 case MPV_DEVCOM_MASTER_DOWN:
191 /* no need for comp set ready false since we unregister after
192 * and it hurts cleanup flow.
193 */
194 break;
195 case MPV_DEVCOM_IPSEC_MASTER_UP:
196 case MPV_DEVCOM_IPSEC_MASTER_DOWN:
197 mlx5e_ipsec_handle_mpv_event(event, slave_priv: my_data, master_priv: event_data);
198 break;
199 }
200
201 return 0;
202}
203
204static int mlx5e_devcom_init_mpv(struct mlx5e_priv *priv, u64 *data)
205{
206 priv->devcom = mlx5_devcom_register_component(devc: priv->mdev->priv.devc,
207 id: MLX5_DEVCOM_MPV,
208 key: *data,
209 handler: mlx5e_devcom_event_mpv,
210 data: priv);
211 if (IS_ERR_OR_NULL(ptr: priv->devcom))
212 return -EOPNOTSUPP;
213
214 if (mlx5_core_is_mp_master(dev: priv->mdev)) {
215 mlx5_devcom_send_event(devcom: priv->devcom, event: MPV_DEVCOM_MASTER_UP,
216 rollback_event: MPV_DEVCOM_MASTER_UP, event_data: priv);
217 mlx5e_ipsec_send_event(priv, event: MPV_DEVCOM_IPSEC_MASTER_UP);
218 }
219
220 return 0;
221}
222
223static void mlx5e_devcom_cleanup_mpv(struct mlx5e_priv *priv)
224{
225 if (IS_ERR_OR_NULL(ptr: priv->devcom))
226 return;
227
228 if (mlx5_core_is_mp_master(dev: priv->mdev)) {
229 mlx5_devcom_send_event(devcom: priv->devcom, event: MPV_DEVCOM_MASTER_DOWN,
230 rollback_event: MPV_DEVCOM_MASTER_DOWN, event_data: priv);
231 mlx5e_ipsec_send_event(priv, event: MPV_DEVCOM_IPSEC_MASTER_DOWN);
232 }
233
234 mlx5_devcom_unregister_component(devcom: priv->devcom);
235}
236
237static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
238{
239 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
240 struct mlx5_devlink_trap_event_ctx *trap_event_ctx = data;
241 int err;
242
243 switch (event) {
244 case MLX5_DRIVER_EVENT_TYPE_TRAP:
245 err = mlx5e_handle_trap_event(priv, trap_ctx: trap_event_ctx->trap);
246 if (err) {
247 trap_event_ctx->err = err;
248 return NOTIFY_BAD;
249 }
250 break;
251 case MLX5_DRIVER_EVENT_AFFILIATION_DONE:
252 if (mlx5e_devcom_init_mpv(priv, data))
253 return NOTIFY_BAD;
254 break;
255 case MLX5_DRIVER_EVENT_AFFILIATION_REMOVED:
256 mlx5e_devcom_cleanup_mpv(priv);
257 break;
258 default:
259 return NOTIFY_DONE;
260 }
261 return NOTIFY_OK;
262}
263
264static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
265{
266 priv->blocking_events_nb.notifier_call = blocking_event;
267 mlx5_blocking_notifier_register(dev: priv->mdev, nb: &priv->blocking_events_nb);
268}
269
270static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
271{
272 mlx5_blocking_notifier_unregister(dev: priv->mdev, nb: &priv->blocking_events_nb);
273}
274
275static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode)
276{
277 u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(mode: umr_mode);
278 u32 sz;
279
280 sz = ALIGN(entries * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT);
281
282 return sz / MLX5_OCTWORD;
283}
284
285static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
286 struct mlx5e_icosq *sq,
287 struct mlx5e_umr_wqe *wqe)
288{
289 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
290 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
291 u16 octowords;
292 u8 ds_cnt;
293
294 ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift,
295 rq->mpwqe.umr_mode),
296 MLX5_SEND_WQE_DS);
297
298 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
299 ds_cnt);
300 cseg->umr_mkey = rq->mpwqe.umr_mkey_be;
301
302 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
303 octowords = mlx5e_mpwrq_umr_octowords(entries: rq->mpwqe.pages_per_wqe, umr_mode: rq->mpwqe.umr_mode);
304 ucseg->xlt_octowords = cpu_to_be16(octowords);
305 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
306}
307
308static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
309{
310 rq->mpwqe.shampo = kvzalloc_node(size: sizeof(*rq->mpwqe.shampo),
311 GFP_KERNEL, node);
312 if (!rq->mpwqe.shampo)
313 return -ENOMEM;
314 return 0;
315}
316
317static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
318{
319 kvfree(addr: rq->mpwqe.shampo);
320}
321
322static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
323{
324 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
325
326 shampo->bitmap = bitmap_zalloc_node(nbits: shampo->hd_per_wq, GFP_KERNEL,
327 node);
328 shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
329 sizeof(*shampo->info)),
330 GFP_KERNEL, node);
331 shampo->pages = kvzalloc_node(array_size(shampo->hd_per_wq,
332 sizeof(*shampo->pages)),
333 GFP_KERNEL, node);
334 if (!shampo->bitmap || !shampo->info || !shampo->pages)
335 goto err_nomem;
336
337 return 0;
338
339err_nomem:
340 kvfree(addr: shampo->info);
341 kvfree(addr: shampo->bitmap);
342 kvfree(addr: shampo->pages);
343
344 return -ENOMEM;
345}
346
347static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
348{
349 kvfree(addr: rq->mpwqe.shampo->bitmap);
350 kvfree(addr: rq->mpwqe.shampo->info);
351 kvfree(addr: rq->mpwqe.shampo->pages);
352}
353
354static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
355{
356 int wq_sz = mlx5_wq_ll_get_size(wq: &rq->mpwqe.wq);
357 size_t alloc_size;
358
359 alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info,
360 alloc_units.frag_pages,
361 rq->mpwqe.pages_per_wqe));
362
363 rq->mpwqe.info = kvzalloc_node(size: alloc_size, GFP_KERNEL, node);
364 if (!rq->mpwqe.info)
365 return -ENOMEM;
366
367 /* For deferred page release (release right before alloc), make sure
368 * that on first round release is not called.
369 */
370 for (int i = 0; i < wq_sz; i++) {
371 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, i);
372
373 bitmap_fill(dst: wi->skip_release_bitmap, nbits: rq->mpwqe.pages_per_wqe);
374 }
375
376 mlx5e_build_umr_wqe(rq, sq: rq->icosq, wqe: &rq->mpwqe.umr_wqe);
377
378 return 0;
379}
380
381
382static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode)
383{
384 switch (umr_mode) {
385 case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
386 return MLX5_MKC_ACCESS_MODE_MTT;
387 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
388 return MLX5_MKC_ACCESS_MODE_KSM;
389 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
390 return MLX5_MKC_ACCESS_MODE_KLMS;
391 case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
392 return MLX5_MKC_ACCESS_MODE_KSM;
393 }
394 WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode);
395 return 0;
396}
397
398static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
399 u32 npages, u8 page_shift, u32 *umr_mkey,
400 dma_addr_t filler_addr,
401 enum mlx5e_mpwrq_umr_mode umr_mode,
402 u32 xsk_chunk_size)
403{
404 struct mlx5_mtt *mtt;
405 struct mlx5_ksm *ksm;
406 struct mlx5_klm *klm;
407 u32 octwords;
408 int inlen;
409 void *mkc;
410 u32 *in;
411 int err;
412 int i;
413
414 if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED ||
415 umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) &&
416 !MLX5_CAP_GEN(mdev, fixed_buffer_size)) {
417 mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n");
418 return -EINVAL;
419 }
420
421 octwords = mlx5e_mpwrq_umr_octowords(entries: npages, umr_mode);
422
423 inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in),
424 MLX5_OCTWORD, octwords);
425 if (inlen < 0)
426 return inlen;
427
428 in = kvzalloc(size: inlen, GFP_KERNEL);
429 if (!in)
430 return -ENOMEM;
431
432 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
433
434 MLX5_SET(mkc, mkc, free, 1);
435 MLX5_SET(mkc, mkc, umr_en, 1);
436 MLX5_SET(mkc, mkc, lw, 1);
437 MLX5_SET(mkc, mkc, lr, 1);
438 MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode));
439 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
440 MLX5_SET(mkc, mkc, qpn, 0xffffff);
441 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
442 MLX5_SET64(mkc, mkc, len, npages << page_shift);
443 MLX5_SET(mkc, mkc, translations_octword_size, octwords);
444 if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE)
445 MLX5_SET(mkc, mkc, log_page_size, page_shift - 2);
446 else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED)
447 MLX5_SET(mkc, mkc, log_page_size, page_shift);
448 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords);
449
450 /* Initialize the mkey with all MTTs pointing to a default
451 * page (filler_addr). When the channels are activated, UMR
452 * WQEs will redirect the RX WQEs to the actual memory from
453 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
454 * to the default page.
455 */
456 switch (umr_mode) {
457 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
458 klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
459 for (i = 0; i < npages; i++) {
460 klm[i << 1] = (struct mlx5_klm) {
461 .va = cpu_to_be64(filler_addr),
462 .bcount = cpu_to_be32(xsk_chunk_size),
463 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
464 };
465 klm[(i << 1) + 1] = (struct mlx5_klm) {
466 .va = cpu_to_be64(filler_addr),
467 .bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size),
468 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
469 };
470 }
471 break;
472 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
473 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
474 for (i = 0; i < npages; i++)
475 ksm[i] = (struct mlx5_ksm) {
476 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
477 .va = cpu_to_be64(filler_addr),
478 };
479 break;
480 case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
481 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
482 for (i = 0; i < npages; i++)
483 mtt[i] = (struct mlx5_mtt) {
484 .ptag = cpu_to_be64(filler_addr),
485 };
486 break;
487 case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
488 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
489 for (i = 0; i < npages * 4; i++) {
490 ksm[i] = (struct mlx5_ksm) {
491 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
492 .va = cpu_to_be64(filler_addr),
493 };
494 }
495 break;
496 }
497
498 err = mlx5_core_create_mkey(dev: mdev, mkey: umr_mkey, in, inlen);
499
500 kvfree(addr: in);
501 return err;
502}
503
504static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
505 u64 nentries,
506 u32 *umr_mkey)
507{
508 int inlen;
509 void *mkc;
510 u32 *in;
511 int err;
512
513 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
514
515 in = kvzalloc(size: inlen, GFP_KERNEL);
516 if (!in)
517 return -ENOMEM;
518
519 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
520
521 MLX5_SET(mkc, mkc, free, 1);
522 MLX5_SET(mkc, mkc, umr_en, 1);
523 MLX5_SET(mkc, mkc, lw, 1);
524 MLX5_SET(mkc, mkc, lr, 1);
525 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
526 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
527 MLX5_SET(mkc, mkc, qpn, 0xffffff);
528 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
529 MLX5_SET(mkc, mkc, translations_octword_size, nentries);
530 MLX5_SET(mkc, mkc, length64, 1);
531 err = mlx5_core_create_mkey(dev: mdev, mkey: umr_mkey, in, inlen);
532
533 kvfree(addr: in);
534 return err;
535}
536
537static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
538{
539 u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0;
540 u32 wq_size = mlx5_wq_ll_get_size(wq: &rq->mpwqe.wq);
541 u32 num_entries, max_num_entries;
542 u32 umr_mkey;
543 int err;
544
545 max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, umr_mode: rq->mpwqe.umr_mode);
546
547 /* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */
548 if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe,
549 &num_entries) ||
550 num_entries > max_num_entries))
551 mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n",
552 __func__, wq_size, rq->mpwqe.mtts_per_wqe,
553 max_num_entries);
554
555 err = mlx5e_create_umr_mkey(mdev, npages: num_entries, page_shift: rq->mpwqe.page_shift,
556 umr_mkey: &umr_mkey, filler_addr: rq->wqe_overflow.addr,
557 umr_mode: rq->mpwqe.umr_mode, xsk_chunk_size);
558 rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey);
559 return err;
560}
561
562static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
563 struct mlx5e_rq *rq)
564{
565 u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
566
567 if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
568 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
569 max_klm_size, rq->mpwqe.shampo->hd_per_wq);
570 return -EINVAL;
571 }
572 return mlx5e_create_umr_klm_mkey(mdev, nentries: rq->mpwqe.shampo->hd_per_wq,
573 umr_mkey: &rq->mpwqe.shampo->mkey);
574}
575
576static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
577{
578 struct mlx5e_wqe_frag_info next_frag = {};
579 struct mlx5e_wqe_frag_info *prev = NULL;
580 int i;
581
582 WARN_ON(rq->xsk_pool);
583
584 next_frag.frag_page = &rq->wqe.alloc_units->frag_pages[0];
585
586 /* Skip first release due to deferred release. */
587 next_frag.flags = BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
588
589 for (i = 0; i < mlx5_wq_cyc_get_size(wq: &rq->wqe.wq); i++) {
590 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
591 struct mlx5e_wqe_frag_info *frag =
592 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
593 int f;
594
595 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
596 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
597 /* Pages are assigned at runtime. */
598 next_frag.frag_page++;
599 next_frag.offset = 0;
600 if (prev)
601 prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
602 }
603 *frag = next_frag;
604
605 /* prepare next */
606 next_frag.offset += frag_info[f].frag_stride;
607 prev = frag;
608 }
609 }
610
611 if (prev)
612 prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
613}
614
615static void mlx5e_init_xsk_buffs(struct mlx5e_rq *rq)
616{
617 int i;
618
619 /* Assumptions used by XSK batched allocator. */
620 WARN_ON(rq->wqe.info.num_frags != 1);
621 WARN_ON(rq->wqe.info.log_num_frags != 0);
622 WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE);
623
624 /* Considering the above assumptions a fragment maps to a single
625 * xsk_buff.
626 */
627 for (i = 0; i < mlx5_wq_cyc_get_size(wq: &rq->wqe.wq); i++) {
628 rq->wqe.frags[i].xskp = &rq->wqe.alloc_units->xsk_buffs[i];
629
630 /* Skip first release due to deferred release as WQES are
631 * not allocated yet.
632 */
633 rq->wqe.frags[i].flags |= BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
634 }
635}
636
637static int mlx5e_init_wqe_alloc_info(struct mlx5e_rq *rq, int node)
638{
639 int wq_sz = mlx5_wq_cyc_get_size(wq: &rq->wqe.wq);
640 int len = wq_sz << rq->wqe.info.log_num_frags;
641 struct mlx5e_wqe_frag_info *frags;
642 union mlx5e_alloc_units *aus;
643 int aus_sz;
644
645 if (rq->xsk_pool)
646 aus_sz = sizeof(*aus->xsk_buffs);
647 else
648 aus_sz = sizeof(*aus->frag_pages);
649
650 aus = kvzalloc_node(array_size(len, aus_sz), GFP_KERNEL, node);
651 if (!aus)
652 return -ENOMEM;
653
654 frags = kvzalloc_node(array_size(len, sizeof(*frags)), GFP_KERNEL, node);
655 if (!frags) {
656 kvfree(addr: aus);
657 return -ENOMEM;
658 }
659
660 rq->wqe.alloc_units = aus;
661 rq->wqe.frags = frags;
662
663 if (rq->xsk_pool)
664 mlx5e_init_xsk_buffs(rq);
665 else
666 mlx5e_init_frags_partition(rq);
667
668 return 0;
669}
670
671static void mlx5e_free_wqe_alloc_info(struct mlx5e_rq *rq)
672{
673 kvfree(addr: rq->wqe.frags);
674 kvfree(addr: rq->wqe.alloc_units);
675}
676
677static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
678{
679 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
680
681 mlx5e_reporter_rq_cqe_err(rq);
682}
683
684static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
685{
686 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
687 if (!rq->wqe_overflow.page)
688 return -ENOMEM;
689
690 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
691 PAGE_SIZE, rq->buff.map_dir);
692 if (dma_mapping_error(dev: rq->pdev, dma_addr: rq->wqe_overflow.addr)) {
693 __free_page(rq->wqe_overflow.page);
694 return -ENOMEM;
695 }
696 return 0;
697}
698
699static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
700{
701 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
702 rq->buff.map_dir);
703 __free_page(rq->wqe_overflow.page);
704}
705
706static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
707 u32 xdp_frag_size, struct mlx5e_rq *rq)
708{
709 struct mlx5_core_dev *mdev = c->mdev;
710 int err;
711
712 rq->wq_type = params->rq_wq_type;
713 rq->pdev = c->pdev;
714 rq->netdev = c->netdev;
715 rq->priv = c->priv;
716 rq->tstamp = c->tstamp;
717 rq->clock = &mdev->clock;
718 rq->icosq = &c->icosq;
719 rq->ix = c->ix;
720 rq->channel = c;
721 rq->mdev = mdev;
722 rq->hw_mtu =
723 MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN * !params->scatter_fcs_en;
724 rq->xdpsq = &c->rq_xdpsq;
725 rq->stats = &c->priv->channel_stats[c->ix]->rq;
726 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
727 err = mlx5e_rq_set_handlers(rq, params, NULL);
728 if (err)
729 return err;
730
731 return __xdp_rxq_info_reg(xdp_rxq: &rq->xdp_rxq, dev: rq->netdev, queue_index: rq->ix, napi_id: c->napi.napi_id,
732 frag_size: xdp_frag_size);
733}
734
735static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
736 struct mlx5e_params *params,
737 struct mlx5e_rq_param *rqp,
738 struct mlx5e_rq *rq,
739 u32 *pool_size,
740 int node)
741{
742 void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
743 int wq_size;
744 int err;
745
746 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
747 return 0;
748 err = mlx5e_rq_shampo_hd_alloc(rq, node);
749 if (err)
750 goto out;
751 rq->mpwqe.shampo->hd_per_wq =
752 mlx5e_shampo_hd_per_wq(mdev, params, rq_param: rqp);
753 err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
754 if (err)
755 goto err_shampo_hd;
756 err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
757 if (err)
758 goto err_shampo_info;
759 rq->hw_gro_data = kvzalloc_node(size: sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
760 if (!rq->hw_gro_data) {
761 err = -ENOMEM;
762 goto err_hw_gro_data;
763 }
764 rq->mpwqe.shampo->key =
765 cpu_to_be32(rq->mpwqe.shampo->mkey);
766 rq->mpwqe.shampo->hd_per_wqe =
767 mlx5e_shampo_hd_per_wqe(mdev, params, rq_param: rqp);
768 wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
769 *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
770 MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
771 return 0;
772
773err_hw_gro_data:
774 mlx5e_rq_shampo_hd_info_free(rq);
775err_shampo_info:
776 mlx5_core_destroy_mkey(dev: mdev, mkey: rq->mpwqe.shampo->mkey);
777err_shampo_hd:
778 mlx5e_rq_shampo_hd_free(rq);
779out:
780 return err;
781}
782
783static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
784{
785 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
786 return;
787
788 kvfree(addr: rq->hw_gro_data);
789 mlx5e_rq_shampo_hd_info_free(rq);
790 mlx5_core_destroy_mkey(dev: rq->mdev, mkey: rq->mpwqe.shampo->mkey);
791 mlx5e_rq_shampo_hd_free(rq);
792}
793
794static int mlx5e_alloc_rq(struct mlx5e_params *params,
795 struct mlx5e_xsk_param *xsk,
796 struct mlx5e_rq_param *rqp,
797 int node, struct mlx5e_rq *rq)
798{
799 struct mlx5_core_dev *mdev = rq->mdev;
800 void *rqc = rqp->rqc;
801 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
802 u32 pool_size;
803 int wq_sz;
804 int err;
805 int i;
806
807 rqp->wq.db_numa_node = node;
808 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
809
810 if (params->xdp_prog)
811 bpf_prog_inc(prog: params->xdp_prog);
812 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
813
814 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
815 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
816 pool_size = 1 << params->log_rq_mtu_frames;
817
818 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
819
820 switch (rq->wq_type) {
821 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
822 err = mlx5_wq_ll_create(mdev, param: &rqp->wq, wqc: rqc_wq, wq: &rq->mpwqe.wq,
823 wq_ctrl: &rq->wq_ctrl);
824 if (err)
825 goto err_rq_xdp_prog;
826
827 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
828 if (err)
829 goto err_rq_wq_destroy;
830
831 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
832
833 wq_sz = mlx5_wq_ll_get_size(wq: &rq->mpwqe.wq);
834
835 rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk);
836 rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk);
837 rq->mpwqe.pages_per_wqe =
838 mlx5e_mpwrq_pages_per_wqe(mdev, page_shift: rq->mpwqe.page_shift,
839 umr_mode: rq->mpwqe.umr_mode);
840 rq->mpwqe.umr_wqebbs =
841 mlx5e_mpwrq_umr_wqebbs(mdev, page_shift: rq->mpwqe.page_shift,
842 umr_mode: rq->mpwqe.umr_mode);
843 rq->mpwqe.mtts_per_wqe =
844 mlx5e_mpwrq_mtts_per_wqe(mdev, page_shift: rq->mpwqe.page_shift,
845 umr_mode: rq->mpwqe.umr_mode);
846
847 pool_size = rq->mpwqe.pages_per_wqe <<
848 mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk);
849
850 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk) && params->xdp_prog)
851 pool_size *= 2; /* additional page per packet for the linear part */
852
853 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
854 rq->mpwqe.num_strides =
855 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
856 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
857
858 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
859
860 err = mlx5e_create_rq_umr_mkey(mdev, rq);
861 if (err)
862 goto err_rq_drop_page;
863
864 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
865 if (err)
866 goto err_rq_mkey;
867
868 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, pool_size: &pool_size, node);
869 if (err)
870 goto err_free_mpwqe_info;
871
872 break;
873 default: /* MLX5_WQ_TYPE_CYCLIC */
874 err = mlx5_wq_cyc_create(mdev, param: &rqp->wq, wqc: rqc_wq, wq: &rq->wqe.wq,
875 wq_ctrl: &rq->wq_ctrl);
876 if (err)
877 goto err_rq_xdp_prog;
878
879 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
880
881 wq_sz = mlx5_wq_cyc_get_size(wq: &rq->wqe.wq);
882
883 rq->wqe.info = rqp->frags_info;
884 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
885
886 err = mlx5e_init_wqe_alloc_info(rq, node);
887 if (err)
888 goto err_rq_wq_destroy;
889 }
890
891 if (xsk) {
892 err = xdp_rxq_info_reg_mem_model(xdp_rxq: &rq->xdp_rxq,
893 type: MEM_TYPE_XSK_BUFF_POOL, NULL);
894 xsk_pool_set_rxq_info(pool: rq->xsk_pool, rxq: &rq->xdp_rxq);
895 } else {
896 /* Create a page_pool and register it with rxq */
897 struct page_pool_params pp_params = { 0 };
898
899 pp_params.order = 0;
900 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
901 pp_params.pool_size = pool_size;
902 pp_params.nid = node;
903 pp_params.dev = rq->pdev;
904 pp_params.napi = rq->cq.napi;
905 pp_params.dma_dir = rq->buff.map_dir;
906 pp_params.max_len = PAGE_SIZE;
907
908 /* page_pool can be used even when there is no rq->xdp_prog,
909 * given page_pool does not handle DMA mapping there is no
910 * required state to clear. And page_pool gracefully handle
911 * elevated refcnt.
912 */
913 rq->page_pool = page_pool_create(params: &pp_params);
914 if (IS_ERR(ptr: rq->page_pool)) {
915 err = PTR_ERR(ptr: rq->page_pool);
916 rq->page_pool = NULL;
917 goto err_free_by_rq_type;
918 }
919 if (xdp_rxq_info_is_reg(xdp_rxq: &rq->xdp_rxq))
920 err = xdp_rxq_info_reg_mem_model(xdp_rxq: &rq->xdp_rxq,
921 type: MEM_TYPE_PAGE_POOL, allocator: rq->page_pool);
922 }
923 if (err)
924 goto err_destroy_page_pool;
925
926 for (i = 0; i < wq_sz; i++) {
927 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
928 struct mlx5e_rx_wqe_ll *wqe =
929 mlx5_wq_ll_get_wqe(wq: &rq->mpwqe.wq, ix: i);
930 u32 byte_count =
931 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
932 u64 dma_offset = mul_u32_u32(a: i, b: rq->mpwqe.mtts_per_wqe) <<
933 rq->mpwqe.page_shift;
934 u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
935 0 : rq->buff.headroom;
936
937 wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
938 wqe->data[0].byte_count = cpu_to_be32(byte_count);
939 wqe->data[0].lkey = rq->mpwqe.umr_mkey_be;
940 } else {
941 struct mlx5e_rx_wqe_cyc *wqe =
942 mlx5_wq_cyc_get_wqe(wq: &rq->wqe.wq, ix: i);
943 int f;
944
945 for (f = 0; f < rq->wqe.info.num_frags; f++) {
946 u32 frag_size = rq->wqe.info.arr[f].frag_size |
947 MLX5_HW_START_PADDING;
948
949 wqe->data[f].byte_count = cpu_to_be32(frag_size);
950 wqe->data[f].lkey = rq->mkey_be;
951 }
952 /* check if num_frags is not a pow of two */
953 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
954 wqe->data[f].byte_count = 0;
955 wqe->data[f].lkey = params->terminate_lkey_be;
956 wqe->data[f].addr = 0;
957 }
958 }
959 }
960
961 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
962
963 switch (params->rx_cq_moderation.cq_period_mode) {
964 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
965 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
966 break;
967 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
968 default:
969 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
970 }
971
972 return 0;
973
974err_destroy_page_pool:
975 page_pool_destroy(pool: rq->page_pool);
976err_free_by_rq_type:
977 switch (rq->wq_type) {
978 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
979 mlx5e_rq_free_shampo(rq);
980err_free_mpwqe_info:
981 kvfree(addr: rq->mpwqe.info);
982err_rq_mkey:
983 mlx5_core_destroy_mkey(dev: mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
984err_rq_drop_page:
985 mlx5e_free_mpwqe_rq_drop_page(rq);
986 break;
987 default: /* MLX5_WQ_TYPE_CYCLIC */
988 mlx5e_free_wqe_alloc_info(rq);
989 }
990err_rq_wq_destroy:
991 mlx5_wq_destroy(wq_ctrl: &rq->wq_ctrl);
992err_rq_xdp_prog:
993 if (params->xdp_prog)
994 bpf_prog_put(prog: params->xdp_prog);
995
996 return err;
997}
998
999static void mlx5e_free_rq(struct mlx5e_rq *rq)
1000{
1001 struct bpf_prog *old_prog;
1002
1003 if (xdp_rxq_info_is_reg(xdp_rxq: &rq->xdp_rxq)) {
1004 old_prog = rcu_dereference_protected(rq->xdp_prog,
1005 lockdep_is_held(&rq->priv->state_lock));
1006 if (old_prog)
1007 bpf_prog_put(prog: old_prog);
1008 }
1009
1010 switch (rq->wq_type) {
1011 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1012 kvfree(addr: rq->mpwqe.info);
1013 mlx5_core_destroy_mkey(dev: rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
1014 mlx5e_free_mpwqe_rq_drop_page(rq);
1015 mlx5e_rq_free_shampo(rq);
1016 break;
1017 default: /* MLX5_WQ_TYPE_CYCLIC */
1018 mlx5e_free_wqe_alloc_info(rq);
1019 }
1020
1021 xdp_rxq_info_unreg(xdp_rxq: &rq->xdp_rxq);
1022 page_pool_destroy(pool: rq->page_pool);
1023 mlx5_wq_destroy(wq_ctrl: &rq->wq_ctrl);
1024}
1025
1026int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1027{
1028 struct mlx5_core_dev *mdev = rq->mdev;
1029 u8 ts_format;
1030 void *in;
1031 void *rqc;
1032 void *wq;
1033 int inlen;
1034 int err;
1035
1036 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1037 sizeof(u64) * rq->wq_ctrl.buf.npages;
1038 in = kvzalloc(size: inlen, GFP_KERNEL);
1039 if (!in)
1040 return -ENOMEM;
1041
1042 ts_format = mlx5_is_real_time_rq(mdev) ?
1043 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1044 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1045 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1046 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1047
1048 memcpy(rqc, param->rqc, sizeof(param->rqc));
1049
1050 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
1051 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1052 MLX5_SET(rqc, rqc, ts_format, ts_format);
1053 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1054 MLX5_ADAPTER_PAGE_SHIFT);
1055 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1056
1057 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1058 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
1059 order_base_2(rq->mpwqe.shampo->hd_per_wq));
1060 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
1061 }
1062
1063 mlx5_fill_page_frag_array(frag_buf: &rq->wq_ctrl.buf,
1064 pas: (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1065
1066 err = mlx5_core_create_rq(dev: mdev, in, inlen, rqn: &rq->rqn);
1067
1068 kvfree(addr: in);
1069
1070 return err;
1071}
1072
1073static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
1074{
1075 struct mlx5_core_dev *mdev = rq->mdev;
1076
1077 void *in;
1078 void *rqc;
1079 int inlen;
1080 int err;
1081
1082 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1083 in = kvzalloc(size: inlen, GFP_KERNEL);
1084 if (!in)
1085 return -ENOMEM;
1086
1087 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
1088 mlx5e_rqwq_reset(rq);
1089
1090 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1091
1092 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1093 MLX5_SET(rqc, rqc, state, next_state);
1094
1095 err = mlx5_core_modify_rq(dev: mdev, rqn: rq->rqn, in);
1096
1097 kvfree(addr: in);
1098
1099 return err;
1100}
1101
1102static void mlx5e_flush_rq_cq(struct mlx5e_rq *rq)
1103{
1104 struct mlx5_cqwq *cqwq = &rq->cq.wq;
1105 struct mlx5_cqe64 *cqe;
1106
1107 if (test_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state)) {
1108 while ((cqe = mlx5_cqwq_get_cqe_enahnced_comp(wq: cqwq)))
1109 mlx5_cqwq_pop(wq: cqwq);
1110 } else {
1111 while ((cqe = mlx5_cqwq_get_cqe(wq: cqwq)))
1112 mlx5_cqwq_pop(wq: cqwq);
1113 }
1114
1115 mlx5_cqwq_update_db_record(wq: cqwq);
1116}
1117
1118int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state)
1119{
1120 struct net_device *dev = rq->netdev;
1121 int err;
1122
1123 err = mlx5e_modify_rq_state(rq, curr_state, next_state: MLX5_RQC_STATE_RST);
1124 if (err) {
1125 netdev_err(dev, format: "Failed to move rq 0x%x to reset\n", rq->rqn);
1126 return err;
1127 }
1128
1129 mlx5e_free_rx_descs(rq);
1130 mlx5e_flush_rq_cq(rq);
1131
1132 err = mlx5e_modify_rq_state(rq, curr_state: MLX5_RQC_STATE_RST, next_state: MLX5_RQC_STATE_RDY);
1133 if (err) {
1134 netdev_err(dev, format: "Failed to move rq 0x%x to ready\n", rq->rqn);
1135 return err;
1136 }
1137
1138 return 0;
1139}
1140
1141static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
1142{
1143 struct mlx5_core_dev *mdev = rq->mdev;
1144 void *in;
1145 void *rqc;
1146 int inlen;
1147 int err;
1148
1149 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1150 in = kvzalloc(size: inlen, GFP_KERNEL);
1151 if (!in)
1152 return -ENOMEM;
1153
1154 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1155
1156 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
1157 MLX5_SET64(modify_rq_in, in, modify_bitmask,
1158 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
1159 MLX5_SET(rqc, rqc, vsd, vsd);
1160 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
1161
1162 err = mlx5_core_modify_rq(dev: mdev, rqn: rq->rqn, in);
1163
1164 kvfree(addr: in);
1165
1166 return err;
1167}
1168
1169void mlx5e_destroy_rq(struct mlx5e_rq *rq)
1170{
1171 mlx5_core_destroy_rq(dev: rq->mdev, rqn: rq->rqn);
1172}
1173
1174int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
1175{
1176 unsigned long exp_time = jiffies + msecs_to_jiffies(m: wait_time);
1177
1178 u16 min_wqes = mlx5_min_rx_wqes(wq_type: rq->wq_type, wq_size: mlx5e_rqwq_get_size(rq));
1179
1180 do {
1181 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
1182 return 0;
1183
1184 msleep(msecs: 20);
1185 } while (time_before(jiffies, exp_time));
1186
1187 netdev_warn(dev: rq->netdev, format: "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
1188 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
1189
1190 mlx5e_reporter_rx_timeout(rq);
1191 return -ETIMEDOUT;
1192}
1193
1194void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq)
1195{
1196 struct mlx5_wq_ll *wq;
1197 u16 head;
1198 int i;
1199
1200 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
1201 return;
1202
1203 wq = &rq->mpwqe.wq;
1204 head = wq->head;
1205
1206 /* Release WQEs that are in missing state: they have been
1207 * popped from the list after completion but were not freed
1208 * due to deferred release.
1209 * Also free the linked-list reserved entry, hence the "+ 1".
1210 */
1211 for (i = 0; i < mlx5_wq_ll_missing(wq) + 1; i++) {
1212 rq->dealloc_wqe(rq, head);
1213 head = mlx5_wq_ll_get_wqe_next_ix(wq, ix: head);
1214 }
1215
1216 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1217 u16 len;
1218
1219 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
1220 (rq->mpwqe.shampo->hd_per_wq - 1);
1221 mlx5e_shampo_dealloc_hd(rq, len, start: rq->mpwqe.shampo->ci, close: false);
1222 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
1223 }
1224
1225 rq->mpwqe.actual_wq_head = wq->head;
1226 rq->mpwqe.umr_in_progress = 0;
1227 rq->mpwqe.umr_completed = 0;
1228}
1229
1230void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
1231{
1232 __be16 wqe_ix_be;
1233 u16 wqe_ix;
1234
1235 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
1236 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
1237
1238 mlx5e_free_rx_missing_descs(rq);
1239
1240 while (!mlx5_wq_ll_is_empty(wq)) {
1241 struct mlx5e_rx_wqe_ll *wqe;
1242
1243 wqe_ix_be = *wq->tail_next;
1244 wqe_ix = be16_to_cpu(wqe_ix_be);
1245 wqe = mlx5_wq_ll_get_wqe(wq, ix: wqe_ix);
1246 rq->dealloc_wqe(rq, wqe_ix);
1247 mlx5_wq_ll_pop(wq, ix: wqe_ix_be,
1248 next_tail_next: &wqe->next.next_wqe_index);
1249 }
1250
1251 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1252 mlx5e_shampo_dealloc_hd(rq, len: rq->mpwqe.shampo->hd_per_wq,
1253 start: 0, close: true);
1254 } else {
1255 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1256 u16 missing = mlx5_wq_cyc_missing(wq);
1257 u16 head = mlx5_wq_cyc_get_head(wq);
1258
1259 while (!mlx5_wq_cyc_is_empty(wq)) {
1260 wqe_ix = mlx5_wq_cyc_get_tail(wq);
1261 rq->dealloc_wqe(rq, wqe_ix);
1262 mlx5_wq_cyc_pop(wq);
1263 }
1264 /* Missing slots might also contain unreleased pages due to
1265 * deferred release.
1266 */
1267 while (missing--) {
1268 wqe_ix = mlx5_wq_cyc_ctr2ix(wq, ctr: head++);
1269 rq->dealloc_wqe(rq, wqe_ix);
1270 }
1271 }
1272
1273}
1274
1275int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1276 struct mlx5e_xsk_param *xsk, int node,
1277 struct mlx5e_rq *rq)
1278{
1279 struct mlx5_core_dev *mdev = rq->mdev;
1280 int err;
1281
1282 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1283 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1284
1285 err = mlx5e_alloc_rq(params, xsk, rqp: param, node, rq);
1286 if (err)
1287 return err;
1288
1289 err = mlx5e_create_rq(rq, param);
1290 if (err)
1291 goto err_free_rq;
1292
1293 err = mlx5e_modify_rq_state(rq, curr_state: MLX5_RQC_STATE_RST, next_state: MLX5_RQC_STATE_RDY);
1294 if (err)
1295 goto err_destroy_rq;
1296
1297 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1298 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1299
1300 if (params->rx_dim_enabled)
1301 __set_bit(MLX5E_RQ_STATE_DIM, &rq->state);
1302
1303 /* We disable csum_complete when XDP is enabled since
1304 * XDP programs might manipulate packets which will render
1305 * skb->checksum incorrect.
1306 */
1307 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1308 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1309
1310 /* For CQE compression on striding RQ, use stride index provided by
1311 * HW if capability is supported.
1312 */
1313 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1314 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1315 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1316
1317 /* For enhanced CQE compression packet processing. decompress
1318 * session according to the enhanced layout.
1319 */
1320 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) &&
1321 MLX5_CAP_GEN(mdev, enhanced_cqe_compression))
1322 __set_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state);
1323
1324 return 0;
1325
1326err_destroy_rq:
1327 mlx5e_destroy_rq(rq);
1328err_free_rq:
1329 mlx5e_free_rq(rq);
1330
1331 return err;
1332}
1333
1334void mlx5e_activate_rq(struct mlx5e_rq *rq)
1335{
1336 set_bit(nr: MLX5E_RQ_STATE_ENABLED, addr: &rq->state);
1337}
1338
1339void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1340{
1341 clear_bit(nr: MLX5E_RQ_STATE_ENABLED, addr: &rq->state);
1342 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1343}
1344
1345void mlx5e_close_rq(struct mlx5e_rq *rq)
1346{
1347 cancel_work_sync(work: &rq->dim.work);
1348 cancel_work_sync(work: &rq->recover_work);
1349 mlx5e_destroy_rq(rq);
1350 mlx5e_free_rx_descs(rq);
1351 mlx5e_free_rq(rq);
1352}
1353
1354static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1355{
1356 kvfree(addr: sq->db.xdpi_fifo.xi);
1357 kvfree(addr: sq->db.wqe_info);
1358}
1359
1360static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1361{
1362 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1363 int wq_sz = mlx5_wq_cyc_get_size(wq: &sq->wq);
1364 int entries;
1365 size_t size;
1366
1367 /* upper bound for maximum num of entries of all xmit_modes. */
1368 entries = roundup_pow_of_two(wq_sz * MLX5_SEND_WQEBB_NUM_DS *
1369 MLX5E_XDP_FIFO_ENTRIES2DS_MAX_RATIO);
1370
1371 size = array_size(sizeof(*xdpi_fifo->xi), entries);
1372 xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, node: numa);
1373 if (!xdpi_fifo->xi)
1374 return -ENOMEM;
1375
1376 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
1377 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
1378 xdpi_fifo->mask = entries - 1;
1379
1380 return 0;
1381}
1382
1383static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1384{
1385 int wq_sz = mlx5_wq_cyc_get_size(wq: &sq->wq);
1386 size_t size;
1387 int err;
1388
1389 size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1390 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, node: numa);
1391 if (!sq->db.wqe_info)
1392 return -ENOMEM;
1393
1394 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1395 if (err) {
1396 mlx5e_free_xdpsq_db(sq);
1397 return err;
1398 }
1399
1400 return 0;
1401}
1402
1403static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1404 struct mlx5e_params *params,
1405 struct xsk_buff_pool *xsk_pool,
1406 struct mlx5e_sq_param *param,
1407 struct mlx5e_xdpsq *sq,
1408 bool is_redirect)
1409{
1410 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1411 struct mlx5_core_dev *mdev = c->mdev;
1412 struct mlx5_wq_cyc *wq = &sq->wq;
1413 int err;
1414
1415 sq->pdev = c->pdev;
1416 sq->mkey_be = c->mkey_be;
1417 sq->channel = c;
1418 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1419 sq->min_inline_mode = params->tx_min_inline_mode;
1420 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN;
1421 sq->xsk_pool = xsk_pool;
1422
1423 sq->stats = sq->xsk_pool ?
1424 &c->priv->channel_stats[c->ix]->xsksq :
1425 is_redirect ?
1426 &c->priv->channel_stats[c->ix]->xdpsq :
1427 &c->priv->channel_stats[c->ix]->rq_xdpsq;
1428 sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) :
1429 mlx5e_stop_room_for_max_wqe(mdev);
1430 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1431
1432 param->wq.db_numa_node = cpu_to_node(cpu: c->cpu);
1433 err = mlx5_wq_cyc_create(mdev, param: &param->wq, wqc: sqc_wq, wq, wq_ctrl: &sq->wq_ctrl);
1434 if (err)
1435 return err;
1436 wq->db = &wq->db[MLX5_SND_DBR];
1437
1438 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(cpu: c->cpu));
1439 if (err)
1440 goto err_sq_wq_destroy;
1441
1442 return 0;
1443
1444err_sq_wq_destroy:
1445 mlx5_wq_destroy(wq_ctrl: &sq->wq_ctrl);
1446
1447 return err;
1448}
1449
1450static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1451{
1452 mlx5e_free_xdpsq_db(sq);
1453 mlx5_wq_destroy(wq_ctrl: &sq->wq_ctrl);
1454}
1455
1456static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1457{
1458 kvfree(addr: sq->db.wqe_info);
1459}
1460
1461static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1462{
1463 int wq_sz = mlx5_wq_cyc_get_size(wq: &sq->wq);
1464 size_t size;
1465
1466 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1467 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, node: numa);
1468 if (!sq->db.wqe_info)
1469 return -ENOMEM;
1470
1471 return 0;
1472}
1473
1474static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1475{
1476 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1477 recover_work);
1478
1479 mlx5e_reporter_icosq_cqe_err(icosq: sq);
1480}
1481
1482static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1483{
1484 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1485 recover_work);
1486
1487 /* Not implemented yet. */
1488
1489 netdev_warn(dev: sq->channel->netdev, format: "async_icosq recovery is not implemented\n");
1490}
1491
1492static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1493 struct mlx5e_sq_param *param,
1494 struct mlx5e_icosq *sq,
1495 work_func_t recover_work_func)
1496{
1497 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1498 struct mlx5_core_dev *mdev = c->mdev;
1499 struct mlx5_wq_cyc *wq = &sq->wq;
1500 int err;
1501
1502 sq->channel = c;
1503 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1504 sq->reserved_room = param->stop_room;
1505
1506 param->wq.db_numa_node = cpu_to_node(cpu: c->cpu);
1507 err = mlx5_wq_cyc_create(mdev, param: &param->wq, wqc: sqc_wq, wq, wq_ctrl: &sq->wq_ctrl);
1508 if (err)
1509 return err;
1510 wq->db = &wq->db[MLX5_SND_DBR];
1511
1512 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(cpu: c->cpu));
1513 if (err)
1514 goto err_sq_wq_destroy;
1515
1516 INIT_WORK(&sq->recover_work, recover_work_func);
1517
1518 return 0;
1519
1520err_sq_wq_destroy:
1521 mlx5_wq_destroy(wq_ctrl: &sq->wq_ctrl);
1522
1523 return err;
1524}
1525
1526static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1527{
1528 mlx5e_free_icosq_db(sq);
1529 mlx5_wq_destroy(wq_ctrl: &sq->wq_ctrl);
1530}
1531
1532void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1533{
1534 kvfree(addr: sq->db.wqe_info);
1535 kvfree(addr: sq->db.skb_fifo.fifo);
1536 kvfree(addr: sq->db.dma_fifo);
1537}
1538
1539int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1540{
1541 int wq_sz = mlx5_wq_cyc_get_size(wq: &sq->wq);
1542 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1543
1544 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1545 sizeof(*sq->db.dma_fifo)),
1546 GFP_KERNEL, node: numa);
1547 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1548 sizeof(*sq->db.skb_fifo.fifo)),
1549 GFP_KERNEL, node: numa);
1550 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1551 sizeof(*sq->db.wqe_info)),
1552 GFP_KERNEL, node: numa);
1553 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1554 mlx5e_free_txqsq_db(sq);
1555 return -ENOMEM;
1556 }
1557
1558 sq->dma_fifo_mask = df_sz - 1;
1559
1560 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1561 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1562 sq->db.skb_fifo.mask = df_sz - 1;
1563
1564 return 0;
1565}
1566
1567static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1568 int txq_ix,
1569 struct mlx5e_params *params,
1570 struct mlx5e_sq_param *param,
1571 struct mlx5e_txqsq *sq,
1572 int tc)
1573{
1574 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1575 struct mlx5_core_dev *mdev = c->mdev;
1576 struct mlx5_wq_cyc *wq = &sq->wq;
1577 int err;
1578
1579 sq->pdev = c->pdev;
1580 sq->clock = &mdev->clock;
1581 sq->mkey_be = c->mkey_be;
1582 sq->netdev = c->netdev;
1583 sq->mdev = c->mdev;
1584 sq->channel = c;
1585 sq->priv = c->priv;
1586 sq->ch_ix = c->ix;
1587 sq->txq_ix = txq_ix;
1588 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1589 sq->min_inline_mode = params->tx_min_inline_mode;
1590 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1591 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1592 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1593 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1594 set_bit(nr: MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, addr: &sq->state);
1595 if (mlx5_ipsec_device_caps(mdev: c->priv->mdev))
1596 set_bit(nr: MLX5E_SQ_STATE_IPSEC, addr: &sq->state);
1597 if (param->is_mpw)
1598 set_bit(nr: MLX5E_SQ_STATE_MPWQE, addr: &sq->state);
1599 sq->stop_room = param->stop_room;
1600 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1601
1602 param->wq.db_numa_node = cpu_to_node(cpu: c->cpu);
1603 err = mlx5_wq_cyc_create(mdev, param: &param->wq, wqc: sqc_wq, wq, wq_ctrl: &sq->wq_ctrl);
1604 if (err)
1605 return err;
1606 wq->db = &wq->db[MLX5_SND_DBR];
1607
1608 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(cpu: c->cpu));
1609 if (err)
1610 goto err_sq_wq_destroy;
1611
1612 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1613 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1614
1615 return 0;
1616
1617err_sq_wq_destroy:
1618 mlx5_wq_destroy(wq_ctrl: &sq->wq_ctrl);
1619
1620 return err;
1621}
1622
1623void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1624{
1625 mlx5e_free_txqsq_db(sq);
1626 mlx5_wq_destroy(wq_ctrl: &sq->wq_ctrl);
1627}
1628
1629static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1630 struct mlx5e_sq_param *param,
1631 struct mlx5e_create_sq_param *csp,
1632 u32 *sqn)
1633{
1634 u8 ts_format;
1635 void *in;
1636 void *sqc;
1637 void *wq;
1638 int inlen;
1639 int err;
1640
1641 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1642 sizeof(u64) * csp->wq_ctrl->buf.npages;
1643 in = kvzalloc(size: inlen, GFP_KERNEL);
1644 if (!in)
1645 return -ENOMEM;
1646
1647 ts_format = mlx5_is_real_time_sq(mdev) ?
1648 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1649 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1650 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1651 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1652
1653 memcpy(sqc, param->sqc, sizeof(param->sqc));
1654 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1655 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1656 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1657 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1658 MLX5_SET(sqc, sqc, ts_format, ts_format);
1659
1660
1661 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1662 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1663
1664 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1665 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1666
1667 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1668 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1669 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1670 MLX5_ADAPTER_PAGE_SHIFT);
1671 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1672
1673 mlx5_fill_page_frag_array(frag_buf: &csp->wq_ctrl->buf,
1674 pas: (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1675
1676 err = mlx5_core_create_sq(dev: mdev, in, inlen, sqn);
1677
1678 kvfree(addr: in);
1679
1680 return err;
1681}
1682
1683int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1684 struct mlx5e_modify_sq_param *p)
1685{
1686 u64 bitmask = 0;
1687 void *in;
1688 void *sqc;
1689 int inlen;
1690 int err;
1691
1692 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1693 in = kvzalloc(size: inlen, GFP_KERNEL);
1694 if (!in)
1695 return -ENOMEM;
1696
1697 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1698
1699 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1700 MLX5_SET(sqc, sqc, state, p->next_state);
1701 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1702 bitmask |= 1;
1703 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1704 }
1705 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1706 bitmask |= 1 << 2;
1707 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1708 }
1709 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1710
1711 err = mlx5_core_modify_sq(dev: mdev, sqn, in);
1712
1713 kvfree(addr: in);
1714
1715 return err;
1716}
1717
1718static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1719{
1720 mlx5_core_destroy_sq(dev: mdev, sqn);
1721}
1722
1723int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1724 struct mlx5e_sq_param *param,
1725 struct mlx5e_create_sq_param *csp,
1726 u16 qos_queue_group_id,
1727 u32 *sqn)
1728{
1729 struct mlx5e_modify_sq_param msp = {0};
1730 int err;
1731
1732 err = mlx5e_create_sq(mdev, param, csp, sqn);
1733 if (err)
1734 return err;
1735
1736 msp.curr_state = MLX5_SQC_STATE_RST;
1737 msp.next_state = MLX5_SQC_STATE_RDY;
1738 if (qos_queue_group_id) {
1739 msp.qos_update = true;
1740 msp.qos_queue_group_id = qos_queue_group_id;
1741 }
1742 err = mlx5e_modify_sq(mdev, sqn: *sqn, p: &msp);
1743 if (err)
1744 mlx5e_destroy_sq(mdev, sqn: *sqn);
1745
1746 return err;
1747}
1748
1749static int mlx5e_set_sq_maxrate(struct net_device *dev,
1750 struct mlx5e_txqsq *sq, u32 rate);
1751
1752int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1753 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1754 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1755 struct mlx5e_sq_stats *sq_stats)
1756{
1757 struct mlx5e_create_sq_param csp = {};
1758 u32 tx_rate;
1759 int err;
1760
1761 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1762 if (err)
1763 return err;
1764
1765 sq->stats = sq_stats;
1766
1767 csp.tisn = tisn;
1768 csp.tis_lst_sz = 1;
1769 csp.cqn = sq->cq.mcq.cqn;
1770 csp.wq_ctrl = &sq->wq_ctrl;
1771 csp.min_inline_mode = sq->min_inline_mode;
1772 err = mlx5e_create_sq_rdy(mdev: c->mdev, param, csp: &csp, qos_queue_group_id, sqn: &sq->sqn);
1773 if (err)
1774 goto err_free_txqsq;
1775
1776 tx_rate = c->priv->tx_rates[sq->txq_ix];
1777 if (tx_rate)
1778 mlx5e_set_sq_maxrate(dev: c->netdev, sq, rate: tx_rate);
1779
1780 if (params->tx_dim_enabled)
1781 sq->state |= BIT(MLX5E_SQ_STATE_DIM);
1782
1783 return 0;
1784
1785err_free_txqsq:
1786 mlx5e_free_txqsq(sq);
1787
1788 return err;
1789}
1790
1791void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1792{
1793 sq->txq = netdev_get_tx_queue(dev: sq->netdev, index: sq->txq_ix);
1794 set_bit(nr: MLX5E_SQ_STATE_ENABLED, addr: &sq->state);
1795 netdev_tx_reset_queue(q: sq->txq);
1796 netif_tx_start_queue(dev_queue: sq->txq);
1797}
1798
1799void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1800{
1801 __netif_tx_lock_bh(txq);
1802 netif_tx_stop_queue(dev_queue: txq);
1803 __netif_tx_unlock_bh(txq);
1804}
1805
1806void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1807{
1808 struct mlx5_wq_cyc *wq = &sq->wq;
1809
1810 clear_bit(nr: MLX5E_SQ_STATE_ENABLED, addr: &sq->state);
1811 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1812
1813 mlx5e_tx_disable_queue(txq: sq->txq);
1814
1815 /* last doorbell out, godspeed .. */
1816 if (mlx5e_wqc_has_room_for(wq, cc: sq->cc, pc: sq->pc, n: 1)) {
1817 u16 pi = mlx5_wq_cyc_ctr2ix(wq, ctr: sq->pc);
1818 struct mlx5e_tx_wqe *nop;
1819
1820 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1821 .num_wqebbs = 1,
1822 };
1823
1824 nop = mlx5e_post_nop(wq, sqn: sq->sqn, pc: &sq->pc);
1825 mlx5e_notify_hw(wq, pc: sq->pc, uar_map: sq->uar_map, ctrl: &nop->ctrl);
1826 }
1827}
1828
1829void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1830{
1831 struct mlx5_core_dev *mdev = sq->mdev;
1832 struct mlx5_rate_limit rl = {0};
1833
1834 cancel_work_sync(work: &sq->dim.work);
1835 cancel_work_sync(work: &sq->recover_work);
1836 mlx5e_destroy_sq(mdev, sqn: sq->sqn);
1837 if (sq->rate_limit) {
1838 rl.rate = sq->rate_limit;
1839 mlx5_rl_remove_rate(dev: mdev, rl: &rl);
1840 }
1841 mlx5e_free_txqsq_descs(sq);
1842 mlx5e_free_txqsq(sq);
1843}
1844
1845void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1846{
1847 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1848 recover_work);
1849
1850 mlx5e_reporter_tx_err_cqe(sq);
1851}
1852
1853static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1854 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1855 work_func_t recover_work_func)
1856{
1857 struct mlx5e_create_sq_param csp = {};
1858 int err;
1859
1860 err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1861 if (err)
1862 return err;
1863
1864 csp.cqn = sq->cq.mcq.cqn;
1865 csp.wq_ctrl = &sq->wq_ctrl;
1866 csp.min_inline_mode = params->tx_min_inline_mode;
1867 err = mlx5e_create_sq_rdy(mdev: c->mdev, param, csp: &csp, qos_queue_group_id: 0, sqn: &sq->sqn);
1868 if (err)
1869 goto err_free_icosq;
1870
1871 if (param->is_tls) {
1872 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1873 if (IS_ERR(ptr: sq->ktls_resync)) {
1874 err = PTR_ERR(ptr: sq->ktls_resync);
1875 goto err_destroy_icosq;
1876 }
1877 }
1878 return 0;
1879
1880err_destroy_icosq:
1881 mlx5e_destroy_sq(mdev: c->mdev, sqn: sq->sqn);
1882err_free_icosq:
1883 mlx5e_free_icosq(sq);
1884
1885 return err;
1886}
1887
1888void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1889{
1890 set_bit(nr: MLX5E_SQ_STATE_ENABLED, addr: &icosq->state);
1891}
1892
1893void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1894{
1895 clear_bit(nr: MLX5E_SQ_STATE_ENABLED, addr: &icosq->state);
1896 synchronize_net(); /* Sync with NAPI. */
1897}
1898
1899static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1900{
1901 struct mlx5e_channel *c = sq->channel;
1902
1903 if (sq->ktls_resync)
1904 mlx5e_ktls_rx_resync_destroy_resp_list(resp_list: sq->ktls_resync);
1905 mlx5e_destroy_sq(mdev: c->mdev, sqn: sq->sqn);
1906 mlx5e_free_icosq_descs(sq);
1907 mlx5e_free_icosq(sq);
1908}
1909
1910int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1911 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1912 struct mlx5e_xdpsq *sq, bool is_redirect)
1913{
1914 struct mlx5e_create_sq_param csp = {};
1915 int err;
1916
1917 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1918 if (err)
1919 return err;
1920
1921 csp.tis_lst_sz = 1;
1922 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1923 csp.cqn = sq->cq.mcq.cqn;
1924 csp.wq_ctrl = &sq->wq_ctrl;
1925 csp.min_inline_mode = sq->min_inline_mode;
1926 set_bit(nr: MLX5E_SQ_STATE_ENABLED, addr: &sq->state);
1927
1928 if (param->is_xdp_mb)
1929 set_bit(nr: MLX5E_SQ_STATE_XDP_MULTIBUF, addr: &sq->state);
1930
1931 err = mlx5e_create_sq_rdy(mdev: c->mdev, param, csp: &csp, qos_queue_group_id: 0, sqn: &sq->sqn);
1932 if (err)
1933 goto err_free_xdpsq;
1934
1935 mlx5e_set_xmit_fp(sq, is_mpw: param->is_mpw);
1936
1937 if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1938 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1939 unsigned int inline_hdr_sz = 0;
1940 int i;
1941
1942 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1943 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1944 ds_cnt++;
1945 }
1946
1947 /* Pre initialize fixed WQE fields */
1948 for (i = 0; i < mlx5_wq_cyc_get_size(wq: &sq->wq); i++) {
1949 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq: &sq->wq, ix: i);
1950 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1951 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1952
1953 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1954 .num_wqebbs = 1,
1955 .num_pkts = 1,
1956 };
1957
1958 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1959 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1960 }
1961 }
1962
1963 return 0;
1964
1965err_free_xdpsq:
1966 clear_bit(nr: MLX5E_SQ_STATE_ENABLED, addr: &sq->state);
1967 mlx5e_free_xdpsq(sq);
1968
1969 return err;
1970}
1971
1972void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1973{
1974 struct mlx5e_channel *c = sq->channel;
1975
1976 clear_bit(nr: MLX5E_SQ_STATE_ENABLED, addr: &sq->state);
1977 synchronize_net(); /* Sync with NAPI. */
1978
1979 mlx5e_destroy_sq(mdev: c->mdev, sqn: sq->sqn);
1980 mlx5e_free_xdpsq_descs(sq);
1981 mlx5e_free_xdpsq(sq);
1982}
1983
1984static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1985 struct mlx5e_cq_param *param,
1986 struct mlx5e_cq *cq)
1987{
1988 struct mlx5_core_dev *mdev = priv->mdev;
1989 struct mlx5_core_cq *mcq = &cq->mcq;
1990 int err;
1991 u32 i;
1992
1993 err = mlx5_cqwq_create(mdev, param: &param->wq, cqc: param->cqc, wq: &cq->wq,
1994 wq_ctrl: &cq->wq_ctrl);
1995 if (err)
1996 return err;
1997
1998 mcq->cqe_sz = 64;
1999 mcq->set_ci_db = cq->wq_ctrl.db.db;
2000 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2001 *mcq->set_ci_db = 0;
2002 *mcq->arm_db = 0;
2003 mcq->vector = param->eq_ix;
2004 mcq->comp = mlx5e_completion_event;
2005 mcq->event = mlx5e_cq_error_event;
2006
2007 for (i = 0; i < mlx5_cqwq_get_size(wq: &cq->wq); i++) {
2008 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq: &cq->wq, ix: i);
2009
2010 cqe->op_own = 0xf1;
2011 cqe->validity_iteration_count = 0xff;
2012 }
2013
2014 cq->mdev = mdev;
2015 cq->netdev = priv->netdev;
2016 cq->priv = priv;
2017
2018 return 0;
2019}
2020
2021static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
2022 struct mlx5e_cq_param *param,
2023 struct mlx5e_create_cq_param *ccp,
2024 struct mlx5e_cq *cq)
2025{
2026 int err;
2027
2028 param->wq.buf_numa_node = ccp->node;
2029 param->wq.db_numa_node = ccp->node;
2030 param->eq_ix = ccp->ix;
2031
2032 err = mlx5e_alloc_cq_common(priv, param, cq);
2033
2034 cq->napi = ccp->napi;
2035 cq->ch_stats = ccp->ch_stats;
2036
2037 return err;
2038}
2039
2040static void mlx5e_free_cq(struct mlx5e_cq *cq)
2041{
2042 mlx5_wq_destroy(wq_ctrl: &cq->wq_ctrl);
2043}
2044
2045static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
2046{
2047 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2048 struct mlx5_core_dev *mdev = cq->mdev;
2049 struct mlx5_core_cq *mcq = &cq->mcq;
2050
2051 void *in;
2052 void *cqc;
2053 int inlen;
2054 int eqn;
2055 int err;
2056
2057 err = mlx5_comp_eqn_get(dev: mdev, vecidx: param->eq_ix, eqn: &eqn);
2058 if (err)
2059 return err;
2060
2061 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2062 sizeof(u64) * cq->wq_ctrl.buf.npages;
2063 in = kvzalloc(size: inlen, GFP_KERNEL);
2064 if (!in)
2065 return -ENOMEM;
2066
2067 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2068
2069 memcpy(cqc, param->cqc, sizeof(param->cqc));
2070
2071 mlx5_fill_page_frag_array(frag_buf: &cq->wq_ctrl.buf,
2072 pas: (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
2073
2074 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
2075 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn);
2076 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
2077 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2078 MLX5_ADAPTER_PAGE_SHIFT);
2079 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2080
2081 err = mlx5_core_create_cq(dev: mdev, cq: mcq, in, inlen, out, outlen: sizeof(out));
2082
2083 kvfree(addr: in);
2084
2085 if (err)
2086 return err;
2087
2088 mlx5e_cq_arm(cq);
2089
2090 return 0;
2091}
2092
2093static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
2094{
2095 mlx5_core_destroy_cq(dev: cq->mdev, cq: &cq->mcq);
2096}
2097
2098int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
2099 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
2100 struct mlx5e_cq *cq)
2101{
2102 struct mlx5_core_dev *mdev = priv->mdev;
2103 int err;
2104
2105 err = mlx5e_alloc_cq(priv, param, ccp, cq);
2106 if (err)
2107 return err;
2108
2109 err = mlx5e_create_cq(cq, param);
2110 if (err)
2111 goto err_free_cq;
2112
2113 if (MLX5_CAP_GEN(mdev, cq_moderation))
2114 mlx5_core_modify_cq_moderation(dev: mdev, cq: &cq->mcq, cq_period: moder.usec, cq_max_count: moder.pkts);
2115 return 0;
2116
2117err_free_cq:
2118 mlx5e_free_cq(cq);
2119
2120 return err;
2121}
2122
2123void mlx5e_close_cq(struct mlx5e_cq *cq)
2124{
2125 mlx5e_destroy_cq(cq);
2126 mlx5e_free_cq(cq);
2127}
2128
2129static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2130 struct mlx5e_params *params,
2131 struct mlx5e_create_cq_param *ccp,
2132 struct mlx5e_channel_param *cparam)
2133{
2134 int err;
2135 int tc;
2136
2137 for (tc = 0; tc < c->num_tc; tc++) {
2138 err = mlx5e_open_cq(priv: c->priv, moder: params->tx_cq_moderation, param: &cparam->txq_sq.cqp,
2139 ccp, cq: &c->sq[tc].cq);
2140 if (err)
2141 goto err_close_tx_cqs;
2142 }
2143
2144 return 0;
2145
2146err_close_tx_cqs:
2147 for (tc--; tc >= 0; tc--)
2148 mlx5e_close_cq(cq: &c->sq[tc].cq);
2149
2150 return err;
2151}
2152
2153static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2154{
2155 int tc;
2156
2157 for (tc = 0; tc < c->num_tc; tc++)
2158 mlx5e_close_cq(cq: &c->sq[tc].cq);
2159}
2160
2161static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
2162{
2163 int tc;
2164
2165 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
2166 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
2167 return tc;
2168
2169 WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
2170 return -ENOENT;
2171}
2172
2173static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
2174 u32 *hw_id)
2175{
2176 int tc;
2177
2178 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) {
2179 *hw_id = 0;
2180 return 0;
2181 }
2182
2183 tc = mlx5e_mqprio_txq_to_tc(tc_to_txq: params->mqprio.tc_to_txq, txq: txq_ix);
2184 if (tc < 0)
2185 return tc;
2186
2187 if (tc >= params->mqprio.num_tc) {
2188 WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u",
2189 tc, params->mqprio.num_tc);
2190 return -EINVAL;
2191 }
2192
2193 *hw_id = params->mqprio.channel.hw_id[tc];
2194 return 0;
2195}
2196
2197static int mlx5e_open_sqs(struct mlx5e_channel *c,
2198 struct mlx5e_params *params,
2199 struct mlx5e_channel_param *cparam)
2200{
2201 int err, tc;
2202
2203 for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
2204 int txq_ix = c->ix + tc * params->num_channels;
2205 u32 qos_queue_group_id;
2206
2207 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, hw_id: &qos_queue_group_id);
2208 if (err)
2209 goto err_close_sqs;
2210
2211 err = mlx5e_open_txqsq(c, tisn: c->priv->tisn[c->lag_port][tc], txq_ix,
2212 params, param: &cparam->txq_sq, sq: &c->sq[tc], tc,
2213 qos_queue_group_id,
2214 sq_stats: &c->priv->channel_stats[c->ix]->sq[tc]);
2215 if (err)
2216 goto err_close_sqs;
2217 }
2218
2219 return 0;
2220
2221err_close_sqs:
2222 for (tc--; tc >= 0; tc--)
2223 mlx5e_close_txqsq(sq: &c->sq[tc]);
2224
2225 return err;
2226}
2227
2228static void mlx5e_close_sqs(struct mlx5e_channel *c)
2229{
2230 int tc;
2231
2232 for (tc = 0; tc < c->num_tc; tc++)
2233 mlx5e_close_txqsq(sq: &c->sq[tc]);
2234}
2235
2236static int mlx5e_set_sq_maxrate(struct net_device *dev,
2237 struct mlx5e_txqsq *sq, u32 rate)
2238{
2239 struct mlx5e_priv *priv = netdev_priv(dev);
2240 struct mlx5_core_dev *mdev = priv->mdev;
2241 struct mlx5e_modify_sq_param msp = {0};
2242 struct mlx5_rate_limit rl = {0};
2243 u16 rl_index = 0;
2244 int err;
2245
2246 if (rate == sq->rate_limit)
2247 /* nothing to do */
2248 return 0;
2249
2250 if (sq->rate_limit) {
2251 rl.rate = sq->rate_limit;
2252 /* remove current rl index to free space to next ones */
2253 mlx5_rl_remove_rate(dev: mdev, rl: &rl);
2254 }
2255
2256 sq->rate_limit = 0;
2257
2258 if (rate) {
2259 rl.rate = rate;
2260 err = mlx5_rl_add_rate(dev: mdev, index: &rl_index, rl: &rl);
2261 if (err) {
2262 netdev_err(dev, format: "Failed configuring rate %u: %d\n",
2263 rate, err);
2264 return err;
2265 }
2266 }
2267
2268 msp.curr_state = MLX5_SQC_STATE_RDY;
2269 msp.next_state = MLX5_SQC_STATE_RDY;
2270 msp.rl_index = rl_index;
2271 msp.rl_update = true;
2272 err = mlx5e_modify_sq(mdev, sqn: sq->sqn, p: &msp);
2273 if (err) {
2274 netdev_err(dev, format: "Failed configuring rate %u: %d\n",
2275 rate, err);
2276 /* remove the rate from the table */
2277 if (rate)
2278 mlx5_rl_remove_rate(dev: mdev, rl: &rl);
2279 return err;
2280 }
2281
2282 sq->rate_limit = rate;
2283 return 0;
2284}
2285
2286static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2287{
2288 struct mlx5e_priv *priv = netdev_priv(dev);
2289 struct mlx5_core_dev *mdev = priv->mdev;
2290 struct mlx5e_txqsq *sq = priv->txq2sq[index];
2291 int err = 0;
2292
2293 if (!mlx5_rl_is_supported(dev: mdev)) {
2294 netdev_err(dev, format: "Rate limiting is not supported on this device\n");
2295 return -EINVAL;
2296 }
2297
2298 /* rate is given in Mb/sec, HW config is in Kb/sec */
2299 rate = rate << 10;
2300
2301 /* Check whether rate in valid range, 0 is always valid */
2302 if (rate && !mlx5_rl_is_in_range(dev: mdev, rate)) {
2303 netdev_err(dev, format: "TX rate %u, is not in range\n", rate);
2304 return -ERANGE;
2305 }
2306
2307 mutex_lock(&priv->state_lock);
2308 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2309 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2310 if (!err)
2311 priv->tx_rates[index] = rate;
2312 mutex_unlock(lock: &priv->state_lock);
2313
2314 return err;
2315}
2316
2317static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2318 struct mlx5e_rq_param *rq_params)
2319{
2320 int err;
2321
2322 err = mlx5e_init_rxq_rq(c, params, xdp_frag_size: rq_params->xdp_frag_size, rq: &c->rq);
2323 if (err)
2324 return err;
2325
2326 return mlx5e_open_rq(params, param: rq_params, NULL, cpu_to_node(cpu: c->cpu), rq: &c->rq);
2327}
2328
2329static int mlx5e_open_queues(struct mlx5e_channel *c,
2330 struct mlx5e_params *params,
2331 struct mlx5e_channel_param *cparam)
2332{
2333 struct dim_cq_moder icocq_moder = {0, 0};
2334 struct mlx5e_create_cq_param ccp;
2335 int err;
2336
2337 mlx5e_build_create_cq_param(ccp: &ccp, c);
2338
2339 err = mlx5e_open_cq(priv: c->priv, moder: icocq_moder, param: &cparam->async_icosq.cqp, ccp: &ccp,
2340 cq: &c->async_icosq.cq);
2341 if (err)
2342 return err;
2343
2344 err = mlx5e_open_cq(priv: c->priv, moder: icocq_moder, param: &cparam->icosq.cqp, ccp: &ccp,
2345 cq: &c->icosq.cq);
2346 if (err)
2347 goto err_close_async_icosq_cq;
2348
2349 err = mlx5e_open_tx_cqs(c, params, ccp: &ccp, cparam);
2350 if (err)
2351 goto err_close_icosq_cq;
2352
2353 err = mlx5e_open_cq(priv: c->priv, moder: params->tx_cq_moderation, param: &cparam->xdp_sq.cqp, ccp: &ccp,
2354 cq: &c->xdpsq.cq);
2355 if (err)
2356 goto err_close_tx_cqs;
2357
2358 err = mlx5e_open_cq(priv: c->priv, moder: params->rx_cq_moderation, param: &cparam->rq.cqp, ccp: &ccp,
2359 cq: &c->rq.cq);
2360 if (err)
2361 goto err_close_xdp_tx_cqs;
2362
2363 err = c->xdp ? mlx5e_open_cq(priv: c->priv, moder: params->tx_cq_moderation, param: &cparam->xdp_sq.cqp,
2364 ccp: &ccp, cq: &c->rq_xdpsq.cq) : 0;
2365 if (err)
2366 goto err_close_rx_cq;
2367
2368 spin_lock_init(&c->async_icosq_lock);
2369
2370 err = mlx5e_open_icosq(c, params, param: &cparam->async_icosq, sq: &c->async_icosq,
2371 recover_work_func: mlx5e_async_icosq_err_cqe_work);
2372 if (err)
2373 goto err_close_xdpsq_cq;
2374
2375 mutex_init(&c->icosq_recovery_lock);
2376
2377 err = mlx5e_open_icosq(c, params, param: &cparam->icosq, sq: &c->icosq,
2378 recover_work_func: mlx5e_icosq_err_cqe_work);
2379 if (err)
2380 goto err_close_async_icosq;
2381
2382 err = mlx5e_open_sqs(c, params, cparam);
2383 if (err)
2384 goto err_close_icosq;
2385
2386 err = mlx5e_open_rxq_rq(c, params, rq_params: &cparam->rq);
2387 if (err)
2388 goto err_close_sqs;
2389
2390 if (c->xdp) {
2391 err = mlx5e_open_xdpsq(c, params, param: &cparam->xdp_sq, NULL,
2392 sq: &c->rq_xdpsq, is_redirect: false);
2393 if (err)
2394 goto err_close_rq;
2395 }
2396
2397 err = mlx5e_open_xdpsq(c, params, param: &cparam->xdp_sq, NULL, sq: &c->xdpsq, is_redirect: true);
2398 if (err)
2399 goto err_close_xdp_sq;
2400
2401 return 0;
2402
2403err_close_xdp_sq:
2404 if (c->xdp)
2405 mlx5e_close_xdpsq(sq: &c->rq_xdpsq);
2406
2407err_close_rq:
2408 mlx5e_close_rq(rq: &c->rq);
2409
2410err_close_sqs:
2411 mlx5e_close_sqs(c);
2412
2413err_close_icosq:
2414 mlx5e_close_icosq(sq: &c->icosq);
2415
2416err_close_async_icosq:
2417 mlx5e_close_icosq(sq: &c->async_icosq);
2418
2419err_close_xdpsq_cq:
2420 if (c->xdp)
2421 mlx5e_close_cq(cq: &c->rq_xdpsq.cq);
2422
2423err_close_rx_cq:
2424 mlx5e_close_cq(cq: &c->rq.cq);
2425
2426err_close_xdp_tx_cqs:
2427 mlx5e_close_cq(cq: &c->xdpsq.cq);
2428
2429err_close_tx_cqs:
2430 mlx5e_close_tx_cqs(c);
2431
2432err_close_icosq_cq:
2433 mlx5e_close_cq(cq: &c->icosq.cq);
2434
2435err_close_async_icosq_cq:
2436 mlx5e_close_cq(cq: &c->async_icosq.cq);
2437
2438 return err;
2439}
2440
2441static void mlx5e_close_queues(struct mlx5e_channel *c)
2442{
2443 mlx5e_close_xdpsq(sq: &c->xdpsq);
2444 if (c->xdp)
2445 mlx5e_close_xdpsq(sq: &c->rq_xdpsq);
2446 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2447 cancel_work_sync(work: &c->icosq.recover_work);
2448 mlx5e_close_rq(rq: &c->rq);
2449 mlx5e_close_sqs(c);
2450 mlx5e_close_icosq(sq: &c->icosq);
2451 mutex_destroy(lock: &c->icosq_recovery_lock);
2452 mlx5e_close_icosq(sq: &c->async_icosq);
2453 if (c->xdp)
2454 mlx5e_close_cq(cq: &c->rq_xdpsq.cq);
2455 mlx5e_close_cq(cq: &c->rq.cq);
2456 mlx5e_close_cq(cq: &c->xdpsq.cq);
2457 mlx5e_close_tx_cqs(c);
2458 mlx5e_close_cq(cq: &c->icosq.cq);
2459 mlx5e_close_cq(cq: &c->async_icosq.cq);
2460}
2461
2462static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2463{
2464 u16 port_aff_bias = mlx5_core_is_pf(dev: mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2465
2466 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2467}
2468
2469static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2470{
2471 if (ix > priv->stats_nch) {
2472 netdev_warn(dev: priv->netdev, format: "Unexpected channel stats index %d > %d\n", ix,
2473 priv->stats_nch);
2474 return -EINVAL;
2475 }
2476
2477 if (priv->channel_stats[ix])
2478 return 0;
2479
2480 /* Asymmetric dynamic memory allocation.
2481 * Freed in mlx5e_priv_arrays_free, not on channel closure.
2482 */
2483 netdev_dbg(priv->netdev, "Creating channel stats %d\n", ix);
2484 priv->channel_stats[ix] = kvzalloc_node(size: sizeof(**priv->channel_stats),
2485 GFP_KERNEL, cpu_to_node(cpu));
2486 if (!priv->channel_stats[ix])
2487 return -ENOMEM;
2488 priv->stats_nch++;
2489
2490 return 0;
2491}
2492
2493void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c)
2494{
2495 spin_lock_bh(lock: &c->async_icosq_lock);
2496 mlx5e_trigger_irq(sq: &c->async_icosq);
2497 spin_unlock_bh(lock: &c->async_icosq_lock);
2498}
2499
2500void mlx5e_trigger_napi_sched(struct napi_struct *napi)
2501{
2502 local_bh_disable();
2503 napi_schedule(n: napi);
2504 local_bh_enable();
2505}
2506
2507static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2508 struct mlx5e_params *params,
2509 struct mlx5e_channel_param *cparam,
2510 struct xsk_buff_pool *xsk_pool,
2511 struct mlx5e_channel **cp)
2512{
2513 int cpu = mlx5_comp_vector_get_cpu(dev: priv->mdev, vector: ix);
2514 struct net_device *netdev = priv->netdev;
2515 struct mlx5e_xsk_param xsk;
2516 struct mlx5e_channel *c;
2517 unsigned int irq;
2518 int err;
2519
2520 err = mlx5_comp_irqn_get(dev: priv->mdev, vector: ix, irqn: &irq);
2521 if (err)
2522 return err;
2523
2524 err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2525 if (err)
2526 return err;
2527
2528 c = kvzalloc_node(size: sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2529 if (!c)
2530 return -ENOMEM;
2531
2532 c->priv = priv;
2533 c->mdev = priv->mdev;
2534 c->tstamp = &priv->tstamp;
2535 c->ix = ix;
2536 c->cpu = cpu;
2537 c->pdev = mlx5_core_dma_dev(dev: priv->mdev);
2538 c->netdev = priv->netdev;
2539 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2540 c->num_tc = mlx5e_get_dcb_num_tc(params);
2541 c->xdp = !!params->xdp_prog;
2542 c->stats = &priv->channel_stats[ix]->ch;
2543 c->aff_mask = irq_get_effective_affinity_mask(irq);
2544 c->lag_port = mlx5e_enumerate_lag_port(mdev: priv->mdev, ix);
2545
2546 netif_napi_add(dev: netdev, napi: &c->napi, poll: mlx5e_napi_poll);
2547
2548 err = mlx5e_open_queues(c, params, cparam);
2549 if (unlikely(err))
2550 goto err_napi_del;
2551
2552 if (xsk_pool) {
2553 mlx5e_build_xsk_param(pool: xsk_pool, xsk: &xsk);
2554 err = mlx5e_open_xsk(priv, params, xsk: &xsk, pool: xsk_pool, c);
2555 if (unlikely(err))
2556 goto err_close_queues;
2557 }
2558
2559 *cp = c;
2560
2561 return 0;
2562
2563err_close_queues:
2564 mlx5e_close_queues(c);
2565
2566err_napi_del:
2567 netif_napi_del(napi: &c->napi);
2568
2569 kvfree(addr: c);
2570
2571 return err;
2572}
2573
2574static void mlx5e_activate_channel(struct mlx5e_channel *c)
2575{
2576 int tc;
2577
2578 napi_enable(n: &c->napi);
2579
2580 for (tc = 0; tc < c->num_tc; tc++)
2581 mlx5e_activate_txqsq(sq: &c->sq[tc]);
2582 mlx5e_activate_icosq(icosq: &c->icosq);
2583 mlx5e_activate_icosq(icosq: &c->async_icosq);
2584
2585 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2586 mlx5e_activate_xsk(c);
2587 else
2588 mlx5e_activate_rq(rq: &c->rq);
2589}
2590
2591static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2592{
2593 int tc;
2594
2595 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2596 mlx5e_deactivate_xsk(c);
2597 else
2598 mlx5e_deactivate_rq(rq: &c->rq);
2599
2600 mlx5e_deactivate_icosq(icosq: &c->async_icosq);
2601 mlx5e_deactivate_icosq(icosq: &c->icosq);
2602 for (tc = 0; tc < c->num_tc; tc++)
2603 mlx5e_deactivate_txqsq(sq: &c->sq[tc]);
2604 mlx5e_qos_deactivate_queues(c);
2605
2606 napi_disable(n: &c->napi);
2607}
2608
2609static void mlx5e_close_channel(struct mlx5e_channel *c)
2610{
2611 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2612 mlx5e_close_xsk(c);
2613 mlx5e_close_queues(c);
2614 mlx5e_qos_close_queues(c);
2615 netif_napi_del(napi: &c->napi);
2616
2617 kvfree(addr: c);
2618}
2619
2620int mlx5e_open_channels(struct mlx5e_priv *priv,
2621 struct mlx5e_channels *chs)
2622{
2623 struct mlx5e_channel_param *cparam;
2624 int err = -ENOMEM;
2625 int i;
2626
2627 chs->num = chs->params.num_channels;
2628
2629 chs->c = kcalloc(n: chs->num, size: sizeof(struct mlx5e_channel *), GFP_KERNEL);
2630 cparam = kvzalloc(size: sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2631 if (!chs->c || !cparam)
2632 goto err_free;
2633
2634 err = mlx5e_build_channel_param(mdev: priv->mdev, params: &chs->params, q_counter: priv->q_counter, cparam);
2635 if (err)
2636 goto err_free;
2637
2638 for (i = 0; i < chs->num; i++) {
2639 struct xsk_buff_pool *xsk_pool = NULL;
2640
2641 if (chs->params.xdp_prog)
2642 xsk_pool = mlx5e_xsk_get_pool(params: &chs->params, xsk: chs->params.xsk, ix: i);
2643
2644 err = mlx5e_open_channel(priv, ix: i, params: &chs->params, cparam, xsk_pool, cp: &chs->c[i]);
2645 if (err)
2646 goto err_close_channels;
2647 }
2648
2649 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2650 err = mlx5e_ptp_open(priv, params: &chs->params, lag_port: chs->c[0]->lag_port, cp: &chs->ptp);
2651 if (err)
2652 goto err_close_channels;
2653 }
2654
2655 if (priv->htb) {
2656 err = mlx5e_qos_open_queues(priv, chs);
2657 if (err)
2658 goto err_close_ptp;
2659 }
2660
2661 mlx5e_health_channels_update(priv);
2662 kvfree(addr: cparam);
2663 return 0;
2664
2665err_close_ptp:
2666 if (chs->ptp)
2667 mlx5e_ptp_close(c: chs->ptp);
2668
2669err_close_channels:
2670 for (i--; i >= 0; i--)
2671 mlx5e_close_channel(c: chs->c[i]);
2672
2673err_free:
2674 kfree(objp: chs->c);
2675 kvfree(addr: cparam);
2676 chs->num = 0;
2677 return err;
2678}
2679
2680static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channels *chs)
2681{
2682 int i;
2683
2684 for (i = 0; i < chs->num; i++)
2685 mlx5e_activate_channel(c: chs->c[i]);
2686
2687 if (priv->htb)
2688 mlx5e_qos_activate_queues(priv);
2689
2690 for (i = 0; i < chs->num; i++)
2691 mlx5e_trigger_napi_icosq(c: chs->c[i]);
2692
2693 if (chs->ptp)
2694 mlx5e_ptp_activate_channel(c: chs->ptp);
2695}
2696
2697static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2698{
2699 int err = 0;
2700 int i;
2701
2702 for (i = 0; i < chs->num; i++) {
2703 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2704 struct mlx5e_channel *c = chs->c[i];
2705
2706 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2707 continue;
2708
2709 err |= mlx5e_wait_for_min_rx_wqes(rq: &c->rq, wait_time: timeout);
2710
2711 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2712 * doesn't provide any Fill Ring entries at the setup stage.
2713 */
2714 }
2715
2716 return err ? -ETIMEDOUT : 0;
2717}
2718
2719static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2720{
2721 int i;
2722
2723 if (chs->ptp)
2724 mlx5e_ptp_deactivate_channel(c: chs->ptp);
2725
2726 for (i = 0; i < chs->num; i++)
2727 mlx5e_deactivate_channel(c: chs->c[i]);
2728}
2729
2730void mlx5e_close_channels(struct mlx5e_channels *chs)
2731{
2732 int i;
2733
2734 if (chs->ptp) {
2735 mlx5e_ptp_close(c: chs->ptp);
2736 chs->ptp = NULL;
2737 }
2738 for (i = 0; i < chs->num; i++)
2739 mlx5e_close_channel(c: chs->c[i]);
2740
2741 kfree(objp: chs->c);
2742 chs->num = 0;
2743}
2744
2745static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2746{
2747 struct mlx5e_rx_res *res = priv->rx_res;
2748
2749 return mlx5e_rx_res_packet_merge_set_param(res, pkt_merge_param: &priv->channels.params.packet_merge);
2750}
2751
2752static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2753
2754static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2755 struct mlx5e_params *params, u16 mtu)
2756{
2757 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2758 int err;
2759
2760 err = mlx5_set_port_mtu(dev: mdev, mtu: hw_mtu, port: 1);
2761 if (err)
2762 return err;
2763
2764 /* Update vport context MTU */
2765 mlx5_modify_nic_vport_mtu(mdev, mtu: hw_mtu);
2766 return 0;
2767}
2768
2769static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2770 struct mlx5e_params *params, u16 *mtu)
2771{
2772 u16 hw_mtu = 0;
2773 int err;
2774
2775 err = mlx5_query_nic_vport_mtu(mdev, mtu: &hw_mtu);
2776 if (err || !hw_mtu) /* fallback to port oper mtu */
2777 mlx5_query_port_oper_mtu(dev: mdev, oper_mtu: &hw_mtu, port: 1);
2778
2779 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2780}
2781
2782int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2783{
2784 struct mlx5e_params *params = &priv->channels.params;
2785 struct net_device *netdev = priv->netdev;
2786 struct mlx5_core_dev *mdev = priv->mdev;
2787 u16 mtu;
2788 int err;
2789
2790 err = mlx5e_set_mtu(mdev, params, mtu: params->sw_mtu);
2791 if (err)
2792 return err;
2793
2794 mlx5e_query_mtu(mdev, params, mtu: &mtu);
2795 if (mtu != params->sw_mtu)
2796 netdev_warn(dev: netdev, format: "%s: VPort MTU %d is different than netdev mtu %d\n",
2797 __func__, mtu, params->sw_mtu);
2798
2799 params->sw_mtu = mtu;
2800 return 0;
2801}
2802
2803MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2804
2805void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2806{
2807 struct mlx5e_params *params = &priv->channels.params;
2808 struct net_device *netdev = priv->netdev;
2809 struct mlx5_core_dev *mdev = priv->mdev;
2810 u16 max_mtu;
2811
2812 /* MTU range: 68 - hw-specific max */
2813 netdev->min_mtu = ETH_MIN_MTU;
2814
2815 mlx5_query_port_max_mtu(dev: mdev, max_mtu: &max_mtu, port: 1);
2816 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2817 ETH_MAX_MTU);
2818}
2819
2820static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2821 struct netdev_tc_txq *tc_to_txq)
2822{
2823 int tc, err;
2824
2825 netdev_reset_tc(dev: netdev);
2826
2827 if (ntc == 1)
2828 return 0;
2829
2830 err = netdev_set_num_tc(dev: netdev, num_tc: ntc);
2831 if (err) {
2832 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2833 return err;
2834 }
2835
2836 for (tc = 0; tc < ntc; tc++) {
2837 u16 count, offset;
2838
2839 count = tc_to_txq[tc].count;
2840 offset = tc_to_txq[tc].offset;
2841 netdev_set_tc_queue(dev: netdev, tc, count, offset);
2842 }
2843
2844 return 0;
2845}
2846
2847int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2848{
2849 int nch, ntc, num_txqs, err;
2850 int qos_queues = 0;
2851
2852 if (priv->htb)
2853 qos_queues = mlx5e_htb_cur_leaf_nodes(htb: priv->htb);
2854
2855 nch = priv->channels.params.num_channels;
2856 ntc = mlx5e_get_dcb_num_tc(params: &priv->channels.params);
2857 num_txqs = nch * ntc + qos_queues;
2858 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2859 num_txqs += ntc;
2860
2861 netdev_dbg(priv->netdev, "Setting num_txqs %d\n", num_txqs);
2862 err = netif_set_real_num_tx_queues(dev: priv->netdev, txq: num_txqs);
2863 if (err)
2864 netdev_warn(dev: priv->netdev, format: "netif_set_real_num_tx_queues failed, %d\n", err);
2865
2866 return err;
2867}
2868
2869static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2870{
2871 struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2872 struct net_device *netdev = priv->netdev;
2873 int old_num_txqs, old_ntc;
2874 int nch, ntc;
2875 int err;
2876 int i;
2877
2878 old_num_txqs = netdev->real_num_tx_queues;
2879 old_ntc = netdev->num_tc ? : 1;
2880 for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2881 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2882
2883 nch = priv->channels.params.num_channels;
2884 ntc = priv->channels.params.mqprio.num_tc;
2885 tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2886
2887 err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2888 if (err)
2889 goto err_out;
2890 err = mlx5e_update_tx_netdev_queues(priv);
2891 if (err)
2892 goto err_tcs;
2893 err = netif_set_real_num_rx_queues(dev: netdev, rxq: nch);
2894 if (err) {
2895 netdev_warn(dev: netdev, format: "netif_set_real_num_rx_queues failed, %d\n", err);
2896 goto err_txqs;
2897 }
2898
2899 return 0;
2900
2901err_txqs:
2902 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2903 * one of nch and ntc is changed in this function. That means, the call
2904 * to netif_set_real_num_tx_queues below should not fail, because it
2905 * decreases the number of TX queues.
2906 */
2907 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2908
2909err_tcs:
2910 WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2911 old_tc_to_txq));
2912err_out:
2913 return err;
2914}
2915
2916static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2917
2918static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2919 struct mlx5e_params *params)
2920{
2921 struct mlx5_core_dev *mdev = priv->mdev;
2922 int num_comp_vectors, ix, irq;
2923
2924 num_comp_vectors = mlx5_comp_vectors_max(dev: mdev);
2925
2926 for (ix = 0; ix < params->num_channels; ix++) {
2927 cpumask_clear(dstp: priv->scratchpad.cpumask);
2928
2929 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2930 int cpu = mlx5_comp_vector_get_cpu(dev: mdev, vector: irq);
2931
2932 cpumask_set_cpu(cpu, dstp: priv->scratchpad.cpumask);
2933 }
2934
2935 netif_set_xps_queue(dev: priv->netdev, mask: priv->scratchpad.cpumask, index: ix);
2936 }
2937}
2938
2939static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2940{
2941 u16 count = priv->channels.params.num_channels;
2942 int err;
2943
2944 err = mlx5e_update_netdev_queues(priv);
2945 if (err)
2946 return err;
2947
2948 mlx5e_set_default_xps_cpumasks(priv, params: &priv->channels.params);
2949
2950 /* This function may be called on attach, before priv->rx_res is created. */
2951 if (priv->rx_res) {
2952 mlx5e_rx_res_rss_update_num_channels(res: priv->rx_res, nch: count);
2953
2954 if (!netif_is_rxfh_configured(dev: priv->netdev))
2955 mlx5e_rx_res_rss_set_indir_uniform(res: priv->rx_res, nch: count);
2956 }
2957
2958 return 0;
2959}
2960
2961MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2962
2963static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2964{
2965 int i, ch, tc, num_tc;
2966
2967 ch = priv->channels.num;
2968 num_tc = mlx5e_get_dcb_num_tc(params: &priv->channels.params);
2969
2970 for (i = 0; i < ch; i++) {
2971 for (tc = 0; tc < num_tc; tc++) {
2972 struct mlx5e_channel *c = priv->channels.c[i];
2973 struct mlx5e_txqsq *sq = &c->sq[tc];
2974
2975 priv->txq2sq[sq->txq_ix] = sq;
2976 }
2977 }
2978
2979 if (!priv->channels.ptp)
2980 goto out;
2981
2982 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2983 goto out;
2984
2985 for (tc = 0; tc < num_tc; tc++) {
2986 struct mlx5e_ptp *c = priv->channels.ptp;
2987 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2988
2989 priv->txq2sq[sq->txq_ix] = sq;
2990 }
2991
2992out:
2993 /* Make the change to txq2sq visible before the queue is started.
2994 * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
2995 * which pairs with this barrier.
2996 */
2997 smp_wmb();
2998}
2999
3000void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
3001{
3002 mlx5e_build_txq_maps(priv);
3003 mlx5e_activate_channels(priv, chs: &priv->channels);
3004 mlx5e_xdp_tx_enable(priv);
3005
3006 /* dev_watchdog() wants all TX queues to be started when the carrier is
3007 * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
3008 * Make it happy to avoid TX timeout false alarms.
3009 */
3010 netif_tx_start_all_queues(dev: priv->netdev);
3011
3012 if (mlx5e_is_vport_rep(priv))
3013 mlx5e_rep_activate_channels(priv);
3014
3015 mlx5e_wait_channels_min_rx_wqes(chs: &priv->channels);
3016
3017 if (priv->rx_res)
3018 mlx5e_rx_res_channels_activate(res: priv->rx_res, chs: &priv->channels);
3019}
3020
3021void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
3022{
3023 if (priv->rx_res)
3024 mlx5e_rx_res_channels_deactivate(res: priv->rx_res);
3025
3026 if (mlx5e_is_vport_rep(priv))
3027 mlx5e_rep_deactivate_channels(priv);
3028
3029 /* The results of ndo_select_queue are unreliable, while netdev config
3030 * is being changed (real_num_tx_queues, num_tc). Stop all queues to
3031 * prevent ndo_start_xmit from being called, so that it can assume that
3032 * the selected queue is always valid.
3033 */
3034 netif_tx_disable(dev: priv->netdev);
3035
3036 mlx5e_xdp_tx_disable(priv);
3037 mlx5e_deactivate_channels(chs: &priv->channels);
3038}
3039
3040static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
3041 struct mlx5e_params *new_params,
3042 mlx5e_fp_preactivate preactivate,
3043 void *context)
3044{
3045 struct mlx5e_params old_params;
3046
3047 old_params = priv->channels.params;
3048 priv->channels.params = *new_params;
3049
3050 if (preactivate) {
3051 int err;
3052
3053 err = preactivate(priv, context);
3054 if (err) {
3055 priv->channels.params = old_params;
3056 return err;
3057 }
3058 }
3059
3060 return 0;
3061}
3062
3063static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3064 struct mlx5e_channels *new_chs,
3065 mlx5e_fp_preactivate preactivate,
3066 void *context)
3067{
3068 struct net_device *netdev = priv->netdev;
3069 struct mlx5e_channels old_chs;
3070 int carrier_ok;
3071 int err = 0;
3072
3073 carrier_ok = netif_carrier_ok(dev: netdev);
3074 netif_carrier_off(dev: netdev);
3075
3076 mlx5e_deactivate_priv_channels(priv);
3077
3078 old_chs = priv->channels;
3079 priv->channels = *new_chs;
3080
3081 /* New channels are ready to roll, call the preactivate hook if needed
3082 * to modify HW settings or update kernel parameters.
3083 */
3084 if (preactivate) {
3085 err = preactivate(priv, context);
3086 if (err) {
3087 priv->channels = old_chs;
3088 goto out;
3089 }
3090 }
3091
3092 mlx5e_close_channels(chs: &old_chs);
3093 priv->profile->update_rx(priv);
3094
3095 mlx5e_selq_apply(selq: &priv->selq);
3096out:
3097 mlx5e_activate_priv_channels(priv);
3098
3099 /* return carrier back if needed */
3100 if (carrier_ok)
3101 netif_carrier_on(dev: netdev);
3102
3103 return err;
3104}
3105
3106int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
3107 struct mlx5e_params *params,
3108 mlx5e_fp_preactivate preactivate,
3109 void *context, bool reset)
3110{
3111 struct mlx5e_channels *new_chs;
3112 int err;
3113
3114 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
3115 if (!reset)
3116 return mlx5e_switch_priv_params(priv, new_params: params, preactivate, context);
3117
3118 new_chs = kzalloc(size: sizeof(*new_chs), GFP_KERNEL);
3119 if (!new_chs)
3120 return -ENOMEM;
3121 new_chs->params = *params;
3122
3123 mlx5e_selq_prepare_params(selq: &priv->selq, params: &new_chs->params);
3124
3125 err = mlx5e_open_channels(priv, chs: new_chs);
3126 if (err)
3127 goto err_cancel_selq;
3128
3129 err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3130 if (err)
3131 goto err_close;
3132
3133 kfree(objp: new_chs);
3134 return 0;
3135
3136err_close:
3137 mlx5e_close_channels(chs: new_chs);
3138
3139err_cancel_selq:
3140 mlx5e_selq_cancel(selq: &priv->selq);
3141 kfree(objp: new_chs);
3142 return err;
3143}
3144
3145int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3146{
3147 return mlx5e_safe_switch_params(priv, params: &priv->channels.params, NULL, NULL, reset: true);
3148}
3149
3150void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3151{
3152 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
3153 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3154}
3155
3156static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3157 enum mlx5_port_status state)
3158{
3159 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3160 int vport_admin_state;
3161
3162 mlx5_set_port_admin_status(dev: mdev, status: state);
3163
3164 if (mlx5_eswitch_mode(dev: mdev) == MLX5_ESWITCH_OFFLOADS ||
3165 !MLX5_CAP_GEN(mdev, uplink_follow))
3166 return;
3167
3168 if (state == MLX5_PORT_UP)
3169 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3170 else
3171 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3172
3173 mlx5_eswitch_set_vport_state(esw, vport: MLX5_VPORT_UPLINK, link_state: vport_admin_state);
3174}
3175
3176int mlx5e_open_locked(struct net_device *netdev)
3177{
3178 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3179 int err;
3180
3181 mlx5e_selq_prepare_params(selq: &priv->selq, params: &priv->channels.params);
3182
3183 set_bit(nr: MLX5E_STATE_OPENED, addr: &priv->state);
3184
3185 err = mlx5e_open_channels(priv, chs: &priv->channels);
3186 if (err)
3187 goto err_clear_state_opened_flag;
3188
3189 err = priv->profile->update_rx(priv);
3190 if (err)
3191 goto err_close_channels;
3192
3193 mlx5e_selq_apply(selq: &priv->selq);
3194 mlx5e_activate_priv_channels(priv);
3195 mlx5e_apply_traps(priv, enable: true);
3196 if (priv->profile->update_carrier)
3197 priv->profile->update_carrier(priv);
3198
3199 mlx5e_queue_update_stats(priv);
3200 return 0;
3201
3202err_close_channels:
3203 mlx5e_close_channels(chs: &priv->channels);
3204err_clear_state_opened_flag:
3205 clear_bit(nr: MLX5E_STATE_OPENED, addr: &priv->state);
3206 mlx5e_selq_cancel(selq: &priv->selq);
3207 return err;
3208}
3209
3210int mlx5e_open(struct net_device *netdev)
3211{
3212 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3213 int err;
3214
3215 mutex_lock(&priv->state_lock);
3216 err = mlx5e_open_locked(netdev);
3217 if (!err)
3218 mlx5e_modify_admin_state(mdev: priv->mdev, state: MLX5_PORT_UP);
3219 mutex_unlock(lock: &priv->state_lock);
3220
3221 return err;
3222}
3223
3224int mlx5e_close_locked(struct net_device *netdev)
3225{
3226 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3227
3228 /* May already be CLOSED in case a previous configuration operation
3229 * (e.g RX/TX queue size change) that involves close&open failed.
3230 */
3231 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3232 return 0;
3233
3234 mlx5e_apply_traps(priv, enable: false);
3235 clear_bit(nr: MLX5E_STATE_OPENED, addr: &priv->state);
3236
3237 netif_carrier_off(dev: priv->netdev);
3238 mlx5e_deactivate_priv_channels(priv);
3239 mlx5e_close_channels(chs: &priv->channels);
3240
3241 return 0;
3242}
3243
3244int mlx5e_close(struct net_device *netdev)
3245{
3246 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3247 int err;
3248
3249 if (!netif_device_present(dev: netdev))
3250 return -ENODEV;
3251
3252 mutex_lock(&priv->state_lock);
3253 mlx5e_modify_admin_state(mdev: priv->mdev, state: MLX5_PORT_DOWN);
3254 err = mlx5e_close_locked(netdev);
3255 mutex_unlock(lock: &priv->state_lock);
3256
3257 return err;
3258}
3259
3260static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3261{
3262 mlx5_wq_destroy(wq_ctrl: &rq->wq_ctrl);
3263}
3264
3265static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3266 struct mlx5e_rq *rq,
3267 struct mlx5e_rq_param *param)
3268{
3269 void *rqc = param->rqc;
3270 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3271 int err;
3272
3273 param->wq.db_numa_node = param->wq.buf_numa_node;
3274
3275 err = mlx5_wq_cyc_create(mdev, param: &param->wq, wqc: rqc_wq, wq: &rq->wqe.wq,
3276 wq_ctrl: &rq->wq_ctrl);
3277 if (err)
3278 return err;
3279
3280 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3281 xdp_rxq_info_unused(xdp_rxq: &rq->xdp_rxq);
3282
3283 rq->mdev = mdev;
3284
3285 return 0;
3286}
3287
3288static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3289 struct mlx5e_cq *cq,
3290 struct mlx5e_cq_param *param)
3291{
3292 struct mlx5_core_dev *mdev = priv->mdev;
3293
3294 param->wq.buf_numa_node = dev_to_node(dev: mlx5_core_dma_dev(dev: mdev));
3295 param->wq.db_numa_node = dev_to_node(dev: mlx5_core_dma_dev(dev: mdev));
3296
3297 return mlx5e_alloc_cq_common(priv, param, cq);
3298}
3299
3300int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3301 struct mlx5e_rq *drop_rq)
3302{
3303 struct mlx5_core_dev *mdev = priv->mdev;
3304 struct mlx5e_cq_param cq_param = {};
3305 struct mlx5e_rq_param rq_param = {};
3306 struct mlx5e_cq *cq = &drop_rq->cq;
3307 int err;
3308
3309 mlx5e_build_drop_rq_param(mdev, q_counter: priv->drop_rq_q_counter, param: &rq_param);
3310
3311 err = mlx5e_alloc_drop_cq(priv, cq, param: &cq_param);
3312 if (err)
3313 return err;
3314
3315 err = mlx5e_create_cq(cq, param: &cq_param);
3316 if (err)
3317 goto err_free_cq;
3318
3319 err = mlx5e_alloc_drop_rq(mdev, rq: drop_rq, param: &rq_param);
3320 if (err)
3321 goto err_destroy_cq;
3322
3323 err = mlx5e_create_rq(rq: drop_rq, param: &rq_param);
3324 if (err)
3325 goto err_free_rq;
3326
3327 err = mlx5e_modify_rq_state(rq: drop_rq, curr_state: MLX5_RQC_STATE_RST, next_state: MLX5_RQC_STATE_RDY);
3328 if (err)
3329 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3330
3331 return 0;
3332
3333err_free_rq:
3334 mlx5e_free_drop_rq(rq: drop_rq);
3335
3336err_destroy_cq:
3337 mlx5e_destroy_cq(cq);
3338
3339err_free_cq:
3340 mlx5e_free_cq(cq);
3341
3342 return err;
3343}
3344
3345void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3346{
3347 mlx5e_destroy_rq(rq: drop_rq);
3348 mlx5e_free_drop_rq(rq: drop_rq);
3349 mlx5e_destroy_cq(cq: &drop_rq->cq);
3350 mlx5e_free_cq(cq: &drop_rq->cq);
3351}
3352
3353int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3354{
3355 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3356
3357 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3358
3359 if (MLX5_GET(tisc, tisc, tls_en))
3360 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3361
3362 if (mlx5_lag_is_lacp_owner(dev: mdev))
3363 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3364
3365 return mlx5_core_create_tis(dev: mdev, in, tisn);
3366}
3367
3368void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3369{
3370 mlx5_core_destroy_tis(dev: mdev, tisn);
3371}
3372
3373void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3374{
3375 int tc, i;
3376
3377 for (i = 0; i < mlx5e_get_num_lag_ports(mdev: priv->mdev); i++)
3378 for (tc = 0; tc < priv->profile->max_tc; tc++)
3379 mlx5e_destroy_tis(mdev: priv->mdev, tisn: priv->tisn[i][tc]);
3380}
3381
3382static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3383{
3384 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3385}
3386
3387int mlx5e_create_tises(struct mlx5e_priv *priv)
3388{
3389 int tc, i;
3390 int err;
3391
3392 for (i = 0; i < mlx5e_get_num_lag_ports(mdev: priv->mdev); i++) {
3393 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3394 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3395 void *tisc;
3396
3397 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3398
3399 MLX5_SET(tisc, tisc, prio, tc << 1);
3400
3401 if (mlx5e_lag_should_assign_affinity(mdev: priv->mdev))
3402 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3403
3404 err = mlx5e_create_tis(mdev: priv->mdev, in, tisn: &priv->tisn[i][tc]);
3405 if (err)
3406 goto err_close_tises;
3407 }
3408 }
3409
3410 return 0;
3411
3412err_close_tises:
3413 for (; i >= 0; i--) {
3414 for (tc--; tc >= 0; tc--)
3415 mlx5e_destroy_tis(mdev: priv->mdev, tisn: priv->tisn[i][tc]);
3416 tc = priv->profile->max_tc;
3417 }
3418
3419 return err;
3420}
3421
3422static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3423{
3424 if (priv->mqprio_rl) {
3425 mlx5e_mqprio_rl_cleanup(rl: priv->mqprio_rl);
3426 mlx5e_mqprio_rl_free(rl: priv->mqprio_rl);
3427 priv->mqprio_rl = NULL;
3428 }
3429 mlx5e_accel_cleanup_tx(priv);
3430 mlx5e_destroy_tises(priv);
3431}
3432
3433static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3434{
3435 int err;
3436 int i;
3437
3438 for (i = 0; i < chs->num; i++) {
3439 err = mlx5e_modify_rq_vsd(rq: &chs->c[i]->rq, vsd);
3440 if (err)
3441 return err;
3442 }
3443 if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3444 return mlx5e_modify_rq_vsd(rq: &chs->ptp->rq, vsd);
3445
3446 return 0;
3447}
3448
3449static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3450 int ntc, int nch)
3451{
3452 int tc;
3453
3454 memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3455
3456 /* Map netdev TCs to offset 0.
3457 * We have our own UP to TXQ mapping for DCB mode of QoS
3458 */
3459 for (tc = 0; tc < ntc; tc++) {
3460 tc_to_txq[tc] = (struct netdev_tc_txq) {
3461 .count = nch,
3462 .offset = 0,
3463 };
3464 }
3465}
3466
3467static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3468 struct tc_mqprio_qopt *qopt)
3469{
3470 int tc;
3471
3472 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3473 tc_to_txq[tc] = (struct netdev_tc_txq) {
3474 .count = qopt->count[tc],
3475 .offset = qopt->offset[tc],
3476 };
3477 }
3478}
3479
3480static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3481{
3482 params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3483 params->mqprio.num_tc = num_tc;
3484 mlx5e_mqprio_build_default_tc_to_txq(tc_to_txq: params->mqprio.tc_to_txq, ntc: num_tc,
3485 nch: params->num_channels);
3486}
3487
3488static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params,
3489 struct mlx5e_mqprio_rl *rl)
3490{
3491 int tc;
3492
3493 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3494 u32 hw_id = 0;
3495
3496 if (rl)
3497 mlx5e_mqprio_rl_get_node_hw_id(rl, tc, hw_id: &hw_id);
3498 params->mqprio.channel.hw_id[tc] = hw_id;
3499 }
3500}
3501
3502static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3503 struct tc_mqprio_qopt_offload *mqprio,
3504 struct mlx5e_mqprio_rl *rl)
3505{
3506 int tc;
3507
3508 params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3509 params->mqprio.num_tc = mqprio->qopt.num_tc;
3510
3511 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
3512 params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc];
3513
3514 mlx5e_mqprio_rl_update_params(params, rl);
3515 mlx5e_mqprio_build_tc_to_txq(tc_to_txq: params->mqprio.tc_to_txq, qopt: &mqprio->qopt);
3516}
3517
3518static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3519{
3520 mlx5e_params_mqprio_dcb_set(params, num_tc: 1);
3521}
3522
3523static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3524 struct tc_mqprio_qopt *mqprio)
3525{
3526 struct mlx5e_params new_params;
3527 u8 tc = mqprio->num_tc;
3528 int err;
3529
3530 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3531
3532 if (tc && tc != MLX5E_MAX_NUM_TC)
3533 return -EINVAL;
3534
3535 new_params = priv->channels.params;
3536 mlx5e_params_mqprio_dcb_set(params: &new_params, num_tc: tc ? tc : 1);
3537
3538 err = mlx5e_safe_switch_params(priv, params: &new_params,
3539 preactivate: mlx5e_num_channels_changed_ctx, NULL, reset: true);
3540
3541 if (!err && priv->mqprio_rl) {
3542 mlx5e_mqprio_rl_cleanup(rl: priv->mqprio_rl);
3543 mlx5e_mqprio_rl_free(rl: priv->mqprio_rl);
3544 priv->mqprio_rl = NULL;
3545 }
3546
3547 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3548 mlx5e_get_dcb_num_tc(&priv->channels.params));
3549 return err;
3550}
3551
3552static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3553 struct tc_mqprio_qopt_offload *mqprio)
3554{
3555 struct net_device *netdev = priv->netdev;
3556 struct mlx5e_ptp *ptp_channel;
3557 int agg_count = 0;
3558 int i;
3559
3560 ptp_channel = priv->channels.ptp;
3561 if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3562 netdev_err(dev: netdev,
3563 format: "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3564 return -EINVAL;
3565 }
3566
3567 if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3568 mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3569 return -EINVAL;
3570
3571 for (i = 0; i < mqprio->qopt.num_tc; i++) {
3572 if (!mqprio->qopt.count[i]) {
3573 netdev_err(dev: netdev, format: "Zero size for queue-group (%d) is not supported\n", i);
3574 return -EINVAL;
3575 }
3576 if (mqprio->min_rate[i]) {
3577 netdev_err(dev: netdev, format: "Min tx rate is not supported\n");
3578 return -EINVAL;
3579 }
3580
3581 if (mqprio->max_rate[i]) {
3582 int err;
3583
3584 err = mlx5e_qos_bytes_rate_check(mdev: priv->mdev, nbytes: mqprio->max_rate[i]);
3585 if (err)
3586 return err;
3587 }
3588
3589 if (mqprio->qopt.offset[i] != agg_count) {
3590 netdev_err(dev: netdev, format: "Discontinuous queues config is not supported\n");
3591 return -EINVAL;
3592 }
3593 agg_count += mqprio->qopt.count[i];
3594 }
3595
3596 if (priv->channels.params.num_channels != agg_count) {
3597 netdev_err(dev: netdev, format: "Num of queues (%d) does not match available (%d)\n",
3598 agg_count, priv->channels.params.num_channels);
3599 return -EINVAL;
3600 }
3601
3602 return 0;
3603}
3604
3605static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[])
3606{
3607 int tc;
3608
3609 for (tc = 0; tc < num_tc; tc++)
3610 if (max_rate[tc])
3611 return true;
3612 return false;
3613}
3614
3615static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev,
3616 u8 num_tc, u64 max_rate[])
3617{
3618 struct mlx5e_mqprio_rl *rl;
3619 int err;
3620
3621 if (!mlx5e_mqprio_rate_limit(num_tc, max_rate))
3622 return NULL;
3623
3624 rl = mlx5e_mqprio_rl_alloc();
3625 if (!rl)
3626 return ERR_PTR(error: -ENOMEM);
3627
3628 err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate);
3629 if (err) {
3630 mlx5e_mqprio_rl_free(rl);
3631 return ERR_PTR(error: err);
3632 }
3633
3634 return rl;
3635}
3636
3637static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3638 struct tc_mqprio_qopt_offload *mqprio)
3639{
3640 mlx5e_fp_preactivate preactivate;
3641 struct mlx5e_params new_params;
3642 struct mlx5e_mqprio_rl *rl;
3643 bool nch_changed;
3644 int err;
3645
3646 err = mlx5e_mqprio_channel_validate(priv, mqprio);
3647 if (err)
3648 return err;
3649
3650 rl = mlx5e_mqprio_rl_create(mdev: priv->mdev, num_tc: mqprio->qopt.num_tc, max_rate: mqprio->max_rate);
3651 if (IS_ERR(ptr: rl))
3652 return PTR_ERR(ptr: rl);
3653
3654 new_params = priv->channels.params;
3655 mlx5e_params_mqprio_channel_set(params: &new_params, mqprio, rl);
3656
3657 nch_changed = mlx5e_get_dcb_num_tc(params: &priv->channels.params) > 1;
3658 preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3659 mlx5e_update_netdev_queues_ctx;
3660 err = mlx5e_safe_switch_params(priv, params: &new_params, preactivate, NULL, reset: true);
3661 if (err) {
3662 if (rl) {
3663 mlx5e_mqprio_rl_cleanup(rl);
3664 mlx5e_mqprio_rl_free(rl);
3665 }
3666 return err;
3667 }
3668
3669 if (priv->mqprio_rl) {
3670 mlx5e_mqprio_rl_cleanup(rl: priv->mqprio_rl);
3671 mlx5e_mqprio_rl_free(rl: priv->mqprio_rl);
3672 }
3673 priv->mqprio_rl = rl;
3674
3675 return 0;
3676}
3677
3678static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3679 struct tc_mqprio_qopt_offload *mqprio)
3680{
3681 /* MQPRIO is another toplevel qdisc that can't be attached
3682 * simultaneously with the offloaded HTB.
3683 */
3684 if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq)))
3685 return -EINVAL;
3686
3687 switch (mqprio->mode) {
3688 case TC_MQPRIO_MODE_DCB:
3689 return mlx5e_setup_tc_mqprio_dcb(priv, mqprio: &mqprio->qopt);
3690 case TC_MQPRIO_MODE_CHANNEL:
3691 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3692 default:
3693 return -EOPNOTSUPP;
3694 }
3695}
3696
3697static LIST_HEAD(mlx5e_block_cb_list);
3698
3699static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3700 void *type_data)
3701{
3702 struct mlx5e_priv *priv = netdev_priv(dev);
3703 bool tc_unbind = false;
3704 int err;
3705
3706 if (type == TC_SETUP_BLOCK &&
3707 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3708 tc_unbind = true;
3709
3710 if (!netif_device_present(dev) && !tc_unbind)
3711 return -ENODEV;
3712
3713 switch (type) {
3714 case TC_SETUP_BLOCK: {
3715 struct flow_block_offload *f = type_data;
3716
3717 f->unlocked_driver_cb = true;
3718 return flow_block_cb_setup_simple(f: type_data,
3719 driver_list: &mlx5e_block_cb_list,
3720 cb: mlx5e_setup_tc_block_cb,
3721 cb_ident: priv, cb_priv: priv, ingress_only: true);
3722 }
3723 case TC_SETUP_QDISC_MQPRIO:
3724 mutex_lock(&priv->state_lock);
3725 err = mlx5e_setup_tc_mqprio(priv, mqprio: type_data);
3726 mutex_unlock(lock: &priv->state_lock);
3727 return err;
3728 case TC_SETUP_QDISC_HTB:
3729 mutex_lock(&priv->state_lock);
3730 err = mlx5e_htb_setup_tc(priv, htb: type_data);
3731 mutex_unlock(lock: &priv->state_lock);
3732 return err;
3733 default:
3734 return -EOPNOTSUPP;
3735 }
3736}
3737
3738void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3739{
3740 int i;
3741
3742 for (i = 0; i < priv->stats_nch; i++) {
3743 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3744 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3745 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3746 int j;
3747
3748 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3749 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3750 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3751
3752 for (j = 0; j < priv->max_opened_tc; j++) {
3753 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3754
3755 s->tx_packets += sq_stats->packets;
3756 s->tx_bytes += sq_stats->bytes;
3757 s->tx_dropped += sq_stats->dropped;
3758 }
3759 }
3760 if (priv->tx_ptp_opened) {
3761 for (i = 0; i < priv->max_opened_tc; i++) {
3762 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3763
3764 s->tx_packets += sq_stats->packets;
3765 s->tx_bytes += sq_stats->bytes;
3766 s->tx_dropped += sq_stats->dropped;
3767 }
3768 }
3769 if (priv->rx_ptp_opened) {
3770 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3771
3772 s->rx_packets += rq_stats->packets;
3773 s->rx_bytes += rq_stats->bytes;
3774 s->multicast += rq_stats->mcast_packets;
3775 }
3776}
3777
3778void
3779mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3780{
3781 struct mlx5e_priv *priv = netdev_priv(dev);
3782 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3783
3784 if (!netif_device_present(dev))
3785 return;
3786
3787 /* In switchdev mode, monitor counters doesn't monitor
3788 * rx/tx stats of 802_3. The update stats mechanism
3789 * should keep the 802_3 layout counters updated
3790 */
3791 if (!mlx5e_monitor_counter_supported(priv) ||
3792 mlx5e_is_uplink_rep(priv)) {
3793 /* update HW stats in background for next time */
3794 mlx5e_queue_update_stats(priv);
3795 }
3796
3797 if (mlx5e_is_uplink_rep(priv)) {
3798 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3799
3800 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3801 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3802 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3803 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3804
3805 /* vport multicast also counts packets that are dropped due to steering
3806 * or rx out of buffer
3807 */
3808 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3809 } else {
3810 mlx5e_fold_sw_stats64(priv, s: stats);
3811 }
3812
3813 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3814
3815 stats->rx_length_errors =
3816 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3817 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3818 PPORT_802_3_GET(pstats, a_frame_too_long_errors) +
3819 VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small);
3820 stats->rx_crc_errors =
3821 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3822 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3823 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3824 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3825 stats->rx_frame_errors;
3826 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3827}
3828
3829static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3830{
3831 if (mlx5e_is_uplink_rep(priv))
3832 return; /* no rx mode for uplink rep */
3833
3834 queue_work(wq: priv->wq, work: &priv->set_rx_mode_work);
3835}
3836
3837static void mlx5e_set_rx_mode(struct net_device *dev)
3838{
3839 struct mlx5e_priv *priv = netdev_priv(dev);
3840
3841 mlx5e_nic_set_rx_mode(priv);
3842}
3843
3844static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3845{
3846 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3847 struct sockaddr *saddr = addr;
3848
3849 if (!is_valid_ether_addr(addr: saddr->sa_data))
3850 return -EADDRNOTAVAIL;
3851
3852 netif_addr_lock_bh(dev: netdev);
3853 eth_hw_addr_set(dev: netdev, addr: saddr->sa_data);
3854 netif_addr_unlock_bh(dev: netdev);
3855
3856 mlx5e_nic_set_rx_mode(priv);
3857
3858 return 0;
3859}
3860
3861#define MLX5E_SET_FEATURE(features, feature, enable) \
3862 do { \
3863 if (enable) \
3864 *features |= feature; \
3865 else \
3866 *features &= ~feature; \
3867 } while (0)
3868
3869typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3870
3871static int set_feature_lro(struct net_device *netdev, bool enable)
3872{
3873 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3874 struct mlx5_core_dev *mdev = priv->mdev;
3875 struct mlx5e_params *cur_params;
3876 struct mlx5e_params new_params;
3877 bool reset = true;
3878 int err = 0;
3879
3880 mutex_lock(&priv->state_lock);
3881
3882 cur_params = &priv->channels.params;
3883 new_params = *cur_params;
3884
3885 if (enable)
3886 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3887 else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3888 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3889 else
3890 goto out;
3891
3892 if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3893 new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3894 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3895 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params: cur_params, NULL) ==
3896 mlx5e_rx_mpwqe_is_linear_skb(mdev, params: &new_params, NULL))
3897 reset = false;
3898 }
3899 }
3900
3901 err = mlx5e_safe_switch_params(priv, params: &new_params,
3902 preactivate: mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3903out:
3904 mutex_unlock(lock: &priv->state_lock);
3905 return err;
3906}
3907
3908static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3909{
3910 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3911 struct mlx5e_params new_params;
3912 bool reset = true;
3913 int err = 0;
3914
3915 mutex_lock(&priv->state_lock);
3916 new_params = priv->channels.params;
3917
3918 if (enable) {
3919 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3920 new_params.packet_merge.shampo.match_criteria_type =
3921 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3922 new_params.packet_merge.shampo.alignment_granularity =
3923 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3924 } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3925 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3926 } else {
3927 goto out;
3928 }
3929
3930 err = mlx5e_safe_switch_params(priv, params: &new_params, NULL, NULL, reset);
3931out:
3932 mutex_unlock(lock: &priv->state_lock);
3933 return err;
3934}
3935
3936static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3937{
3938 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3939
3940 if (enable)
3941 mlx5e_enable_cvlan_filter(fs: priv->fs,
3942 promisc: !!(priv->netdev->flags & IFF_PROMISC));
3943 else
3944 mlx5e_disable_cvlan_filter(fs: priv->fs,
3945 promisc: !!(priv->netdev->flags & IFF_PROMISC));
3946
3947 return 0;
3948}
3949
3950static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3951{
3952 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3953 int err = 0;
3954
3955#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3956 int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) :
3957 MLX5_TC_FLAG(NIC_OFFLOAD);
3958 if (!enable && mlx5e_tc_num_filters(priv, flags: tc_flag)) {
3959 netdev_err(dev: netdev,
3960 format: "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3961 return -EINVAL;
3962 }
3963#endif
3964
3965 mutex_lock(&priv->state_lock);
3966 if (!enable && mlx5e_selq_is_htb_enabled(selq: &priv->selq)) {
3967 netdev_err(dev: netdev, format: "Active HTB offload, can't turn hw_tc_offload off\n");
3968 err = -EINVAL;
3969 }
3970 mutex_unlock(lock: &priv->state_lock);
3971
3972 return err;
3973}
3974
3975static int set_feature_rx_all(struct net_device *netdev, bool enable)
3976{
3977 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
3978 struct mlx5_core_dev *mdev = priv->mdev;
3979
3980 return mlx5_set_port_fcs(mdev, enable: !enable);
3981}
3982
3983static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3984{
3985 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3986 bool supported, curr_state;
3987 int err;
3988
3989 if (!MLX5_CAP_GEN(mdev, ports_check))
3990 return 0;
3991
3992 err = mlx5_query_ports_check(mdev, out: in, outlen: sizeof(in));
3993 if (err)
3994 return err;
3995
3996 supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3997 curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3998
3999 if (!supported || enable == curr_state)
4000 return 0;
4001
4002 MLX5_SET(pcmr_reg, in, local_port, 1);
4003 MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
4004
4005 return mlx5_set_ports_check(mdev, in, inlen: sizeof(in));
4006}
4007
4008static int mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv *priv, void *ctx)
4009{
4010 struct mlx5_core_dev *mdev = priv->mdev;
4011 bool enable = *(bool *)ctx;
4012
4013 return mlx5e_set_rx_port_ts(mdev, enable);
4014}
4015
4016static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
4017{
4018 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4019 struct mlx5e_channels *chs = &priv->channels;
4020 struct mlx5e_params new_params;
4021 int err;
4022 bool rx_ts_over_crc = !enable;
4023
4024 mutex_lock(&priv->state_lock);
4025
4026 new_params = chs->params;
4027 new_params.scatter_fcs_en = enable;
4028 err = mlx5e_safe_switch_params(priv, params: &new_params, preactivate: mlx5e_set_rx_port_ts_wrap,
4029 context: &rx_ts_over_crc, reset: true);
4030 mutex_unlock(lock: &priv->state_lock);
4031 return err;
4032}
4033
4034static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
4035{
4036 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4037 int err = 0;
4038
4039 mutex_lock(&priv->state_lock);
4040
4041 mlx5e_fs_set_vlan_strip_disable(fs: priv->fs, vlan_strip_disable: !enable);
4042 priv->channels.params.vlan_strip_disable = !enable;
4043
4044 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4045 goto unlock;
4046
4047 err = mlx5e_modify_channels_vsd(chs: &priv->channels, vsd: !enable);
4048 if (err) {
4049 mlx5e_fs_set_vlan_strip_disable(fs: priv->fs, vlan_strip_disable: enable);
4050 priv->channels.params.vlan_strip_disable = enable;
4051 }
4052unlock:
4053 mutex_unlock(lock: &priv->state_lock);
4054
4055 return err;
4056}
4057
4058int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
4059{
4060 struct mlx5e_priv *priv = netdev_priv(dev);
4061 struct mlx5e_flow_steering *fs = priv->fs;
4062
4063 if (mlx5e_is_uplink_rep(priv))
4064 return 0; /* no vlan table for uplink rep */
4065
4066 return mlx5e_fs_vlan_rx_add_vid(fs, netdev: dev, proto, vid);
4067}
4068
4069int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
4070{
4071 struct mlx5e_priv *priv = netdev_priv(dev);
4072 struct mlx5e_flow_steering *fs = priv->fs;
4073
4074 if (mlx5e_is_uplink_rep(priv))
4075 return 0; /* no vlan table for uplink rep */
4076
4077 return mlx5e_fs_vlan_rx_kill_vid(fs, netdev: dev, proto, vid);
4078}
4079
4080#ifdef CONFIG_MLX5_EN_ARFS
4081static int set_feature_arfs(struct net_device *netdev, bool enable)
4082{
4083 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4084 int err;
4085
4086 if (enable)
4087 err = mlx5e_arfs_enable(fs: priv->fs);
4088 else
4089 err = mlx5e_arfs_disable(fs: priv->fs);
4090
4091 return err;
4092}
4093#endif
4094
4095static int mlx5e_handle_feature(struct net_device *netdev,
4096 netdev_features_t *features,
4097 netdev_features_t feature,
4098 mlx5e_feature_handler feature_handler)
4099{
4100 netdev_features_t changes = *features ^ netdev->features;
4101 bool enable = !!(*features & feature);
4102 int err;
4103
4104 if (!(changes & feature))
4105 return 0;
4106
4107 err = feature_handler(netdev, enable);
4108 if (err) {
4109 MLX5E_SET_FEATURE(features, feature, !enable);
4110 netdev_err(dev: netdev, format: "%s feature %pNF failed, err %d\n",
4111 enable ? "Enable" : "Disable", &feature, err);
4112 return err;
4113 }
4114
4115 return 0;
4116}
4117
4118void mlx5e_set_xdp_feature(struct net_device *netdev)
4119{
4120 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4121 struct mlx5e_params *params = &priv->channels.params;
4122 xdp_features_t val;
4123
4124 if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4125 xdp_clear_features_flag(dev: netdev);
4126 return;
4127 }
4128
4129 val = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
4130 NETDEV_XDP_ACT_XSK_ZEROCOPY |
4131 NETDEV_XDP_ACT_RX_SG |
4132 NETDEV_XDP_ACT_NDO_XMIT |
4133 NETDEV_XDP_ACT_NDO_XMIT_SG;
4134 xdp_set_features_flag(dev: netdev, val);
4135}
4136
4137int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
4138{
4139 netdev_features_t oper_features = features;
4140 int err = 0;
4141
4142#define MLX5E_HANDLE_FEATURE(feature, handler) \
4143 mlx5e_handle_feature(netdev, &oper_features, feature, handler)
4144
4145 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
4146 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
4147 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
4148 set_feature_cvlan_filter);
4149 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
4150 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
4151 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
4152 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
4153#ifdef CONFIG_MLX5_EN_ARFS
4154 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
4155#endif
4156 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
4157
4158 if (err) {
4159 netdev->features = oper_features;
4160 return -EINVAL;
4161 }
4162
4163 /* update XDP supported features */
4164 mlx5e_set_xdp_feature(netdev);
4165
4166 return 0;
4167}
4168
4169static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
4170 netdev_features_t features)
4171{
4172 features &= ~NETIF_F_HW_TLS_RX;
4173 if (netdev->features & NETIF_F_HW_TLS_RX)
4174 netdev_warn(dev: netdev, format: "Disabling hw_tls_rx, not supported in switchdev mode\n");
4175
4176 features &= ~NETIF_F_HW_TLS_TX;
4177 if (netdev->features & NETIF_F_HW_TLS_TX)
4178 netdev_warn(dev: netdev, format: "Disabling hw_tls_tx, not supported in switchdev mode\n");
4179
4180 features &= ~NETIF_F_NTUPLE;
4181 if (netdev->features & NETIF_F_NTUPLE)
4182 netdev_warn(dev: netdev, format: "Disabling ntuple, not supported in switchdev mode\n");
4183
4184 features &= ~NETIF_F_GRO_HW;
4185 if (netdev->features & NETIF_F_GRO_HW)
4186 netdev_warn(dev: netdev, format: "Disabling HW_GRO, not supported in switchdev mode\n");
4187
4188 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4189 if (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
4190 netdev_warn(dev: netdev, format: "Disabling HW_VLAN CTAG FILTERING, not supported in switchdev mode\n");
4191
4192 return features;
4193}
4194
4195static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
4196 netdev_features_t features)
4197{
4198 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4199 struct mlx5e_vlan_table *vlan;
4200 struct mlx5e_params *params;
4201
4202 if (!netif_device_present(dev: netdev))
4203 return features;
4204
4205 vlan = mlx5e_fs_get_vlan(fs: priv->fs);
4206 mutex_lock(&priv->state_lock);
4207 params = &priv->channels.params;
4208 if (!vlan ||
4209 !bitmap_empty(src: mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) {
4210 /* HW strips the outer C-tag header, this is a problem
4211 * for S-tag traffic.
4212 */
4213 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
4214 if (!params->vlan_strip_disable)
4215 netdev_warn(dev: netdev, format: "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
4216 }
4217
4218 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
4219 if (features & NETIF_F_LRO) {
4220 netdev_warn(dev: netdev, format: "Disabling LRO, not supported in legacy RQ\n");
4221 features &= ~NETIF_F_LRO;
4222 }
4223 if (features & NETIF_F_GRO_HW) {
4224 netdev_warn(dev: netdev, format: "Disabling HW-GRO, not supported in legacy RQ\n");
4225 features &= ~NETIF_F_GRO_HW;
4226 }
4227 }
4228
4229 if (params->xdp_prog) {
4230 if (features & NETIF_F_LRO) {
4231 netdev_warn(dev: netdev, format: "LRO is incompatible with XDP\n");
4232 features &= ~NETIF_F_LRO;
4233 }
4234 if (features & NETIF_F_GRO_HW) {
4235 netdev_warn(dev: netdev, format: "HW GRO is incompatible with XDP\n");
4236 features &= ~NETIF_F_GRO_HW;
4237 }
4238 }
4239
4240 if (priv->xsk.refcnt) {
4241 if (features & NETIF_F_LRO) {
4242 netdev_warn(dev: netdev, format: "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
4243 priv->xsk.refcnt);
4244 features &= ~NETIF_F_LRO;
4245 }
4246 if (features & NETIF_F_GRO_HW) {
4247 netdev_warn(dev: netdev, format: "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
4248 priv->xsk.refcnt);
4249 features &= ~NETIF_F_GRO_HW;
4250 }
4251 }
4252
4253 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
4254 features &= ~NETIF_F_RXHASH;
4255 if (netdev->features & NETIF_F_RXHASH)
4256 netdev_warn(dev: netdev, format: "Disabling rxhash, not supported when CQE compress is active\n");
4257
4258 if (features & NETIF_F_GRO_HW) {
4259 netdev_warn(dev: netdev, format: "Disabling HW-GRO, not supported when CQE compress is active\n");
4260 features &= ~NETIF_F_GRO_HW;
4261 }
4262 }
4263
4264 if (mlx5e_is_uplink_rep(priv)) {
4265 features = mlx5e_fix_uplink_rep_features(netdev, features);
4266 features |= NETIF_F_NETNS_LOCAL;
4267 } else {
4268 features &= ~NETIF_F_NETNS_LOCAL;
4269 }
4270
4271 mutex_unlock(lock: &priv->state_lock);
4272
4273 return features;
4274}
4275
4276static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
4277 struct mlx5e_channels *chs,
4278 struct mlx5e_params *new_params,
4279 struct mlx5_core_dev *mdev)
4280{
4281 u16 ix;
4282
4283 for (ix = 0; ix < chs->params.num_channels; ix++) {
4284 struct xsk_buff_pool *xsk_pool =
4285 mlx5e_xsk_get_pool(params: &chs->params, xsk: chs->params.xsk, ix);
4286 struct mlx5e_xsk_param xsk;
4287 int max_xdp_mtu;
4288
4289 if (!xsk_pool)
4290 continue;
4291
4292 mlx5e_build_xsk_param(pool: xsk_pool, xsk: &xsk);
4293 max_xdp_mtu = mlx5e_xdp_max_mtu(params: new_params, xsk: &xsk);
4294
4295 /* Validate XSK params and XDP MTU in advance */
4296 if (!mlx5e_validate_xsk_param(params: new_params, xsk: &xsk, mdev) ||
4297 new_params->sw_mtu > max_xdp_mtu) {
4298 u32 hr = mlx5e_get_linear_rq_headroom(params: new_params, xsk: &xsk);
4299 int max_mtu_frame, max_mtu_page, max_mtu;
4300
4301 /* Two criteria must be met:
4302 * 1. HW MTU + all headrooms <= XSK frame size.
4303 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
4304 */
4305 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
4306 max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0));
4307 max_mtu = min3(max_mtu_frame, max_mtu_page, max_xdp_mtu);
4308
4309 netdev_err(dev: netdev, format: "MTU %d is too big for an XSK running on channel %u or its redirection XDP program. Try MTU <= %d\n",
4310 new_params->sw_mtu, ix, max_mtu);
4311 return false;
4312 }
4313 }
4314
4315 return true;
4316}
4317
4318static bool mlx5e_params_validate_xdp(struct net_device *netdev,
4319 struct mlx5_core_dev *mdev,
4320 struct mlx5e_params *params)
4321{
4322 bool is_linear;
4323
4324 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4325 * the XDP program.
4326 */
4327 is_linear = params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC ?
4328 mlx5e_rx_is_linear_skb(mdev, params, NULL) :
4329 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL);
4330
4331 if (!is_linear) {
4332 if (!params->xdp_prog->aux->xdp_has_frags) {
4333 netdev_warn(dev: netdev, format: "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
4334 params->sw_mtu,
4335 mlx5e_xdp_max_mtu(params, NULL));
4336 return false;
4337 }
4338 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4339 !mlx5e_verify_params_rx_mpwqe_strides(mdev, params, NULL)) {
4340 netdev_warn(dev: netdev, format: "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
4341 params->sw_mtu,
4342 mlx5e_xdp_max_mtu(params, NULL));
4343 return false;
4344 }
4345 }
4346
4347 return true;
4348}
4349
4350int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4351 mlx5e_fp_preactivate preactivate)
4352{
4353 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4354 struct mlx5e_params new_params;
4355 struct mlx5e_params *params;
4356 bool reset = true;
4357 int err = 0;
4358
4359 mutex_lock(&priv->state_lock);
4360
4361 params = &priv->channels.params;
4362
4363 new_params = *params;
4364 new_params.sw_mtu = new_mtu;
4365 err = mlx5e_validate_params(mdev: priv->mdev, params: &new_params);
4366 if (err)
4367 goto out;
4368
4369 if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, mdev: priv->mdev,
4370 params: &new_params)) {
4371 err = -EINVAL;
4372 goto out;
4373 }
4374
4375 if (priv->xsk.refcnt &&
4376 !mlx5e_xsk_validate_mtu(netdev, chs: &priv->channels,
4377 new_params: &new_params, mdev: priv->mdev)) {
4378 err = -EINVAL;
4379 goto out;
4380 }
4381
4382 if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4383 reset = false;
4384
4385 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4386 params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) {
4387 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(mdev: priv->mdev, params, NULL);
4388 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(mdev: priv->mdev,
4389 params: &new_params, NULL);
4390 u8 sz_old = mlx5e_mpwqe_get_log_rq_size(mdev: priv->mdev, params, NULL);
4391 u8 sz_new = mlx5e_mpwqe_get_log_rq_size(mdev: priv->mdev, params: &new_params, NULL);
4392
4393 /* Always reset in linear mode - hw_mtu is used in data path.
4394 * Check that the mode was non-linear and didn't change.
4395 * If XSK is active, XSK RQs are linear.
4396 * Reset if the RQ size changed, even if it's non-linear.
4397 */
4398 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4399 sz_old == sz_new)
4400 reset = false;
4401 }
4402
4403 err = mlx5e_safe_switch_params(priv, params: &new_params, preactivate, NULL, reset);
4404
4405out:
4406 netdev->mtu = params->sw_mtu;
4407 mutex_unlock(lock: &priv->state_lock);
4408 return err;
4409}
4410
4411static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4412{
4413 return mlx5e_change_mtu(netdev, new_mtu, preactivate: mlx5e_set_dev_port_mtu_ctx);
4414}
4415
4416int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4417{
4418 bool set = *(bool *)ctx;
4419
4420 return mlx5e_ptp_rx_manage_fs(priv, set);
4421}
4422
4423static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4424{
4425 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4426 int err;
4427
4428 if (!rx_filter)
4429 /* Reset CQE compression to Admin default */
4430 return mlx5e_modify_rx_cqe_compression_locked(priv, val: rx_cqe_compress_def, rx_filter: false);
4431
4432 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4433 return 0;
4434
4435 /* Disable CQE compression */
4436 netdev_warn(dev: priv->netdev, format: "Disabling RX cqe compression\n");
4437 err = mlx5e_modify_rx_cqe_compression_locked(priv, val: false, rx_filter: true);
4438 if (err)
4439 netdev_err(dev: priv->netdev, format: "Failed disabling cqe compression err=%d\n", err);
4440
4441 return err;
4442}
4443
4444static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4445{
4446 struct mlx5e_params new_params;
4447
4448 if (ptp_rx == priv->channels.params.ptp_rx)
4449 return 0;
4450
4451 new_params = priv->channels.params;
4452 new_params.ptp_rx = ptp_rx;
4453 return mlx5e_safe_switch_params(priv, params: &new_params, preactivate: mlx5e_ptp_rx_manage_fs_ctx,
4454 context: &new_params.ptp_rx, reset: true);
4455}
4456
4457int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4458{
4459 struct hwtstamp_config config;
4460 bool rx_cqe_compress_def;
4461 bool ptp_rx;
4462 int err;
4463
4464 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4465 (mlx5_clock_get_ptp_index(mdev: priv->mdev) == -1))
4466 return -EOPNOTSUPP;
4467
4468 if (copy_from_user(to: &config, from: ifr->ifr_data, n: sizeof(config)))
4469 return -EFAULT;
4470
4471 /* TX HW timestamp */
4472 switch (config.tx_type) {
4473 case HWTSTAMP_TX_OFF:
4474 case HWTSTAMP_TX_ON:
4475 break;
4476 default:
4477 return -ERANGE;
4478 }
4479
4480 mutex_lock(&priv->state_lock);
4481 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4482
4483 /* RX HW timestamp */
4484 switch (config.rx_filter) {
4485 case HWTSTAMP_FILTER_NONE:
4486 ptp_rx = false;
4487 break;
4488 case HWTSTAMP_FILTER_ALL:
4489 case HWTSTAMP_FILTER_SOME:
4490 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4491 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4492 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4493 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4494 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4495 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4496 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4497 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4498 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4499 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4500 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4501 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4502 case HWTSTAMP_FILTER_NTP_ALL:
4503 config.rx_filter = HWTSTAMP_FILTER_ALL;
4504 /* ptp_rx is set if both HW TS is set and CQE
4505 * compression is set
4506 */
4507 ptp_rx = rx_cqe_compress_def;
4508 break;
4509 default:
4510 err = -ERANGE;
4511 goto err_unlock;
4512 }
4513
4514 if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4515 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4516 rx_filter: config.rx_filter != HWTSTAMP_FILTER_NONE);
4517 else
4518 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4519 if (err)
4520 goto err_unlock;
4521
4522 memcpy(&priv->tstamp, &config, sizeof(config));
4523 mutex_unlock(lock: &priv->state_lock);
4524
4525 /* might need to fix some features */
4526 netdev_update_features(dev: priv->netdev);
4527
4528 return copy_to_user(to: ifr->ifr_data, from: &config,
4529 n: sizeof(config)) ? -EFAULT : 0;
4530err_unlock:
4531 mutex_unlock(lock: &priv->state_lock);
4532 return err;
4533}
4534
4535int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4536{
4537 struct hwtstamp_config *cfg = &priv->tstamp;
4538
4539 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4540 return -EOPNOTSUPP;
4541
4542 return copy_to_user(to: ifr->ifr_data, from: cfg, n: sizeof(*cfg)) ? -EFAULT : 0;
4543}
4544
4545static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4546{
4547 struct mlx5e_priv *priv = netdev_priv(dev);
4548
4549 switch (cmd) {
4550 case SIOCSHWTSTAMP:
4551 return mlx5e_hwstamp_set(priv, ifr);
4552 case SIOCGHWTSTAMP:
4553 return mlx5e_hwstamp_get(priv, ifr);
4554 default:
4555 return -EOPNOTSUPP;
4556 }
4557}
4558
4559#ifdef CONFIG_MLX5_ESWITCH
4560int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4561{
4562 struct mlx5e_priv *priv = netdev_priv(dev);
4563 struct mlx5_core_dev *mdev = priv->mdev;
4564
4565 return mlx5_eswitch_set_vport_mac(esw: mdev->priv.eswitch, vport: vf + 1, mac);
4566}
4567
4568static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4569 __be16 vlan_proto)
4570{
4571 struct mlx5e_priv *priv = netdev_priv(dev);
4572 struct mlx5_core_dev *mdev = priv->mdev;
4573
4574 if (vlan_proto != htons(ETH_P_8021Q))
4575 return -EPROTONOSUPPORT;
4576
4577 return mlx5_eswitch_set_vport_vlan(esw: mdev->priv.eswitch, vport: vf + 1,
4578 vlan, qos);
4579}
4580
4581static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4582{
4583 struct mlx5e_priv *priv = netdev_priv(dev);
4584 struct mlx5_core_dev *mdev = priv->mdev;
4585
4586 return mlx5_eswitch_set_vport_spoofchk(esw: mdev->priv.eswitch, vport: vf + 1, spoofchk: setting);
4587}
4588
4589static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4590{
4591 struct mlx5e_priv *priv = netdev_priv(dev);
4592 struct mlx5_core_dev *mdev = priv->mdev;
4593
4594 return mlx5_eswitch_set_vport_trust(esw: mdev->priv.eswitch, vport_num: vf + 1, setting);
4595}
4596
4597int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4598 int max_tx_rate)
4599{
4600 struct mlx5e_priv *priv = netdev_priv(dev);
4601 struct mlx5_core_dev *mdev = priv->mdev;
4602
4603 return mlx5_eswitch_set_vport_rate(esw: mdev->priv.eswitch, vport: vf + 1,
4604 max_rate: max_tx_rate, min_rate: min_tx_rate);
4605}
4606
4607static int mlx5_vport_link2ifla(u8 esw_link)
4608{
4609 switch (esw_link) {
4610 case MLX5_VPORT_ADMIN_STATE_DOWN:
4611 return IFLA_VF_LINK_STATE_DISABLE;
4612 case MLX5_VPORT_ADMIN_STATE_UP:
4613 return IFLA_VF_LINK_STATE_ENABLE;
4614 }
4615 return IFLA_VF_LINK_STATE_AUTO;
4616}
4617
4618static int mlx5_ifla_link2vport(u8 ifla_link)
4619{
4620 switch (ifla_link) {
4621 case IFLA_VF_LINK_STATE_DISABLE:
4622 return MLX5_VPORT_ADMIN_STATE_DOWN;
4623 case IFLA_VF_LINK_STATE_ENABLE:
4624 return MLX5_VPORT_ADMIN_STATE_UP;
4625 }
4626 return MLX5_VPORT_ADMIN_STATE_AUTO;
4627}
4628
4629static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4630 int link_state)
4631{
4632 struct mlx5e_priv *priv = netdev_priv(dev);
4633 struct mlx5_core_dev *mdev = priv->mdev;
4634
4635 if (mlx5e_is_uplink_rep(priv))
4636 return -EOPNOTSUPP;
4637
4638 return mlx5_eswitch_set_vport_state(esw: mdev->priv.eswitch, vport: vf + 1,
4639 link_state: mlx5_ifla_link2vport(ifla_link: link_state));
4640}
4641
4642int mlx5e_get_vf_config(struct net_device *dev,
4643 int vf, struct ifla_vf_info *ivi)
4644{
4645 struct mlx5e_priv *priv = netdev_priv(dev);
4646 struct mlx5_core_dev *mdev = priv->mdev;
4647 int err;
4648
4649 if (!netif_device_present(dev))
4650 return -EOPNOTSUPP;
4651
4652 err = mlx5_eswitch_get_vport_config(esw: mdev->priv.eswitch, vport: vf + 1, ivi);
4653 if (err)
4654 return err;
4655 ivi->linkstate = mlx5_vport_link2ifla(esw_link: ivi->linkstate);
4656 return 0;
4657}
4658
4659int mlx5e_get_vf_stats(struct net_device *dev,
4660 int vf, struct ifla_vf_stats *vf_stats)
4661{
4662 struct mlx5e_priv *priv = netdev_priv(dev);
4663 struct mlx5_core_dev *mdev = priv->mdev;
4664
4665 return mlx5_eswitch_get_vport_stats(esw: mdev->priv.eswitch, vport: vf + 1,
4666 vf_stats);
4667}
4668
4669static bool
4670mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4671{
4672 struct mlx5e_priv *priv = netdev_priv(dev);
4673
4674 if (!netif_device_present(dev))
4675 return false;
4676
4677 if (!mlx5e_is_uplink_rep(priv))
4678 return false;
4679
4680 return mlx5e_rep_has_offload_stats(dev, attr_id);
4681}
4682
4683static int
4684mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4685 void *sp)
4686{
4687 struct mlx5e_priv *priv = netdev_priv(dev);
4688
4689 if (!mlx5e_is_uplink_rep(priv))
4690 return -EOPNOTSUPP;
4691
4692 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4693}
4694#endif
4695
4696static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4697{
4698 switch (proto_type) {
4699 case IPPROTO_GRE:
4700 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4701 case IPPROTO_IPIP:
4702 case IPPROTO_IPV6:
4703 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4704 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4705 default:
4706 return false;
4707 }
4708}
4709
4710static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4711 struct sk_buff *skb)
4712{
4713 switch (skb->inner_protocol) {
4714 case htons(ETH_P_IP):
4715 case htons(ETH_P_IPV6):
4716 case htons(ETH_P_TEB):
4717 return true;
4718 case htons(ETH_P_MPLS_UC):
4719 case htons(ETH_P_MPLS_MC):
4720 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4721 }
4722 return false;
4723}
4724
4725static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4726 struct sk_buff *skb,
4727 netdev_features_t features)
4728{
4729 unsigned int offset = 0;
4730 struct udphdr *udph;
4731 u8 proto;
4732 u16 port;
4733
4734 switch (vlan_get_protocol(skb)) {
4735 case htons(ETH_P_IP):
4736 proto = ip_hdr(skb)->protocol;
4737 break;
4738 case htons(ETH_P_IPV6):
4739 proto = ipv6_find_hdr(skb, offset: &offset, target: -1, NULL, NULL);
4740 break;
4741 default:
4742 goto out;
4743 }
4744
4745 switch (proto) {
4746 case IPPROTO_GRE:
4747 if (mlx5e_gre_tunnel_inner_proto_offload_supported(mdev: priv->mdev, skb))
4748 return features;
4749 break;
4750 case IPPROTO_IPIP:
4751 case IPPROTO_IPV6:
4752 if (mlx5e_tunnel_proto_supported_tx(mdev: priv->mdev, IPPROTO_IPIP))
4753 return features;
4754 break;
4755 case IPPROTO_UDP:
4756 udph = udp_hdr(skb);
4757 port = be16_to_cpu(udph->dest);
4758
4759 /* Verify if UDP port is being offloaded by HW */
4760 if (mlx5_vxlan_lookup_port(vxlan: priv->mdev->vxlan, port))
4761 return features;
4762
4763#if IS_ENABLED(CONFIG_GENEVE)
4764 /* Support Geneve offload for default UDP port */
4765 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(mdev: priv->mdev))
4766 return features;
4767#endif
4768 break;
4769#ifdef CONFIG_MLX5_EN_IPSEC
4770 case IPPROTO_ESP:
4771 return mlx5e_ipsec_feature_check(skb, features);
4772#endif
4773 }
4774
4775out:
4776 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4777 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4778}
4779
4780netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4781 struct net_device *netdev,
4782 netdev_features_t features)
4783{
4784 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4785
4786 features = vlan_features_check(skb, features);
4787 features = vxlan_features_check(skb, features);
4788
4789 /* Validate if the tunneled packet is being offloaded by HW */
4790 if (skb->encapsulation &&
4791 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4792 return mlx5e_tunnel_features_check(priv, skb, features);
4793
4794 return features;
4795}
4796
4797static void mlx5e_tx_timeout_work(struct work_struct *work)
4798{
4799 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4800 tx_timeout_work);
4801 struct net_device *netdev = priv->netdev;
4802 int i;
4803
4804 rtnl_lock();
4805 mutex_lock(&priv->state_lock);
4806
4807 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4808 goto unlock;
4809
4810 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4811 struct netdev_queue *dev_queue =
4812 netdev_get_tx_queue(dev: netdev, index: i);
4813 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4814
4815 if (!netif_xmit_stopped(dev_queue))
4816 continue;
4817
4818 if (mlx5e_reporter_tx_timeout(sq))
4819 /* break if tried to reopened channels */
4820 break;
4821 }
4822
4823unlock:
4824 mutex_unlock(lock: &priv->state_lock);
4825 rtnl_unlock();
4826}
4827
4828static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4829{
4830 struct mlx5e_priv *priv = netdev_priv(dev);
4831
4832 netdev_err(dev, format: "TX timeout detected\n");
4833 queue_work(wq: priv->wq, work: &priv->tx_timeout_work);
4834}
4835
4836static int mlx5e_xdp_allowed(struct net_device *netdev, struct mlx5_core_dev *mdev,
4837 struct mlx5e_params *params)
4838{
4839 if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4840 netdev_warn(dev: netdev, format: "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4841 return -EINVAL;
4842 }
4843
4844 if (!mlx5e_params_validate_xdp(netdev, mdev, params))
4845 return -EINVAL;
4846
4847 return 0;
4848}
4849
4850static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4851{
4852 struct bpf_prog *old_prog;
4853
4854 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4855 lockdep_is_held(&rq->priv->state_lock));
4856 if (old_prog)
4857 bpf_prog_put(prog: old_prog);
4858}
4859
4860static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4861{
4862 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
4863 struct mlx5e_params new_params;
4864 struct bpf_prog *old_prog;
4865 int err = 0;
4866 bool reset;
4867 int i;
4868
4869 mutex_lock(&priv->state_lock);
4870
4871 new_params = priv->channels.params;
4872 new_params.xdp_prog = prog;
4873
4874 if (prog) {
4875 err = mlx5e_xdp_allowed(netdev, mdev: priv->mdev, params: &new_params);
4876 if (err)
4877 goto unlock;
4878 }
4879
4880 /* no need for full reset when exchanging programs */
4881 reset = (!priv->channels.params.xdp_prog || !prog);
4882
4883 old_prog = priv->channels.params.xdp_prog;
4884
4885 err = mlx5e_safe_switch_params(priv, params: &new_params, NULL, NULL, reset);
4886 if (err)
4887 goto unlock;
4888
4889 if (old_prog)
4890 bpf_prog_put(prog: old_prog);
4891
4892 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4893 goto unlock;
4894
4895 /* exchanging programs w/o reset, we update ref counts on behalf
4896 * of the channels RQs here.
4897 */
4898 bpf_prog_add(prog, i: priv->channels.num);
4899 for (i = 0; i < priv->channels.num; i++) {
4900 struct mlx5e_channel *c = priv->channels.c[i];
4901
4902 mlx5e_rq_replace_xdp_prog(rq: &c->rq, prog);
4903 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4904 bpf_prog_inc(prog);
4905 mlx5e_rq_replace_xdp_prog(rq: &c->xskrq, prog);
4906 }
4907 }
4908
4909unlock:
4910 mutex_unlock(lock: &priv->state_lock);
4911
4912 /* Need to fix some features. */
4913 if (!err)
4914 netdev_update_features(dev: netdev);
4915
4916 return err;
4917}
4918
4919static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4920{
4921 switch (xdp->command) {
4922 case XDP_SETUP_PROG:
4923 return mlx5e_xdp_set(netdev: dev, prog: xdp->prog);
4924 case XDP_SETUP_XSK_POOL:
4925 return mlx5e_xsk_setup_pool(dev, pool: xdp->xsk.pool,
4926 qid: xdp->xsk.queue_id);
4927 default:
4928 return -EINVAL;
4929 }
4930}
4931
4932#ifdef CONFIG_MLX5_ESWITCH
4933static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4934 struct net_device *dev, u32 filter_mask,
4935 int nlflags)
4936{
4937 struct mlx5e_priv *priv = netdev_priv(dev);
4938 struct mlx5_core_dev *mdev = priv->mdev;
4939 u8 mode, setting;
4940 int err;
4941
4942 err = mlx5_eswitch_get_vepa(esw: mdev->priv.eswitch, setting: &setting);
4943 if (err)
4944 return err;
4945 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4946 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4947 mode,
4948 flags: 0, mask: 0, nlflags, filter_mask, NULL);
4949}
4950
4951static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4952 u16 flags, struct netlink_ext_ack *extack)
4953{
4954 struct mlx5e_priv *priv = netdev_priv(dev);
4955 struct mlx5_core_dev *mdev = priv->mdev;
4956 struct nlattr *attr, *br_spec;
4957 u16 mode = BRIDGE_MODE_UNDEF;
4958 u8 setting;
4959 int rem;
4960
4961 br_spec = nlmsg_find_attr(nlh, hdrlen: sizeof(struct ifinfomsg), attrtype: IFLA_AF_SPEC);
4962 if (!br_spec)
4963 return -EINVAL;
4964
4965 nla_for_each_nested(attr, br_spec, rem) {
4966 if (nla_type(nla: attr) != IFLA_BRIDGE_MODE)
4967 continue;
4968
4969 mode = nla_get_u16(nla: attr);
4970 if (mode > BRIDGE_MODE_VEPA)
4971 return -EINVAL;
4972
4973 break;
4974 }
4975
4976 if (mode == BRIDGE_MODE_UNDEF)
4977 return -EINVAL;
4978
4979 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4980 return mlx5_eswitch_set_vepa(esw: mdev->priv.eswitch, setting);
4981}
4982#endif
4983
4984const struct net_device_ops mlx5e_netdev_ops = {
4985 .ndo_open = mlx5e_open,
4986 .ndo_stop = mlx5e_close,
4987 .ndo_start_xmit = mlx5e_xmit,
4988 .ndo_setup_tc = mlx5e_setup_tc,
4989 .ndo_select_queue = mlx5e_select_queue,
4990 .ndo_get_stats64 = mlx5e_get_stats,
4991 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4992 .ndo_set_mac_address = mlx5e_set_mac,
4993 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4994 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4995 .ndo_set_features = mlx5e_set_features,
4996 .ndo_fix_features = mlx5e_fix_features,
4997 .ndo_change_mtu = mlx5e_change_nic_mtu,
4998 .ndo_eth_ioctl = mlx5e_ioctl,
4999 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
5000 .ndo_features_check = mlx5e_features_check,
5001 .ndo_tx_timeout = mlx5e_tx_timeout,
5002 .ndo_bpf = mlx5e_xdp,
5003 .ndo_xdp_xmit = mlx5e_xdp_xmit,
5004 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
5005#ifdef CONFIG_MLX5_EN_ARFS
5006 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
5007#endif
5008#ifdef CONFIG_MLX5_ESWITCH
5009 .ndo_bridge_setlink = mlx5e_bridge_setlink,
5010 .ndo_bridge_getlink = mlx5e_bridge_getlink,
5011
5012 /* SRIOV E-Switch NDOs */
5013 .ndo_set_vf_mac = mlx5e_set_vf_mac,
5014 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
5015 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
5016 .ndo_set_vf_trust = mlx5e_set_vf_trust,
5017 .ndo_set_vf_rate = mlx5e_set_vf_rate,
5018 .ndo_get_vf_config = mlx5e_get_vf_config,
5019 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
5020 .ndo_get_vf_stats = mlx5e_get_vf_stats,
5021 .ndo_has_offload_stats = mlx5e_has_offload_stats,
5022 .ndo_get_offload_stats = mlx5e_get_offload_stats,
5023#endif
5024};
5025
5026static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
5027{
5028 int i;
5029
5030 /* The supported periods are organized in ascending order */
5031 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
5032 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
5033 break;
5034
5035 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
5036}
5037
5038void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
5039{
5040 struct mlx5e_params *params = &priv->channels.params;
5041 struct mlx5_core_dev *mdev = priv->mdev;
5042 u8 rx_cq_period_mode;
5043
5044 params->sw_mtu = mtu;
5045 params->hard_mtu = MLX5E_ETH_HARD_MTU;
5046 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
5047 priv->max_nch);
5048 mlx5e_params_mqprio_reset(params);
5049
5050 /* SQ */
5051 params->log_sq_size = is_kdump_kernel() ?
5052 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
5053 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
5054 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5055
5056 /* XDP SQ */
5057 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5058
5059 /* set CQE compression */
5060 params->rx_cqe_compress_def = false;
5061 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
5062 MLX5_CAP_GEN(mdev, vport_group_manager))
5063 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
5064
5065 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
5066 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
5067
5068 /* RQ */
5069 mlx5e_build_rq_params(mdev, params);
5070
5071 params->terminate_lkey_be = mlx5_core_get_terminate_scatter_list_mkey(dev: mdev);
5072
5073 params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
5074
5075 /* CQ moderation params */
5076 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
5077 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
5078 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
5079 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5080 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5081 mlx5e_set_rx_cq_mode_params(params, cq_period_mode: rx_cq_period_mode);
5082 mlx5e_set_tx_cq_mode_params(params, cq_period_mode: MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
5083
5084 /* TX inline */
5085 mlx5_query_min_inline(mdev, min_inline: &params->tx_min_inline_mode);
5086
5087 /* AF_XDP */
5088 params->xsk = xsk;
5089
5090 /* Do not update netdev->features directly in here
5091 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
5092 * To update netdev->features please modify mlx5e_fix_features()
5093 */
5094}
5095
5096static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
5097{
5098 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
5099 u8 addr[ETH_ALEN];
5100
5101 mlx5_query_mac_address(mdev: priv->mdev, addr);
5102 if (is_zero_ether_addr(addr) &&
5103 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
5104 eth_hw_addr_random(dev: netdev);
5105 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
5106 return;
5107 }
5108
5109 eth_hw_addr_set(dev: netdev, addr);
5110}
5111
5112static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
5113 unsigned int entry, struct udp_tunnel_info *ti)
5114{
5115 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
5116
5117 return mlx5_vxlan_add_port(vxlan: priv->mdev->vxlan, ntohs(ti->port));
5118}
5119
5120static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
5121 unsigned int entry, struct udp_tunnel_info *ti)
5122{
5123 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
5124
5125 return mlx5_vxlan_del_port(vxlan: priv->mdev->vxlan, ntohs(ti->port));
5126}
5127
5128void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
5129{
5130 if (!mlx5_vxlan_allowed(vxlan: priv->mdev->vxlan))
5131 return;
5132
5133 priv->nic_info.set_port = mlx5e_vxlan_set_port;
5134 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
5135 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
5136 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
5137 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
5138 /* Don't count the space hard-coded to the IANA port */
5139 priv->nic_info.tables[0].n_entries =
5140 mlx5_vxlan_max_udp_ports(mdev: priv->mdev) - 1;
5141
5142 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
5143}
5144
5145static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
5146{
5147 int tt;
5148
5149 for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
5150 if (mlx5e_tunnel_proto_supported_tx(mdev, proto_type: mlx5_get_proto_by_tunnel_type(tt)))
5151 return true;
5152 }
5153 return (mlx5_vxlan_allowed(vxlan: mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
5154}
5155
5156static void mlx5e_build_nic_netdev(struct net_device *netdev)
5157{
5158 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
5159 struct mlx5_core_dev *mdev = priv->mdev;
5160 bool fcs_supported;
5161 bool fcs_enabled;
5162
5163 SET_NETDEV_DEV(netdev, mdev->device);
5164
5165 netdev->netdev_ops = &mlx5e_netdev_ops;
5166 netdev->xdp_metadata_ops = &mlx5e_xdp_metadata_ops;
5167
5168 mlx5e_dcbnl_build_netdev(netdev);
5169
5170 netdev->watchdog_timeo = 15 * HZ;
5171
5172 netdev->ethtool_ops = &mlx5e_ethtool_ops;
5173
5174 netdev->vlan_features |= NETIF_F_SG;
5175 netdev->vlan_features |= NETIF_F_HW_CSUM;
5176 netdev->vlan_features |= NETIF_F_HW_MACSEC;
5177 netdev->vlan_features |= NETIF_F_GRO;
5178 netdev->vlan_features |= NETIF_F_TSO;
5179 netdev->vlan_features |= NETIF_F_TSO6;
5180 netdev->vlan_features |= NETIF_F_RXCSUM;
5181 netdev->vlan_features |= NETIF_F_RXHASH;
5182 netdev->vlan_features |= NETIF_F_GSO_PARTIAL;
5183
5184 netdev->mpls_features |= NETIF_F_SG;
5185 netdev->mpls_features |= NETIF_F_HW_CSUM;
5186 netdev->mpls_features |= NETIF_F_TSO;
5187 netdev->mpls_features |= NETIF_F_TSO6;
5188
5189 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
5190 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
5191
5192 /* Tunneled LRO is not supported in the driver, and the same RQs are
5193 * shared between inner and outer TIRs, so the driver can't disable LRO
5194 * for inner TIRs while having it enabled for outer TIRs. Due to this,
5195 * block LRO altogether if the firmware declares tunneled LRO support.
5196 */
5197 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
5198 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
5199 !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
5200 mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT,
5201 umr_mode: MLX5E_MPWRQ_UMR_MODE_ALIGNED))
5202 netdev->vlan_features |= NETIF_F_LRO;
5203
5204 netdev->hw_features = netdev->vlan_features;
5205 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
5206 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
5207 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
5208 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
5209
5210 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
5211 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
5212 netdev->hw_enc_features |= NETIF_F_TSO;
5213 netdev->hw_enc_features |= NETIF_F_TSO6;
5214 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
5215 }
5216
5217 if (mlx5_vxlan_allowed(vxlan: mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
5218 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5219 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5220 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
5221 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5222 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
5223 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
5224 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5225 }
5226
5227 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
5228 netdev->hw_features |= NETIF_F_GSO_GRE |
5229 NETIF_F_GSO_GRE_CSUM;
5230 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
5231 NETIF_F_GSO_GRE_CSUM;
5232 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
5233 NETIF_F_GSO_GRE_CSUM;
5234 }
5235
5236 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
5237 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
5238 NETIF_F_GSO_IPXIP6;
5239 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
5240 NETIF_F_GSO_IPXIP6;
5241 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
5242 NETIF_F_GSO_IPXIP6;
5243 }
5244
5245 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
5246 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
5247 netdev->features |= NETIF_F_GSO_UDP_L4;
5248
5249 mlx5_query_port_fcs(mdev, supported: &fcs_supported, enabled: &fcs_enabled);
5250
5251 if (fcs_supported)
5252 netdev->hw_features |= NETIF_F_RXALL;
5253
5254 if (MLX5_CAP_ETH(mdev, scatter_fcs))
5255 netdev->hw_features |= NETIF_F_RXFCS;
5256
5257 if (mlx5_qos_is_supported(mdev))
5258 netdev->hw_features |= NETIF_F_HW_TC;
5259
5260 netdev->features = netdev->hw_features;
5261
5262 /* Defaults */
5263 if (fcs_enabled)
5264 netdev->features &= ~NETIF_F_RXALL;
5265 netdev->features &= ~NETIF_F_LRO;
5266 netdev->features &= ~NETIF_F_GRO_HW;
5267 netdev->features &= ~NETIF_F_RXFCS;
5268
5269#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5270 if (FT_CAP(flow_modify_en) &&
5271 FT_CAP(modify_root) &&
5272 FT_CAP(identified_miss_table_mode) &&
5273 FT_CAP(flow_table_modify)) {
5274#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
5275 netdev->hw_features |= NETIF_F_HW_TC;
5276#endif
5277#ifdef CONFIG_MLX5_EN_ARFS
5278 netdev->hw_features |= NETIF_F_NTUPLE;
5279#endif
5280 }
5281
5282 netdev->features |= NETIF_F_HIGHDMA;
5283 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
5284
5285 netdev->priv_flags |= IFF_UNICAST_FLT;
5286
5287 netif_set_tso_max_size(dev: netdev, GSO_MAX_SIZE);
5288 mlx5e_set_xdp_feature(netdev);
5289 mlx5e_set_netdev_dev_addr(netdev);
5290 mlx5e_macsec_build_netdev(priv);
5291 mlx5e_ipsec_build_netdev(priv);
5292 mlx5e_ktls_build_netdev(priv);
5293}
5294
5295void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5296{
5297 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5298 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5299 struct mlx5_core_dev *mdev = priv->mdev;
5300 int err;
5301
5302 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5303 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5304 if (!err)
5305 priv->q_counter =
5306 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5307
5308 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5309 if (!err)
5310 priv->drop_rq_q_counter =
5311 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5312}
5313
5314void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5315{
5316 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5317
5318 MLX5_SET(dealloc_q_counter_in, in, opcode,
5319 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5320 if (priv->q_counter) {
5321 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5322 priv->q_counter);
5323 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5324 }
5325
5326 if (priv->drop_rq_q_counter) {
5327 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5328 priv->drop_rq_q_counter);
5329 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5330 }
5331}
5332
5333static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5334 struct net_device *netdev)
5335{
5336 const bool take_rtnl = netdev->reg_state == NETREG_REGISTERED;
5337 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
5338 struct mlx5e_flow_steering *fs;
5339 int err;
5340
5341 mlx5e_build_nic_params(priv, xsk: &priv->xsk, mtu: netdev->mtu);
5342 mlx5e_vxlan_set_netdev_info(priv);
5343
5344 mlx5e_timestamp_init(priv);
5345
5346 priv->dfs_root = debugfs_create_dir(name: "nic",
5347 parent: mlx5_debugfs_get_dev_root(dev: mdev));
5348
5349 fs = mlx5e_fs_init(profile: priv->profile, mdev,
5350 state_destroy: !test_bit(MLX5E_STATE_DESTROYING, &priv->state),
5351 dfs_root: priv->dfs_root);
5352 if (!fs) {
5353 err = -ENOMEM;
5354 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5355 debugfs_remove_recursive(dentry: priv->dfs_root);
5356 return err;
5357 }
5358 priv->fs = fs;
5359
5360 err = mlx5e_ktls_init(priv);
5361 if (err)
5362 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5363
5364 mlx5e_health_create_reporters(priv);
5365
5366 /* If netdev is already registered (e.g. move from uplink to nic profile),
5367 * RTNL lock must be held before triggering netdev notifiers.
5368 */
5369 if (take_rtnl)
5370 rtnl_lock();
5371
5372 /* update XDP supported features */
5373 mlx5e_set_xdp_feature(netdev);
5374
5375 if (take_rtnl)
5376 rtnl_unlock();
5377
5378 return 0;
5379}
5380
5381static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5382{
5383 mlx5e_health_destroy_reporters(priv);
5384 mlx5e_ktls_cleanup(priv);
5385 mlx5e_fs_cleanup(fs: priv->fs);
5386 debugfs_remove_recursive(dentry: priv->dfs_root);
5387 priv->fs = NULL;
5388}
5389
5390static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5391{
5392 struct mlx5_core_dev *mdev = priv->mdev;
5393 enum mlx5e_rx_res_features features;
5394 int err;
5395
5396 mlx5e_create_q_counters(priv);
5397
5398 err = mlx5e_open_drop_rq(priv, drop_rq: &priv->drop_rq);
5399 if (err) {
5400 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5401 goto err_destroy_q_counters;
5402 }
5403
5404 features = MLX5E_RX_RES_FEATURE_PTP;
5405 if (mlx5_tunnel_inner_ft_supported(mdev))
5406 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5407
5408 priv->rx_res = mlx5e_rx_res_create(mdev: priv->mdev, features, max_nch: priv->max_nch, drop_rqn: priv->drop_rq.rqn,
5409 init_pkt_merge_param: &priv->channels.params.packet_merge,
5410 init_nch: priv->channels.params.num_channels);
5411 if (IS_ERR(ptr: priv->rx_res)) {
5412 err = PTR_ERR(ptr: priv->rx_res);
5413 priv->rx_res = NULL;
5414 mlx5_core_err(mdev, "create rx resources failed, %d\n", err);
5415 goto err_close_drop_rq;
5416 }
5417
5418 err = mlx5e_create_flow_steering(fs: priv->fs, rx_res: priv->rx_res, profile: priv->profile,
5419 netdev: priv->netdev);
5420 if (err) {
5421 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5422 goto err_destroy_rx_res;
5423 }
5424
5425 err = mlx5e_tc_nic_init(priv);
5426 if (err)
5427 goto err_destroy_flow_steering;
5428
5429 err = mlx5e_accel_init_rx(priv);
5430 if (err)
5431 goto err_tc_nic_cleanup;
5432
5433#ifdef CONFIG_MLX5_EN_ARFS
5434 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(dev: priv->mdev);
5435#endif
5436
5437 return 0;
5438
5439err_tc_nic_cleanup:
5440 mlx5e_tc_nic_cleanup(priv);
5441err_destroy_flow_steering:
5442 mlx5e_destroy_flow_steering(fs: priv->fs, ntuple: !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5443 profile: priv->profile);
5444err_destroy_rx_res:
5445 mlx5e_rx_res_destroy(res: priv->rx_res);
5446 priv->rx_res = NULL;
5447err_close_drop_rq:
5448 mlx5e_close_drop_rq(drop_rq: &priv->drop_rq);
5449err_destroy_q_counters:
5450 mlx5e_destroy_q_counters(priv);
5451 return err;
5452}
5453
5454static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5455{
5456 mlx5e_accel_cleanup_rx(priv);
5457 mlx5e_tc_nic_cleanup(priv);
5458 mlx5e_destroy_flow_steering(fs: priv->fs, ntuple: !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5459 profile: priv->profile);
5460 mlx5e_rx_res_destroy(res: priv->rx_res);
5461 priv->rx_res = NULL;
5462 mlx5e_close_drop_rq(drop_rq: &priv->drop_rq);
5463 mlx5e_destroy_q_counters(priv);
5464}
5465
5466static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv)
5467{
5468 struct mlx5e_params *params;
5469 struct mlx5e_mqprio_rl *rl;
5470
5471 params = &priv->channels.params;
5472 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL)
5473 return;
5474
5475 rl = mlx5e_mqprio_rl_create(mdev: priv->mdev, num_tc: params->mqprio.num_tc,
5476 max_rate: params->mqprio.channel.max_rate);
5477 if (IS_ERR(ptr: rl))
5478 rl = NULL;
5479 priv->mqprio_rl = rl;
5480 mlx5e_mqprio_rl_update_params(params, rl);
5481}
5482
5483static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5484{
5485 int err;
5486
5487 err = mlx5e_create_tises(priv);
5488 if (err) {
5489 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5490 return err;
5491 }
5492
5493 err = mlx5e_accel_init_tx(priv);
5494 if (err)
5495 goto err_destroy_tises;
5496
5497 mlx5e_set_mqprio_rl(priv);
5498 mlx5e_dcbnl_initialize(priv);
5499 return 0;
5500
5501err_destroy_tises:
5502 mlx5e_destroy_tises(priv);
5503 return err;
5504}
5505
5506static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5507{
5508 struct net_device *netdev = priv->netdev;
5509 struct mlx5_core_dev *mdev = priv->mdev;
5510 int err;
5511
5512 mlx5e_fs_init_l2_addr(fs: priv->fs, netdev);
5513 mlx5e_ipsec_init(priv);
5514
5515 err = mlx5e_macsec_init(priv);
5516 if (err)
5517 mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err);
5518
5519 /* Marking the link as currently not needed by the Driver */
5520 if (!netif_running(dev: netdev))
5521 mlx5e_modify_admin_state(mdev, state: MLX5_PORT_DOWN);
5522
5523 mlx5e_set_netdev_mtu_boundaries(priv);
5524 mlx5e_set_dev_port_mtu(priv);
5525
5526 mlx5_lag_add_netdev(dev: mdev, netdev);
5527
5528 mlx5e_enable_async_events(priv);
5529 mlx5e_enable_blocking_events(priv);
5530 if (mlx5e_monitor_counter_supported(priv))
5531 mlx5e_monitor_counter_init(priv);
5532
5533 mlx5e_hv_vhca_stats_create(priv);
5534 if (netdev->reg_state != NETREG_REGISTERED)
5535 return;
5536 mlx5e_dcbnl_init_app(priv);
5537
5538 mlx5e_nic_set_rx_mode(priv);
5539
5540 rtnl_lock();
5541 if (netif_running(dev: netdev))
5542 mlx5e_open(netdev);
5543 udp_tunnel_nic_reset_ntf(dev: priv->netdev);
5544 netif_device_attach(dev: netdev);
5545 rtnl_unlock();
5546}
5547
5548static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5549{
5550 struct mlx5_core_dev *mdev = priv->mdev;
5551
5552 if (priv->netdev->reg_state == NETREG_REGISTERED)
5553 mlx5e_dcbnl_delete_app(priv);
5554
5555 rtnl_lock();
5556 if (netif_running(dev: priv->netdev))
5557 mlx5e_close(netdev: priv->netdev);
5558 netif_device_detach(dev: priv->netdev);
5559 rtnl_unlock();
5560
5561 mlx5e_nic_set_rx_mode(priv);
5562
5563 mlx5e_hv_vhca_stats_destroy(priv);
5564 if (mlx5e_monitor_counter_supported(priv))
5565 mlx5e_monitor_counter_cleanup(priv);
5566
5567 mlx5e_disable_blocking_events(priv);
5568 if (priv->en_trap) {
5569 mlx5e_deactivate_trap(priv);
5570 mlx5e_close_trap(trap: priv->en_trap);
5571 priv->en_trap = NULL;
5572 }
5573 mlx5e_disable_async_events(priv);
5574 mlx5_lag_remove_netdev(dev: mdev, netdev: priv->netdev);
5575 mlx5_vxlan_reset_to_default(vxlan: mdev->vxlan);
5576 mlx5e_macsec_cleanup(priv);
5577 mlx5e_ipsec_cleanup(priv);
5578}
5579
5580int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5581{
5582 return mlx5e_refresh_tirs(priv, enable_uc_lb: false, enable_mc_lb: false);
5583}
5584
5585static const struct mlx5e_profile mlx5e_nic_profile = {
5586 .init = mlx5e_nic_init,
5587 .cleanup = mlx5e_nic_cleanup,
5588 .init_rx = mlx5e_init_nic_rx,
5589 .cleanup_rx = mlx5e_cleanup_nic_rx,
5590 .init_tx = mlx5e_init_nic_tx,
5591 .cleanup_tx = mlx5e_cleanup_nic_tx,
5592 .enable = mlx5e_nic_enable,
5593 .disable = mlx5e_nic_disable,
5594 .update_rx = mlx5e_update_nic_rx,
5595 .update_stats = mlx5e_stats_update_ndo_stats,
5596 .update_carrier = mlx5e_update_carrier,
5597 .rx_handlers = &mlx5e_rx_handlers_nic,
5598 .max_tc = MLX5E_MAX_NUM_TC,
5599 .stats_grps = mlx5e_nic_stats_grps,
5600 .stats_grps_num = mlx5e_nic_stats_grps_num,
5601 .features = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5602 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5603 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) |
5604 BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) |
5605 BIT(MLX5E_PROFILE_FEATURE_FS_TC),
5606};
5607
5608static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5609 const struct mlx5e_profile *profile)
5610{
5611 int nch;
5612
5613 nch = mlx5e_get_max_num_channels(mdev);
5614
5615 if (profile->max_nch_limit)
5616 nch = min_t(int, nch, profile->max_nch_limit(mdev));
5617 return nch;
5618}
5619
5620static unsigned int
5621mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5622 const struct mlx5e_profile *profile)
5623
5624{
5625 unsigned int max_nch, tmp;
5626
5627 /* core resources */
5628 max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5629
5630 /* netdev rx queues */
5631 max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues);
5632
5633 /* netdev tx queues */
5634 tmp = netdev->num_tx_queues;
5635 if (mlx5_qos_is_supported(mdev))
5636 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5637 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5638 tmp -= profile->max_tc;
5639 tmp = tmp / profile->max_tc;
5640 max_nch = min_t(unsigned int, max_nch, tmp);
5641
5642 return max_nch;
5643}
5644
5645int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev)
5646{
5647 /* Indirect TIRS: 2 sets of TTCs (inner + outer steering)
5648 * and 1 set of direct TIRS
5649 */
5650 return 2 * MLX5E_NUM_INDIR_TIRS
5651 + mlx5e_profile_max_num_channels(mdev, profile: &mlx5e_nic_profile);
5652}
5653
5654void mlx5e_set_rx_mode_work(struct work_struct *work)
5655{
5656 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
5657 set_rx_mode_work);
5658
5659 return mlx5e_fs_set_rx_mode_work(fs: priv->fs, netdev: priv->netdev);
5660}
5661
5662/* mlx5e generic netdev management API (move to en_common.c) */
5663int mlx5e_priv_init(struct mlx5e_priv *priv,
5664 const struct mlx5e_profile *profile,
5665 struct net_device *netdev,
5666 struct mlx5_core_dev *mdev)
5667{
5668 int nch, num_txqs, node;
5669 int err;
5670
5671 num_txqs = netdev->num_tx_queues;
5672 nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5673 node = dev_to_node(dev: mlx5_core_dma_dev(dev: mdev));
5674
5675 /* priv init */
5676 priv->mdev = mdev;
5677 priv->netdev = netdev;
5678 priv->max_nch = nch;
5679 priv->max_opened_tc = 1;
5680
5681 if (!alloc_cpumask_var(mask: &priv->scratchpad.cpumask, GFP_KERNEL))
5682 return -ENOMEM;
5683
5684 mutex_init(&priv->state_lock);
5685
5686 err = mlx5e_selq_init(selq: &priv->selq, state_lock: &priv->state_lock);
5687 if (err)
5688 goto err_free_cpumask;
5689
5690 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5691 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5692 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5693 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5694
5695 priv->wq = create_singlethread_workqueue("mlx5e");
5696 if (!priv->wq)
5697 goto err_free_selq;
5698
5699 priv->txq2sq = kcalloc_node(n: num_txqs, size: sizeof(*priv->txq2sq), GFP_KERNEL, node);
5700 if (!priv->txq2sq)
5701 goto err_destroy_workqueue;
5702
5703 priv->tx_rates = kcalloc_node(n: num_txqs, size: sizeof(*priv->tx_rates), GFP_KERNEL, node);
5704 if (!priv->tx_rates)
5705 goto err_free_txq2sq;
5706
5707 priv->channel_stats =
5708 kcalloc_node(n: nch, size: sizeof(*priv->channel_stats), GFP_KERNEL, node);
5709 if (!priv->channel_stats)
5710 goto err_free_tx_rates;
5711
5712 return 0;
5713
5714err_free_tx_rates:
5715 kfree(objp: priv->tx_rates);
5716err_free_txq2sq:
5717 kfree(objp: priv->txq2sq);
5718err_destroy_workqueue:
5719 destroy_workqueue(wq: priv->wq);
5720err_free_selq:
5721 mlx5e_selq_cleanup(selq: &priv->selq);
5722err_free_cpumask:
5723 free_cpumask_var(mask: priv->scratchpad.cpumask);
5724 return -ENOMEM;
5725}
5726
5727void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5728{
5729 int i;
5730
5731 /* bail if change profile failed and also rollback failed */
5732 if (!priv->mdev)
5733 return;
5734
5735 for (i = 0; i < priv->stats_nch; i++)
5736 kvfree(addr: priv->channel_stats[i]);
5737 kfree(objp: priv->channel_stats);
5738 kfree(objp: priv->tx_rates);
5739 kfree(objp: priv->txq2sq);
5740 destroy_workqueue(wq: priv->wq);
5741 mutex_lock(&priv->state_lock);
5742 mlx5e_selq_cleanup(selq: &priv->selq);
5743 mutex_unlock(lock: &priv->state_lock);
5744 free_cpumask_var(mask: priv->scratchpad.cpumask);
5745
5746 for (i = 0; i < priv->htb_max_qos_sqs; i++)
5747 kfree(objp: priv->htb_qos_sq_stats[i]);
5748 kvfree(addr: priv->htb_qos_sq_stats);
5749
5750 memset(priv, 0, sizeof(*priv));
5751}
5752
5753static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5754 const struct mlx5e_profile *profile)
5755{
5756 unsigned int nch, ptp_txqs, qos_txqs;
5757
5758 nch = mlx5e_profile_max_num_channels(mdev, profile);
5759
5760 ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5761 mlx5e_profile_feature_cap(profile, PTP_TX) ?
5762 profile->max_tc : 0;
5763
5764 qos_txqs = mlx5_qos_is_supported(mdev) &&
5765 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5766 mlx5e_qos_max_leaf_nodes(mdev) : 0;
5767
5768 return nch * profile->max_tc + ptp_txqs + qos_txqs;
5769}
5770
5771static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5772 const struct mlx5e_profile *profile)
5773{
5774 return mlx5e_profile_max_num_channels(mdev, profile);
5775}
5776
5777struct net_device *
5778mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5779{
5780 struct net_device *netdev;
5781 unsigned int txqs, rxqs;
5782 int err;
5783
5784 txqs = mlx5e_get_max_num_txqs(mdev, profile);
5785 rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5786
5787 netdev = alloc_etherdev_mqs(sizeof_priv: sizeof(struct mlx5e_priv), txqs, rxqs);
5788 if (!netdev) {
5789 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5790 return NULL;
5791 }
5792
5793 err = mlx5e_priv_init(priv: netdev_priv(dev: netdev), profile, netdev, mdev);
5794 if (err) {
5795 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5796 goto err_free_netdev;
5797 }
5798
5799 netif_carrier_off(dev: netdev);
5800 netif_tx_disable(dev: netdev);
5801 dev_net_set(dev: netdev, net: mlx5_core_net(dev: mdev));
5802
5803 return netdev;
5804
5805err_free_netdev:
5806 free_netdev(dev: netdev);
5807
5808 return NULL;
5809}
5810
5811static void mlx5e_update_features(struct net_device *netdev)
5812{
5813 if (netdev->reg_state != NETREG_REGISTERED)
5814 return; /* features will be updated on netdev registration */
5815
5816 rtnl_lock();
5817 netdev_update_features(dev: netdev);
5818 rtnl_unlock();
5819}
5820
5821static void mlx5e_reset_channels(struct net_device *netdev)
5822{
5823 netdev_reset_tc(dev: netdev);
5824}
5825
5826int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5827{
5828 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5829 const struct mlx5e_profile *profile = priv->profile;
5830 int max_nch;
5831 int err;
5832
5833 clear_bit(nr: MLX5E_STATE_DESTROYING, addr: &priv->state);
5834 if (priv->fs)
5835 mlx5e_fs_set_state_destroy(fs: priv->fs,
5836 state_destroy: !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5837
5838 /* Validate the max_wqe_size_sq capability. */
5839 if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) {
5840 mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %u\n",
5841 mlx5e_get_max_sq_wqebbs(priv->mdev), (unsigned int)MLX5E_MAX_TX_WQEBBS);
5842 return -EIO;
5843 }
5844
5845 /* max number of channels may have changed */
5846 max_nch = mlx5e_calc_max_nch(mdev: priv->mdev, netdev: priv->netdev, profile);
5847 if (priv->channels.params.num_channels > max_nch) {
5848 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5849 /* Reducing the number of channels - RXFH has to be reset, and
5850 * mlx5e_num_channels_changed below will build the RQT.
5851 */
5852 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5853 priv->channels.params.num_channels = max_nch;
5854 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5855 mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5856 mlx5e_params_mqprio_reset(params: &priv->channels.params);
5857 }
5858 }
5859 if (max_nch != priv->max_nch) {
5860 mlx5_core_warn(priv->mdev,
5861 "MLX5E: Updating max number of channels from %u to %u\n",
5862 priv->max_nch, max_nch);
5863 priv->max_nch = max_nch;
5864 }
5865
5866 /* 1. Set the real number of queues in the kernel the first time.
5867 * 2. Set our default XPS cpumask.
5868 * 3. Build the RQT.
5869 *
5870 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5871 * netdev has been registered by this point (if this function was called
5872 * in the reload or resume flow).
5873 */
5874 if (take_rtnl)
5875 rtnl_lock();
5876 err = mlx5e_num_channels_changed(priv);
5877 if (take_rtnl)
5878 rtnl_unlock();
5879 if (err)
5880 goto out;
5881
5882 err = profile->init_tx(priv);
5883 if (err)
5884 goto out;
5885
5886 err = profile->init_rx(priv);
5887 if (err)
5888 goto err_cleanup_tx;
5889
5890 if (profile->enable)
5891 profile->enable(priv);
5892
5893 mlx5e_update_features(netdev: priv->netdev);
5894
5895 return 0;
5896
5897err_cleanup_tx:
5898 profile->cleanup_tx(priv);
5899
5900out:
5901 mlx5e_reset_channels(netdev: priv->netdev);
5902 set_bit(nr: MLX5E_STATE_DESTROYING, addr: &priv->state);
5903 if (priv->fs)
5904 mlx5e_fs_set_state_destroy(fs: priv->fs,
5905 state_destroy: !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5906 cancel_work_sync(work: &priv->update_stats_work);
5907 return err;
5908}
5909
5910void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5911{
5912 const struct mlx5e_profile *profile = priv->profile;
5913
5914 set_bit(nr: MLX5E_STATE_DESTROYING, addr: &priv->state);
5915 if (priv->fs)
5916 mlx5e_fs_set_state_destroy(fs: priv->fs,
5917 state_destroy: !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5918
5919 if (profile->disable)
5920 profile->disable(priv);
5921 flush_workqueue(priv->wq);
5922
5923 profile->cleanup_rx(priv);
5924 profile->cleanup_tx(priv);
5925 mlx5e_reset_channels(netdev: priv->netdev);
5926 cancel_work_sync(work: &priv->update_stats_work);
5927}
5928
5929static int
5930mlx5e_netdev_init_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5931 const struct mlx5e_profile *new_profile, void *new_ppriv)
5932{
5933 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
5934 int err;
5935
5936 err = mlx5e_priv_init(priv, profile: new_profile, netdev, mdev);
5937 if (err) {
5938 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5939 return err;
5940 }
5941 netif_carrier_off(dev: netdev);
5942 priv->profile = new_profile;
5943 priv->ppriv = new_ppriv;
5944 err = new_profile->init(priv->mdev, priv->netdev);
5945 if (err)
5946 goto priv_cleanup;
5947
5948 return 0;
5949
5950priv_cleanup:
5951 mlx5e_priv_cleanup(priv);
5952 return err;
5953}
5954
5955static int
5956mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5957 const struct mlx5e_profile *new_profile, void *new_ppriv)
5958{
5959 struct mlx5e_priv *priv = netdev_priv(dev: netdev);
5960 int err;
5961
5962 err = mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5963 if (err)
5964 return err;
5965
5966 err = mlx5e_attach_netdev(priv);
5967 if (err)
5968 goto profile_cleanup;
5969 return err;
5970
5971profile_cleanup:
5972 new_profile->cleanup(priv);
5973 mlx5e_priv_cleanup(priv);
5974 return err;
5975}
5976
5977int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5978 const struct mlx5e_profile *new_profile, void *new_ppriv)
5979{
5980 const struct mlx5e_profile *orig_profile = priv->profile;
5981 struct net_device *netdev = priv->netdev;
5982 struct mlx5_core_dev *mdev = priv->mdev;
5983 void *orig_ppriv = priv->ppriv;
5984 int err, rollback_err;
5985
5986 /* cleanup old profile */
5987 mlx5e_detach_netdev(priv);
5988 priv->profile->cleanup(priv);
5989 mlx5e_priv_cleanup(priv);
5990
5991 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5992 mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5993 set_bit(nr: MLX5E_STATE_DESTROYING, addr: &priv->state);
5994 return -EIO;
5995 }
5996
5997 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5998 if (err) { /* roll back to original profile */
5999 netdev_warn(dev: netdev, format: "%s: new profile init failed, %d\n", __func__, err);
6000 goto rollback;
6001 }
6002
6003 return 0;
6004
6005rollback:
6006 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile: orig_profile, new_ppriv: orig_ppriv);
6007 if (rollback_err)
6008 netdev_err(dev: netdev, format: "%s: failed to rollback to orig profile, %d\n",
6009 __func__, rollback_err);
6010 return err;
6011}
6012
6013void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
6014{
6015 mlx5e_netdev_change_profile(priv, new_profile: &mlx5e_nic_profile, NULL);
6016}
6017
6018void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
6019{
6020 struct net_device *netdev = priv->netdev;
6021
6022 mlx5e_priv_cleanup(priv);
6023 free_netdev(dev: netdev);
6024}
6025
6026static int mlx5e_resume(struct auxiliary_device *adev)
6027{
6028 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6029 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(auxdev: adev);
6030 struct mlx5e_priv *priv = mlx5e_dev->priv;
6031 struct net_device *netdev = priv->netdev;
6032 struct mlx5_core_dev *mdev = edev->mdev;
6033 int err;
6034
6035 if (netif_device_present(dev: netdev))
6036 return 0;
6037
6038 err = mlx5e_create_mdev_resources(mdev);
6039 if (err)
6040 return err;
6041
6042 err = mlx5e_attach_netdev(priv);
6043 if (err) {
6044 mlx5e_destroy_mdev_resources(mdev);
6045 return err;
6046 }
6047
6048 return 0;
6049}
6050
6051static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
6052{
6053 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(auxdev: adev);
6054 struct mlx5e_priv *priv = mlx5e_dev->priv;
6055 struct net_device *netdev = priv->netdev;
6056 struct mlx5_core_dev *mdev = priv->mdev;
6057
6058 if (!netif_device_present(dev: netdev)) {
6059 if (test_bit(MLX5E_STATE_DESTROYING, &priv->state))
6060 mlx5e_destroy_mdev_resources(mdev);
6061 return -ENODEV;
6062 }
6063
6064 mlx5e_detach_netdev(priv);
6065 mlx5e_destroy_mdev_resources(mdev);
6066 return 0;
6067}
6068
6069static int mlx5e_probe(struct auxiliary_device *adev,
6070 const struct auxiliary_device_id *id)
6071{
6072 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6073 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
6074 struct mlx5_core_dev *mdev = edev->mdev;
6075 struct mlx5e_dev *mlx5e_dev;
6076 struct net_device *netdev;
6077 pm_message_t state = {};
6078 struct mlx5e_priv *priv;
6079 int err;
6080
6081 mlx5e_dev = mlx5e_create_devlink(dev: &adev->dev, mdev);
6082 if (IS_ERR(ptr: mlx5e_dev))
6083 return PTR_ERR(ptr: mlx5e_dev);
6084 auxiliary_set_drvdata(auxdev: adev, data: mlx5e_dev);
6085
6086 err = mlx5e_devlink_port_register(mlx5e_dev, mdev);
6087 if (err) {
6088 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
6089 goto err_devlink_unregister;
6090 }
6091
6092 netdev = mlx5e_create_netdev(mdev, profile);
6093 if (!netdev) {
6094 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
6095 err = -ENOMEM;
6096 goto err_devlink_port_unregister;
6097 }
6098 SET_NETDEV_DEVLINK_PORT(netdev, &mlx5e_dev->dl_port);
6099
6100 mlx5e_build_nic_netdev(netdev);
6101
6102 priv = netdev_priv(dev: netdev);
6103 mlx5e_dev->priv = priv;
6104
6105 priv->profile = profile;
6106 priv->ppriv = NULL;
6107
6108 err = profile->init(mdev, netdev);
6109 if (err) {
6110 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
6111 goto err_destroy_netdev;
6112 }
6113
6114 err = mlx5e_resume(adev);
6115 if (err) {
6116 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
6117 goto err_profile_cleanup;
6118 }
6119
6120 err = register_netdev(dev: netdev);
6121 if (err) {
6122 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
6123 goto err_resume;
6124 }
6125
6126 mlx5e_dcbnl_init_app(priv);
6127 mlx5_core_uplink_netdev_set(mdev, netdev);
6128 mlx5e_params_print_info(mdev, params: &priv->channels.params);
6129 return 0;
6130
6131err_resume:
6132 mlx5e_suspend(adev, state);
6133err_profile_cleanup:
6134 profile->cleanup(priv);
6135err_destroy_netdev:
6136 mlx5e_destroy_netdev(priv);
6137err_devlink_port_unregister:
6138 mlx5e_devlink_port_unregister(mlx5e_dev);
6139err_devlink_unregister:
6140 mlx5e_destroy_devlink(mlx5e_dev);
6141 return err;
6142}
6143
6144static void mlx5e_remove(struct auxiliary_device *adev)
6145{
6146 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(auxdev: adev);
6147 struct mlx5e_priv *priv = mlx5e_dev->priv;
6148 pm_message_t state = {};
6149
6150 mlx5_core_uplink_netdev_set(mdev: priv->mdev, NULL);
6151 mlx5e_dcbnl_delete_app(priv);
6152 unregister_netdev(dev: priv->netdev);
6153 mlx5e_suspend(adev, state);
6154 priv->profile->cleanup(priv);
6155 mlx5e_destroy_netdev(priv);
6156 mlx5e_devlink_port_unregister(mlx5e_dev);
6157 mlx5e_destroy_devlink(mlx5e_dev);
6158}
6159
6160static const struct auxiliary_device_id mlx5e_id_table[] = {
6161 { .name = MLX5_ADEV_NAME ".eth", },
6162 {},
6163};
6164
6165MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
6166
6167static struct auxiliary_driver mlx5e_driver = {
6168 .name = "eth",
6169 .probe = mlx5e_probe,
6170 .remove = mlx5e_remove,
6171 .suspend = mlx5e_suspend,
6172 .resume = mlx5e_resume,
6173 .id_table = mlx5e_id_table,
6174};
6175
6176int mlx5e_init(void)
6177{
6178 int ret;
6179
6180 mlx5e_build_ptys2ethtool_map();
6181 ret = auxiliary_driver_register(&mlx5e_driver);
6182 if (ret)
6183 return ret;
6184
6185 ret = mlx5e_rep_init();
6186 if (ret)
6187 auxiliary_driver_unregister(auxdrv: &mlx5e_driver);
6188 return ret;
6189}
6190
6191void mlx5e_cleanup(void)
6192{
6193 mlx5e_rep_cleanup();
6194 auxiliary_driver_unregister(auxdrv: &mlx5e_driver);
6195}
6196

source code of linux/drivers/net/ethernet/mellanox/mlx5/core/en_main.c