1 | /* |
2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any |
5 | * purpose with or without fee is hereby granted, provided that the above |
6 | * copyright notice and this permission notice appear in all copies. |
7 | * |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
15 | */ |
16 | |
17 | /** |
18 | * DOC: Programming Atheros 802.11n analog front end radios |
19 | * |
20 | * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express |
21 | * devices have either an external AR2133 analog front end radio for single |
22 | * band 2.4 GHz communication or an AR5133 analog front end radio for dual |
23 | * band 2.4 GHz / 5 GHz communication. |
24 | * |
25 | * All devices after the AR5416 and AR5418 family starting with the AR9280 |
26 | * have their analog front radios, MAC/BB and host PCIe/USB interface embedded |
27 | * into a single-chip and require less programming. |
28 | * |
29 | * The following single-chips exist with a respective embedded radio: |
30 | * |
31 | * AR9280 - 11n dual-band 2x2 MIMO for PCIe |
32 | * AR9281 - 11n single-band 1x2 MIMO for PCIe |
33 | * AR9285 - 11n single-band 1x1 for PCIe |
34 | * AR9287 - 11n single-band 2x2 MIMO for PCIe |
35 | * |
36 | * AR9220 - 11n dual-band 2x2 MIMO for PCI |
37 | * AR9223 - 11n single-band 2x2 MIMO for PCI |
38 | * |
39 | * AR9287 - 11n single-band 1x1 MIMO for USB |
40 | */ |
41 | |
42 | #include "hw.h" |
43 | #include "ar9002_phy.h" |
44 | |
45 | /** |
46 | * ar9002_hw_set_channel - set channel on single-chip device |
47 | * @ah: atheros hardware structure |
48 | * @chan: |
49 | * |
50 | * This is the function to change channel on single-chip devices, that is |
51 | * all devices after ar9280. |
52 | * |
53 | * This function takes the channel value in MHz and sets |
54 | * hardware channel value. Assumes writes have been enabled to analog bus. |
55 | * |
56 | * Actual Expression, |
57 | * |
58 | * For 2GHz channel, |
59 | * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) |
60 | * (freq_ref = 40MHz) |
61 | * |
62 | * For 5GHz channel, |
63 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) |
64 | * (freq_ref = 40MHz/(24>>amodeRefSel)) |
65 | */ |
66 | static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) |
67 | { |
68 | u16 bMode, fracMode, aModeRefSel = 0; |
69 | u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; |
70 | struct chan_centers centers; |
71 | u32 refDivA = 24; |
72 | |
73 | ath9k_hw_get_channel_centers(ah, chan, centers: ¢ers); |
74 | freq = centers.synth_center; |
75 | |
76 | reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); |
77 | reg32 &= 0xc0000000; |
78 | |
79 | if (freq < 4800) { /* 2 GHz, fractional mode */ |
80 | u32 txctl; |
81 | int regWrites = 0; |
82 | |
83 | bMode = 1; |
84 | fracMode = 1; |
85 | aModeRefSel = 0; |
86 | channelSel = CHANSEL_2G(freq); |
87 | |
88 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
89 | if (freq == 2484) { |
90 | /* Enable channel spreading for channel 14 */ |
91 | REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, |
92 | 1, regWrites); |
93 | } else { |
94 | REG_WRITE_ARRAY(&ah->iniCckfirNormal, |
95 | 1, regWrites); |
96 | } |
97 | } else { |
98 | txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); |
99 | if (freq == 2484) { |
100 | /* Enable channel spreading for channel 14 */ |
101 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, |
102 | txctl | AR_PHY_CCK_TX_CTRL_JAPAN); |
103 | } else { |
104 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, |
105 | txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); |
106 | } |
107 | } |
108 | } else { |
109 | bMode = 0; |
110 | fracMode = 0; |
111 | |
112 | switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { |
113 | case 0: |
114 | if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) |
115 | aModeRefSel = 0; |
116 | else if ((freq % 20) == 0) |
117 | aModeRefSel = 3; |
118 | else if ((freq % 10) == 0) |
119 | aModeRefSel = 2; |
120 | if (aModeRefSel) |
121 | break; |
122 | fallthrough; |
123 | case 1: |
124 | default: |
125 | aModeRefSel = 0; |
126 | /* |
127 | * Enable 2G (fractional) mode for channels |
128 | * which are 5MHz spaced. |
129 | */ |
130 | fracMode = 1; |
131 | refDivA = 1; |
132 | channelSel = CHANSEL_5G(freq); |
133 | |
134 | /* RefDivA setting */ |
135 | ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9, |
136 | AR_AN_SYNTH9_REFDIVA, |
137 | AR_AN_SYNTH9_REFDIVA_S, val: refDivA); |
138 | |
139 | } |
140 | |
141 | if (!fracMode) { |
142 | ndiv = (freq * (refDivA >> aModeRefSel)) / 60; |
143 | channelSel = ndiv & 0x1ff; |
144 | channelFrac = (ndiv & 0xfffffe00) * 2; |
145 | channelSel = (channelSel << 17) | channelFrac; |
146 | } |
147 | } |
148 | |
149 | reg32 = reg32 | |
150 | (bMode << 29) | |
151 | (fracMode << 28) | (aModeRefSel << 26) | (channelSel); |
152 | |
153 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); |
154 | |
155 | ah->curchan = chan; |
156 | |
157 | return 0; |
158 | } |
159 | |
160 | /** |
161 | * ar9002_hw_spur_mitigate - convert baseband spur frequency |
162 | * @ah: atheros hardware structure |
163 | * @chan: |
164 | * |
165 | * For single-chip solutions. Converts to baseband spur frequency given the |
166 | * input channel frequency and compute register settings below. |
167 | */ |
168 | static void ar9002_hw_spur_mitigate(struct ath_hw *ah, |
169 | struct ath9k_channel *chan) |
170 | { |
171 | int bb_spur = AR_NO_SPUR; |
172 | int freq; |
173 | int bin; |
174 | int bb_spur_off, spur_subchannel_sd; |
175 | int spur_freq_sd; |
176 | int spur_delta_phase; |
177 | int denominator; |
178 | int tmp, newVal; |
179 | int i; |
180 | struct chan_centers centers; |
181 | |
182 | int cur_bb_spur; |
183 | bool is2GHz = IS_CHAN_2GHZ(chan); |
184 | |
185 | ath9k_hw_get_channel_centers(ah, chan, centers: ¢ers); |
186 | freq = centers.synth_center; |
187 | |
188 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
189 | cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); |
190 | |
191 | if (AR_NO_SPUR == cur_bb_spur) |
192 | break; |
193 | |
194 | if (is2GHz) |
195 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; |
196 | else |
197 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; |
198 | |
199 | cur_bb_spur = cur_bb_spur - freq; |
200 | |
201 | if (IS_CHAN_HT40(chan)) { |
202 | if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && |
203 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { |
204 | bb_spur = cur_bb_spur; |
205 | break; |
206 | } |
207 | } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && |
208 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { |
209 | bb_spur = cur_bb_spur; |
210 | break; |
211 | } |
212 | } |
213 | |
214 | if (AR_NO_SPUR == bb_spur) { |
215 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, |
216 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); |
217 | return; |
218 | } else { |
219 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, |
220 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); |
221 | } |
222 | |
223 | bin = bb_spur * 320; |
224 | |
225 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); |
226 | |
227 | ENABLE_REGWRITE_BUFFER(ah); |
228 | |
229 | newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | |
230 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | |
231 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | |
232 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); |
233 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); |
234 | |
235 | newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | |
236 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | |
237 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | |
238 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | |
239 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); |
240 | REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); |
241 | |
242 | if (IS_CHAN_HT40(chan)) { |
243 | if (bb_spur < 0) { |
244 | spur_subchannel_sd = 1; |
245 | bb_spur_off = bb_spur + 10; |
246 | } else { |
247 | spur_subchannel_sd = 0; |
248 | bb_spur_off = bb_spur - 10; |
249 | } |
250 | } else { |
251 | spur_subchannel_sd = 0; |
252 | bb_spur_off = bb_spur; |
253 | } |
254 | |
255 | if (IS_CHAN_HT40(chan)) |
256 | spur_delta_phase = |
257 | ((bb_spur * 262144) / |
258 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; |
259 | else |
260 | spur_delta_phase = |
261 | ((bb_spur * 524288) / |
262 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; |
263 | |
264 | denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; |
265 | spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; |
266 | |
267 | newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | |
268 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | |
269 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); |
270 | REG_WRITE(ah, AR_PHY_TIMING11, newVal); |
271 | |
272 | newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; |
273 | REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); |
274 | |
275 | ar5008_hw_cmn_spur_mitigate(ah, chan, bin); |
276 | |
277 | REGWRITE_BUFFER_FLUSH(ah); |
278 | } |
279 | |
280 | static void ar9002_olc_init(struct ath_hw *ah) |
281 | { |
282 | u32 i; |
283 | |
284 | if (!OLC_FOR_AR9280_20_LATER(ah)) |
285 | return; |
286 | |
287 | if (OLC_FOR_AR9287_10_LATER(ah)) { |
288 | REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, |
289 | AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); |
290 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, |
291 | AR9287_AN_TXPC0_TXPCMODE, |
292 | AR9287_AN_TXPC0_TXPCMODE_S, |
293 | AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); |
294 | udelay(100); |
295 | } else { |
296 | for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) |
297 | ah->originalGain[i] = |
298 | MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), |
299 | AR_PHY_TX_GAIN); |
300 | ah->PDADCdelta = 0; |
301 | } |
302 | } |
303 | |
304 | static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, |
305 | struct ath9k_channel *chan) |
306 | { |
307 | int ref_div = 5; |
308 | int pll_div = 0x2c; |
309 | u32 pll; |
310 | |
311 | if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) { |
312 | if (AR_SREV_9280_20(ah)) { |
313 | ref_div = 10; |
314 | pll_div = 0x50; |
315 | } else { |
316 | pll_div = 0x28; |
317 | } |
318 | } |
319 | |
320 | pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); |
321 | pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); |
322 | |
323 | if (chan && IS_CHAN_HALF_RATE(chan)) |
324 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); |
325 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) |
326 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); |
327 | |
328 | return pll; |
329 | } |
330 | |
331 | static void ar9002_hw_do_getnf(struct ath_hw *ah, |
332 | int16_t nfarray[NUM_NF_READINGS]) |
333 | { |
334 | int16_t nf; |
335 | |
336 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); |
337 | nfarray[0] = sign_extend32(value: nf, index: 8); |
338 | |
339 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); |
340 | if (IS_CHAN_HT40(ah->curchan)) |
341 | nfarray[3] = sign_extend32(value: nf, index: 8); |
342 | |
343 | if (!(ah->rxchainmask & BIT(1))) |
344 | return; |
345 | |
346 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); |
347 | nfarray[1] = sign_extend32(value: nf, index: 8); |
348 | |
349 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); |
350 | if (IS_CHAN_HT40(ah->curchan)) |
351 | nfarray[4] = sign_extend32(value: nf, index: 8); |
352 | } |
353 | |
354 | static void ar9002_hw_set_nf_limits(struct ath_hw *ah) |
355 | { |
356 | if (AR_SREV_9285(ah)) { |
357 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ; |
358 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ; |
359 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ; |
360 | } else if (AR_SREV_9287(ah)) { |
361 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ; |
362 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ; |
363 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ; |
364 | } else if (AR_SREV_9271(ah)) { |
365 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ; |
366 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ; |
367 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ; |
368 | } else { |
369 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; |
370 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; |
371 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; |
372 | ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; |
373 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; |
374 | ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; |
375 | } |
376 | } |
377 | |
378 | static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah, |
379 | struct ath_hw_antcomb_conf *antconf) |
380 | { |
381 | u32 regval; |
382 | |
383 | regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); |
384 | antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >> |
385 | AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S; |
386 | antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >> |
387 | AR_PHY_9285_ANT_DIV_ALT_LNACONF_S; |
388 | antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >> |
389 | AR_PHY_9285_FAST_DIV_BIAS_S; |
390 | antconf->lna1_lna2_switch_delta = -1; |
391 | antconf->lna1_lna2_delta = -3; |
392 | antconf->div_group = 0; |
393 | } |
394 | |
395 | static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah, |
396 | struct ath_hw_antcomb_conf *antconf) |
397 | { |
398 | u32 regval; |
399 | |
400 | regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); |
401 | regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | |
402 | AR_PHY_9285_ANT_DIV_ALT_LNACONF | |
403 | AR_PHY_9285_FAST_DIV_BIAS); |
404 | regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S) |
405 | & AR_PHY_9285_ANT_DIV_MAIN_LNACONF); |
406 | regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S) |
407 | & AR_PHY_9285_ANT_DIV_ALT_LNACONF); |
408 | regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S) |
409 | & AR_PHY_9285_FAST_DIV_BIAS); |
410 | |
411 | REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); |
412 | } |
413 | |
414 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
415 | |
416 | static void ar9002_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) |
417 | { |
418 | struct ath_btcoex_hw *btcoex = &ah->btcoex_hw; |
419 | u8 antdiv_ctrl1, antdiv_ctrl2; |
420 | u32 regval; |
421 | |
422 | if (enable) { |
423 | antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_ENABLE; |
424 | antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_ENABLE; |
425 | |
426 | /* |
427 | * Don't disable BT ant to allow BB to control SWCOM. |
428 | */ |
429 | btcoex->bt_coex_mode2 &= (~(AR_BT_DISABLE_BT_ANT)); |
430 | REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); |
431 | |
432 | REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); |
433 | REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); |
434 | } else { |
435 | /* |
436 | * Disable antenna diversity, use LNA1 only. |
437 | */ |
438 | antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_FIXED_A; |
439 | antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_FIXED_A; |
440 | |
441 | /* |
442 | * Disable BT Ant. to allow concurrent BT and WLAN receive. |
443 | */ |
444 | btcoex->bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; |
445 | REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); |
446 | |
447 | /* |
448 | * Program SWCOM table to make sure RF switch always parks |
449 | * at BT side. |
450 | */ |
451 | REG_WRITE(ah, AR_PHY_SWITCH_COM, 0); |
452 | REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); |
453 | } |
454 | |
455 | regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); |
456 | regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); |
457 | /* |
458 | * Clear ant_fast_div_bias [14:9] since for WB195, |
459 | * the main LNA is always LNA1. |
460 | */ |
461 | regval &= (~(AR_PHY_9285_FAST_DIV_BIAS)); |
462 | regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); |
463 | regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); |
464 | regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); |
465 | regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); |
466 | regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); |
467 | REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); |
468 | |
469 | regval = REG_READ(ah, AR_PHY_CCK_DETECT); |
470 | regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); |
471 | regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); |
472 | REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); |
473 | } |
474 | |
475 | #endif |
476 | |
477 | static void ar9002_hw_spectral_scan_config(struct ath_hw *ah, |
478 | struct ath_spec_scan *param) |
479 | { |
480 | u32 repeat_bit; |
481 | u8 count; |
482 | |
483 | if (!param->enabled) { |
484 | REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, |
485 | AR_PHY_SPECTRAL_SCAN_ENABLE); |
486 | return; |
487 | } |
488 | REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); |
489 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); |
490 | |
491 | if (AR_SREV_9280(ah)) |
492 | repeat_bit = AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT; |
493 | else |
494 | repeat_bit = AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI; |
495 | |
496 | if (param->short_repeat) |
497 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit); |
498 | else |
499 | REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit); |
500 | |
501 | /* on AR92xx, the highest bit of count will make the chip send |
502 | * spectral samples endlessly. Check if this really was intended, |
503 | * and fix otherwise. |
504 | */ |
505 | count = param->count; |
506 | if (param->endless) { |
507 | if (AR_SREV_9280(ah)) |
508 | count = 0x80; |
509 | else |
510 | count = 0; |
511 | } else if (count & 0x80) |
512 | count = 0x7f; |
513 | else if (!count) |
514 | count = 1; |
515 | |
516 | if (AR_SREV_9280(ah)) { |
517 | REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, |
518 | AR_PHY_SPECTRAL_SCAN_COUNT, count); |
519 | } else { |
520 | REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, |
521 | AR_PHY_SPECTRAL_SCAN_COUNT_KIWI, count); |
522 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, |
523 | AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT); |
524 | } |
525 | |
526 | REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, |
527 | AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); |
528 | REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, |
529 | AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); |
530 | |
531 | return; |
532 | } |
533 | |
534 | static void ar9002_hw_spectral_scan_trigger(struct ath_hw *ah) |
535 | { |
536 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); |
537 | /* Activate spectral scan */ |
538 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, |
539 | AR_PHY_SPECTRAL_SCAN_ACTIVE); |
540 | } |
541 | |
542 | static void ar9002_hw_spectral_scan_wait(struct ath_hw *ah) |
543 | { |
544 | struct ath_common *common = ath9k_hw_common(ah); |
545 | |
546 | /* Poll for spectral scan complete */ |
547 | if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, |
548 | AR_PHY_SPECTRAL_SCAN_ACTIVE, |
549 | val: 0, AH_WAIT_TIMEOUT)) { |
550 | ath_err(common, "spectral scan wait failed\n" ); |
551 | return; |
552 | } |
553 | } |
554 | |
555 | static void ar9002_hw_tx99_start(struct ath_hw *ah, u32 qnum) |
556 | { |
557 | REG_SET_BIT(ah, 0x9864, 0x7f000); |
558 | REG_SET_BIT(ah, 0x9924, 0x7f00fe); |
559 | REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); |
560 | REG_WRITE(ah, AR_CR, AR_CR_RXD); |
561 | REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); |
562 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); |
563 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); |
564 | REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum); |
565 | REG_WRITE(ah, AR_TIME_OUT, 0x00000400); |
566 | REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); |
567 | REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); |
568 | } |
569 | |
570 | static void ar9002_hw_tx99_stop(struct ath_hw *ah) |
571 | { |
572 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); |
573 | } |
574 | |
575 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah) |
576 | { |
577 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
578 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
579 | |
580 | priv_ops->set_rf_regs = NULL; |
581 | priv_ops->rf_set_freq = ar9002_hw_set_channel; |
582 | priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate; |
583 | priv_ops->olc_init = ar9002_olc_init; |
584 | priv_ops->compute_pll_control = ar9002_hw_compute_pll_control; |
585 | priv_ops->do_getnf = ar9002_hw_do_getnf; |
586 | |
587 | ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get; |
588 | ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set; |
589 | ops->spectral_scan_config = ar9002_hw_spectral_scan_config; |
590 | ops->spectral_scan_trigger = ar9002_hw_spectral_scan_trigger; |
591 | ops->spectral_scan_wait = ar9002_hw_spectral_scan_wait; |
592 | |
593 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
594 | ops->set_bt_ant_diversity = ar9002_hw_set_bt_ant_diversity; |
595 | #endif |
596 | ops->tx99_start = ar9002_hw_tx99_start; |
597 | ops->tx99_stop = ar9002_hw_tx99_stop; |
598 | |
599 | ar9002_hw_set_nf_limits(ah); |
600 | } |
601 | |