1 | /* |
2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any |
5 | * purpose with or without fee is hereby granted, provided that the above |
6 | * copyright notice and this permission notice appear in all copies. |
7 | * |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
15 | */ |
16 | |
17 | #ifndef HW_H |
18 | #define HW_H |
19 | |
20 | #include <linux/if_ether.h> |
21 | #include <linux/delay.h> |
22 | #include <linux/io.h> |
23 | #include <linux/firmware.h> |
24 | |
25 | #include "mac.h" |
26 | #include "ani.h" |
27 | #include "eeprom.h" |
28 | #include "calib.h" |
29 | #include "reg.h" |
30 | #include "reg_mci.h" |
31 | #include "phy.h" |
32 | #include "btcoex.h" |
33 | #include "dynack.h" |
34 | |
35 | #include "../regd.h" |
36 | |
37 | #define ATHEROS_VENDOR_ID 0x168c |
38 | |
39 | #define AR5416_DEVID_PCI 0x0023 |
40 | #define AR5416_DEVID_PCIE 0x0024 |
41 | #define AR9160_DEVID_PCI 0x0027 |
42 | #define AR9280_DEVID_PCI 0x0029 |
43 | #define AR9280_DEVID_PCIE 0x002a |
44 | #define AR9285_DEVID_PCIE 0x002b |
45 | #define AR2427_DEVID_PCIE 0x002c |
46 | #define AR9287_DEVID_PCI 0x002d |
47 | #define AR9287_DEVID_PCIE 0x002e |
48 | #define AR9300_DEVID_PCIE 0x0030 |
49 | #define AR9300_DEVID_AR9340 0x0031 |
50 | #define AR9300_DEVID_AR9485_PCIE 0x0032 |
51 | #define AR9300_DEVID_AR9580 0x0033 |
52 | #define AR9300_DEVID_AR9462 0x0034 |
53 | #define AR9300_DEVID_AR9330 0x0035 |
54 | #define AR9300_DEVID_QCA955X 0x0038 |
55 | #define AR9485_DEVID_AR1111 0x0037 |
56 | #define AR9300_DEVID_AR9565 0x0036 |
57 | #define AR9300_DEVID_AR953X 0x003d |
58 | #define AR9300_DEVID_QCA956X 0x003f |
59 | |
60 | #define AR5416_AR9100_DEVID 0x000b |
61 | |
62 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
63 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 |
64 | #define AR5416_MAGIC 0x19641014 |
65 | |
66 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
67 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa |
68 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab |
69 | |
70 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
71 | |
72 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
73 | |
74 | #define -128 |
75 | |
76 | #define ATH9K_NUM_CHANNELS 38 |
77 | |
78 | /* Register read/write primitives */ |
79 | #define REG_WRITE(_ah, _reg, _val) \ |
80 | (_ah)->reg_ops.write((_ah), (_val), (_reg)) |
81 | |
82 | #define REG_READ(_ah, _reg) \ |
83 | (_ah)->reg_ops.read((_ah), (_reg)) |
84 | |
85 | #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ |
86 | (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) |
87 | |
88 | #define REG_RMW(_ah, _reg, _set, _clr) \ |
89 | (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) |
90 | |
91 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
92 | do { \ |
93 | if ((_ah)->reg_ops.enable_write_buffer) \ |
94 | (_ah)->reg_ops.enable_write_buffer((_ah)); \ |
95 | } while (0) |
96 | |
97 | #define REGWRITE_BUFFER_FLUSH(_ah) \ |
98 | do { \ |
99 | if ((_ah)->reg_ops.write_flush) \ |
100 | (_ah)->reg_ops.write_flush((_ah)); \ |
101 | } while (0) |
102 | |
103 | #define ENABLE_REG_RMW_BUFFER(_ah) \ |
104 | do { \ |
105 | if ((_ah)->reg_ops.enable_rmw_buffer) \ |
106 | (_ah)->reg_ops.enable_rmw_buffer((_ah)); \ |
107 | } while (0) |
108 | |
109 | #define REG_RMW_BUFFER_FLUSH(_ah) \ |
110 | do { \ |
111 | if ((_ah)->reg_ops.rmw_flush) \ |
112 | (_ah)->reg_ops.rmw_flush((_ah)); \ |
113 | } while (0) |
114 | |
115 | #define PR_EEP(_s, _val) \ |
116 | do { \ |
117 | len += scnprintf(buf + len, size - len, "%20s : %10d\n",\ |
118 | _s, (_val)); \ |
119 | } while (0) |
120 | |
121 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
122 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) |
123 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
124 | REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) |
125 | #define REG_READ_FIELD(_a, _r, _f) \ |
126 | (((REG_READ(_a, _r) & _f) >> _f##_S)) |
127 | #define REG_SET_BIT(_a, _r, _f) \ |
128 | REG_RMW(_a, _r, (_f), 0) |
129 | #define REG_CLR_BIT(_a, _r, _f) \ |
130 | REG_RMW(_a, _r, 0, (_f)) |
131 | |
132 | #define DO_DELAY(x) do { \ |
133 | if (((++(x) % 64) == 0) && \ |
134 | (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ |
135 | != ATH_USB)) \ |
136 | udelay(1); \ |
137 | } while (0) |
138 | |
139 | #define REG_WRITE_ARRAY(iniarray, column, regWr) \ |
140 | ath9k_hw_write_array(ah, iniarray, column, &(regWr)) |
141 | #define REG_READ_ARRAY(ah, array, size) \ |
142 | ath9k_hw_read_array(ah, array, size) |
143 | |
144 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
145 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 |
146 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 |
147 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 |
148 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
149 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
150 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 |
151 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 |
152 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 |
153 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 |
154 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 |
155 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 |
156 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 |
157 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 |
158 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 |
159 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d |
160 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e |
161 | |
162 | #define AR_GPIOD_MASK 0x00001FFF |
163 | |
164 | #define BASE_ACTIVATE_DELAY 100 |
165 | #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) |
166 | #define COEF_SCALE_S 24 |
167 | #define HT40_CHANNEL_CENTER_SHIFT 10 |
168 | |
169 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
170 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 |
171 | |
172 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 |
173 | #define ATH9K_NUM_QUEUES 10 |
174 | |
175 | #define MAX_RATE_POWER 63 |
176 | #define MAX_COMBINED_POWER 254 /* 128 dBm, chosen to fit in u8 */ |
177 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
178 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
179 | #define AH_TIME_QUANTUM 10 |
180 | #define AR_KEYTABLE_SIZE 128 |
181 | #define POWER_UP_TIME 10000 |
182 | #define 40 |
183 | #define UPPER_5G_SUB_BAND_START 5700 |
184 | #define MID_5G_SUB_BAND_START 5400 |
185 | |
186 | #define CAB_TIMEOUT_VAL 10 |
187 | #define BEACON_TIMEOUT_VAL 10 |
188 | #define MIN_BEACON_TIMEOUT_VAL 1 |
189 | #define SLEEP_SLOP TU_TO_USEC(3) |
190 | |
191 | #define INIT_CONFIG_STATUS 0x00000000 |
192 | #define 0x00000700 |
193 | #define INIT_BCON_CNTRL_REG 0x00000000 |
194 | |
195 | #define TU_TO_USEC(_tu) ((_tu) << 10) |
196 | |
197 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
198 | #define ATH9K_HW_RX_LP_QDEPTH 128 |
199 | |
200 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
201 | #define PAPRD_TABLE_SZ 24 |
202 | #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 |
203 | |
204 | /* |
205 | * Wake on Wireless |
206 | */ |
207 | |
208 | /* Keep Alive Frame */ |
209 | #define KAL_FRAME_LEN 28 |
210 | #define KAL_FRAME_TYPE 0x2 /* data frame */ |
211 | #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ |
212 | #define KAL_DURATION_ID 0x3d |
213 | #define KAL_NUM_DATA_WORDS 6 |
214 | #define KAL_NUM_DESC_WORDS 12 |
215 | #define KAL_ANTENNA_MODE 1 |
216 | #define KAL_TO_DS 1 |
217 | #define KAL_DELAY 4 /* delay of 4ms between 2 KAL frames */ |
218 | #define KAL_TIMEOUT 900 |
219 | |
220 | #define MAX_PATTERN_SIZE 256 |
221 | #define MAX_PATTERN_MASK_SIZE 32 |
222 | #define MAX_NUM_PATTERN 16 |
223 | #define MAX_NUM_PATTERN_LEGACY 8 |
224 | #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and |
225 | deauthenticate packets */ |
226 | |
227 | /* |
228 | * WoW trigger mapping to hardware code |
229 | */ |
230 | |
231 | #define AH_WOW_USER_PATTERN_EN BIT(0) |
232 | #define AH_WOW_MAGIC_PATTERN_EN BIT(1) |
233 | #define AH_WOW_LINK_CHANGE BIT(2) |
234 | #define AH_WOW_BEACON_MISS BIT(3) |
235 | |
236 | enum ath_hw_txq_subtype { |
237 | ATH_TXQ_AC_BK = 0, |
238 | ATH_TXQ_AC_BE = 1, |
239 | ATH_TXQ_AC_VI = 2, |
240 | ATH_TXQ_AC_VO = 3, |
241 | }; |
242 | |
243 | enum ath_ini_subsys { |
244 | ATH_INI_PRE = 0, |
245 | ATH_INI_CORE, |
246 | ATH_INI_POST, |
247 | ATH_INI_NUM_SPLIT, |
248 | }; |
249 | |
250 | enum ath9k_hw_caps { |
251 | ATH9K_HW_CAP_HT = BIT(0), |
252 | ATH9K_HW_CAP_RFSILENT = BIT(1), |
253 | ATH9K_HW_CAP_AUTOSLEEP = BIT(2), |
254 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), |
255 | ATH9K_HW_CAP_EDMA = BIT(4), |
256 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), |
257 | ATH9K_HW_CAP_LDPC = BIT(6), |
258 | ATH9K_HW_CAP_FASTCLOCK = BIT(7), |
259 | ATH9K_HW_CAP_SGI_20 = BIT(8), |
260 | ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), |
261 | ATH9K_HW_CAP_2GHZ = BIT(11), |
262 | ATH9K_HW_CAP_5GHZ = BIT(12), |
263 | ATH9K_HW_CAP_APM = BIT(13), |
264 | #ifdef CONFIG_ATH9K_PCOEM |
265 | ATH9K_HW_CAP_RTT = BIT(14), |
266 | ATH9K_HW_CAP_MCI = BIT(15), |
267 | ATH9K_HW_CAP_BT_ANT_DIV = BIT(17), |
268 | #else |
269 | ATH9K_HW_CAP_RTT = 0, |
270 | ATH9K_HW_CAP_MCI = 0, |
271 | ATH9K_HW_CAP_BT_ANT_DIV = 0, |
272 | #endif |
273 | ATH9K_HW_CAP_DFS = BIT(18), |
274 | ATH9K_HW_CAP_PAPRD = BIT(19), |
275 | ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20), |
276 | }; |
277 | |
278 | /* |
279 | * WoW device capabilities |
280 | * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. |
281 | * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching |
282 | * an exact user defined pattern or de-authentication/disassoc pattern. |
283 | * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four |
284 | * bytes of the pattern for user defined pattern, de-authentication and |
285 | * disassociation patterns for all types of possible frames recieved |
286 | * of those types. |
287 | */ |
288 | |
289 | struct ath9k_hw_wow { |
290 | u32 wow_event_mask; |
291 | u32 wow_event_mask2; |
292 | u8 max_patterns; |
293 | }; |
294 | |
295 | struct ath9k_hw_capabilities { |
296 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ |
297 | u16 rts_aggr_limit; |
298 | u8 tx_chainmask; |
299 | u8 rx_chainmask; |
300 | u8 chip_chainmask; |
301 | u8 max_txchains; |
302 | u8 max_rxchains; |
303 | u8 num_gpio_pins; |
304 | u32 gpio_mask; |
305 | u32 gpio_requested; |
306 | u8 rx_hp_qdepth; |
307 | u8 rx_lp_qdepth; |
308 | u8 rx_status_len; |
309 | u8 tx_desc_len; |
310 | u8 txs_len; |
311 | }; |
312 | |
313 | #define AR_NO_SPUR 0x8000 |
314 | #define AR_BASE_FREQ_2GHZ 2300 |
315 | #define AR_BASE_FREQ_5GHZ 4900 |
316 | #define AR_SPUR_FEEQ_BOUND_HT40 19 |
317 | #define AR_SPUR_FEEQ_BOUND_HT20 10 |
318 | |
319 | enum ath9k_hw_hang_checks { |
320 | HW_BB_WATCHDOG = BIT(0), |
321 | HW_PHYRESTART_CLC_WAR = BIT(1), |
322 | HW_BB_RIFS_HANG = BIT(2), |
323 | HW_BB_DFS_HANG = BIT(3), |
324 | HW_BB_RX_CLEAR_STUCK_HANG = BIT(4), |
325 | HW_MAC_HANG = BIT(5), |
326 | }; |
327 | |
328 | #define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0) |
329 | #define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1) |
330 | #define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2) |
331 | #define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3) |
332 | #define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4) |
333 | |
334 | struct ath9k_ops_config { |
335 | int dma_beacon_response_time; |
336 | int sw_beacon_response_time; |
337 | bool cwm_ignore_extcca; |
338 | u32 pcie_waen; |
339 | u8 analog_shiftreg; |
340 | u32 ofdm_trig_low; |
341 | u32 ofdm_trig_high; |
342 | u32 cck_trig_high; |
343 | u32 cck_trig_low; |
344 | bool enable_paprd; |
345 | int serialize_regmode; |
346 | bool rx_intr_mitigation; |
347 | bool tx_intr_mitigation; |
348 | u8 max_txtrig_level; |
349 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
350 | u16 hw_hang_checks; |
351 | u16 rimt_first; |
352 | u16 rimt_last; |
353 | |
354 | /* Platform specific config */ |
355 | u32 aspm_l1_fix; |
356 | u32 xlna_gpio; |
357 | u32 ant_ctrl_comm2g_switch_enable; |
358 | bool xatten_margin_cfg; |
359 | bool alt_mingainidx; |
360 | u8 pll_pwrsave; |
361 | bool tx_gain_buffalo; |
362 | bool led_active_high; |
363 | }; |
364 | |
365 | enum ath9k_int { |
366 | ATH9K_INT_RX = 0x00000001, |
367 | ATH9K_INT_RXDESC = 0x00000002, |
368 | ATH9K_INT_RXHP = 0x00000001, |
369 | ATH9K_INT_RXLP = 0x00000002, |
370 | ATH9K_INT_RXNOFRM = 0x00000008, |
371 | ATH9K_INT_RXEOL = 0x00000010, |
372 | ATH9K_INT_RXORN = 0x00000020, |
373 | ATH9K_INT_TX = 0x00000040, |
374 | ATH9K_INT_TXDESC = 0x00000080, |
375 | ATH9K_INT_TIM_TIMER = 0x00000100, |
376 | ATH9K_INT_MCI = 0x00000200, |
377 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
378 | ATH9K_INT_TXURN = 0x00000800, |
379 | ATH9K_INT_MIB = 0x00001000, |
380 | ATH9K_INT_RXPHY = 0x00004000, |
381 | ATH9K_INT_RXKCM = 0x00008000, |
382 | ATH9K_INT_SWBA = 0x00010000, |
383 | ATH9K_INT_BMISS = 0x00040000, |
384 | ATH9K_INT_BNR = 0x00100000, |
385 | ATH9K_INT_TIM = 0x00200000, |
386 | ATH9K_INT_DTIM = 0x00400000, |
387 | ATH9K_INT_DTIMSYNC = 0x00800000, |
388 | ATH9K_INT_GPIO = 0x01000000, |
389 | ATH9K_INT_CABEND = 0x02000000, |
390 | ATH9K_INT_TSFOOR = 0x04000000, |
391 | ATH9K_INT_GENTIMER = 0x08000000, |
392 | ATH9K_INT_CST = 0x10000000, |
393 | ATH9K_INT_GTT = 0x20000000, |
394 | ATH9K_INT_FATAL = 0x40000000, |
395 | ATH9K_INT_GLOBAL = 0x80000000, |
396 | ATH9K_INT_BMISC = ATH9K_INT_TIM | |
397 | ATH9K_INT_DTIM | |
398 | ATH9K_INT_DTIMSYNC | |
399 | ATH9K_INT_TSFOOR | |
400 | ATH9K_INT_CABEND, |
401 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | |
402 | ATH9K_INT_RXDESC | |
403 | ATH9K_INT_RXEOL | |
404 | ATH9K_INT_RXORN | |
405 | ATH9K_INT_TXURN | |
406 | ATH9K_INT_TXDESC | |
407 | ATH9K_INT_MIB | |
408 | ATH9K_INT_RXPHY | |
409 | ATH9K_INT_RXKCM | |
410 | ATH9K_INT_SWBA | |
411 | ATH9K_INT_BMISS | |
412 | ATH9K_INT_GPIO, |
413 | ATH9K_INT_NOCARD = 0xffffffff |
414 | }; |
415 | |
416 | #define MAX_RTT_TABLE_ENTRY 6 |
417 | #define MAX_IQCAL_MEASUREMENT 8 |
418 | #define MAX_CL_TAB_ENTRY 16 |
419 | #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) |
420 | |
421 | enum ath9k_cal_flags { |
422 | RTT_DONE, |
423 | PAPRD_PACKET_SENT, |
424 | PAPRD_DONE, |
425 | NFCAL_PENDING, |
426 | NFCAL_INTF, |
427 | TXIQCAL_DONE, |
428 | TXCLCAL_DONE, |
429 | SW_PKDET_DONE, |
430 | LONGCAL_PENDING, |
431 | }; |
432 | |
433 | struct ath9k_hw_cal_data { |
434 | u16 channel; |
435 | u16 channelFlags; |
436 | unsigned long cal_flags; |
437 | int32_t CalValid; |
438 | int8_t iCoff; |
439 | int8_t qCoff; |
440 | u8 caldac[2]; |
441 | u16 small_signal_gain[AR9300_MAX_CHAINS]; |
442 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; |
443 | u32 num_measures[AR9300_MAX_CHAINS]; |
444 | int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; |
445 | u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; |
446 | u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; |
447 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
448 | }; |
449 | |
450 | struct ath9k_channel { |
451 | struct ieee80211_channel *chan; |
452 | u16 channel; |
453 | u16 channelFlags; |
454 | s16 noisefloor; |
455 | }; |
456 | |
457 | #define CHANNEL_5GHZ BIT(0) |
458 | #define CHANNEL_HALF BIT(1) |
459 | #define CHANNEL_QUARTER BIT(2) |
460 | #define CHANNEL_HT BIT(3) |
461 | #define CHANNEL_HT40PLUS BIT(4) |
462 | #define CHANNEL_HT40MINUS BIT(5) |
463 | |
464 | #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ)) |
465 | #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) |
466 | |
467 | #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF)) |
468 | #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER)) |
469 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
470 | (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
471 | |
472 | #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT) |
473 | |
474 | #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c)) |
475 | |
476 | #define IS_CHAN_HT40(_c) \ |
477 | (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS))) |
478 | |
479 | #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS) |
480 | #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS) |
481 | |
482 | enum ath9k_power_mode { |
483 | ATH9K_PM_AWAKE = 0, |
484 | ATH9K_PM_FULL_SLEEP, |
485 | ATH9K_PM_NETWORK_SLEEP, |
486 | ATH9K_PM_UNDEFINED |
487 | }; |
488 | |
489 | enum ser_reg_mode { |
490 | SER_REG_MODE_OFF = 0, |
491 | SER_REG_MODE_ON = 1, |
492 | SER_REG_MODE_AUTO = 2, |
493 | }; |
494 | |
495 | enum ath9k_rx_qtype { |
496 | ATH9K_RX_QUEUE_HP, |
497 | ATH9K_RX_QUEUE_LP, |
498 | ATH9K_RX_QUEUE_MAX, |
499 | }; |
500 | |
501 | struct ath9k_beacon_state { |
502 | u32 bs_nexttbtt; |
503 | u32 bs_nextdtim; |
504 | u32 bs_intval; |
505 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
506 | u32 bs_dtimperiod; |
507 | u16 bs_bmissthreshold; |
508 | u32 bs_sleepduration; |
509 | u32 bs_tsfoor_threshold; |
510 | }; |
511 | |
512 | struct chan_centers { |
513 | u16 synth_center; |
514 | u16 ctl_center; |
515 | u16 ext_center; |
516 | }; |
517 | |
518 | enum { |
519 | ATH9K_RESET_POWER_ON, |
520 | ATH9K_RESET_WARM, |
521 | ATH9K_RESET_COLD, |
522 | }; |
523 | |
524 | struct ath9k_hw_version { |
525 | u32 magic; |
526 | u16 devid; |
527 | u16 subvendorid; |
528 | u32 macVersion; |
529 | u16 macRev; |
530 | u16 phyRev; |
531 | u16 analog5GhzRev; |
532 | u16 analog2GhzRev; |
533 | enum ath_usb_dev usbdev; |
534 | }; |
535 | |
536 | /* Generic TSF timer definitions */ |
537 | |
538 | #define ATH_MAX_GEN_TIMER 16 |
539 | |
540 | #define AR_GENTMR_BIT(_index) (1 << (_index)) |
541 | |
542 | struct ath_gen_timer_configuration { |
543 | u32 next_addr; |
544 | u32 period_addr; |
545 | u32 mode_addr; |
546 | u32 mode_mask; |
547 | }; |
548 | |
549 | struct ath_gen_timer { |
550 | void (*trigger)(void *arg); |
551 | void (*overflow)(void *arg); |
552 | void *arg; |
553 | u8 index; |
554 | }; |
555 | |
556 | struct ath_gen_timer_table { |
557 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; |
558 | u16 timer_mask; |
559 | bool tsf2_enabled; |
560 | }; |
561 | |
562 | struct ath_hw_antcomb_conf { |
563 | u8 main_lna_conf; |
564 | u8 alt_lna_conf; |
565 | u8 fast_div_bias; |
566 | u8 main_gaintb; |
567 | u8 alt_gaintb; |
568 | int lna1_lna2_delta; |
569 | int lna1_lna2_switch_delta; |
570 | u8 div_group; |
571 | }; |
572 | |
573 | /** |
574 | * struct ath_hw_radar_conf - radar detection initialization parameters |
575 | * |
576 | * @pulse_inband: threshold for checking the ratio of in-band power |
577 | * to total power for short radar pulses (half dB steps) |
578 | * @pulse_inband_step: threshold for checking an in-band power to total |
579 | * power ratio increase for short radar pulses (half dB steps) |
580 | * @pulse_height: threshold for detecting the beginning of a short |
581 | * radar pulse (dB step) |
582 | * @pulse_rssi: threshold for detecting if a short radar pulse is |
583 | * gone (dB step) |
584 | * @pulse_maxlen: maximum pulse length (0.8 us steps) |
585 | * |
586 | * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) |
587 | * @radar_inband: threshold for checking the ratio of in-band power |
588 | * to total power for long radar pulses (half dB steps) |
589 | * @fir_power: threshold for detecting the end of a long radar pulse (dB) |
590 | * |
591 | * @ext_channel: enable extension channel radar detection |
592 | */ |
593 | struct ath_hw_radar_conf { |
594 | unsigned int pulse_inband; |
595 | unsigned int pulse_inband_step; |
596 | unsigned int pulse_height; |
597 | unsigned int ; |
598 | unsigned int pulse_maxlen; |
599 | |
600 | unsigned int ; |
601 | unsigned int radar_inband; |
602 | int fir_power; |
603 | |
604 | bool ext_channel; |
605 | }; |
606 | |
607 | /** |
608 | * struct ath_hw_private_ops - callbacks used internally by hardware code |
609 | * |
610 | * This structure contains private callbacks designed to only be used internally |
611 | * by the hardware core. |
612 | * |
613 | * @init_cal_settings: setup types of calibrations supported |
614 | * @init_cal: starts actual calibration |
615 | * |
616 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
617 | * |
618 | * @rf_set_freq: change frequency |
619 | * @spur_mitigate_freq: spur mitigation |
620 | * @set_rf_regs: |
621 | * @compute_pll_control: compute the PLL control value to use for |
622 | * AR_RTC_PLL_CONTROL for a given channel |
623 | * @setup_calibration: set up calibration |
624 | * @iscal_supported: used to query if a type of calibration is supported |
625 | * |
626 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
627 | * register settings through the register initialization. |
628 | */ |
629 | struct ath_hw_private_ops { |
630 | void (*init_hang_checks)(struct ath_hw *ah); |
631 | bool (*detect_mac_hang)(struct ath_hw *ah); |
632 | bool (*detect_bb_hang)(struct ath_hw *ah); |
633 | |
634 | /* Calibration ops */ |
635 | void (*init_cal_settings)(struct ath_hw *ah); |
636 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
637 | |
638 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
639 | void (*setup_calibration)(struct ath_hw *ah, |
640 | struct ath9k_cal_list *currCal); |
641 | |
642 | /* PHY ops */ |
643 | int (*rf_set_freq)(struct ath_hw *ah, |
644 | struct ath9k_channel *chan); |
645 | void (*spur_mitigate_freq)(struct ath_hw *ah, |
646 | struct ath9k_channel *chan); |
647 | bool (*set_rf_regs)(struct ath_hw *ah, |
648 | struct ath9k_channel *chan, |
649 | u16 modesIndex); |
650 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); |
651 | void (*init_bb)(struct ath_hw *ah, |
652 | struct ath9k_channel *chan); |
653 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); |
654 | void (*olc_init)(struct ath_hw *ah); |
655 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); |
656 | void (*mark_phy_inactive)(struct ath_hw *ah); |
657 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); |
658 | bool (*rfbus_req)(struct ath_hw *ah); |
659 | void (*rfbus_done)(struct ath_hw *ah); |
660 | void (*restore_chainmask)(struct ath_hw *ah); |
661 | u32 (*compute_pll_control)(struct ath_hw *ah, |
662 | struct ath9k_channel *chan); |
663 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
664 | int param); |
665 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
666 | void (*set_radar_params)(struct ath_hw *ah, |
667 | struct ath_hw_radar_conf *conf); |
668 | int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, |
669 | u8 *ini_reloaded); |
670 | |
671 | /* ANI */ |
672 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
673 | |
674 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
675 | bool (*is_aic_enabled)(struct ath_hw *ah); |
676 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
677 | }; |
678 | |
679 | /** |
680 | * struct ath_spec_scan - parameters for Atheros spectral scan |
681 | * |
682 | * @enabled: enable/disable spectral scan |
683 | * @short_repeat: controls whether the chip is in spectral scan mode |
684 | * for 4 usec (enabled) or 204 usec (disabled) |
685 | * @count: number of scan results requested. There are special meanings |
686 | * in some chip revisions: |
687 | * AR92xx: highest bit set (>=128) for endless mode |
688 | * (spectral scan won't stopped until explicitly disabled) |
689 | * AR9300 and newer: 0 for endless mode |
690 | * @endless: true if endless mode is intended. Otherwise, count value is |
691 | * corrected to the next possible value. |
692 | * @period: time duration between successive spectral scan entry points |
693 | * (period*256*Tclk). Tclk = ath_common->clockrate |
694 | * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS |
695 | * |
696 | * Note: Tclk = 40MHz or 44MHz depending upon operating mode. |
697 | * Typically it's 44MHz in 2/5GHz on later chips, but there's |
698 | * a "fast clock" check for this in 5GHz. |
699 | * |
700 | */ |
701 | struct ath_spec_scan { |
702 | bool enabled; |
703 | bool short_repeat; |
704 | bool endless; |
705 | u8 count; |
706 | u8 period; |
707 | u8 fft_period; |
708 | }; |
709 | |
710 | /** |
711 | * struct ath_hw_ops - callbacks used by hardware code and driver code |
712 | * |
713 | * This structure contains callbacks designed to be used internally by |
714 | * hardware code and also by the lower level driver. |
715 | * |
716 | * @config_pci_powersave: |
717 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
718 | * |
719 | * @spectral_scan_config: set parameters for spectral scan and enable/disable it |
720 | * @spectral_scan_trigger: trigger a spectral scan run |
721 | * @spectral_scan_wait: wait for a spectral scan run to finish |
722 | */ |
723 | struct ath_hw_ops { |
724 | void (*config_pci_powersave)(struct ath_hw *ah, |
725 | bool power_off); |
726 | void (*rx_enable)(struct ath_hw *ah); |
727 | void (*set_desc_link)(void *ds, u32 link); |
728 | int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, |
729 | u8 rxchainmask, bool longcal); |
730 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked, |
731 | u32 *sync_cause_p); |
732 | void (*set_txdesc)(struct ath_hw *ah, void *ds, |
733 | struct ath_tx_info *i); |
734 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, |
735 | struct ath_tx_status *ts); |
736 | int (*get_duration)(struct ath_hw *ah, const void *ds, int index); |
737 | void (*antdiv_comb_conf_get)(struct ath_hw *ah, |
738 | struct ath_hw_antcomb_conf *antconf); |
739 | void (*antdiv_comb_conf_set)(struct ath_hw *ah, |
740 | struct ath_hw_antcomb_conf *antconf); |
741 | void (*spectral_scan_config)(struct ath_hw *ah, |
742 | struct ath_spec_scan *param); |
743 | void (*spectral_scan_trigger)(struct ath_hw *ah); |
744 | void (*spectral_scan_wait)(struct ath_hw *ah); |
745 | |
746 | void (*tx99_start)(struct ath_hw *ah, u32 qnum); |
747 | void (*tx99_stop)(struct ath_hw *ah); |
748 | void (*tx99_set_txpower)(struct ath_hw *ah, u8 power); |
749 | |
750 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
751 | void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable); |
752 | #endif |
753 | }; |
754 | |
755 | struct ath_nf_limits { |
756 | s16 max; |
757 | s16 min; |
758 | s16 nominal; |
759 | s16 cal[AR5416_MAX_CHAINS]; |
760 | s16 pwr[AR5416_MAX_CHAINS]; |
761 | }; |
762 | |
763 | enum ath_cal_list { |
764 | TX_IQ_CAL = BIT(0), |
765 | TX_IQ_ON_AGC_CAL = BIT(1), |
766 | TX_CL_CAL = BIT(2), |
767 | }; |
768 | |
769 | /* ah_flags */ |
770 | #define AH_USE_EEPROM 0x1 |
771 | #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ |
772 | #define AH_FASTCC 0x4 |
773 | #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */ |
774 | |
775 | struct ath_hw { |
776 | struct ath_ops reg_ops; |
777 | |
778 | struct device *dev; |
779 | struct ieee80211_hw *hw; |
780 | struct ath_common common; |
781 | struct ath9k_hw_version hw_version; |
782 | struct ath9k_ops_config config; |
783 | struct ath9k_hw_capabilities caps; |
784 | struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; |
785 | struct ath9k_channel *curchan; |
786 | |
787 | union { |
788 | struct ar5416_eeprom_def def; |
789 | struct ar5416_eeprom_4k map4k; |
790 | struct ar9287_eeprom map9287; |
791 | struct ar9300_eeprom ar9300_eep; |
792 | } eeprom; |
793 | const struct eeprom_ops *eep_ops; |
794 | |
795 | bool sw_mgmt_crypto_tx; |
796 | bool sw_mgmt_crypto_rx; |
797 | bool is_pciexpress; |
798 | bool aspm_enabled; |
799 | bool is_monitoring; |
800 | bool need_an_top2_fixup; |
801 | u16 tx_trig_level; |
802 | |
803 | u32 nf_regs[6]; |
804 | struct ath_nf_limits nf_2g; |
805 | struct ath_nf_limits nf_5g; |
806 | u16 rfsilent; |
807 | u32 rfkill_gpio; |
808 | u32 rfkill_polarity; |
809 | u32 ah_flags; |
810 | s16 nf_override; |
811 | |
812 | bool reset_power_on; |
813 | bool htc_reset_init; |
814 | |
815 | enum nl80211_iftype opmode; |
816 | enum ath9k_power_mode power_mode; |
817 | |
818 | s8 noise; |
819 | struct ath9k_hw_cal_data *caldata; |
820 | struct ath9k_pacal_info pacal_info; |
821 | struct ar5416Stats stats; |
822 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; |
823 | DECLARE_BITMAP(pending_del_keymap, ATH_KEYMAX); |
824 | |
825 | enum ath9k_int imask; |
826 | u32 imrs2_reg; |
827 | u32 txok_interrupt_mask; |
828 | u32 txerr_interrupt_mask; |
829 | u32 txdesc_interrupt_mask; |
830 | u32 txeol_interrupt_mask; |
831 | u32 txurn_interrupt_mask; |
832 | atomic_t intr_ref_cnt; |
833 | bool chip_fullsleep; |
834 | u32 modes_index; |
835 | |
836 | /* Calibration */ |
837 | u32 supp_cals; |
838 | unsigned long cal_start_time; |
839 | struct ath9k_cal_list iq_caldata; |
840 | struct ath9k_cal_list adcgain_caldata; |
841 | struct ath9k_cal_list adcdc_caldata; |
842 | struct ath9k_cal_list *cal_list; |
843 | struct ath9k_cal_list *cal_list_last; |
844 | struct ath9k_cal_list *cal_list_curr; |
845 | #define totalPowerMeasI meas0.unsign |
846 | #define totalPowerMeasQ meas1.unsign |
847 | #define totalIqCorrMeas meas2.sign |
848 | #define totalAdcIOddPhase meas0.unsign |
849 | #define totalAdcIEvenPhase meas1.unsign |
850 | #define totalAdcQOddPhase meas2.unsign |
851 | #define totalAdcQEvenPhase meas3.unsign |
852 | #define totalAdcDcOffsetIOddPhase meas0.sign |
853 | #define totalAdcDcOffsetIEvenPhase meas1.sign |
854 | #define totalAdcDcOffsetQOddPhase meas2.sign |
855 | #define totalAdcDcOffsetQEvenPhase meas3.sign |
856 | union { |
857 | u32 unsign[AR5416_MAX_CHAINS]; |
858 | int32_t sign[AR5416_MAX_CHAINS]; |
859 | } meas0; |
860 | union { |
861 | u32 unsign[AR5416_MAX_CHAINS]; |
862 | int32_t sign[AR5416_MAX_CHAINS]; |
863 | } meas1; |
864 | union { |
865 | u32 unsign[AR5416_MAX_CHAINS]; |
866 | int32_t sign[AR5416_MAX_CHAINS]; |
867 | } meas2; |
868 | union { |
869 | u32 unsign[AR5416_MAX_CHAINS]; |
870 | int32_t sign[AR5416_MAX_CHAINS]; |
871 | } meas3; |
872 | u16 cal_samples; |
873 | u8 enabled_cals; |
874 | |
875 | u32 sta_id1_defaults; |
876 | u32 misc_mode; |
877 | |
878 | /* Private to hardware code */ |
879 | struct ath_hw_private_ops private_ops; |
880 | /* Accessed by the lower level driver */ |
881 | struct ath_hw_ops ops; |
882 | |
883 | /* Used to program the radio on non single-chip devices */ |
884 | u32 *analogBank6Data; |
885 | |
886 | int coverage_class; |
887 | u32 slottime; |
888 | u32 globaltxtimeout; |
889 | |
890 | /* ANI */ |
891 | u32 aniperiod; |
892 | enum ath9k_ani_cmd ani_function; |
893 | u32 ani_skip_count; |
894 | struct ar5416AniState ani; |
895 | |
896 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
897 | struct ath_btcoex_hw btcoex_hw; |
898 | #endif |
899 | |
900 | u32 intr_txqs; |
901 | u8 txchainmask; |
902 | u8 rxchainmask; |
903 | |
904 | struct ath_hw_radar_conf radar_conf; |
905 | |
906 | u32 originalGain[22]; |
907 | int initPDADC; |
908 | int PDADCdelta; |
909 | int led_pin; |
910 | u32 gpio_mask; |
911 | u32 gpio_val; |
912 | |
913 | struct ar5416IniArray ini_dfs; |
914 | struct ar5416IniArray iniModes; |
915 | struct ar5416IniArray iniCommon; |
916 | struct ar5416IniArray iniBB_RfGain; |
917 | struct ar5416IniArray iniBank6; |
918 | struct ar5416IniArray iniAddac; |
919 | struct ar5416IniArray iniPcieSerdes; |
920 | struct ar5416IniArray iniPcieSerdesLowPower; |
921 | struct ar5416IniArray iniModesFastClock; |
922 | struct ar5416IniArray iniAdditional; |
923 | struct ar5416IniArray iniModesRxGain; |
924 | struct ar5416IniArray ini_modes_rx_gain_bounds; |
925 | struct ar5416IniArray iniModesTxGain; |
926 | struct ar5416IniArray iniCckfirNormal; |
927 | struct ar5416IniArray iniCckfirJapan2484; |
928 | struct ar5416IniArray iniModes_9271_ANI_reg; |
929 | struct ar5416IniArray ini_radio_post_sys2ant; |
930 | struct ar5416IniArray ini_modes_rxgain_xlna; |
931 | struct ar5416IniArray ini_modes_rxgain_bb_core; |
932 | struct ar5416IniArray ini_modes_rxgain_bb_postamble; |
933 | |
934 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
935 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; |
936 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; |
937 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; |
938 | |
939 | u32 intr_gen_timer_trigger; |
940 | u32 intr_gen_timer_thresh; |
941 | struct ath_gen_timer_table hw_gen_timers; |
942 | |
943 | struct ar9003_txs *ts_ring; |
944 | u32 ts_paddr_start; |
945 | u32 ts_paddr_end; |
946 | u16 ts_tail; |
947 | u16 ts_size; |
948 | |
949 | u32 bb_watchdog_last_status; |
950 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ |
951 | u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ |
952 | |
953 | unsigned int paprd_target_power; |
954 | unsigned int paprd_training_power; |
955 | unsigned int paprd_ratemask; |
956 | unsigned int paprd_ratemask_ht40; |
957 | bool paprd_table_write_done; |
958 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; |
959 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; |
960 | /* |
961 | * Store the permanent value of Reg 0x4004in WARegVal |
962 | * so we dont have to R/M/W. We should not be reading |
963 | * this register when in sleep states. |
964 | */ |
965 | u32 WARegVal; |
966 | |
967 | /* Enterprise mode cap */ |
968 | u32 ent_mode; |
969 | |
970 | #ifdef CONFIG_ATH9K_WOW |
971 | struct ath9k_hw_wow wow; |
972 | #endif |
973 | bool is_clk_25mhz; |
974 | int (*get_mac_revision)(void); |
975 | int (*external_reset)(void); |
976 | bool disable_2ghz; |
977 | bool disable_5ghz; |
978 | |
979 | const struct firmware *eeprom_blob; |
980 | u16 *nvmem_blob; /* devres managed */ |
981 | size_t nvmem_blob_len; |
982 | |
983 | struct ath_dynack dynack; |
984 | |
985 | bool tpc_enabled; |
986 | u8 tx_power[Ar5416RateSize]; |
987 | u8 tx_power_stbc[Ar5416RateSize]; |
988 | bool msi_enabled; |
989 | u32 msi_mask; |
990 | u32 msi_reg; |
991 | }; |
992 | |
993 | struct ath_bus_ops { |
994 | enum ath_bus_type ath_bus_type; |
995 | void (*read_cachesize)(struct ath_common *common, int *csz); |
996 | bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); |
997 | void (*bt_coex_prep)(struct ath_common *common); |
998 | void (*aspm_init)(struct ath_common *common); |
999 | }; |
1000 | |
1001 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
1002 | { |
1003 | return &ah->common; |
1004 | } |
1005 | |
1006 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) |
1007 | { |
1008 | return &(ath9k_hw_common(ah)->regulatory); |
1009 | } |
1010 | |
1011 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
1012 | { |
1013 | return &ah->private_ops; |
1014 | } |
1015 | |
1016 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) |
1017 | { |
1018 | return &ah->ops; |
1019 | } |
1020 | |
1021 | static inline u8 get_streams(int mask) |
1022 | { |
1023 | return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); |
1024 | } |
1025 | |
1026 | /* Initialization, Detach, Reset */ |
1027 | void ath9k_hw_deinit(struct ath_hw *ah); |
1028 | int ath9k_hw_init(struct ath_hw *ah); |
1029 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
1030 | struct ath9k_hw_cal_data *caldata, bool fastcc); |
1031 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
1032 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
1033 | |
1034 | /* GPIO / RFKILL / Antennae */ |
1035 | void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label); |
1036 | void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, |
1037 | u32 ah_signal_type); |
1038 | void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio); |
1039 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); |
1040 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
1041 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); |
1042 | |
1043 | /* General Operation */ |
1044 | void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, |
1045 | int hw_delay); |
1046 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
1047 | void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, |
1048 | int column, unsigned int *writecnt); |
1049 | void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size); |
1050 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
1051 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
1052 | u8 phy, int kbps, |
1053 | u32 frameLen, u16 rateix, bool shortPreamble); |
1054 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
1055 | struct ath9k_channel *chan, |
1056 | struct chan_centers *centers); |
1057 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
1058 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); |
1059 | bool ath9k_hw_phy_disable(struct ath_hw *ah); |
1060 | bool ath9k_hw_disable(struct ath_hw *ah); |
1061 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); |
1062 | void ath9k_hw_setopmode(struct ath_hw *ah); |
1063 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); |
1064 | void ath9k_hw_write_associd(struct ath_hw *ah); |
1065 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
1066 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
1067 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); |
1068 | void ath9k_hw_reset_tsf(struct ath_hw *ah); |
1069 | u32 ath9k_hw_get_tsf_offset(struct timespec64 *last, struct timespec64 *cur); |
1070 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); |
1071 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
1072 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); |
1073 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); |
1074 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
1075 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
1076 | const struct ath9k_beacon_state *bs); |
1077 | void ath9k_hw_check_nav(struct ath_hw *ah); |
1078 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
1079 | |
1080 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
1081 | |
1082 | /* Generic hw timer primitives */ |
1083 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
1084 | void (*trigger)(void *), |
1085 | void (*overflow)(void *), |
1086 | void *arg, |
1087 | u8 timer_index); |
1088 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
1089 | struct ath_gen_timer *timer, |
1090 | u32 timer_next, |
1091 | u32 timer_period); |
1092 | void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah); |
1093 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); |
1094 | |
1095 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
1096 | void ath_gen_timer_isr(struct ath_hw *hw); |
1097 | |
1098 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
1099 | |
1100 | /* PHY */ |
1101 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
1102 | u32 *coef_mantissa, u32 *coef_exponent); |
1103 | void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, |
1104 | bool test); |
1105 | |
1106 | /* |
1107 | * Code Specific to AR5008, AR9001 or AR9002, |
1108 | * we stuff these here to avoid callbacks for AR9003. |
1109 | */ |
1110 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
1111 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
1112 | |
1113 | /* |
1114 | * Code specific to AR9003, we stuff these here to avoid callbacks |
1115 | * for older families |
1116 | */ |
1117 | bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah); |
1118 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
1119 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); |
1120 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); |
1121 | void ar9003_hw_disable_phy_restart(struct ath_hw *ah); |
1122 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
1123 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, |
1124 | struct ath9k_hw_cal_data *caldata, |
1125 | int chain); |
1126 | int ar9003_paprd_create_curve(struct ath_hw *ah, |
1127 | struct ath9k_hw_cal_data *caldata, int chain); |
1128 | void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); |
1129 | int ar9003_paprd_init_table(struct ath_hw *ah); |
1130 | bool ar9003_paprd_is_done(struct ath_hw *ah); |
1131 | bool ar9003_is_paprd_enabled(struct ath_hw *ah); |
1132 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); |
1133 | void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, |
1134 | struct ath9k_channel *chan); |
1135 | void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, |
1136 | struct ath9k_channel *chan, int bin); |
1137 | void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, |
1138 | struct ath9k_channel *chan, int ht40_delta); |
1139 | |
1140 | /* Hardware family op attach helpers */ |
1141 | int ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
1142 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
1143 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); |
1144 | |
1145 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
1146 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); |
1147 | |
1148 | int ar9002_hw_attach_ops(struct ath_hw *ah); |
1149 | void ar9003_hw_attach_ops(struct ath_hw *ah); |
1150 | |
1151 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); |
1152 | |
1153 | void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); |
1154 | void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); |
1155 | |
1156 | void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us); |
1157 | void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us); |
1158 | void ath9k_hw_setslottime(struct ath_hw *ah, u32 us); |
1159 | |
1160 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
1161 | void ar9003_hw_attach_aic_ops(struct ath_hw *ah); |
1162 | static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) |
1163 | { |
1164 | return ah->btcoex_hw.enabled; |
1165 | } |
1166 | static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) |
1167 | { |
1168 | return ah->common.btcoex_enabled && |
1169 | (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); |
1170 | |
1171 | } |
1172 | void ath9k_hw_btcoex_enable(struct ath_hw *ah); |
1173 | static inline enum ath_btcoex_scheme |
1174 | ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) |
1175 | { |
1176 | return ah->btcoex_hw.scheme; |
1177 | } |
1178 | #else |
1179 | static inline void ar9003_hw_attach_aic_ops(struct ath_hw *ah) |
1180 | { |
1181 | } |
1182 | static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) |
1183 | { |
1184 | return false; |
1185 | } |
1186 | static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) |
1187 | { |
1188 | return false; |
1189 | } |
1190 | static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) |
1191 | { |
1192 | } |
1193 | static inline enum ath_btcoex_scheme |
1194 | ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) |
1195 | { |
1196 | return ATH_BTCOEX_CFG_NONE; |
1197 | } |
1198 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
1199 | |
1200 | |
1201 | #ifdef CONFIG_ATH9K_WOW |
1202 | int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, |
1203 | u8 *user_mask, int pattern_count, |
1204 | int pattern_len); |
1205 | u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); |
1206 | void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); |
1207 | #else |
1208 | static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, |
1209 | u8 *user_pattern, |
1210 | u8 *user_mask, |
1211 | int pattern_count, |
1212 | int pattern_len) |
1213 | { |
1214 | return 0; |
1215 | } |
1216 | static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) |
1217 | { |
1218 | return 0; |
1219 | } |
1220 | static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) |
1221 | { |
1222 | } |
1223 | #endif |
1224 | |
1225 | #define ATH9K_CLOCK_RATE_CCK 22 |
1226 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 |
1227 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 |
1228 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 |
1229 | |
1230 | #endif |
1231 | |