1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Driver for Cadence QSPI Controller |
4 | // |
5 | // Copyright Altera Corporation (C) 2012-2014. All rights reserved. |
6 | // Copyright Intel Corporation (C) 2019-2020. All rights reserved. |
7 | // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com |
8 | |
9 | #include <linux/clk.h> |
10 | #include <linux/completion.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/dma-mapping.h> |
13 | #include <linux/dmaengine.h> |
14 | #include <linux/err.h> |
15 | #include <linux/errno.h> |
16 | #include <linux/firmware/xlnx-zynqmp.h> |
17 | #include <linux/interrupt.h> |
18 | #include <linux/io.h> |
19 | #include <linux/iopoll.h> |
20 | #include <linux/jiffies.h> |
21 | #include <linux/kernel.h> |
22 | #include <linux/log2.h> |
23 | #include <linux/module.h> |
24 | #include <linux/of.h> |
25 | #include <linux/platform_device.h> |
26 | #include <linux/pm_runtime.h> |
27 | #include <linux/reset.h> |
28 | #include <linux/sched.h> |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/spi/spi-mem.h> |
31 | #include <linux/timer.h> |
32 | |
33 | #define CQSPI_NAME "cadence-qspi" |
34 | #define CQSPI_MAX_CHIPSELECT 4 |
35 | |
36 | static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); |
37 | |
38 | /* Quirks */ |
39 | #define CQSPI_NEEDS_WR_DELAY BIT(0) |
40 | #define CQSPI_DISABLE_DAC_MODE BIT(1) |
41 | #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) |
42 | #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) |
43 | #define CQSPI_SLOW_SRAM BIT(4) |
44 | #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) |
45 | |
46 | /* Capabilities */ |
47 | #define CQSPI_SUPPORTS_OCTAL BIT(0) |
48 | |
49 | #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) |
50 | |
51 | enum { |
52 | CLK_QSPI_APB = 0, |
53 | CLK_QSPI_AHB, |
54 | CLK_QSPI_NUM, |
55 | }; |
56 | |
57 | struct cqspi_st; |
58 | |
59 | struct cqspi_flash_pdata { |
60 | struct cqspi_st *cqspi; |
61 | u32 clk_rate; |
62 | u32 read_delay; |
63 | u32 tshsl_ns; |
64 | u32 tsd2d_ns; |
65 | u32 tchsh_ns; |
66 | u32 tslch_ns; |
67 | u8 cs; |
68 | }; |
69 | |
70 | struct cqspi_st { |
71 | struct platform_device *pdev; |
72 | struct spi_controller *host; |
73 | struct clk *clk; |
74 | struct clk *clks[CLK_QSPI_NUM]; |
75 | unsigned int sclk; |
76 | |
77 | void __iomem *iobase; |
78 | void __iomem *ahb_base; |
79 | resource_size_t ahb_size; |
80 | struct completion transfer_complete; |
81 | |
82 | struct dma_chan *rx_chan; |
83 | struct completion rx_dma_complete; |
84 | dma_addr_t mmap_phys_base; |
85 | |
86 | int current_cs; |
87 | unsigned long master_ref_clk_hz; |
88 | bool is_decoded_cs; |
89 | u32 fifo_depth; |
90 | u32 fifo_width; |
91 | u32 num_chipselect; |
92 | bool rclk_en; |
93 | u32 trigger_address; |
94 | u32 wr_delay; |
95 | bool use_direct_mode; |
96 | bool use_direct_mode_wr; |
97 | struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; |
98 | bool use_dma_read; |
99 | u32 pd_dev_id; |
100 | bool wr_completion; |
101 | bool slow_sram; |
102 | bool apb_ahb_hazard; |
103 | |
104 | bool is_jh7110; /* Flag for StarFive JH7110 SoC */ |
105 | }; |
106 | |
107 | struct cqspi_driver_platdata { |
108 | u32 hwcaps_mask; |
109 | u8 quirks; |
110 | int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, |
111 | u_char *rxbuf, loff_t from_addr, size_t n_rx); |
112 | u32 (*get_dma_status)(struct cqspi_st *cqspi); |
113 | int (*jh7110_clk_init)(struct platform_device *pdev, |
114 | struct cqspi_st *cqspi); |
115 | }; |
116 | |
117 | /* Operation timeout value */ |
118 | #define CQSPI_TIMEOUT_MS 500 |
119 | #define CQSPI_READ_TIMEOUT_MS 10 |
120 | |
121 | /* Runtime_pm autosuspend delay */ |
122 | #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 |
123 | |
124 | #define CQSPI_DUMMY_CLKS_PER_BYTE 8 |
125 | #define CQSPI_DUMMY_BYTES_MAX 4 |
126 | #define CQSPI_DUMMY_CLKS_MAX 31 |
127 | |
128 | #define CQSPI_STIG_DATA_LEN_MAX 8 |
129 | |
130 | /* Register map */ |
131 | #define CQSPI_REG_CONFIG 0x00 |
132 | #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) |
133 | #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) |
134 | #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) |
135 | #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 |
136 | #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) |
137 | #define CQSPI_REG_CONFIG_BAUD_LSB 19 |
138 | #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) |
139 | #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) |
140 | #define CQSPI_REG_CONFIG_IDLE_LSB 31 |
141 | #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF |
142 | #define CQSPI_REG_CONFIG_BAUD_MASK 0xF |
143 | |
144 | #define CQSPI_REG_RD_INSTR 0x04 |
145 | #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 |
146 | #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 |
147 | #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 |
148 | #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 |
149 | #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 |
150 | #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 |
151 | #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 |
152 | #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 |
153 | #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 |
154 | #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F |
155 | |
156 | #define CQSPI_REG_WR_INSTR 0x08 |
157 | #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 |
158 | #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 |
159 | #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 |
160 | |
161 | #define CQSPI_REG_DELAY 0x0C |
162 | #define CQSPI_REG_DELAY_TSLCH_LSB 0 |
163 | #define CQSPI_REG_DELAY_TCHSH_LSB 8 |
164 | #define CQSPI_REG_DELAY_TSD2D_LSB 16 |
165 | #define CQSPI_REG_DELAY_TSHSL_LSB 24 |
166 | #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF |
167 | #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF |
168 | #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF |
169 | #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF |
170 | |
171 | #define CQSPI_REG_READCAPTURE 0x10 |
172 | #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 |
173 | #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 |
174 | #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF |
175 | |
176 | #define CQSPI_REG_SIZE 0x14 |
177 | #define CQSPI_REG_SIZE_ADDRESS_LSB 0 |
178 | #define CQSPI_REG_SIZE_PAGE_LSB 4 |
179 | #define CQSPI_REG_SIZE_BLOCK_LSB 16 |
180 | #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF |
181 | #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF |
182 | #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F |
183 | |
184 | #define CQSPI_REG_SRAMPARTITION 0x18 |
185 | #define CQSPI_REG_INDIRECTTRIGGER 0x1C |
186 | |
187 | #define CQSPI_REG_DMA 0x20 |
188 | #define CQSPI_REG_DMA_SINGLE_LSB 0 |
189 | #define CQSPI_REG_DMA_BURST_LSB 8 |
190 | #define CQSPI_REG_DMA_SINGLE_MASK 0xFF |
191 | #define CQSPI_REG_DMA_BURST_MASK 0xFF |
192 | |
193 | #define CQSPI_REG_REMAP 0x24 |
194 | #define CQSPI_REG_MODE_BIT 0x28 |
195 | |
196 | #define CQSPI_REG_SDRAMLEVEL 0x2C |
197 | #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 |
198 | #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 |
199 | #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF |
200 | #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF |
201 | |
202 | #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 |
203 | #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) |
204 | |
205 | #define CQSPI_REG_IRQSTATUS 0x40 |
206 | #define CQSPI_REG_IRQMASK 0x44 |
207 | |
208 | #define CQSPI_REG_INDIRECTRD 0x60 |
209 | #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) |
210 | #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) |
211 | #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) |
212 | |
213 | #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 |
214 | #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 |
215 | #define CQSPI_REG_INDIRECTRDBYTES 0x6C |
216 | |
217 | #define CQSPI_REG_CMDCTRL 0x90 |
218 | #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) |
219 | #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) |
220 | #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 |
221 | #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 |
222 | #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 |
223 | #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 |
224 | #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 |
225 | #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 |
226 | #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 |
227 | #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 |
228 | #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 |
229 | #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 |
230 | #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 |
231 | #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F |
232 | |
233 | #define CQSPI_REG_INDIRECTWR 0x70 |
234 | #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) |
235 | #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) |
236 | #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) |
237 | |
238 | #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 |
239 | #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 |
240 | #define CQSPI_REG_INDIRECTWRBYTES 0x7C |
241 | |
242 | #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 |
243 | |
244 | #define CQSPI_REG_CMDADDRESS 0x94 |
245 | #define CQSPI_REG_CMDREADDATALOWER 0xA0 |
246 | #define CQSPI_REG_CMDREADDATAUPPER 0xA4 |
247 | #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 |
248 | #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC |
249 | |
250 | #define CQSPI_REG_POLLING_STATUS 0xB0 |
251 | #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 |
252 | |
253 | #define CQSPI_REG_OP_EXT_LOWER 0xE0 |
254 | #define CQSPI_REG_OP_EXT_READ_LSB 24 |
255 | #define CQSPI_REG_OP_EXT_WRITE_LSB 16 |
256 | #define CQSPI_REG_OP_EXT_STIG_LSB 0 |
257 | |
258 | #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 |
259 | |
260 | #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 |
261 | #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 |
262 | |
263 | #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C |
264 | |
265 | #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 |
266 | #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 |
267 | #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C |
268 | #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) |
269 | |
270 | #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 |
271 | |
272 | #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 |
273 | #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 |
274 | |
275 | /* Interrupt status bits */ |
276 | #define CQSPI_REG_IRQ_MODE_ERR BIT(0) |
277 | #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) |
278 | #define CQSPI_REG_IRQ_IND_COMP BIT(2) |
279 | #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) |
280 | #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) |
281 | #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) |
282 | #define CQSPI_REG_IRQ_WATERMARK BIT(6) |
283 | #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) |
284 | |
285 | #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ |
286 | CQSPI_REG_IRQ_IND_SRAM_FULL | \ |
287 | CQSPI_REG_IRQ_IND_COMP) |
288 | |
289 | #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ |
290 | CQSPI_REG_IRQ_WATERMARK | \ |
291 | CQSPI_REG_IRQ_UNDERFLOW) |
292 | |
293 | #define CQSPI_IRQ_STATUS_MASK 0x1FFFF |
294 | #define CQSPI_DMA_UNALIGN 0x3 |
295 | |
296 | #define CQSPI_REG_VERSAL_DMA_VAL 0x602 |
297 | |
298 | static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) |
299 | { |
300 | u32 val; |
301 | |
302 | return readl_relaxed_poll_timeout(reg, val, |
303 | (((clr ? ~val : val) & mask) == mask), |
304 | 10, CQSPI_TIMEOUT_MS * 1000); |
305 | } |
306 | |
307 | static bool cqspi_is_idle(struct cqspi_st *cqspi) |
308 | { |
309 | u32 reg = readl(addr: cqspi->iobase + CQSPI_REG_CONFIG); |
310 | |
311 | return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); |
312 | } |
313 | |
314 | static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) |
315 | { |
316 | u32 reg = readl(addr: cqspi->iobase + CQSPI_REG_SDRAMLEVEL); |
317 | |
318 | reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; |
319 | return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; |
320 | } |
321 | |
322 | static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) |
323 | { |
324 | u32 dma_status; |
325 | |
326 | dma_status = readl(addr: cqspi->iobase + |
327 | CQSPI_REG_VERSAL_DMA_DST_I_STS); |
328 | writel(val: dma_status, addr: cqspi->iobase + |
329 | CQSPI_REG_VERSAL_DMA_DST_I_STS); |
330 | |
331 | return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; |
332 | } |
333 | |
334 | static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) |
335 | { |
336 | struct cqspi_st *cqspi = dev; |
337 | unsigned int irq_status; |
338 | struct device *device = &cqspi->pdev->dev; |
339 | const struct cqspi_driver_platdata *ddata; |
340 | |
341 | ddata = of_device_get_match_data(dev: device); |
342 | |
343 | /* Read interrupt status */ |
344 | irq_status = readl(addr: cqspi->iobase + CQSPI_REG_IRQSTATUS); |
345 | |
346 | /* Clear interrupt */ |
347 | writel(val: irq_status, addr: cqspi->iobase + CQSPI_REG_IRQSTATUS); |
348 | |
349 | if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { |
350 | if (ddata->get_dma_status(cqspi)) { |
351 | complete(&cqspi->transfer_complete); |
352 | return IRQ_HANDLED; |
353 | } |
354 | } |
355 | |
356 | else if (!cqspi->slow_sram) |
357 | irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; |
358 | else |
359 | irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; |
360 | |
361 | if (irq_status) |
362 | complete(&cqspi->transfer_complete); |
363 | |
364 | return IRQ_HANDLED; |
365 | } |
366 | |
367 | static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) |
368 | { |
369 | u32 rdreg = 0; |
370 | |
371 | rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; |
372 | rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; |
373 | rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; |
374 | |
375 | return rdreg; |
376 | } |
377 | |
378 | static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) |
379 | { |
380 | unsigned int dummy_clk; |
381 | |
382 | if (!op->dummy.nbytes) |
383 | return 0; |
384 | |
385 | dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); |
386 | if (op->cmd.dtr) |
387 | dummy_clk /= 2; |
388 | |
389 | return dummy_clk; |
390 | } |
391 | |
392 | static int cqspi_wait_idle(struct cqspi_st *cqspi) |
393 | { |
394 | const unsigned int poll_idle_retry = 3; |
395 | unsigned int count = 0; |
396 | unsigned long timeout; |
397 | |
398 | timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); |
399 | while (1) { |
400 | /* |
401 | * Read few times in succession to ensure the controller |
402 | * is indeed idle, that is, the bit does not transition |
403 | * low again. |
404 | */ |
405 | if (cqspi_is_idle(cqspi)) |
406 | count++; |
407 | else |
408 | count = 0; |
409 | |
410 | if (count >= poll_idle_retry) |
411 | return 0; |
412 | |
413 | if (time_after(jiffies, timeout)) { |
414 | /* Timeout, in busy mode. */ |
415 | dev_err(&cqspi->pdev->dev, |
416 | "QSPI is still busy after %dms timeout.\n" , |
417 | CQSPI_TIMEOUT_MS); |
418 | return -ETIMEDOUT; |
419 | } |
420 | |
421 | cpu_relax(); |
422 | } |
423 | } |
424 | |
425 | static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) |
426 | { |
427 | void __iomem *reg_base = cqspi->iobase; |
428 | int ret; |
429 | |
430 | /* Write the CMDCTRL without start execution. */ |
431 | writel(val: reg, addr: reg_base + CQSPI_REG_CMDCTRL); |
432 | /* Start execute */ |
433 | reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; |
434 | writel(val: reg, addr: reg_base + CQSPI_REG_CMDCTRL); |
435 | |
436 | /* Polling for completion. */ |
437 | ret = cqspi_wait_for_bit(reg: reg_base + CQSPI_REG_CMDCTRL, |
438 | CQSPI_REG_CMDCTRL_INPROGRESS_MASK, clr: 1); |
439 | if (ret) { |
440 | dev_err(&cqspi->pdev->dev, |
441 | "Flash command execution timed out.\n" ); |
442 | return ret; |
443 | } |
444 | |
445 | /* Polling QSPI idle status. */ |
446 | return cqspi_wait_idle(cqspi); |
447 | } |
448 | |
449 | static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, |
450 | const struct spi_mem_op *op, |
451 | unsigned int shift) |
452 | { |
453 | struct cqspi_st *cqspi = f_pdata->cqspi; |
454 | void __iomem *reg_base = cqspi->iobase; |
455 | unsigned int reg; |
456 | u8 ext; |
457 | |
458 | if (op->cmd.nbytes != 2) |
459 | return -EINVAL; |
460 | |
461 | /* Opcode extension is the LSB. */ |
462 | ext = op->cmd.opcode & 0xff; |
463 | |
464 | reg = readl(addr: reg_base + CQSPI_REG_OP_EXT_LOWER); |
465 | reg &= ~(0xff << shift); |
466 | reg |= ext << shift; |
467 | writel(val: reg, addr: reg_base + CQSPI_REG_OP_EXT_LOWER); |
468 | |
469 | return 0; |
470 | } |
471 | |
472 | static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, |
473 | const struct spi_mem_op *op, unsigned int shift) |
474 | { |
475 | struct cqspi_st *cqspi = f_pdata->cqspi; |
476 | void __iomem *reg_base = cqspi->iobase; |
477 | unsigned int reg; |
478 | int ret; |
479 | |
480 | reg = readl(addr: reg_base + CQSPI_REG_CONFIG); |
481 | |
482 | /* |
483 | * We enable dual byte opcode here. The callers have to set up the |
484 | * extension opcode based on which type of operation it is. |
485 | */ |
486 | if (op->cmd.dtr) { |
487 | reg |= CQSPI_REG_CONFIG_DTR_PROTO; |
488 | reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; |
489 | |
490 | /* Set up command opcode extension. */ |
491 | ret = cqspi_setup_opcode_ext(f_pdata, op, shift); |
492 | if (ret) |
493 | return ret; |
494 | } else { |
495 | reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; |
496 | reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; |
497 | } |
498 | |
499 | writel(val: reg, addr: reg_base + CQSPI_REG_CONFIG); |
500 | |
501 | return cqspi_wait_idle(cqspi); |
502 | } |
503 | |
504 | static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, |
505 | const struct spi_mem_op *op) |
506 | { |
507 | struct cqspi_st *cqspi = f_pdata->cqspi; |
508 | void __iomem *reg_base = cqspi->iobase; |
509 | u8 *rxbuf = op->data.buf.in; |
510 | u8 opcode; |
511 | size_t n_rx = op->data.nbytes; |
512 | unsigned int rdreg; |
513 | unsigned int reg; |
514 | unsigned int dummy_clk; |
515 | size_t read_len; |
516 | int status; |
517 | |
518 | status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); |
519 | if (status) |
520 | return status; |
521 | |
522 | if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { |
523 | dev_err(&cqspi->pdev->dev, |
524 | "Invalid input argument, len %zu rxbuf 0x%p\n" , |
525 | n_rx, rxbuf); |
526 | return -EINVAL; |
527 | } |
528 | |
529 | if (op->cmd.dtr) |
530 | opcode = op->cmd.opcode >> 8; |
531 | else |
532 | opcode = op->cmd.opcode; |
533 | |
534 | reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; |
535 | |
536 | rdreg = cqspi_calc_rdreg(op); |
537 | writel(val: rdreg, addr: reg_base + CQSPI_REG_RD_INSTR); |
538 | |
539 | dummy_clk = cqspi_calc_dummy(op); |
540 | if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) |
541 | return -EOPNOTSUPP; |
542 | |
543 | if (dummy_clk) |
544 | reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) |
545 | << CQSPI_REG_CMDCTRL_DUMMY_LSB; |
546 | |
547 | reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); |
548 | |
549 | /* 0 means 1 byte. */ |
550 | reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) |
551 | << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); |
552 | |
553 | /* setup ADDR BIT field */ |
554 | if (op->addr.nbytes) { |
555 | reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); |
556 | reg |= ((op->addr.nbytes - 1) & |
557 | CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) |
558 | << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; |
559 | |
560 | writel(val: op->addr.val, addr: reg_base + CQSPI_REG_CMDADDRESS); |
561 | } |
562 | |
563 | status = cqspi_exec_flash_cmd(cqspi, reg); |
564 | if (status) |
565 | return status; |
566 | |
567 | reg = readl(addr: reg_base + CQSPI_REG_CMDREADDATALOWER); |
568 | |
569 | /* Put the read value into rx_buf */ |
570 | read_len = (n_rx > 4) ? 4 : n_rx; |
571 | memcpy(rxbuf, ®, read_len); |
572 | rxbuf += read_len; |
573 | |
574 | if (n_rx > 4) { |
575 | reg = readl(addr: reg_base + CQSPI_REG_CMDREADDATAUPPER); |
576 | |
577 | read_len = n_rx - read_len; |
578 | memcpy(rxbuf, ®, read_len); |
579 | } |
580 | |
581 | /* Reset CMD_CTRL Reg once command read completes */ |
582 | writel(val: 0, addr: reg_base + CQSPI_REG_CMDCTRL); |
583 | |
584 | return 0; |
585 | } |
586 | |
587 | static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, |
588 | const struct spi_mem_op *op) |
589 | { |
590 | struct cqspi_st *cqspi = f_pdata->cqspi; |
591 | void __iomem *reg_base = cqspi->iobase; |
592 | u8 opcode; |
593 | const u8 *txbuf = op->data.buf.out; |
594 | size_t n_tx = op->data.nbytes; |
595 | unsigned int reg; |
596 | unsigned int data; |
597 | size_t write_len; |
598 | int ret; |
599 | |
600 | ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); |
601 | if (ret) |
602 | return ret; |
603 | |
604 | if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { |
605 | dev_err(&cqspi->pdev->dev, |
606 | "Invalid input argument, cmdlen %zu txbuf 0x%p\n" , |
607 | n_tx, txbuf); |
608 | return -EINVAL; |
609 | } |
610 | |
611 | reg = cqspi_calc_rdreg(op); |
612 | writel(val: reg, addr: reg_base + CQSPI_REG_RD_INSTR); |
613 | |
614 | if (op->cmd.dtr) |
615 | opcode = op->cmd.opcode >> 8; |
616 | else |
617 | opcode = op->cmd.opcode; |
618 | |
619 | reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; |
620 | |
621 | if (op->addr.nbytes) { |
622 | reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); |
623 | reg |= ((op->addr.nbytes - 1) & |
624 | CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) |
625 | << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; |
626 | |
627 | writel(val: op->addr.val, addr: reg_base + CQSPI_REG_CMDADDRESS); |
628 | } |
629 | |
630 | if (n_tx) { |
631 | reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); |
632 | reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) |
633 | << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; |
634 | data = 0; |
635 | write_len = (n_tx > 4) ? 4 : n_tx; |
636 | memcpy(&data, txbuf, write_len); |
637 | txbuf += write_len; |
638 | writel(val: data, addr: reg_base + CQSPI_REG_CMDWRITEDATALOWER); |
639 | |
640 | if (n_tx > 4) { |
641 | data = 0; |
642 | write_len = n_tx - 4; |
643 | memcpy(&data, txbuf, write_len); |
644 | writel(val: data, addr: reg_base + CQSPI_REG_CMDWRITEDATAUPPER); |
645 | } |
646 | } |
647 | |
648 | ret = cqspi_exec_flash_cmd(cqspi, reg); |
649 | |
650 | /* Reset CMD_CTRL Reg once command write completes */ |
651 | writel(val: 0, addr: reg_base + CQSPI_REG_CMDCTRL); |
652 | |
653 | return ret; |
654 | } |
655 | |
656 | static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, |
657 | const struct spi_mem_op *op) |
658 | { |
659 | struct cqspi_st *cqspi = f_pdata->cqspi; |
660 | void __iomem *reg_base = cqspi->iobase; |
661 | unsigned int dummy_clk = 0; |
662 | unsigned int reg; |
663 | int ret; |
664 | u8 opcode; |
665 | |
666 | ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); |
667 | if (ret) |
668 | return ret; |
669 | |
670 | if (op->cmd.dtr) |
671 | opcode = op->cmd.opcode >> 8; |
672 | else |
673 | opcode = op->cmd.opcode; |
674 | |
675 | reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; |
676 | reg |= cqspi_calc_rdreg(op); |
677 | |
678 | /* Setup dummy clock cycles */ |
679 | dummy_clk = cqspi_calc_dummy(op); |
680 | |
681 | if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) |
682 | return -EOPNOTSUPP; |
683 | |
684 | if (dummy_clk) |
685 | reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) |
686 | << CQSPI_REG_RD_INSTR_DUMMY_LSB; |
687 | |
688 | writel(val: reg, addr: reg_base + CQSPI_REG_RD_INSTR); |
689 | |
690 | /* Set address width */ |
691 | reg = readl(addr: reg_base + CQSPI_REG_SIZE); |
692 | reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; |
693 | reg |= (op->addr.nbytes - 1); |
694 | writel(val: reg, addr: reg_base + CQSPI_REG_SIZE); |
695 | return 0; |
696 | } |
697 | |
698 | static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, |
699 | u8 *rxbuf, loff_t from_addr, |
700 | const size_t n_rx) |
701 | { |
702 | struct cqspi_st *cqspi = f_pdata->cqspi; |
703 | struct device *dev = &cqspi->pdev->dev; |
704 | void __iomem *reg_base = cqspi->iobase; |
705 | void __iomem *ahb_base = cqspi->ahb_base; |
706 | unsigned int remaining = n_rx; |
707 | unsigned int mod_bytes = n_rx % 4; |
708 | unsigned int bytes_to_read = 0; |
709 | u8 *rxbuf_end = rxbuf + n_rx; |
710 | int ret = 0; |
711 | |
712 | writel(val: from_addr, addr: reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); |
713 | writel(val: remaining, addr: reg_base + CQSPI_REG_INDIRECTRDBYTES); |
714 | |
715 | /* Clear all interrupts. */ |
716 | writel(CQSPI_IRQ_STATUS_MASK, addr: reg_base + CQSPI_REG_IRQSTATUS); |
717 | |
718 | /* |
719 | * On SoCFPGA platform reading the SRAM is slow due to |
720 | * hardware limitation and causing read interrupt storm to CPU, |
721 | * so enabling only watermark interrupt to disable all read |
722 | * interrupts later as we want to run "bytes to read" loop with |
723 | * all the read interrupts disabled for max performance. |
724 | */ |
725 | |
726 | if (!cqspi->slow_sram) |
727 | writel(CQSPI_IRQ_MASK_RD, addr: reg_base + CQSPI_REG_IRQMASK); |
728 | else |
729 | writel(CQSPI_REG_IRQ_WATERMARK, addr: reg_base + CQSPI_REG_IRQMASK); |
730 | |
731 | reinit_completion(x: &cqspi->transfer_complete); |
732 | writel(CQSPI_REG_INDIRECTRD_START_MASK, |
733 | addr: reg_base + CQSPI_REG_INDIRECTRD); |
734 | |
735 | while (remaining > 0) { |
736 | if (!wait_for_completion_timeout(x: &cqspi->transfer_complete, |
737 | timeout: msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) |
738 | ret = -ETIMEDOUT; |
739 | |
740 | /* |
741 | * Disable all read interrupts until |
742 | * we are out of "bytes to read" |
743 | */ |
744 | if (cqspi->slow_sram) |
745 | writel(val: 0x0, addr: reg_base + CQSPI_REG_IRQMASK); |
746 | |
747 | bytes_to_read = cqspi_get_rd_sram_level(cqspi); |
748 | |
749 | if (ret && bytes_to_read == 0) { |
750 | dev_err(dev, "Indirect read timeout, no bytes\n" ); |
751 | goto failrd; |
752 | } |
753 | |
754 | while (bytes_to_read != 0) { |
755 | unsigned int word_remain = round_down(remaining, 4); |
756 | |
757 | bytes_to_read *= cqspi->fifo_width; |
758 | bytes_to_read = bytes_to_read > remaining ? |
759 | remaining : bytes_to_read; |
760 | bytes_to_read = round_down(bytes_to_read, 4); |
761 | /* Read 4 byte word chunks then single bytes */ |
762 | if (bytes_to_read) { |
763 | ioread32_rep(port: ahb_base, buf: rxbuf, |
764 | count: (bytes_to_read / 4)); |
765 | } else if (!word_remain && mod_bytes) { |
766 | unsigned int temp = ioread32(ahb_base); |
767 | |
768 | bytes_to_read = mod_bytes; |
769 | memcpy(rxbuf, &temp, min((unsigned int) |
770 | (rxbuf_end - rxbuf), |
771 | bytes_to_read)); |
772 | } |
773 | rxbuf += bytes_to_read; |
774 | remaining -= bytes_to_read; |
775 | bytes_to_read = cqspi_get_rd_sram_level(cqspi); |
776 | } |
777 | |
778 | if (remaining > 0) { |
779 | reinit_completion(x: &cqspi->transfer_complete); |
780 | if (cqspi->slow_sram) |
781 | writel(CQSPI_REG_IRQ_WATERMARK, addr: reg_base + CQSPI_REG_IRQMASK); |
782 | } |
783 | } |
784 | |
785 | /* Check indirect done status */ |
786 | ret = cqspi_wait_for_bit(reg: reg_base + CQSPI_REG_INDIRECTRD, |
787 | CQSPI_REG_INDIRECTRD_DONE_MASK, clr: 0); |
788 | if (ret) { |
789 | dev_err(dev, "Indirect read completion error (%i)\n" , ret); |
790 | goto failrd; |
791 | } |
792 | |
793 | /* Disable interrupt */ |
794 | writel(val: 0, addr: reg_base + CQSPI_REG_IRQMASK); |
795 | |
796 | /* Clear indirect completion status */ |
797 | writel(CQSPI_REG_INDIRECTRD_DONE_MASK, addr: reg_base + CQSPI_REG_INDIRECTRD); |
798 | |
799 | return 0; |
800 | |
801 | failrd: |
802 | /* Disable interrupt */ |
803 | writel(val: 0, addr: reg_base + CQSPI_REG_IRQMASK); |
804 | |
805 | /* Cancel the indirect read */ |
806 | writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, |
807 | addr: reg_base + CQSPI_REG_INDIRECTRD); |
808 | return ret; |
809 | } |
810 | |
811 | static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) |
812 | { |
813 | void __iomem *reg_base = cqspi->iobase; |
814 | unsigned int reg; |
815 | |
816 | reg = readl(addr: reg_base + CQSPI_REG_CONFIG); |
817 | |
818 | if (enable) |
819 | reg |= CQSPI_REG_CONFIG_ENABLE_MASK; |
820 | else |
821 | reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; |
822 | |
823 | writel(val: reg, addr: reg_base + CQSPI_REG_CONFIG); |
824 | } |
825 | |
826 | static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, |
827 | u_char *rxbuf, loff_t from_addr, |
828 | size_t n_rx) |
829 | { |
830 | struct cqspi_st *cqspi = f_pdata->cqspi; |
831 | struct device *dev = &cqspi->pdev->dev; |
832 | void __iomem *reg_base = cqspi->iobase; |
833 | u32 reg, bytes_to_dma; |
834 | loff_t addr = from_addr; |
835 | void *buf = rxbuf; |
836 | dma_addr_t dma_addr; |
837 | u8 bytes_rem; |
838 | int ret = 0; |
839 | |
840 | bytes_rem = n_rx % 4; |
841 | bytes_to_dma = (n_rx - bytes_rem); |
842 | |
843 | if (!bytes_to_dma) |
844 | goto nondmard; |
845 | |
846 | ret = zynqmp_pm_ospi_mux_select(dev_id: cqspi->pd_dev_id, select: PM_OSPI_MUX_SEL_DMA); |
847 | if (ret) |
848 | return ret; |
849 | |
850 | cqspi_controller_enable(cqspi, enable: 0); |
851 | |
852 | reg = readl(addr: cqspi->iobase + CQSPI_REG_CONFIG); |
853 | reg |= CQSPI_REG_CONFIG_DMA_MASK; |
854 | writel(val: reg, addr: cqspi->iobase + CQSPI_REG_CONFIG); |
855 | |
856 | cqspi_controller_enable(cqspi, enable: 1); |
857 | |
858 | dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); |
859 | if (dma_mapping_error(dev, dma_addr)) { |
860 | dev_err(dev, "dma mapping failed\n" ); |
861 | return -ENOMEM; |
862 | } |
863 | |
864 | writel(val: from_addr, addr: reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); |
865 | writel(val: bytes_to_dma, addr: reg_base + CQSPI_REG_INDIRECTRDBYTES); |
866 | writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, |
867 | addr: reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); |
868 | |
869 | /* Clear all interrupts. */ |
870 | writel(CQSPI_IRQ_STATUS_MASK, addr: reg_base + CQSPI_REG_IRQSTATUS); |
871 | |
872 | /* Enable DMA done interrupt */ |
873 | writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, |
874 | addr: reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); |
875 | |
876 | /* Default DMA periph configuration */ |
877 | writel(CQSPI_REG_VERSAL_DMA_VAL, addr: reg_base + CQSPI_REG_DMA); |
878 | |
879 | /* Configure DMA Dst address */ |
880 | writel(lower_32_bits(dma_addr), |
881 | addr: reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); |
882 | writel(upper_32_bits(dma_addr), |
883 | addr: reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); |
884 | |
885 | /* Configure DMA Src address */ |
886 | writel(val: cqspi->trigger_address, addr: reg_base + |
887 | CQSPI_REG_VERSAL_DMA_SRC_ADDR); |
888 | |
889 | /* Set DMA destination size */ |
890 | writel(val: bytes_to_dma, addr: reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); |
891 | |
892 | /* Set DMA destination control */ |
893 | writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, |
894 | addr: reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); |
895 | |
896 | writel(CQSPI_REG_INDIRECTRD_START_MASK, |
897 | addr: reg_base + CQSPI_REG_INDIRECTRD); |
898 | |
899 | reinit_completion(x: &cqspi->transfer_complete); |
900 | |
901 | if (!wait_for_completion_timeout(x: &cqspi->transfer_complete, |
902 | timeout: msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { |
903 | ret = -ETIMEDOUT; |
904 | goto failrd; |
905 | } |
906 | |
907 | /* Disable DMA interrupt */ |
908 | writel(val: 0x0, addr: cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); |
909 | |
910 | /* Clear indirect completion status */ |
911 | writel(CQSPI_REG_INDIRECTRD_DONE_MASK, |
912 | addr: cqspi->iobase + CQSPI_REG_INDIRECTRD); |
913 | dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); |
914 | |
915 | cqspi_controller_enable(cqspi, enable: 0); |
916 | |
917 | reg = readl(addr: cqspi->iobase + CQSPI_REG_CONFIG); |
918 | reg &= ~CQSPI_REG_CONFIG_DMA_MASK; |
919 | writel(val: reg, addr: cqspi->iobase + CQSPI_REG_CONFIG); |
920 | |
921 | cqspi_controller_enable(cqspi, enable: 1); |
922 | |
923 | ret = zynqmp_pm_ospi_mux_select(dev_id: cqspi->pd_dev_id, |
924 | select: PM_OSPI_MUX_SEL_LINEAR); |
925 | if (ret) |
926 | return ret; |
927 | |
928 | nondmard: |
929 | if (bytes_rem) { |
930 | addr += bytes_to_dma; |
931 | buf += bytes_to_dma; |
932 | ret = cqspi_indirect_read_execute(f_pdata, rxbuf: buf, from_addr: addr, |
933 | n_rx: bytes_rem); |
934 | if (ret) |
935 | return ret; |
936 | } |
937 | |
938 | return 0; |
939 | |
940 | failrd: |
941 | /* Disable DMA interrupt */ |
942 | writel(val: 0x0, addr: reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); |
943 | |
944 | /* Cancel the indirect read */ |
945 | writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, |
946 | addr: reg_base + CQSPI_REG_INDIRECTRD); |
947 | |
948 | dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); |
949 | |
950 | reg = readl(addr: cqspi->iobase + CQSPI_REG_CONFIG); |
951 | reg &= ~CQSPI_REG_CONFIG_DMA_MASK; |
952 | writel(val: reg, addr: cqspi->iobase + CQSPI_REG_CONFIG); |
953 | |
954 | zynqmp_pm_ospi_mux_select(dev_id: cqspi->pd_dev_id, select: PM_OSPI_MUX_SEL_LINEAR); |
955 | |
956 | return ret; |
957 | } |
958 | |
959 | static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, |
960 | const struct spi_mem_op *op) |
961 | { |
962 | unsigned int reg; |
963 | int ret; |
964 | struct cqspi_st *cqspi = f_pdata->cqspi; |
965 | void __iomem *reg_base = cqspi->iobase; |
966 | u8 opcode; |
967 | |
968 | ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); |
969 | if (ret) |
970 | return ret; |
971 | |
972 | if (op->cmd.dtr) |
973 | opcode = op->cmd.opcode >> 8; |
974 | else |
975 | opcode = op->cmd.opcode; |
976 | |
977 | /* Set opcode. */ |
978 | reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; |
979 | reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; |
980 | reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; |
981 | writel(val: reg, addr: reg_base + CQSPI_REG_WR_INSTR); |
982 | reg = cqspi_calc_rdreg(op); |
983 | writel(val: reg, addr: reg_base + CQSPI_REG_RD_INSTR); |
984 | |
985 | /* |
986 | * SPI NAND flashes require the address of the status register to be |
987 | * passed in the Read SR command. Also, some SPI NOR flashes like the |
988 | * cypress Semper flash expect a 4-byte dummy address in the Read SR |
989 | * command in DTR mode. |
990 | * |
991 | * But this controller does not support address phase in the Read SR |
992 | * command when doing auto-HW polling. So, disable write completion |
993 | * polling on the controller's side. spinand and spi-nor will take |
994 | * care of polling the status register. |
995 | */ |
996 | if (cqspi->wr_completion) { |
997 | reg = readl(addr: reg_base + CQSPI_REG_WR_COMPLETION_CTRL); |
998 | reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; |
999 | writel(val: reg, addr: reg_base + CQSPI_REG_WR_COMPLETION_CTRL); |
1000 | /* |
1001 | * DAC mode require auto polling as flash needs to be polled |
1002 | * for write completion in case of bubble in SPI transaction |
1003 | * due to slow CPU/DMA master. |
1004 | */ |
1005 | cqspi->use_direct_mode_wr = false; |
1006 | } |
1007 | |
1008 | reg = readl(addr: reg_base + CQSPI_REG_SIZE); |
1009 | reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; |
1010 | reg |= (op->addr.nbytes - 1); |
1011 | writel(val: reg, addr: reg_base + CQSPI_REG_SIZE); |
1012 | return 0; |
1013 | } |
1014 | |
1015 | static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, |
1016 | loff_t to_addr, const u8 *txbuf, |
1017 | const size_t n_tx) |
1018 | { |
1019 | struct cqspi_st *cqspi = f_pdata->cqspi; |
1020 | struct device *dev = &cqspi->pdev->dev; |
1021 | void __iomem *reg_base = cqspi->iobase; |
1022 | unsigned int remaining = n_tx; |
1023 | unsigned int write_bytes; |
1024 | int ret; |
1025 | |
1026 | writel(val: to_addr, addr: reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); |
1027 | writel(val: remaining, addr: reg_base + CQSPI_REG_INDIRECTWRBYTES); |
1028 | |
1029 | /* Clear all interrupts. */ |
1030 | writel(CQSPI_IRQ_STATUS_MASK, addr: reg_base + CQSPI_REG_IRQSTATUS); |
1031 | |
1032 | writel(CQSPI_IRQ_MASK_WR, addr: reg_base + CQSPI_REG_IRQMASK); |
1033 | |
1034 | reinit_completion(x: &cqspi->transfer_complete); |
1035 | writel(CQSPI_REG_INDIRECTWR_START_MASK, |
1036 | addr: reg_base + CQSPI_REG_INDIRECTWR); |
1037 | /* |
1038 | * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access |
1039 | * Controller programming sequence, couple of cycles of |
1040 | * QSPI_REF_CLK delay is required for the above bit to |
1041 | * be internally synchronized by the QSPI module. Provide 5 |
1042 | * cycles of delay. |
1043 | */ |
1044 | if (cqspi->wr_delay) |
1045 | ndelay(cqspi->wr_delay); |
1046 | |
1047 | /* |
1048 | * If a hazard exists between the APB and AHB interfaces, perform a |
1049 | * dummy readback from the controller to ensure synchronization. |
1050 | */ |
1051 | if (cqspi->apb_ahb_hazard) |
1052 | readl(addr: reg_base + CQSPI_REG_INDIRECTWR); |
1053 | |
1054 | while (remaining > 0) { |
1055 | size_t write_words, mod_bytes; |
1056 | |
1057 | write_bytes = remaining; |
1058 | write_words = write_bytes / 4; |
1059 | mod_bytes = write_bytes % 4; |
1060 | /* Write 4 bytes at a time then single bytes. */ |
1061 | if (write_words) { |
1062 | iowrite32_rep(port: cqspi->ahb_base, buf: txbuf, count: write_words); |
1063 | txbuf += (write_words * 4); |
1064 | } |
1065 | if (mod_bytes) { |
1066 | unsigned int temp = 0xFFFFFFFF; |
1067 | |
1068 | memcpy(&temp, txbuf, mod_bytes); |
1069 | iowrite32(temp, cqspi->ahb_base); |
1070 | txbuf += mod_bytes; |
1071 | } |
1072 | |
1073 | if (!wait_for_completion_timeout(x: &cqspi->transfer_complete, |
1074 | timeout: msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { |
1075 | dev_err(dev, "Indirect write timeout\n" ); |
1076 | ret = -ETIMEDOUT; |
1077 | goto failwr; |
1078 | } |
1079 | |
1080 | remaining -= write_bytes; |
1081 | |
1082 | if (remaining > 0) |
1083 | reinit_completion(x: &cqspi->transfer_complete); |
1084 | } |
1085 | |
1086 | /* Check indirect done status */ |
1087 | ret = cqspi_wait_for_bit(reg: reg_base + CQSPI_REG_INDIRECTWR, |
1088 | CQSPI_REG_INDIRECTWR_DONE_MASK, clr: 0); |
1089 | if (ret) { |
1090 | dev_err(dev, "Indirect write completion error (%i)\n" , ret); |
1091 | goto failwr; |
1092 | } |
1093 | |
1094 | /* Disable interrupt. */ |
1095 | writel(val: 0, addr: reg_base + CQSPI_REG_IRQMASK); |
1096 | |
1097 | /* Clear indirect completion status */ |
1098 | writel(CQSPI_REG_INDIRECTWR_DONE_MASK, addr: reg_base + CQSPI_REG_INDIRECTWR); |
1099 | |
1100 | cqspi_wait_idle(cqspi); |
1101 | |
1102 | return 0; |
1103 | |
1104 | failwr: |
1105 | /* Disable interrupt. */ |
1106 | writel(val: 0, addr: reg_base + CQSPI_REG_IRQMASK); |
1107 | |
1108 | /* Cancel the indirect write */ |
1109 | writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, |
1110 | addr: reg_base + CQSPI_REG_INDIRECTWR); |
1111 | return ret; |
1112 | } |
1113 | |
1114 | static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) |
1115 | { |
1116 | struct cqspi_st *cqspi = f_pdata->cqspi; |
1117 | void __iomem *reg_base = cqspi->iobase; |
1118 | unsigned int chip_select = f_pdata->cs; |
1119 | unsigned int reg; |
1120 | |
1121 | reg = readl(addr: reg_base + CQSPI_REG_CONFIG); |
1122 | if (cqspi->is_decoded_cs) { |
1123 | reg |= CQSPI_REG_CONFIG_DECODE_MASK; |
1124 | } else { |
1125 | reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; |
1126 | |
1127 | /* Convert CS if without decoder. |
1128 | * CS0 to 4b'1110 |
1129 | * CS1 to 4b'1101 |
1130 | * CS2 to 4b'1011 |
1131 | * CS3 to 4b'0111 |
1132 | */ |
1133 | chip_select = 0xF & ~(1 << chip_select); |
1134 | } |
1135 | |
1136 | reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK |
1137 | << CQSPI_REG_CONFIG_CHIPSELECT_LSB); |
1138 | reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) |
1139 | << CQSPI_REG_CONFIG_CHIPSELECT_LSB; |
1140 | writel(val: reg, addr: reg_base + CQSPI_REG_CONFIG); |
1141 | } |
1142 | |
1143 | static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, |
1144 | const unsigned int ns_val) |
1145 | { |
1146 | unsigned int ticks; |
1147 | |
1148 | ticks = ref_clk_hz / 1000; /* kHz */ |
1149 | ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); |
1150 | |
1151 | return ticks; |
1152 | } |
1153 | |
1154 | static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) |
1155 | { |
1156 | struct cqspi_st *cqspi = f_pdata->cqspi; |
1157 | void __iomem *iobase = cqspi->iobase; |
1158 | const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; |
1159 | unsigned int tshsl, tchsh, tslch, tsd2d; |
1160 | unsigned int reg; |
1161 | unsigned int tsclk; |
1162 | |
1163 | /* calculate the number of ref ticks for one sclk tick */ |
1164 | tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); |
1165 | |
1166 | tshsl = calculate_ticks_for_ns(ref_clk_hz, ns_val: f_pdata->tshsl_ns); |
1167 | /* this particular value must be at least one sclk */ |
1168 | if (tshsl < tsclk) |
1169 | tshsl = tsclk; |
1170 | |
1171 | tchsh = calculate_ticks_for_ns(ref_clk_hz, ns_val: f_pdata->tchsh_ns); |
1172 | tslch = calculate_ticks_for_ns(ref_clk_hz, ns_val: f_pdata->tslch_ns); |
1173 | tsd2d = calculate_ticks_for_ns(ref_clk_hz, ns_val: f_pdata->tsd2d_ns); |
1174 | |
1175 | reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) |
1176 | << CQSPI_REG_DELAY_TSHSL_LSB; |
1177 | reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) |
1178 | << CQSPI_REG_DELAY_TCHSH_LSB; |
1179 | reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) |
1180 | << CQSPI_REG_DELAY_TSLCH_LSB; |
1181 | reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) |
1182 | << CQSPI_REG_DELAY_TSD2D_LSB; |
1183 | writel(val: reg, addr: iobase + CQSPI_REG_DELAY); |
1184 | } |
1185 | |
1186 | static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) |
1187 | { |
1188 | const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; |
1189 | void __iomem *reg_base = cqspi->iobase; |
1190 | u32 reg, div; |
1191 | |
1192 | /* Recalculate the baudrate divisor based on QSPI specification. */ |
1193 | div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; |
1194 | |
1195 | /* Maximum baud divisor */ |
1196 | if (div > CQSPI_REG_CONFIG_BAUD_MASK) { |
1197 | div = CQSPI_REG_CONFIG_BAUD_MASK; |
1198 | dev_warn(&cqspi->pdev->dev, |
1199 | "Unable to adjust clock <= %d hz. Reduced to %d hz\n" , |
1200 | cqspi->sclk, ref_clk_hz/((div+1)*2)); |
1201 | } |
1202 | |
1203 | reg = readl(addr: reg_base + CQSPI_REG_CONFIG); |
1204 | reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); |
1205 | reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; |
1206 | writel(val: reg, addr: reg_base + CQSPI_REG_CONFIG); |
1207 | } |
1208 | |
1209 | static void cqspi_readdata_capture(struct cqspi_st *cqspi, |
1210 | const bool bypass, |
1211 | const unsigned int delay) |
1212 | { |
1213 | void __iomem *reg_base = cqspi->iobase; |
1214 | unsigned int reg; |
1215 | |
1216 | reg = readl(addr: reg_base + CQSPI_REG_READCAPTURE); |
1217 | |
1218 | if (bypass) |
1219 | reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); |
1220 | else |
1221 | reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); |
1222 | |
1223 | reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK |
1224 | << CQSPI_REG_READCAPTURE_DELAY_LSB); |
1225 | |
1226 | reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) |
1227 | << CQSPI_REG_READCAPTURE_DELAY_LSB; |
1228 | |
1229 | writel(val: reg, addr: reg_base + CQSPI_REG_READCAPTURE); |
1230 | } |
1231 | |
1232 | static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, |
1233 | unsigned long sclk) |
1234 | { |
1235 | struct cqspi_st *cqspi = f_pdata->cqspi; |
1236 | int switch_cs = (cqspi->current_cs != f_pdata->cs); |
1237 | int switch_ck = (cqspi->sclk != sclk); |
1238 | |
1239 | if (switch_cs || switch_ck) |
1240 | cqspi_controller_enable(cqspi, enable: 0); |
1241 | |
1242 | /* Switch chip select. */ |
1243 | if (switch_cs) { |
1244 | cqspi->current_cs = f_pdata->cs; |
1245 | cqspi_chipselect(f_pdata); |
1246 | } |
1247 | |
1248 | /* Setup baudrate divisor and delays */ |
1249 | if (switch_ck) { |
1250 | cqspi->sclk = sclk; |
1251 | cqspi_config_baudrate_div(cqspi); |
1252 | cqspi_delay(f_pdata); |
1253 | cqspi_readdata_capture(cqspi, bypass: !cqspi->rclk_en, |
1254 | delay: f_pdata->read_delay); |
1255 | } |
1256 | |
1257 | if (switch_cs || switch_ck) |
1258 | cqspi_controller_enable(cqspi, enable: 1); |
1259 | } |
1260 | |
1261 | static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, |
1262 | const struct spi_mem_op *op) |
1263 | { |
1264 | struct cqspi_st *cqspi = f_pdata->cqspi; |
1265 | loff_t to = op->addr.val; |
1266 | size_t len = op->data.nbytes; |
1267 | const u_char *buf = op->data.buf.out; |
1268 | int ret; |
1269 | |
1270 | ret = cqspi_write_setup(f_pdata, op); |
1271 | if (ret) |
1272 | return ret; |
1273 | |
1274 | /* |
1275 | * Some flashes like the Cypress Semper flash expect a dummy 4-byte |
1276 | * address (all 0s) with the read status register command in DTR mode. |
1277 | * But this controller does not support sending dummy address bytes to |
1278 | * the flash when it is polling the write completion register in DTR |
1279 | * mode. So, we can not use direct mode when in DTR mode for writing |
1280 | * data. |
1281 | */ |
1282 | if (!op->cmd.dtr && cqspi->use_direct_mode && |
1283 | cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { |
1284 | memcpy_toio(cqspi->ahb_base + to, buf, len); |
1285 | return cqspi_wait_idle(cqspi); |
1286 | } |
1287 | |
1288 | return cqspi_indirect_write_execute(f_pdata, to_addr: to, txbuf: buf, n_tx: len); |
1289 | } |
1290 | |
1291 | static void cqspi_rx_dma_callback(void *param) |
1292 | { |
1293 | struct cqspi_st *cqspi = param; |
1294 | |
1295 | complete(&cqspi->rx_dma_complete); |
1296 | } |
1297 | |
1298 | static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, |
1299 | u_char *buf, loff_t from, size_t len) |
1300 | { |
1301 | struct cqspi_st *cqspi = f_pdata->cqspi; |
1302 | struct device *dev = &cqspi->pdev->dev; |
1303 | enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
1304 | dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; |
1305 | int ret = 0; |
1306 | struct dma_async_tx_descriptor *tx; |
1307 | dma_cookie_t cookie; |
1308 | dma_addr_t dma_dst; |
1309 | struct device *ddev; |
1310 | |
1311 | if (!cqspi->rx_chan || !virt_addr_valid(buf)) { |
1312 | memcpy_fromio(buf, cqspi->ahb_base + from, len); |
1313 | return 0; |
1314 | } |
1315 | |
1316 | ddev = cqspi->rx_chan->device->dev; |
1317 | dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); |
1318 | if (dma_mapping_error(dev: ddev, dma_addr: dma_dst)) { |
1319 | dev_err(dev, "dma mapping failed\n" ); |
1320 | return -ENOMEM; |
1321 | } |
1322 | tx = dmaengine_prep_dma_memcpy(chan: cqspi->rx_chan, dest: dma_dst, src: dma_src, |
1323 | len, flags); |
1324 | if (!tx) { |
1325 | dev_err(dev, "device_prep_dma_memcpy error\n" ); |
1326 | ret = -EIO; |
1327 | goto err_unmap; |
1328 | } |
1329 | |
1330 | tx->callback = cqspi_rx_dma_callback; |
1331 | tx->callback_param = cqspi; |
1332 | cookie = tx->tx_submit(tx); |
1333 | reinit_completion(x: &cqspi->rx_dma_complete); |
1334 | |
1335 | ret = dma_submit_error(cookie); |
1336 | if (ret) { |
1337 | dev_err(dev, "dma_submit_error %d\n" , cookie); |
1338 | ret = -EIO; |
1339 | goto err_unmap; |
1340 | } |
1341 | |
1342 | dma_async_issue_pending(chan: cqspi->rx_chan); |
1343 | if (!wait_for_completion_timeout(x: &cqspi->rx_dma_complete, |
1344 | timeout: msecs_to_jiffies(max_t(size_t, len, 500)))) { |
1345 | dmaengine_terminate_sync(chan: cqspi->rx_chan); |
1346 | dev_err(dev, "DMA wait_for_completion_timeout\n" ); |
1347 | ret = -ETIMEDOUT; |
1348 | goto err_unmap; |
1349 | } |
1350 | |
1351 | err_unmap: |
1352 | dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); |
1353 | |
1354 | return ret; |
1355 | } |
1356 | |
1357 | static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, |
1358 | const struct spi_mem_op *op) |
1359 | { |
1360 | struct cqspi_st *cqspi = f_pdata->cqspi; |
1361 | struct device *dev = &cqspi->pdev->dev; |
1362 | const struct cqspi_driver_platdata *ddata; |
1363 | loff_t from = op->addr.val; |
1364 | size_t len = op->data.nbytes; |
1365 | u_char *buf = op->data.buf.in; |
1366 | u64 dma_align = (u64)(uintptr_t)buf; |
1367 | int ret; |
1368 | |
1369 | ddata = of_device_get_match_data(dev); |
1370 | |
1371 | ret = cqspi_read_setup(f_pdata, op); |
1372 | if (ret) |
1373 | return ret; |
1374 | |
1375 | if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) |
1376 | return cqspi_direct_read_execute(f_pdata, buf, from, len); |
1377 | |
1378 | if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && |
1379 | virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) |
1380 | return ddata->indirect_read_dma(f_pdata, buf, from, len); |
1381 | |
1382 | return cqspi_indirect_read_execute(f_pdata, rxbuf: buf, from_addr: from, n_rx: len); |
1383 | } |
1384 | |
1385 | static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) |
1386 | { |
1387 | struct cqspi_st *cqspi = spi_controller_get_devdata(ctlr: mem->spi->controller); |
1388 | struct cqspi_flash_pdata *f_pdata; |
1389 | |
1390 | f_pdata = &cqspi->f_pdata[spi_get_chipselect(spi: mem->spi, idx: 0)]; |
1391 | cqspi_configure(f_pdata, sclk: mem->spi->max_speed_hz); |
1392 | |
1393 | if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { |
1394 | /* |
1395 | * Performing reads in DAC mode forces to read minimum 4 bytes |
1396 | * which is unsupported on some flash devices during register |
1397 | * reads, prefer STIG mode for such small reads. |
1398 | */ |
1399 | if (!op->addr.nbytes || |
1400 | op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) |
1401 | return cqspi_command_read(f_pdata, op); |
1402 | |
1403 | return cqspi_read(f_pdata, op); |
1404 | } |
1405 | |
1406 | if (!op->addr.nbytes || !op->data.buf.out) |
1407 | return cqspi_command_write(f_pdata, op); |
1408 | |
1409 | return cqspi_write(f_pdata, op); |
1410 | } |
1411 | |
1412 | static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) |
1413 | { |
1414 | int ret; |
1415 | struct cqspi_st *cqspi = spi_controller_get_devdata(ctlr: mem->spi->controller); |
1416 | struct device *dev = &cqspi->pdev->dev; |
1417 | |
1418 | ret = pm_runtime_resume_and_get(dev); |
1419 | if (ret) { |
1420 | dev_err(&mem->spi->dev, "resume failed with %d\n" , ret); |
1421 | return ret; |
1422 | } |
1423 | |
1424 | ret = cqspi_mem_process(mem, op); |
1425 | |
1426 | pm_runtime_mark_last_busy(dev); |
1427 | pm_runtime_put_autosuspend(dev); |
1428 | |
1429 | if (ret) |
1430 | dev_err(&mem->spi->dev, "operation failed with %d\n" , ret); |
1431 | |
1432 | return ret; |
1433 | } |
1434 | |
1435 | static bool cqspi_supports_mem_op(struct spi_mem *mem, |
1436 | const struct spi_mem_op *op) |
1437 | { |
1438 | bool all_true, all_false; |
1439 | |
1440 | /* |
1441 | * op->dummy.dtr is required for converting nbytes into ncycles. |
1442 | * Also, don't check the dtr field of the op phase having zero nbytes. |
1443 | */ |
1444 | all_true = op->cmd.dtr && |
1445 | (!op->addr.nbytes || op->addr.dtr) && |
1446 | (!op->dummy.nbytes || op->dummy.dtr) && |
1447 | (!op->data.nbytes || op->data.dtr); |
1448 | |
1449 | all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && |
1450 | !op->data.dtr; |
1451 | |
1452 | if (all_true) { |
1453 | /* Right now we only support 8-8-8 DTR mode. */ |
1454 | if (op->cmd.nbytes && op->cmd.buswidth != 8) |
1455 | return false; |
1456 | if (op->addr.nbytes && op->addr.buswidth != 8) |
1457 | return false; |
1458 | if (op->data.nbytes && op->data.buswidth != 8) |
1459 | return false; |
1460 | } else if (!all_false) { |
1461 | /* Mixed DTR modes are not supported. */ |
1462 | return false; |
1463 | } |
1464 | |
1465 | return spi_mem_default_supports_op(mem, op); |
1466 | } |
1467 | |
1468 | static int cqspi_of_get_flash_pdata(struct platform_device *pdev, |
1469 | struct cqspi_flash_pdata *f_pdata, |
1470 | struct device_node *np) |
1471 | { |
1472 | if (of_property_read_u32(np, propname: "cdns,read-delay" , out_value: &f_pdata->read_delay)) { |
1473 | dev_err(&pdev->dev, "couldn't determine read-delay\n" ); |
1474 | return -ENXIO; |
1475 | } |
1476 | |
1477 | if (of_property_read_u32(np, propname: "cdns,tshsl-ns" , out_value: &f_pdata->tshsl_ns)) { |
1478 | dev_err(&pdev->dev, "couldn't determine tshsl-ns\n" ); |
1479 | return -ENXIO; |
1480 | } |
1481 | |
1482 | if (of_property_read_u32(np, propname: "cdns,tsd2d-ns" , out_value: &f_pdata->tsd2d_ns)) { |
1483 | dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n" ); |
1484 | return -ENXIO; |
1485 | } |
1486 | |
1487 | if (of_property_read_u32(np, propname: "cdns,tchsh-ns" , out_value: &f_pdata->tchsh_ns)) { |
1488 | dev_err(&pdev->dev, "couldn't determine tchsh-ns\n" ); |
1489 | return -ENXIO; |
1490 | } |
1491 | |
1492 | if (of_property_read_u32(np, propname: "cdns,tslch-ns" , out_value: &f_pdata->tslch_ns)) { |
1493 | dev_err(&pdev->dev, "couldn't determine tslch-ns\n" ); |
1494 | return -ENXIO; |
1495 | } |
1496 | |
1497 | if (of_property_read_u32(np, propname: "spi-max-frequency" , out_value: &f_pdata->clk_rate)) { |
1498 | dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n" ); |
1499 | return -ENXIO; |
1500 | } |
1501 | |
1502 | return 0; |
1503 | } |
1504 | |
1505 | static int cqspi_of_get_pdata(struct cqspi_st *cqspi) |
1506 | { |
1507 | struct device *dev = &cqspi->pdev->dev; |
1508 | struct device_node *np = dev->of_node; |
1509 | u32 id[2]; |
1510 | |
1511 | cqspi->is_decoded_cs = of_property_read_bool(np, propname: "cdns,is-decoded-cs" ); |
1512 | |
1513 | if (of_property_read_u32(np, propname: "cdns,fifo-depth" , out_value: &cqspi->fifo_depth)) { |
1514 | dev_err(dev, "couldn't determine fifo-depth\n" ); |
1515 | return -ENXIO; |
1516 | } |
1517 | |
1518 | if (of_property_read_u32(np, propname: "cdns,fifo-width" , out_value: &cqspi->fifo_width)) { |
1519 | dev_err(dev, "couldn't determine fifo-width\n" ); |
1520 | return -ENXIO; |
1521 | } |
1522 | |
1523 | if (of_property_read_u32(np, propname: "cdns,trigger-address" , |
1524 | out_value: &cqspi->trigger_address)) { |
1525 | dev_err(dev, "couldn't determine trigger-address\n" ); |
1526 | return -ENXIO; |
1527 | } |
1528 | |
1529 | if (of_property_read_u32(np, propname: "num-cs" , out_value: &cqspi->num_chipselect)) |
1530 | cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; |
1531 | |
1532 | cqspi->rclk_en = of_property_read_bool(np, propname: "cdns,rclk-en" ); |
1533 | |
1534 | if (!of_property_read_u32_array(np, propname: "power-domains" , out_values: id, |
1535 | ARRAY_SIZE(id))) |
1536 | cqspi->pd_dev_id = id[1]; |
1537 | |
1538 | return 0; |
1539 | } |
1540 | |
1541 | static void cqspi_controller_init(struct cqspi_st *cqspi) |
1542 | { |
1543 | u32 reg; |
1544 | |
1545 | cqspi_controller_enable(cqspi, enable: 0); |
1546 | |
1547 | /* Configure the remap address register, no remap */ |
1548 | writel(val: 0, addr: cqspi->iobase + CQSPI_REG_REMAP); |
1549 | |
1550 | /* Disable all interrupts. */ |
1551 | writel(val: 0, addr: cqspi->iobase + CQSPI_REG_IRQMASK); |
1552 | |
1553 | /* Configure the SRAM split to 1:1 . */ |
1554 | writel(val: cqspi->fifo_depth / 2, addr: cqspi->iobase + CQSPI_REG_SRAMPARTITION); |
1555 | |
1556 | /* Load indirect trigger address. */ |
1557 | writel(val: cqspi->trigger_address, |
1558 | addr: cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); |
1559 | |
1560 | /* Program read watermark -- 1/2 of the FIFO. */ |
1561 | writel(val: cqspi->fifo_depth * cqspi->fifo_width / 2, |
1562 | addr: cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); |
1563 | /* Program write watermark -- 1/8 of the FIFO. */ |
1564 | writel(val: cqspi->fifo_depth * cqspi->fifo_width / 8, |
1565 | addr: cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); |
1566 | |
1567 | /* Disable direct access controller */ |
1568 | if (!cqspi->use_direct_mode) { |
1569 | reg = readl(addr: cqspi->iobase + CQSPI_REG_CONFIG); |
1570 | reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; |
1571 | writel(val: reg, addr: cqspi->iobase + CQSPI_REG_CONFIG); |
1572 | } |
1573 | |
1574 | /* Enable DMA interface */ |
1575 | if (cqspi->use_dma_read) { |
1576 | reg = readl(addr: cqspi->iobase + CQSPI_REG_CONFIG); |
1577 | reg |= CQSPI_REG_CONFIG_DMA_MASK; |
1578 | writel(val: reg, addr: cqspi->iobase + CQSPI_REG_CONFIG); |
1579 | } |
1580 | |
1581 | cqspi_controller_enable(cqspi, enable: 1); |
1582 | } |
1583 | |
1584 | static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) |
1585 | { |
1586 | dma_cap_mask_t mask; |
1587 | |
1588 | dma_cap_zero(mask); |
1589 | dma_cap_set(DMA_MEMCPY, mask); |
1590 | |
1591 | cqspi->rx_chan = dma_request_chan_by_mask(mask: &mask); |
1592 | if (IS_ERR(ptr: cqspi->rx_chan)) { |
1593 | int ret = PTR_ERR(ptr: cqspi->rx_chan); |
1594 | |
1595 | cqspi->rx_chan = NULL; |
1596 | return dev_err_probe(dev: &cqspi->pdev->dev, err: ret, fmt: "No Rx DMA available\n" ); |
1597 | } |
1598 | init_completion(x: &cqspi->rx_dma_complete); |
1599 | |
1600 | return 0; |
1601 | } |
1602 | |
1603 | static const char *cqspi_get_name(struct spi_mem *mem) |
1604 | { |
1605 | struct cqspi_st *cqspi = spi_controller_get_devdata(ctlr: mem->spi->controller); |
1606 | struct device *dev = &cqspi->pdev->dev; |
1607 | |
1608 | return devm_kasprintf(dev, GFP_KERNEL, fmt: "%s.%d" , dev_name(dev), |
1609 | spi_get_chipselect(spi: mem->spi, idx: 0)); |
1610 | } |
1611 | |
1612 | static const struct spi_controller_mem_ops cqspi_mem_ops = { |
1613 | .exec_op = cqspi_exec_mem_op, |
1614 | .get_name = cqspi_get_name, |
1615 | .supports_op = cqspi_supports_mem_op, |
1616 | }; |
1617 | |
1618 | static const struct spi_controller_mem_caps cqspi_mem_caps = { |
1619 | .dtr = true, |
1620 | }; |
1621 | |
1622 | static int cqspi_setup_flash(struct cqspi_st *cqspi) |
1623 | { |
1624 | unsigned int max_cs = cqspi->num_chipselect - 1; |
1625 | struct platform_device *pdev = cqspi->pdev; |
1626 | struct device *dev = &pdev->dev; |
1627 | struct device_node *np = dev->of_node; |
1628 | struct cqspi_flash_pdata *f_pdata; |
1629 | unsigned int cs; |
1630 | int ret; |
1631 | |
1632 | /* Get flash device data */ |
1633 | for_each_available_child_of_node(dev->of_node, np) { |
1634 | ret = of_property_read_u32(np, propname: "reg" , out_value: &cs); |
1635 | if (ret) { |
1636 | dev_err(dev, "Couldn't determine chip select.\n" ); |
1637 | of_node_put(node: np); |
1638 | return ret; |
1639 | } |
1640 | |
1641 | if (cs >= cqspi->num_chipselect) { |
1642 | dev_err(dev, "Chip select %d out of range.\n" , cs); |
1643 | of_node_put(node: np); |
1644 | return -EINVAL; |
1645 | } else if (cs < max_cs) { |
1646 | max_cs = cs; |
1647 | } |
1648 | |
1649 | f_pdata = &cqspi->f_pdata[cs]; |
1650 | f_pdata->cqspi = cqspi; |
1651 | f_pdata->cs = cs; |
1652 | |
1653 | ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); |
1654 | if (ret) { |
1655 | of_node_put(node: np); |
1656 | return ret; |
1657 | } |
1658 | } |
1659 | |
1660 | cqspi->num_chipselect = max_cs + 1; |
1661 | return 0; |
1662 | } |
1663 | |
1664 | static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi) |
1665 | { |
1666 | static struct clk_bulk_data qspiclk[] = { |
1667 | { .id = "apb" }, |
1668 | { .id = "ahb" }, |
1669 | }; |
1670 | |
1671 | int ret = 0; |
1672 | |
1673 | ret = devm_clk_bulk_get(dev: &pdev->dev, ARRAY_SIZE(qspiclk), clks: qspiclk); |
1674 | if (ret) { |
1675 | dev_err(&pdev->dev, "%s: failed to get qspi clocks\n" , __func__); |
1676 | return ret; |
1677 | } |
1678 | |
1679 | cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; |
1680 | cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; |
1681 | |
1682 | ret = clk_prepare_enable(clk: cqspi->clks[CLK_QSPI_APB]); |
1683 | if (ret) { |
1684 | dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n" , __func__); |
1685 | return ret; |
1686 | } |
1687 | |
1688 | ret = clk_prepare_enable(clk: cqspi->clks[CLK_QSPI_AHB]); |
1689 | if (ret) { |
1690 | dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n" , __func__); |
1691 | goto disable_apb_clk; |
1692 | } |
1693 | |
1694 | cqspi->is_jh7110 = true; |
1695 | |
1696 | return 0; |
1697 | |
1698 | disable_apb_clk: |
1699 | clk_disable_unprepare(clk: cqspi->clks[CLK_QSPI_APB]); |
1700 | |
1701 | return ret; |
1702 | } |
1703 | |
1704 | static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi) |
1705 | { |
1706 | clk_disable_unprepare(clk: cqspi->clks[CLK_QSPI_AHB]); |
1707 | clk_disable_unprepare(clk: cqspi->clks[CLK_QSPI_APB]); |
1708 | } |
1709 | static int cqspi_probe(struct platform_device *pdev) |
1710 | { |
1711 | const struct cqspi_driver_platdata *ddata; |
1712 | struct reset_control *rstc, *rstc_ocp, *rstc_ref; |
1713 | struct device *dev = &pdev->dev; |
1714 | struct spi_controller *host; |
1715 | struct resource *res_ahb; |
1716 | struct cqspi_st *cqspi; |
1717 | int ret; |
1718 | int irq; |
1719 | |
1720 | host = devm_spi_alloc_host(dev: &pdev->dev, size: sizeof(*cqspi)); |
1721 | if (!host) |
1722 | return -ENOMEM; |
1723 | |
1724 | host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; |
1725 | host->mem_ops = &cqspi_mem_ops; |
1726 | host->mem_caps = &cqspi_mem_caps; |
1727 | host->dev.of_node = pdev->dev.of_node; |
1728 | |
1729 | cqspi = spi_controller_get_devdata(ctlr: host); |
1730 | |
1731 | cqspi->pdev = pdev; |
1732 | cqspi->host = host; |
1733 | cqspi->is_jh7110 = false; |
1734 | platform_set_drvdata(pdev, data: cqspi); |
1735 | |
1736 | /* Obtain configuration from OF. */ |
1737 | ret = cqspi_of_get_pdata(cqspi); |
1738 | if (ret) { |
1739 | dev_err(dev, "Cannot get mandatory OF data.\n" ); |
1740 | return -ENODEV; |
1741 | } |
1742 | |
1743 | /* Obtain QSPI clock. */ |
1744 | cqspi->clk = devm_clk_get(dev, NULL); |
1745 | if (IS_ERR(ptr: cqspi->clk)) { |
1746 | dev_err(dev, "Cannot claim QSPI clock.\n" ); |
1747 | ret = PTR_ERR(ptr: cqspi->clk); |
1748 | return ret; |
1749 | } |
1750 | |
1751 | /* Obtain and remap controller address. */ |
1752 | cqspi->iobase = devm_platform_ioremap_resource(pdev, index: 0); |
1753 | if (IS_ERR(ptr: cqspi->iobase)) { |
1754 | dev_err(dev, "Cannot remap controller address.\n" ); |
1755 | ret = PTR_ERR(ptr: cqspi->iobase); |
1756 | return ret; |
1757 | } |
1758 | |
1759 | /* Obtain and remap AHB address. */ |
1760 | cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, index: 1, res: &res_ahb); |
1761 | if (IS_ERR(ptr: cqspi->ahb_base)) { |
1762 | dev_err(dev, "Cannot remap AHB address.\n" ); |
1763 | ret = PTR_ERR(ptr: cqspi->ahb_base); |
1764 | return ret; |
1765 | } |
1766 | cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; |
1767 | cqspi->ahb_size = resource_size(res: res_ahb); |
1768 | |
1769 | init_completion(x: &cqspi->transfer_complete); |
1770 | |
1771 | /* Obtain IRQ line. */ |
1772 | irq = platform_get_irq(pdev, 0); |
1773 | if (irq < 0) |
1774 | return -ENXIO; |
1775 | |
1776 | ret = pm_runtime_set_active(dev); |
1777 | if (ret) |
1778 | return ret; |
1779 | |
1780 | |
1781 | ret = clk_prepare_enable(clk: cqspi->clk); |
1782 | if (ret) { |
1783 | dev_err(dev, "Cannot enable QSPI clock.\n" ); |
1784 | goto probe_clk_failed; |
1785 | } |
1786 | |
1787 | /* Obtain QSPI reset control */ |
1788 | rstc = devm_reset_control_get_optional_exclusive(dev, id: "qspi" ); |
1789 | if (IS_ERR(ptr: rstc)) { |
1790 | ret = PTR_ERR(ptr: rstc); |
1791 | dev_err(dev, "Cannot get QSPI reset.\n" ); |
1792 | goto probe_reset_failed; |
1793 | } |
1794 | |
1795 | rstc_ocp = devm_reset_control_get_optional_exclusive(dev, id: "qspi-ocp" ); |
1796 | if (IS_ERR(ptr: rstc_ocp)) { |
1797 | ret = PTR_ERR(ptr: rstc_ocp); |
1798 | dev_err(dev, "Cannot get QSPI OCP reset.\n" ); |
1799 | goto probe_reset_failed; |
1800 | } |
1801 | |
1802 | if (of_device_is_compatible(device: pdev->dev.of_node, "starfive,jh7110-qspi" )) { |
1803 | rstc_ref = devm_reset_control_get_optional_exclusive(dev, id: "rstc_ref" ); |
1804 | if (IS_ERR(ptr: rstc_ref)) { |
1805 | ret = PTR_ERR(ptr: rstc_ref); |
1806 | dev_err(dev, "Cannot get QSPI REF reset.\n" ); |
1807 | goto probe_reset_failed; |
1808 | } |
1809 | reset_control_assert(rstc: rstc_ref); |
1810 | reset_control_deassert(rstc: rstc_ref); |
1811 | } |
1812 | |
1813 | reset_control_assert(rstc); |
1814 | reset_control_deassert(rstc); |
1815 | |
1816 | reset_control_assert(rstc: rstc_ocp); |
1817 | reset_control_deassert(rstc: rstc_ocp); |
1818 | |
1819 | cqspi->master_ref_clk_hz = clk_get_rate(clk: cqspi->clk); |
1820 | host->max_speed_hz = cqspi->master_ref_clk_hz; |
1821 | |
1822 | /* write completion is supported by default */ |
1823 | cqspi->wr_completion = true; |
1824 | |
1825 | ddata = of_device_get_match_data(dev); |
1826 | if (ddata) { |
1827 | if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) |
1828 | cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, |
1829 | cqspi->master_ref_clk_hz); |
1830 | if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) |
1831 | host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; |
1832 | if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { |
1833 | cqspi->use_direct_mode = true; |
1834 | cqspi->use_direct_mode_wr = true; |
1835 | } |
1836 | if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) |
1837 | cqspi->use_dma_read = true; |
1838 | if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) |
1839 | cqspi->wr_completion = false; |
1840 | if (ddata->quirks & CQSPI_SLOW_SRAM) |
1841 | cqspi->slow_sram = true; |
1842 | if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) |
1843 | cqspi->apb_ahb_hazard = true; |
1844 | |
1845 | if (ddata->jh7110_clk_init) { |
1846 | ret = cqspi_jh7110_clk_init(pdev, cqspi); |
1847 | if (ret) |
1848 | goto probe_reset_failed; |
1849 | } |
1850 | |
1851 | if (of_device_is_compatible(device: pdev->dev.of_node, |
1852 | "xlnx,versal-ospi-1.0" )) { |
1853 | ret = dma_set_mask(dev: &pdev->dev, DMA_BIT_MASK(64)); |
1854 | if (ret) |
1855 | goto probe_reset_failed; |
1856 | } |
1857 | } |
1858 | |
1859 | ret = devm_request_irq(dev, irq, handler: cqspi_irq_handler, irqflags: 0, |
1860 | devname: pdev->name, dev_id: cqspi); |
1861 | if (ret) { |
1862 | dev_err(dev, "Cannot request IRQ.\n" ); |
1863 | goto probe_reset_failed; |
1864 | } |
1865 | |
1866 | cqspi_wait_idle(cqspi); |
1867 | cqspi_controller_init(cqspi); |
1868 | cqspi->current_cs = -1; |
1869 | cqspi->sclk = 0; |
1870 | |
1871 | ret = cqspi_setup_flash(cqspi); |
1872 | if (ret) { |
1873 | dev_err(dev, "failed to setup flash parameters %d\n" , ret); |
1874 | goto probe_setup_failed; |
1875 | } |
1876 | |
1877 | host->num_chipselect = cqspi->num_chipselect; |
1878 | |
1879 | if (cqspi->use_direct_mode) { |
1880 | ret = cqspi_request_mmap_dma(cqspi); |
1881 | if (ret == -EPROBE_DEFER) |
1882 | goto probe_setup_failed; |
1883 | } |
1884 | |
1885 | ret = devm_pm_runtime_enable(dev); |
1886 | if (ret) { |
1887 | if (cqspi->rx_chan) |
1888 | dma_release_channel(chan: cqspi->rx_chan); |
1889 | goto probe_setup_failed; |
1890 | } |
1891 | |
1892 | pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT); |
1893 | pm_runtime_use_autosuspend(dev); |
1894 | pm_runtime_get_noresume(dev); |
1895 | |
1896 | ret = spi_register_controller(ctlr: host); |
1897 | if (ret) { |
1898 | dev_err(&pdev->dev, "failed to register SPI ctlr %d\n" , ret); |
1899 | goto probe_setup_failed; |
1900 | } |
1901 | |
1902 | pm_runtime_mark_last_busy(dev); |
1903 | pm_runtime_put_autosuspend(dev); |
1904 | |
1905 | return 0; |
1906 | probe_setup_failed: |
1907 | cqspi_controller_enable(cqspi, enable: 0); |
1908 | probe_reset_failed: |
1909 | if (cqspi->is_jh7110) |
1910 | cqspi_jh7110_disable_clk(pdev, cqspi); |
1911 | clk_disable_unprepare(clk: cqspi->clk); |
1912 | probe_clk_failed: |
1913 | return ret; |
1914 | } |
1915 | |
1916 | static void cqspi_remove(struct platform_device *pdev) |
1917 | { |
1918 | struct cqspi_st *cqspi = platform_get_drvdata(pdev); |
1919 | |
1920 | spi_unregister_controller(ctlr: cqspi->host); |
1921 | cqspi_controller_enable(cqspi, enable: 0); |
1922 | |
1923 | if (cqspi->rx_chan) |
1924 | dma_release_channel(chan: cqspi->rx_chan); |
1925 | |
1926 | clk_disable_unprepare(clk: cqspi->clk); |
1927 | |
1928 | if (cqspi->is_jh7110) |
1929 | cqspi_jh7110_disable_clk(pdev, cqspi); |
1930 | |
1931 | pm_runtime_put_sync(dev: &pdev->dev); |
1932 | pm_runtime_disable(dev: &pdev->dev); |
1933 | } |
1934 | |
1935 | static int cqspi_runtime_suspend(struct device *dev) |
1936 | { |
1937 | struct cqspi_st *cqspi = dev_get_drvdata(dev); |
1938 | |
1939 | cqspi_controller_enable(cqspi, enable: 0); |
1940 | clk_disable_unprepare(clk: cqspi->clk); |
1941 | return 0; |
1942 | } |
1943 | |
1944 | static int cqspi_runtime_resume(struct device *dev) |
1945 | { |
1946 | struct cqspi_st *cqspi = dev_get_drvdata(dev); |
1947 | |
1948 | clk_prepare_enable(clk: cqspi->clk); |
1949 | cqspi_wait_idle(cqspi); |
1950 | cqspi_controller_init(cqspi); |
1951 | |
1952 | cqspi->current_cs = -1; |
1953 | cqspi->sclk = 0; |
1954 | return 0; |
1955 | } |
1956 | |
1957 | static int cqspi_suspend(struct device *dev) |
1958 | { |
1959 | struct cqspi_st *cqspi = dev_get_drvdata(dev); |
1960 | |
1961 | return spi_controller_suspend(ctlr: cqspi->host); |
1962 | } |
1963 | |
1964 | static int cqspi_resume(struct device *dev) |
1965 | { |
1966 | struct cqspi_st *cqspi = dev_get_drvdata(dev); |
1967 | |
1968 | return spi_controller_resume(ctlr: cqspi->host); |
1969 | } |
1970 | |
1971 | static const struct dev_pm_ops cqspi_dev_pm_ops = { |
1972 | RUNTIME_PM_OPS(cqspi_runtime_suspend, cqspi_runtime_resume, NULL) |
1973 | SYSTEM_SLEEP_PM_OPS(cqspi_suspend, cqspi_resume) |
1974 | }; |
1975 | |
1976 | static const struct cqspi_driver_platdata cdns_qspi = { |
1977 | .quirks = CQSPI_DISABLE_DAC_MODE, |
1978 | }; |
1979 | |
1980 | static const struct cqspi_driver_platdata k2g_qspi = { |
1981 | .quirks = CQSPI_NEEDS_WR_DELAY, |
1982 | }; |
1983 | |
1984 | static const struct cqspi_driver_platdata am654_ospi = { |
1985 | .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, |
1986 | .quirks = CQSPI_NEEDS_WR_DELAY, |
1987 | }; |
1988 | |
1989 | static const struct cqspi_driver_platdata intel_lgm_qspi = { |
1990 | .quirks = CQSPI_DISABLE_DAC_MODE, |
1991 | }; |
1992 | |
1993 | static const struct cqspi_driver_platdata socfpga_qspi = { |
1994 | .quirks = CQSPI_DISABLE_DAC_MODE |
1995 | | CQSPI_NO_SUPPORT_WR_COMPLETION |
1996 | | CQSPI_SLOW_SRAM, |
1997 | }; |
1998 | |
1999 | static const struct cqspi_driver_platdata versal_ospi = { |
2000 | .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, |
2001 | .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, |
2002 | .indirect_read_dma = cqspi_versal_indirect_read_dma, |
2003 | .get_dma_status = cqspi_get_versal_dma_status, |
2004 | }; |
2005 | |
2006 | static const struct cqspi_driver_platdata jh7110_qspi = { |
2007 | .quirks = CQSPI_DISABLE_DAC_MODE, |
2008 | .jh7110_clk_init = cqspi_jh7110_clk_init, |
2009 | }; |
2010 | |
2011 | static const struct cqspi_driver_platdata pensando_cdns_qspi = { |
2012 | .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, |
2013 | }; |
2014 | |
2015 | static const struct of_device_id cqspi_dt_ids[] = { |
2016 | { |
2017 | .compatible = "cdns,qspi-nor" , |
2018 | .data = &cdns_qspi, |
2019 | }, |
2020 | { |
2021 | .compatible = "ti,k2g-qspi" , |
2022 | .data = &k2g_qspi, |
2023 | }, |
2024 | { |
2025 | .compatible = "ti,am654-ospi" , |
2026 | .data = &am654_ospi, |
2027 | }, |
2028 | { |
2029 | .compatible = "intel,lgm-qspi" , |
2030 | .data = &intel_lgm_qspi, |
2031 | }, |
2032 | { |
2033 | .compatible = "xlnx,versal-ospi-1.0" , |
2034 | .data = &versal_ospi, |
2035 | }, |
2036 | { |
2037 | .compatible = "intel,socfpga-qspi" , |
2038 | .data = &socfpga_qspi, |
2039 | }, |
2040 | { |
2041 | .compatible = "starfive,jh7110-qspi" , |
2042 | .data = &jh7110_qspi, |
2043 | }, |
2044 | { |
2045 | .compatible = "amd,pensando-elba-qspi" , |
2046 | .data = &pensando_cdns_qspi, |
2047 | }, |
2048 | { /* end of table */ } |
2049 | }; |
2050 | |
2051 | MODULE_DEVICE_TABLE(of, cqspi_dt_ids); |
2052 | |
2053 | static struct platform_driver cqspi_platform_driver = { |
2054 | .probe = cqspi_probe, |
2055 | .remove_new = cqspi_remove, |
2056 | .driver = { |
2057 | .name = CQSPI_NAME, |
2058 | .pm = pm_ptr(&cqspi_dev_pm_ops), |
2059 | .of_match_table = cqspi_dt_ids, |
2060 | }, |
2061 | }; |
2062 | |
2063 | module_platform_driver(cqspi_platform_driver); |
2064 | |
2065 | MODULE_DESCRIPTION("Cadence QSPI Controller Driver" ); |
2066 | MODULE_LICENSE("GPL v2" ); |
2067 | MODULE_ALIAS("platform:" CQSPI_NAME); |
2068 | MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>" ); |
2069 | MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>" ); |
2070 | MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>" ); |
2071 | MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>" ); |
2072 | MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>" ); |
2073 | |