1	/*
2	* drivers/video/aty/radeon_base.c
3	*
4	* framebuffer driver for ATI Radeon chipset video boards
5	*
6	* Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7	* Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8	*
9	* i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10	*
11	* Special thanks to ATI DevRel team for their hardware donations.
12	*
13	* ...Insert GPL boilerplate here...
14	*
15	* Significant portions of this driver apdated from XFree86 Radeon
16	* driver which has the following copyright notice:
17	*
18	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19	* VA Linux Systems Inc., Fremont, California.
20	*
21	* All Rights Reserved.
22	*
23	* Permission is hereby granted, free of charge, to any person obtaining
24	* a copy of this software and associated documentation files (the
25	* "Software"), to deal in the Software without restriction, including
26	* without limitation on the rights to use, copy, modify, merge,
27	* publish, distribute, sublicense, and/or sell copies of the Software,
28	* and to permit persons to whom the Software is furnished to do so,
29	* subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice (including the
32	* next paragraph) shall be included in all copies or substantial
33	* portions of the Software.
34	*
35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38	* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39	* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42	* DEALINGS IN THE SOFTWARE.
43	*
44	* XFree86 driver authors:
45	*
46	* Kevin E. Martin <martin@xfree86.org>
47	* Rickard E. Faith <faith@valinux.com>
48	* Alan Hourihane <alanh@fairlite.demon.co.uk>
49	*
50	*/
51
52
53	#define RADEON_VERSION "0.2.0"
54
55	#include "radeonfb.h"
56
57	#include <linux/aperture.h>
58	#include <linux/module.h>
59	#include <linux/moduleparam.h>
60	#include <linux/kernel.h>
61	#include <linux/errno.h>
62	#include <linux/string.h>
63	#include <linux/ctype.h>
64	#include <linux/mm.h>
65	#include <linux/slab.h>
66	#include <linux/delay.h>
67	#include <linux/time.h>
68	#include <linux/fb.h>
69	#include <linux/ioport.h>
70	#include <linux/init.h>
71	#include <linux/pci.h>
72	#include <linux/vmalloc.h>
73	#include <linux/device.h>
74
75	#include <asm/io.h>
76	#include <linux/uaccess.h>
77
78	#ifdef CONFIG_PPC
79
80	#include "../macmodes.h"
81
82	#ifdef CONFIG_BOOTX_TEXT
83	#include <asm/btext.h>
84	#endif
85
86	#endif /* CONFIG_PPC */
87
88	#include <video/radeon.h>
89	#include <linux/radeonfb.h>
90
91	#include "../edid.h" // MOVE THAT TO include/video
92	#include "ati_ids.h"
93
94	#define MAX_MAPPED_VRAM (2048*2048*4)
95	#define MIN_MAPPED_VRAM (1024*768*1)
96
97	#define CHIP_DEF(id, family, flags) \
98	{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
99
100	static const struct pci_device_id radeonfb_pci_table[] = {
101	/* Radeon Xpress 200m */
102	CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
103	CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
104	/* Mobility M6 */
105	CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
106	CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
107	/* Radeon VE/7000 */
108	CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
109	CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
110	CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
111	/* Radeon IGP320M (U1) */
112	CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
113	/* Radeon IGP320 (A3) */
114	CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
115	/* IGP330M/340M/350M (U2) */
116	CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117	/* IGP330/340/350 (A4) */
118	CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119	/* Mobility 7000 IGP */
120	CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121	/* 7000 IGP (A4+) */
122	CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123	/* 8500 AIW */
124	CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
125	CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
126	/* 8700/8800 */
127	CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
128	/* 8500 */
129	CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
130	/* 9100 */
131	CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
132	/* Mobility M7 */
133	CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
134	CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
135	/* 7500 */
136	CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
137	CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
138	/* Mobility M9 */
139	CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140	CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141	CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142	CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
143	/* 9000/Pro */
144	CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
145	CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
146
147	CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
148	/* Mobility 9100 IGP (U3) */
149	CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150	CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
151	/* 9100 IGP (A5) */
152	CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
153	CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
154	/* Mobility 9200 (M9+) */
155	CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156	CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
157	/* 9200 */
158	CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
159	CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
160	CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
161	CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
162	/* 9500 */
163	CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
164	CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
165	/* 9600TX / FireGL Z1 */
166	CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
167	CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
168	/* 9700/9500/Pro/FireGL X1 */
169	CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
170	CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
171	CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
172	CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
173	/* Mobility M10/M11 */
174	CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175	CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176	CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177	CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178	CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179	CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180	/* 9600/FireGL T2 */
181	CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
182	CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
183	CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
184	CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
185	CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
186	CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
187	/* 9800/Pro/FileGL X2 */
188	CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
189	CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
190	CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
191	CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
192	CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
193	CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
194	CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
195	CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
196	/* Newer stuff */
197	CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
198	CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
199	CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
200	CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
201	CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
202	CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
203	CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
204	CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
205	CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
206	CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
207	CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
208	CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
209	CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
210	CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
211	CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
212	CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
213	CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
214	CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
215	CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
216	CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
217	CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
218	CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
219	CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
220	CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
221	CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
222	CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
223	CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
224	/* Original Radeon/7200 */
225	CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
226	CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
227	CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
228	CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
229	{ 0, }
230	};
231	MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
232
233
234	typedef struct {
235	u16 reg;
236	u32 val;
237	} reg_val;
238
239
240	/* these common regs are cleared before mode setting so they do not
241	* interfere with anything
242	*/
243	static reg_val common_regs[] = {
244	{ OVR_CLR, 0 },
245	{ OVR_WID_LEFT_RIGHT, 0 },
246	{ OVR_WID_TOP_BOTTOM, 0 },
247	{ OV0_SCALE_CNTL, 0 },
248	{ SUBPIC_CNTL, 0 },
249	{ VIPH_CONTROL, 0 },
250	{ I2C_CNTL_1, 0 },
251	{ GEN_INT_CNTL, 0 },
252	{ CAP0_TRIG_CNTL, 0 },
253	{ CAP1_TRIG_CNTL, 0 },
254	};
255
256	/*
257	* globals
258	*/
259
260	static char *mode_option;
261	static char *monitor_layout;
262	static bool noaccel = 0;
263	static int default_dynclk = -2;
264	static bool nomodeset = 0;
265	static bool ignore_edid = 0;
266	static bool mirror = 0;
267	static int panel_yres = 0;
268	static bool force_dfp = 0;
269	static bool force_measure_pll = 0;
270	static bool nomtrr = 0;
271	static bool force_sleep;
272	static bool ignore_devlist;
273	static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
274
275	/* Note about this function: we have some rare cases where we must not schedule,
276	* this typically happen with our special "wake up early" hook which allows us to
277	* wake up the graphic chip (and thus get the console back) before everything else
278	* on some machines that support that mechanism. At this point, interrupts are off
279	* and scheduling is not permitted
280	*/
281	void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
282	{
283	if (rinfo->no_schedule || oops_in_progress)
284	mdelay(ms);
285	else
286	msleep(msecs: ms);
287	}
288
289	void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo)
290	{
291	/* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */
292	(void)INREG(CLOCK_CNTL_DATA);
293	(void)INREG(CRTC_GEN_CNTL);
294	}
295
296	void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo)
297	{
298	if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
299	/* we can't deal with posted writes here ... */
300	_radeon_msleep(rinfo, ms: 5);
301	}
302	if (rinfo->errata & CHIP_ERRATA_R300_CG) {
303	u32 save, tmp;
304	save = INREG(CLOCK_CNTL_INDEX);
305	tmp = save & ~(0x3f | PLL_WR_EN);
306	OUTREG(CLOCK_CNTL_INDEX, tmp);
307	tmp = INREG(CLOCK_CNTL_DATA);
308	OUTREG(CLOCK_CNTL_INDEX, save);
309	}
310	}
311
312	void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask)
313	{
314	unsigned long flags;
315	unsigned int tmp;
316
317	spin_lock_irqsave(&rinfo->reg_lock, flags);
318	tmp = INREG(addr);
319	tmp &= (mask);
320	tmp |= (val);
321	OUTREG(addr, tmp);
322	spin_unlock_irqrestore(lock: &rinfo->reg_lock, flags);
323	}
324
325	u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
326	{
327	u32 data;
328
329	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
330	radeon_pll_errata_after_index(rinfo);
331	data = INREG(CLOCK_CNTL_DATA);
332	radeon_pll_errata_after_data(rinfo);
333	return data;
334	}
335
336	void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
337	{
338	OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
339	radeon_pll_errata_after_index(rinfo);
340	OUTREG(CLOCK_CNTL_DATA, val);
341	radeon_pll_errata_after_data(rinfo);
342	}
343
344	void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
345	u32 val, u32 mask)
346	{
347	unsigned int tmp;
348
349	tmp = __INPLL(rinfo, addr: index);
350	tmp &= (mask);
351	tmp |= (val);
352	__OUTPLL(rinfo, index, val: tmp);
353	}
354
355	void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
356	{
357	int i;
358
359	for (i=0; i<2000000; i++) {
360	if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
361	return;
362	udelay(1);
363	}
364	printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
365	}
366
367	void radeon_engine_flush(struct radeonfb_info *rinfo)
368	{
369	int i;
370
371	/* Initiate flush */
372	OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
373	~RB2D_DC_FLUSH_ALL);
374
375	/* Ensure FIFO is empty, ie, make sure the flush commands
376	* has reached the cache
377	*/
378	_radeon_fifo_wait(rinfo, entries: 64);
379
380	/* Wait for the flush to complete */
381	for (i=0; i < 2000000; i++) {
382	if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
383	return;
384	udelay(1);
385	}
386	printk(KERN_ERR "radeonfb: Flush Timeout !\n");
387	}
388
389	void _radeon_engine_idle(struct radeonfb_info *rinfo)
390	{
391	int i;
392
393	/* ensure FIFO is empty before waiting for idle */
394	_radeon_fifo_wait(rinfo, entries: 64);
395
396	for (i=0; i<2000000; i++) {
397	if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
398	radeon_engine_flush(rinfo);
399	return;
400	}
401	udelay(1);
402	}
403	printk(KERN_ERR "radeonfb: Idle Timeout !\n");
404	}
405
406
407
408	static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
409	{
410	if (!rinfo->bios_seg)
411	return;
412	pci_unmap_rom(pdev: dev, rom: rinfo->bios_seg);
413	}
414
415	static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
416	{
417	void __iomem *rom;
418	u16 dptr;
419	u8 rom_type;
420	size_t rom_size;
421
422	/* If this is a primary card, there is a shadow copy of the
423	* ROM somewhere in the first meg. We will just ignore the copy
424	* and use the ROM directly.
425	*/
426
427	/* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
428	unsigned int temp;
429	temp = INREG(MPP_TB_CONFIG);
430	temp &= 0x00ffffffu;
431	temp |= 0x04 << 24;
432	OUTREG(MPP_TB_CONFIG, temp);
433	temp = INREG(MPP_TB_CONFIG);
434
435	rom = pci_map_rom(pdev: dev, size: &rom_size);
436	if (!rom) {
437	printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
438	pci_name(rinfo->pdev));
439	return -ENOMEM;
440	}
441
442	rinfo->bios_seg = rom;
443
444	/* Very simple test to make sure it appeared */
445	if (BIOS_IN16(0) != 0xaa55) {
446	printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
447	"should be 0xaa55\n",
448	pci_name(rinfo->pdev), BIOS_IN16(0));
449	goto failed;
450	}
451	/* Look for the PCI data to check the ROM type */
452	dptr = BIOS_IN16(0x18);
453
454	/* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
455	* for now, until I've verified this works everywhere. The goal here is more
456	* to phase out Open Firmware images.
457	*
458	* Currently, we only look at the first PCI data, we could iteratre and deal with
459	* them all, and we should use fb_bios_start relative to start of image and not
460	* relative start of ROM, but so far, I never found a dual-image ATI card
461	*
462	* typedef struct {
463	* u32 signature; + 0x00
464	* u16 vendor; + 0x04
465	* u16 device; + 0x06
466	* u16 reserved_1; + 0x08
467	* u16 dlen; + 0x0a
468	* u8 drevision; + 0x0c
469	* u8 class_hi; + 0x0d
470	* u16 class_lo; + 0x0e
471	* u16 ilen; + 0x10
472	* u16 irevision; + 0x12
473	* u8 type; + 0x14
474	* u8 indicator; + 0x15
475	* u16 reserved_2; + 0x16
476	* } pci_data_t;
477	*/
478	if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
479	printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
480	"incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
481	goto anyway;
482	}
483	rom_type = BIOS_IN8(dptr + 0x14);
484	switch(rom_type) {
485	case 0:
486	printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
487	break;
488	case 1:
489	printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
490	goto failed;
491	case 2:
492	printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
493	goto failed;
494	default:
495	printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
496	goto failed;
497	}
498	anyway:
499	/* Locate the flat panel infos, do some sanity checking !!! */
500	rinfo->fp_bios_start = BIOS_IN16(0x48);
501	return 0;
502
503	failed:
504	rinfo->bios_seg = NULL;
505	radeon_unmap_ROM(rinfo, dev);
506	return -ENXIO;
507	}
508
509	#ifdef CONFIG_X86
510	static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
511	{
512	/* I simplified this code as we used to miss the signatures in
513	* a lot of case. It's now closer to XFree, we just don't check
514	* for signatures at all... Something better will have to be done
515	* if we end up having conflicts
516	*/
517	u32 segstart;
518	void __iomem *rom_base = NULL;
519
520	for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
521	rom_base = ioremap(offset: segstart, size: 0x10000);
522	if (rom_base == NULL)
523	return -ENOMEM;
524	if (readb(addr: rom_base) == 0x55 && readb(addr: rom_base + 1) == 0xaa)
525	break;
526	iounmap(addr: rom_base);
527	rom_base = NULL;
528	}
529	if (rom_base == NULL)
530	return -ENXIO;
531
532	/* Locate the flat panel infos, do some sanity checking !!! */
533	rinfo->bios_seg = rom_base;
534	rinfo->fp_bios_start = BIOS_IN16(0x48);
535
536	return 0;
537	}
538	#endif
539
540	#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
541	/*
542	* Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
543	* tree. Hopefully, ATI OF driver is kind enough to fill these
544	*/
545	static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
546	{
547	struct device_node *dp = rinfo->of_node;
548	const u32 *val;
549
550	if (dp == NULL)
551	return -ENODEV;
552	val = of_get_property(dp, "ATY,RefCLK", NULL);
553	if (!val || !*val) {
554	printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
555	return -EINVAL;
556	}
557
558	rinfo->pll.ref_clk = (*val) / 10;
559
560	val = of_get_property(dp, "ATY,SCLK", NULL);
561	if (val && *val)
562	rinfo->pll.sclk = (*val) / 10;
563
564	val = of_get_property(dp, "ATY,MCLK", NULL);
565	if (val && *val)
566	rinfo->pll.mclk = (*val) / 10;
567
568	return 0;
569	}
570	#endif /* CONFIG_PPC || CONFIG_SPARC */
571
572	/*
573	* Read PLL infos from chip registers
574	*/
575	static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
576	{
577	unsigned char ppll_div_sel;
578	unsigned Ns, Nm, M;
579	unsigned sclk, mclk, tmp, ref_div;
580	int hTotal, vTotal, num, denom, m, n;
581	unsigned long long hz, vclk;
582	long xtal;
583	ktime_t start_time, stop_time;
584	u64 total_usecs;
585	int i;
586
587	/* Ugh, we cut interrupts, bad bad bad, but we want some precision
588	* here, so... --BenH
589	*/
590
591	/* Flush PCI buffers ? */
592	tmp = INREG16(DEVICE_ID);
593
594	local_irq_disable();
595
596	for(i=0; i<1000000; i++)
597	if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
598	break;
599
600	start_time = ktime_get();
601
602	for(i=0; i<1000000; i++)
603	if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
604	break;
605
606	for(i=0; i<1000000; i++)
607	if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
608	break;
609
610	stop_time = ktime_get();
611
612	local_irq_enable();
613
614	total_usecs = ktime_us_delta(later: stop_time, earlier: start_time);
615	if (total_usecs >= 10 * USEC_PER_SEC || total_usecs == 0)
616	return -1;
617	hz = USEC_PER_SEC/(u32)total_usecs;
618
619	hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
620	vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
621	vclk = (long long)hTotal * (long long)vTotal * hz;
622
623	switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
624	case 0:
625	default:
626	num = 1;
627	denom = 1;
628	break;
629	case 1:
630	n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
631	m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
632	num = 2*n;
633	denom = 2*m;
634	break;
635	case 2:
636	n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
637	m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
638	num = 2*n;
639	denom = 2*m;
640	break;
641	}
642
643	ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
644	radeon_pll_errata_after_index(rinfo);
645
646	n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
647	m = (INPLL(PPLL_REF_DIV) & 0x3ff);
648
649	num *= n;
650	denom *= m;
651
652	switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
653	case 1:
654	denom *= 2;
655	break;
656	case 2:
657	denom *= 4;
658	break;
659	case 3:
660	denom *= 8;
661	break;
662	case 4:
663	denom *= 3;
664	break;
665	case 6:
666	denom *= 6;
667	break;
668	case 7:
669	denom *= 12;
670	break;
671	}
672
673	vclk *= denom;
674	do_div(vclk, 1000 * num);
675	xtal = vclk;
676
677	if ((xtal > 26900) && (xtal < 27100))
678	xtal = 2700;
679	else if ((xtal > 14200) && (xtal < 14400))
680	xtal = 1432;
681	else if ((xtal > 29400) && (xtal < 29600))
682	xtal = 2950;
683	else {
684	printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
685	return -1;
686	}
687
688	tmp = INPLL(M_SPLL_REF_FB_DIV);
689	ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
690
691	Ns = (tmp & 0xff0000) >> 16;
692	Nm = (tmp & 0xff00) >> 8;
693	M = (tmp & 0xff);
694	sclk = round_div(num: (2 * Ns * xtal), den: (2 * M));
695	mclk = round_div(num: (2 * Nm * xtal), den: (2 * M));
696
697	/* we're done, hopefully these are sane values */
698	rinfo->pll.ref_clk = xtal;
699	rinfo->pll.ref_div = ref_div;
700	rinfo->pll.sclk = sclk;
701	rinfo->pll.mclk = mclk;
702
703	return 0;
704	}
705
706	/*
707	* Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
708	*/
709	static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
710	{
711	/*
712	* In the case nothing works, these are defaults; they are mostly
713	* incomplete, however. It does provide ppll_max and _min values
714	* even for most other methods, however.
715	*/
716	switch (rinfo->chipset) {
717	case PCI_DEVICE_ID_ATI_RADEON_QW:
718	case PCI_DEVICE_ID_ATI_RADEON_QX:
719	rinfo->pll.ppll_max = 35000;
720	rinfo->pll.ppll_min = 12000;
721	rinfo->pll.mclk = 23000;
722	rinfo->pll.sclk = 23000;
723	rinfo->pll.ref_clk = 2700;
724	break;
725	case PCI_DEVICE_ID_ATI_RADEON_QL:
726	case PCI_DEVICE_ID_ATI_RADEON_QN:
727	case PCI_DEVICE_ID_ATI_RADEON_QO:
728	case PCI_DEVICE_ID_ATI_RADEON_Ql:
729	case PCI_DEVICE_ID_ATI_RADEON_BB:
730	rinfo->pll.ppll_max = 35000;
731	rinfo->pll.ppll_min = 12000;
732	rinfo->pll.mclk = 27500;
733	rinfo->pll.sclk = 27500;
734	rinfo->pll.ref_clk = 2700;
735	break;
736	case PCI_DEVICE_ID_ATI_RADEON_Id:
737	case PCI_DEVICE_ID_ATI_RADEON_Ie:
738	case PCI_DEVICE_ID_ATI_RADEON_If:
739	case PCI_DEVICE_ID_ATI_RADEON_Ig:
740	rinfo->pll.ppll_max = 35000;
741	rinfo->pll.ppll_min = 12000;
742	rinfo->pll.mclk = 25000;
743	rinfo->pll.sclk = 25000;
744	rinfo->pll.ref_clk = 2700;
745	break;
746	case PCI_DEVICE_ID_ATI_RADEON_ND:
747	case PCI_DEVICE_ID_ATI_RADEON_NE:
748	case PCI_DEVICE_ID_ATI_RADEON_NF:
749	case PCI_DEVICE_ID_ATI_RADEON_NG:
750	rinfo->pll.ppll_max = 40000;
751	rinfo->pll.ppll_min = 20000;
752	rinfo->pll.mclk = 27000;
753	rinfo->pll.sclk = 27000;
754	rinfo->pll.ref_clk = 2700;
755	break;
756	case PCI_DEVICE_ID_ATI_RADEON_QD:
757	case PCI_DEVICE_ID_ATI_RADEON_QE:
758	case PCI_DEVICE_ID_ATI_RADEON_QF:
759	case PCI_DEVICE_ID_ATI_RADEON_QG:
760	default:
761	rinfo->pll.ppll_max = 35000;
762	rinfo->pll.ppll_min = 12000;
763	rinfo->pll.mclk = 16600;
764	rinfo->pll.sclk = 16600;
765	rinfo->pll.ref_clk = 2700;
766	break;
767	}
768	rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
769
770
771	#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
772	/*
773	* Retrieve PLL infos from Open Firmware first
774	*/
775	if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
776	printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
777	goto found;
778	}
779	#endif /* CONFIG_PPC || CONFIG_SPARC */
780
781	/*
782	* Check out if we have an X86 which gave us some PLL informations
783	* and if yes, retrieve them
784	*/
785	if (!force_measure_pll && rinfo->bios_seg) {
786	u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
787
788	rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
789	rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
790	rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
791	rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
792	rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
793	rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
794
795	printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
796	goto found;
797	}
798
799	/*
800	* We didn't get PLL parameters from either OF or BIOS, we try to
801	* probe them
802	*/
803	if (radeon_probe_pll_params(rinfo) == 0) {
804	printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
805	goto found;
806	}
807
808	/*
809	* Fall back to already-set defaults...
810	*/
811	printk(KERN_INFO "radeonfb: Used default PLL infos\n");
812
813	found:
814	/*
815	* Some methods fail to retrieve SCLK and MCLK values, we apply default
816	* settings in this case (200Mhz). If that really happens often, we
817	* could fetch from registers instead...
818	*/
819	if (rinfo->pll.mclk == 0)
820	rinfo->pll.mclk = 20000;
821	if (rinfo->pll.sclk == 0)
822	rinfo->pll.sclk = 20000;
823
824	printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
825	rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
826	rinfo->pll.ref_div,
827	rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
828	rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
829	printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
830	}
831
832	static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
833	{
834	struct radeonfb_info *rinfo = info->par;
835	struct fb_var_screeninfo v;
836	int nom, den;
837	unsigned int pitch;
838
839	if (radeon_match_mode(rinfo, dest: &v, src: var))
840	return -EINVAL;
841
842	switch (v.bits_per_pixel) {
843	case 0 ... 8:
844	v.bits_per_pixel = 8;
845	break;
846	case 9 ... 16:
847	v.bits_per_pixel = 16;
848	break;
849	case 25 ... 32:
850	v.bits_per_pixel = 32;
851	break;
852	default:
853	return -EINVAL;
854	}
855
856	switch (var_to_depth(var: &v)) {
857	case 8:
858	nom = den = 1;
859	v.red.offset = v.green.offset = v.blue.offset = 0;
860	v.red.length = v.green.length = v.blue.length = 8;
861	v.transp.offset = v.transp.length = 0;
862	break;
863	case 15:
864	nom = 2;
865	den = 1;
866	v.red.offset = 10;
867	v.green.offset = 5;
868	v.blue.offset = 0;
869	v.red.length = v.green.length = v.blue.length = 5;
870	v.transp.offset = v.transp.length = 0;
871	break;
872	case 16:
873	nom = 2;
874	den = 1;
875	v.red.offset = 11;
876	v.green.offset = 5;
877	v.blue.offset = 0;
878	v.red.length = 5;
879	v.green.length = 6;
880	v.blue.length = 5;
881	v.transp.offset = v.transp.length = 0;
882	break;
883	case 24:
884	nom = 4;
885	den = 1;
886	v.red.offset = 16;
887	v.green.offset = 8;
888	v.blue.offset = 0;
889	v.red.length = v.blue.length = v.green.length = 8;
890	v.transp.offset = v.transp.length = 0;
891	break;
892	case 32:
893	nom = 4;
894	den = 1;
895	v.red.offset = 16;
896	v.green.offset = 8;
897	v.blue.offset = 0;
898	v.red.length = v.blue.length = v.green.length = 8;
899	v.transp.offset = 24;
900	v.transp.length = 8;
901	break;
902	default:
903	printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
904	var->xres, var->yres, var->bits_per_pixel);
905	return -EINVAL;
906	}
907
908	if (v.yres_virtual < v.yres)
909	v.yres_virtual = v.yres;
910	if (v.xres_virtual < v.xres)
911	v.xres_virtual = v.xres;
912
913
914	/* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
915	* with some panels, though I don't quite like this solution
916	*/
917	if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
918	v.xres_virtual = v.xres_virtual & ~7ul;
919	} else {
920	pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
921	& ~(0x3f)) >> 6;
922	v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
923	}
924
925	if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
926	return -EINVAL;
927
928	if (v.xres_virtual < v.xres)
929	v.xres = v.xres_virtual;
930
931	if (v.xoffset > v.xres_virtual - v.xres)
932	v.xoffset = v.xres_virtual - v.xres - 1;
933
934	if (v.yoffset > v.yres_virtual - v.yres)
935	v.yoffset = v.yres_virtual - v.yres - 1;
936
937	v.red.msb_right = v.green.msb_right = v.blue.msb_right =
938	v.transp.offset = v.transp.length =
939	v.transp.msb_right = 0;
940
941	memcpy(var, &v, sizeof(v));
942
943	return 0;
944	}
945
946
947	static int radeonfb_pan_display (struct fb_var_screeninfo *var,
948	struct fb_info *info)
949	{
950	struct radeonfb_info *rinfo = info->par;
951
952	if ((var->xoffset + info->var.xres > info->var.xres_virtual)
953	|| (var->yoffset + info->var.yres > info->var.yres_virtual))
954	return -EINVAL;
955
956	if (rinfo->asleep)
957	return 0;
958
959	radeon_fifo_wait(2);
960	OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
961	var->xoffset * info->var.bits_per_pixel / 8) & ~7);
962	return 0;
963	}
964
965
966	static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
967	unsigned long arg)
968	{
969	struct radeonfb_info *rinfo = info->par;
970	unsigned int tmp;
971	u32 value = 0;
972	int rc;
973
974	switch (cmd) {
975	/*
976	* TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
977	* and do something better using 2nd CRTC instead of just hackish
978	* routing to second output
979	*/
980	case FBIO_RADEON_SET_MIRROR:
981	if (!rinfo->is_mobility)
982	return -EINVAL;
983
984	rc = get_user(value, (__u32 __user *)arg);
985
986	if (rc)
987	return rc;
988
989	radeon_fifo_wait(2);
990	if (value & 0x01) {
991	tmp = INREG(LVDS_GEN_CNTL);
992
993	tmp |= (LVDS_ON | LVDS_BLON);
994	} else {
995	tmp = INREG(LVDS_GEN_CNTL);
996
997	tmp &= ~(LVDS_ON | LVDS_BLON);
998	}
999
1000	OUTREG(LVDS_GEN_CNTL, tmp);
1001
1002	if (value & 0x02) {
1003	tmp = INREG(CRTC_EXT_CNTL);
1004	tmp |= CRTC_CRT_ON;
1005
1006	mirror = 1;
1007	} else {
1008	tmp = INREG(CRTC_EXT_CNTL);
1009	tmp &= ~CRTC_CRT_ON;
1010
1011	mirror = 0;
1012	}
1013
1014	OUTREG(CRTC_EXT_CNTL, tmp);
1015
1016	return 0;
1017	case FBIO_RADEON_GET_MIRROR:
1018	if (!rinfo->is_mobility)
1019	return -EINVAL;
1020
1021	tmp = INREG(LVDS_GEN_CNTL);
1022	if ((LVDS_ON | LVDS_BLON) & tmp)
1023	value |= 0x01;
1024
1025	tmp = INREG(CRTC_EXT_CNTL);
1026	if (CRTC_CRT_ON & tmp)
1027	value |= 0x02;
1028
1029	return put_user(value, (__u32 __user *)arg);
1030	default:
1031	return -EINVAL;
1032	}
1033
1034	return -EINVAL;
1035	}
1036
1037
1038	int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
1039	{
1040	u32 val;
1041	u32 tmp_pix_clks;
1042	int unblank = 0;
1043
1044	if (rinfo->lock_blank)
1045	return 0;
1046
1047	radeon_engine_idle();
1048
1049	val = INREG(CRTC_EXT_CNTL);
1050	val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1051	CRTC_VSYNC_DIS);
1052	switch (blank) {
1053	case FB_BLANK_VSYNC_SUSPEND:
1054	val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1055	break;
1056	case FB_BLANK_HSYNC_SUSPEND:
1057	val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1058	break;
1059	case FB_BLANK_POWERDOWN:
1060	val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1061	CRTC_HSYNC_DIS);
1062	break;
1063	case FB_BLANK_NORMAL:
1064	val |= CRTC_DISPLAY_DIS;
1065	break;
1066	case FB_BLANK_UNBLANK:
1067	default:
1068	unblank = 1;
1069	}
1070	OUTREG(CRTC_EXT_CNTL, val);
1071
1072
1073	switch (rinfo->mon1_type) {
1074	case MT_DFP:
1075	if (unblank)
1076	OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
1077	~(FP_FPON | FP_TMDS_EN));
1078	else {
1079	if (mode_switch || blank == FB_BLANK_NORMAL)
1080	break;
1081	OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
1082	}
1083	break;
1084	case MT_LCD:
1085	del_timer_sync(timer: &rinfo->lvds_timer);
1086	val = INREG(LVDS_GEN_CNTL);
1087	if (unblank) {
1088	u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
1089	| LVDS_EN | (rinfo->init_state.lvds_gen_cntl
1090	& (LVDS_DIGON | LVDS_BL_MOD_EN));
1091	if ((val ^ target_val) == LVDS_DISPLAY_DIS)
1092	OUTREG(LVDS_GEN_CNTL, target_val);
1093	else if ((val ^ target_val) != 0) {
1094	OUTREG(LVDS_GEN_CNTL, target_val
1095	& ~(LVDS_ON | LVDS_BL_MOD_EN));
1096	rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1097	rinfo->init_state.lvds_gen_cntl |=
1098	target_val & LVDS_STATE_MASK;
1099	if (mode_switch) {
1100	radeon_msleep(rinfo->panel_info.pwr_delay);
1101	OUTREG(LVDS_GEN_CNTL, target_val);
1102	}
1103	else {
1104	rinfo->pending_lvds_gen_cntl = target_val;
1105	mod_timer(timer: &rinfo->lvds_timer,
1106	expires: jiffies +
1107	msecs_to_jiffies(m: rinfo->panel_info.pwr_delay));
1108	}
1109	}
1110	} else {
1111	val |= LVDS_DISPLAY_DIS;
1112	OUTREG(LVDS_GEN_CNTL, val);
1113
1114	/* We don't do a full switch-off on a simple mode switch */
1115	if (mode_switch || blank == FB_BLANK_NORMAL)
1116	break;
1117
1118	/* Asic bug, when turning off LVDS_ON, we have to make sure
1119	* RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1120	*/
1121	tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1122	if (rinfo->is_mobility || rinfo->is_IGP)
1123	OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1124	val &= ~(LVDS_BL_MOD_EN);
1125	OUTREG(LVDS_GEN_CNTL, val);
1126	udelay(100);
1127	val &= ~(LVDS_ON | LVDS_EN);
1128	OUTREG(LVDS_GEN_CNTL, val);
1129	val &= ~LVDS_DIGON;
1130	rinfo->pending_lvds_gen_cntl = val;
1131	mod_timer(timer: &rinfo->lvds_timer,
1132	expires: jiffies +
1133	msecs_to_jiffies(m: rinfo->panel_info.pwr_delay));
1134	rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1135	rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1136	if (rinfo->is_mobility || rinfo->is_IGP)
1137	OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1138	}
1139	break;
1140	case MT_CRT:
1141	// todo: powerdown DAC
1142	default:
1143	break;
1144	}
1145
1146	return 0;
1147	}
1148
1149	static int radeonfb_blank (int blank, struct fb_info *info)
1150	{
1151	struct radeonfb_info *rinfo = info->par;
1152
1153	if (rinfo->asleep)
1154	return 0;
1155
1156	return radeon_screen_blank(rinfo, blank, mode_switch: 0);
1157	}
1158
1159	static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1160	unsigned blue, unsigned transp,
1161	struct radeonfb_info *rinfo)
1162	{
1163	u32 pindex;
1164	unsigned int i;
1165
1166
1167	if (regno > 255)
1168	return -EINVAL;
1169
1170	red >>= 8;
1171	green >>= 8;
1172	blue >>= 8;
1173	rinfo->palette[regno].red = red;
1174	rinfo->palette[regno].green = green;
1175	rinfo->palette[regno].blue = blue;
1176
1177	/* default */
1178	pindex = regno;
1179
1180	if (!rinfo->asleep) {
1181	radeon_fifo_wait(9);
1182
1183	if (rinfo->bpp == 16) {
1184	pindex = regno * 8;
1185
1186	if (rinfo->depth == 16 && regno > 63)
1187	return -EINVAL;
1188	if (rinfo->depth == 15 && regno > 31)
1189	return -EINVAL;
1190
1191	/* For 565, the green component is mixed one order
1192	* below
1193	*/
1194	if (rinfo->depth == 16) {
1195	OUTREG(PALETTE_INDEX, pindex>>1);
1196	OUTREG(PALETTE_DATA,
1197	(rinfo->palette[regno>>1].red << 16) |
1198	(green << 8) |
1199	(rinfo->palette[regno>>1].blue));
1200	green = rinfo->palette[regno<<1].green;
1201	}
1202	}
1203
1204	if (rinfo->depth != 16 || regno < 32) {
1205	OUTREG(PALETTE_INDEX, pindex);
1206	OUTREG(PALETTE_DATA, (red << 16) |
1207	(green << 8) | blue);
1208	}
1209	}
1210	if (regno < 16) {
1211	u32 *pal = rinfo->info->pseudo_palette;
1212	switch (rinfo->depth) {
1213	case 15:
1214	pal[regno] = (regno << 10) | (regno << 5) | regno;
1215	break;
1216	case 16:
1217	pal[regno] = (regno << 11) | (regno << 5) | regno;
1218	break;
1219	case 24:
1220	pal[regno] = (regno << 16) | (regno << 8) | regno;
1221	break;
1222	case 32:
1223	i = (regno << 8) | regno;
1224	pal[regno] = (i << 16) | i;
1225	break;
1226	}
1227	}
1228	return 0;
1229	}
1230
1231	static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1232	unsigned blue, unsigned transp,
1233	struct fb_info *info)
1234	{
1235	struct radeonfb_info *rinfo = info->par;
1236	u32 dac_cntl2, vclk_cntl = 0;
1237	int rc;
1238
1239	if (!rinfo->asleep) {
1240	if (rinfo->is_mobility) {
1241	vclk_cntl = INPLL(VCLK_ECP_CNTL);
1242	OUTPLL(VCLK_ECP_CNTL,
1243	vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1244	}
1245
1246	/* Make sure we are on first palette */
1247	if (rinfo->has_CRTC2) {
1248	dac_cntl2 = INREG(DAC_CNTL2);
1249	dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1250	OUTREG(DAC_CNTL2, dac_cntl2);
1251	}
1252	}
1253
1254	rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1255
1256	if (!rinfo->asleep && rinfo->is_mobility)
1257	OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1258
1259	return rc;
1260	}
1261
1262	static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1263	{
1264	struct radeonfb_info *rinfo = info->par;
1265	u16 *red, *green, *blue, *transp;
1266	u32 dac_cntl2, vclk_cntl = 0;
1267	int i, start, rc = 0;
1268
1269	if (!rinfo->asleep) {
1270	if (rinfo->is_mobility) {
1271	vclk_cntl = INPLL(VCLK_ECP_CNTL);
1272	OUTPLL(VCLK_ECP_CNTL,
1273	vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1274	}
1275
1276	/* Make sure we are on first palette */
1277	if (rinfo->has_CRTC2) {
1278	dac_cntl2 = INREG(DAC_CNTL2);
1279	dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1280	OUTREG(DAC_CNTL2, dac_cntl2);
1281	}
1282	}
1283
1284	red = cmap->red;
1285	green = cmap->green;
1286	blue = cmap->blue;
1287	transp = cmap->transp;
1288	start = cmap->start;
1289
1290	for (i = 0; i < cmap->len; i++) {
1291	u_int hred, hgreen, hblue, htransp = 0xffff;
1292
1293	hred = *red++;
1294	hgreen = *green++;
1295	hblue = *blue++;
1296	if (transp)
1297	htransp = *transp++;
1298	rc = radeon_setcolreg (regno: start++, red: hred, green: hgreen, blue: hblue, transp: htransp,
1299	rinfo);
1300	if (rc)
1301	break;
1302	}
1303
1304	if (!rinfo->asleep && rinfo->is_mobility)
1305	OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1306
1307	return rc;
1308	}
1309
1310	static void radeon_save_state (struct radeonfb_info *rinfo,
1311	struct radeon_regs *save)
1312	{
1313	/* CRTC regs */
1314	save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1315	save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1316	save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1317	save->dac_cntl = INREG(DAC_CNTL);
1318	save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1319	save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1320	save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1321	save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1322	save->crtc_pitch = INREG(CRTC_PITCH);
1323	save->surface_cntl = INREG(SURFACE_CNTL);
1324
1325	/* FP regs */
1326	save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1327	save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1328	save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1329	save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1330	save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1331	save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1332	save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1333	save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1334	save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1335	save->tmds_crc = INREG(TMDS_CRC);
1336	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1337	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1338
1339	/* PLL regs */
1340	save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1341	radeon_pll_errata_after_index(rinfo);
1342	save->ppll_div_3 = INPLL(PPLL_DIV_3);
1343	save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1344	}
1345
1346
1347	static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1348	{
1349	int i;
1350
1351	radeon_fifo_wait(20);
1352
1353	/* Workaround from XFree */
1354	if (rinfo->is_mobility) {
1355	/* A temporal workaround for the occasional blanking on certain laptop
1356	* panels. This appears to related to the PLL divider registers
1357	* (fail to lock?). It occurs even when all dividers are the same
1358	* with their old settings. In this case we really don't need to
1359	* fiddle with PLL registers. By doing this we can avoid the blanking
1360	* problem with some panels.
1361	*/
1362	if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1363	(mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1364	(PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1365	/* We still have to force a switch to selected PPLL div thanks to
1366	* an XFree86 driver bug which will switch it away in some cases
1367	* even when using UseFDev */
1368	OUTREGP(CLOCK_CNTL_INDEX,
1369	mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1370	~PPLL_DIV_SEL_MASK);
1371	radeon_pll_errata_after_index(rinfo);
1372	radeon_pll_errata_after_data(rinfo);
1373	return;
1374	}
1375	}
1376
1377	/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1378	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1379
1380	/* Reset PPLL & enable atomic update */
1381	OUTPLLP(PPLL_CNTL,
1382	PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1383	~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1384
1385	/* Switch to selected PPLL divider */
1386	OUTREGP(CLOCK_CNTL_INDEX,
1387	mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1388	~PPLL_DIV_SEL_MASK);
1389	radeon_pll_errata_after_index(rinfo);
1390	radeon_pll_errata_after_data(rinfo);
1391
1392	/* Set PPLL ref. div */
1393	if (IS_R300_VARIANT(rinfo) ||
1394	rinfo->family == CHIP_FAMILY_RS300 ||
1395	rinfo->family == CHIP_FAMILY_RS400 ||
1396	rinfo->family == CHIP_FAMILY_RS480) {
1397	if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1398	/* When restoring console mode, use saved PPLL_REF_DIV
1399	* setting.
1400	*/
1401	OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1402	} else {
1403	/* R300 uses ref_div_acc field as real ref divider */
1404	OUTPLLP(PPLL_REF_DIV,
1405	(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1406	~R300_PPLL_REF_DIV_ACC_MASK);
1407	}
1408	} else
1409	OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1410
1411	/* Set PPLL divider 3 & post divider*/
1412	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1413	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1414
1415	/* Write update */
1416	while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1417	;
1418	OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1419
1420	/* Wait read update complete */
1421	/* FIXME: Certain revisions of R300 can't recover here. Not sure of
1422	the cause yet, but this workaround will mask the problem for now.
1423	Other chips usually will pass at the very first test, so the
1424	workaround shouldn't have any effect on them. */
1425	for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1426	;
1427
1428	OUTPLL(HTOTAL_CNTL, 0);
1429
1430	/* Clear reset & atomic update */
1431	OUTPLLP(PPLL_CNTL, 0,
1432	~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1433
1434	/* We may want some locking ... oh well */
1435	radeon_msleep(5);
1436
1437	/* Switch back VCLK source to PPLL */
1438	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1439	}
1440
1441	/*
1442	* Timer function for delayed LVDS panel power up/down
1443	*/
1444	static void radeon_lvds_timer_func(struct timer_list *t)
1445	{
1446	struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer);
1447
1448	radeon_engine_idle();
1449
1450	OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1451	}
1452
1453	/*
1454	* Apply a video mode. This will apply the whole register set, including
1455	* the PLL registers, to the card
1456	*/
1457	void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1458	int regs_only)
1459	{
1460	int i;
1461	int primary_mon = PRIMARY_MONITOR(rinfo);
1462
1463	if (nomodeset)
1464	return;
1465
1466	if (!regs_only)
1467	radeon_screen_blank(rinfo, blank: FB_BLANK_NORMAL, mode_switch: 0);
1468
1469	radeon_fifo_wait(31);
1470	for (i=0; i<10; i++)
1471	OUTREG(common_regs[i].reg, common_regs[i].val);
1472
1473	/* Apply surface registers */
1474	for (i=0; i<8; i++) {
1475	OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1476	OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1477	OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1478	}
1479
1480	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1481	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1482	~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1483	OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1484	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1485	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1486	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1487	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1488	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1489	OUTREG(CRTC_OFFSET, 0);
1490	OUTREG(CRTC_OFFSET_CNTL, 0);
1491	OUTREG(CRTC_PITCH, mode->crtc_pitch);
1492	OUTREG(SURFACE_CNTL, mode->surface_cntl);
1493
1494	radeon_write_pll_regs(rinfo, mode);
1495
1496	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1497	radeon_fifo_wait(10);
1498	OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1499	OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1500	OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1501	OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1502	OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1503	OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1504	OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1505	OUTREG(TMDS_CRC, mode->tmds_crc);
1506	OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1507	}
1508
1509	if (!regs_only)
1510	radeon_screen_blank(rinfo, blank: FB_BLANK_UNBLANK, mode_switch: 0);
1511
1512	radeon_fifo_wait(2);
1513	OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1514
1515	return;
1516	}
1517
1518	/*
1519	* Calculate the PLL values for a given mode
1520	*/
1521	static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1522	unsigned long freq)
1523	{
1524	static const struct {
1525	int divider;
1526	int bitvalue;
1527	} *post_div,
1528	post_divs[] = {
1529	{ 1, 0 },
1530	{ 2, 1 },
1531	{ 4, 2 },
1532	{ 8, 3 },
1533	{ 3, 4 },
1534	{ 16, 5 },
1535	{ 6, 6 },
1536	{ 12, 7 },
1537	{ 0, 0 },
1538	};
1539	int fb_div, pll_output_freq = 0;
1540	int uses_dvo = 0;
1541
1542	/* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1543	* not sure which model starts having FP2_GEN_CNTL, I assume anything more
1544	* recent than an r(v)100...
1545	*/
1546	#if 1
1547	/* XXX I had reports of flicker happening with the cinema display
1548	* on TMDS1 that seem to be fixed if I also forbit odd dividers in
1549	* this case. This could just be a bandwidth calculation issue, I
1550	* haven't implemented the bandwidth code yet, but in the meantime,
1551	* forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1552	* I haven't seen a case were were absolutely needed an odd PLL
1553	* divider. I'll find a better fix once I have more infos on the
1554	* real cause of the problem.
1555	*/
1556	while (rinfo->has_CRTC2) {
1557	u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1558	u32 disp_output_cntl;
1559	int source;
1560
1561	/* FP2 path not enabled */
1562	if ((fp2_gen_cntl & FP2_ON) == 0)
1563	break;
1564	/* Not all chip revs have the same format for this register,
1565	* extract the source selection
1566	*/
1567	if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1568	source = (fp2_gen_cntl >> 10) & 0x3;
1569	/* sourced from transform unit, check for transform unit
1570	* own source
1571	*/
1572	if (source == 3) {
1573	disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1574	source = (disp_output_cntl >> 12) & 0x3;
1575	}
1576	} else
1577	source = (fp2_gen_cntl >> 13) & 0x1;
1578	/* sourced from CRTC2 -> exit */
1579	if (source == 1)
1580	break;
1581
1582	/* so we end up on CRTC1, let's set uses_dvo to 1 now */
1583	uses_dvo = 1;
1584	break;
1585	}
1586	#else
1587	uses_dvo = 1;
1588	#endif
1589	if (freq > rinfo->pll.ppll_max)
1590	freq = rinfo->pll.ppll_max;
1591	if (freq*12 < rinfo->pll.ppll_min)
1592	freq = rinfo->pll.ppll_min / 12;
1593	pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1594	freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1595
1596	for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1597	pll_output_freq = post_div->divider * freq;
1598	/* If we output to the DVO port (external TMDS), we don't allow an
1599	* odd PLL divider as those aren't supported on this path
1600	*/
1601	if (uses_dvo && (post_div->divider & 1))
1602	continue;
1603	if (pll_output_freq >= rinfo->pll.ppll_min &&
1604	pll_output_freq <= rinfo->pll.ppll_max)
1605	break;
1606	}
1607
1608	/* If we fall through the bottom, try the "default value"
1609	given by the terminal post_div->bitvalue */
1610	if ( !post_div->divider ) {
1611	post_div = &post_divs[post_div->bitvalue];
1612	pll_output_freq = post_div->divider * freq;
1613	}
1614	pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1615	rinfo->pll.ref_div, rinfo->pll.ref_clk,
1616	pll_output_freq);
1617
1618	/* If we fall through the bottom, try the "default value"
1619	given by the terminal post_div->bitvalue */
1620	if ( !post_div->divider ) {
1621	post_div = &post_divs[post_div->bitvalue];
1622	pll_output_freq = post_div->divider * freq;
1623	}
1624	pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1625	rinfo->pll.ref_div, rinfo->pll.ref_clk,
1626	pll_output_freq);
1627
1628	fb_div = round_div(num: rinfo->pll.ref_div*pll_output_freq,
1629	den: rinfo->pll.ref_clk);
1630	regs->ppll_ref_div = rinfo->pll.ref_div;
1631	regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1632
1633	pr_debug("post div = 0x%x\n", post_div->bitvalue);
1634	pr_debug("fb_div = 0x%x\n", fb_div);
1635	pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1636	}
1637
1638	static int radeonfb_set_par(struct fb_info *info)
1639	{
1640	struct radeonfb_info *rinfo = info->par;
1641	struct fb_var_screeninfo *mode = &info->var;
1642	struct radeon_regs *newmode;
1643	int hTotal, vTotal, hSyncStart, hSyncEnd,
1644	vSyncStart, vSyncEnd;
1645	u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1646	u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1647	u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1648	int i, freq;
1649	int format = 0;
1650	int nopllcalc = 0;
1651	int hsync_start, hsync_fudge, hsync_wid, vsync_wid;
1652	int primary_mon = PRIMARY_MONITOR(rinfo);
1653	int depth = var_to_depth(var: mode);
1654	int use_rmx = 0;
1655
1656	newmode = kmalloc(size: sizeof(struct radeon_regs), GFP_KERNEL);
1657	if (!newmode)
1658	return -ENOMEM;
1659
1660	/* We always want engine to be idle on a mode switch, even
1661	* if we won't actually change the mode
1662	*/
1663	radeon_engine_idle();
1664
1665	hSyncStart = mode->xres + mode->right_margin;
1666	hSyncEnd = hSyncStart + mode->hsync_len;
1667	hTotal = hSyncEnd + mode->left_margin;
1668
1669	vSyncStart = mode->yres + mode->lower_margin;
1670	vSyncEnd = vSyncStart + mode->vsync_len;
1671	vTotal = vSyncEnd + mode->upper_margin;
1672	pixClock = mode->pixclock;
1673
1674	sync = mode->sync;
1675	h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1676	v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1677
1678	if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1679	if (rinfo->panel_info.xres < mode->xres)
1680	mode->xres = rinfo->panel_info.xres;
1681	if (rinfo->panel_info.yres < mode->yres)
1682	mode->yres = rinfo->panel_info.yres;
1683
1684	hTotal = mode->xres + rinfo->panel_info.hblank;
1685	hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1686	hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1687
1688	vTotal = mode->yres + rinfo->panel_info.vblank;
1689	vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1690	vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1691
1692	h_sync_pol = !rinfo->panel_info.hAct_high;
1693	v_sync_pol = !rinfo->panel_info.vAct_high;
1694
1695	pixClock = 100000000 / rinfo->panel_info.clock;
1696
1697	if (rinfo->panel_info.use_bios_dividers) {
1698	nopllcalc = 1;
1699	newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1700	(rinfo->panel_info.post_divider << 16);
1701	newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1702	}
1703	}
1704	dotClock = 1000000000 / pixClock;
1705	freq = dotClock / 10; /* x100 */
1706
1707	pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1708	hSyncStart, hSyncEnd, hTotal);
1709	pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1710	vSyncStart, vSyncEnd, vTotal);
1711
1712	hsync_wid = (hSyncEnd - hSyncStart) / 8;
1713	vsync_wid = vSyncEnd - vSyncStart;
1714	if (hsync_wid == 0)
1715	hsync_wid = 1;
1716	else if (hsync_wid > 0x3f) /* max */
1717	hsync_wid = 0x3f;
1718
1719	if (vsync_wid == 0)
1720	vsync_wid = 1;
1721	else if (vsync_wid > 0x1f) /* max */
1722	vsync_wid = 0x1f;
1723
1724	format = radeon_get_dstbpp(depth);
1725
1726	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1727	hsync_fudge = hsync_fudge_fp[format-1];
1728	else
1729	hsync_fudge = hsync_adj_tab[format-1];
1730
1731	hsync_start = hSyncStart - 8 + hsync_fudge;
1732
1733	newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1734	(format << 8);
1735
1736	/* Clear auto-center etc... */
1737	newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1738	newmode->crtc_more_cntl &= 0xfffffff0;
1739
1740	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1741	newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1742	if (mirror)
1743	newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1744
1745	newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1746	CRTC_INTERLACE_EN);
1747	} else {
1748	newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1749	CRTC_CRT_ON;
1750	}
1751
1752	newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1753	DAC_8BIT_EN;
1754
1755	newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1756	(((mode->xres / 8) - 1) << 16));
1757
1758	newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1759	(hsync_wid << 16) | (h_sync_pol << 23));
1760
1761	newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1762	((mode->yres - 1) << 16);
1763
1764	newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1765	(vsync_wid << 16) | (v_sync_pol << 23));
1766
1767	if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1768	/* We first calculate the engine pitch */
1769	rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1770	& ~(0x3f)) >> 6;
1771
1772	/* Then, re-multiply it to get the CRTC pitch */
1773	newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1774	} else
1775	newmode->crtc_pitch = (mode->xres_virtual >> 3);
1776
1777	newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1778
1779	/*
1780	* It looks like recent chips have a problem with SURFACE_CNTL,
1781	* setting SURF_TRANSLATION_DIS completely disables the
1782	* swapper as well, so we leave it unset now.
1783	*/
1784	newmode->surface_cntl = 0;
1785
1786	#if defined(__BIG_ENDIAN)
1787
1788	/* Setup swapping on both apertures, though we currently
1789	* only use aperture 0, enabling swapper on aperture 1
1790	* won't harm
1791	*/
1792	switch (mode->bits_per_pixel) {
1793	case 16:
1794	newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1795	newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1796	break;
1797	case 24:
1798	case 32:
1799	newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1800	newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1801	break;
1802	}
1803	#endif
1804
1805	/* Clear surface registers */
1806	for (i=0; i<8; i++) {
1807	newmode->surf_lower_bound[i] = 0;
1808	newmode->surf_upper_bound[i] = 0x1f;
1809	newmode->surf_info[i] = 0;
1810	}
1811
1812	pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1813	newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1814	pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1815	newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1816
1817	rinfo->bpp = mode->bits_per_pixel;
1818	rinfo->depth = depth;
1819
1820	pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1821	pr_debug("freq = %lu\n", (unsigned long)freq);
1822
1823	/* We use PPLL_DIV_3 */
1824	newmode->clk_cntl_index = 0x300;
1825
1826	/* Calculate PPLL value if necessary */
1827	if (!nopllcalc)
1828	radeon_calc_pll_regs(rinfo, regs: newmode, freq);
1829
1830	newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1831
1832	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1833	unsigned int hRatio, vRatio;
1834
1835	if (mode->xres > rinfo->panel_info.xres)
1836	mode->xres = rinfo->panel_info.xres;
1837	if (mode->yres > rinfo->panel_info.yres)
1838	mode->yres = rinfo->panel_info.yres;
1839
1840	newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1841	<< HORZ_PANEL_SHIFT);
1842	newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1843	<< VERT_PANEL_SHIFT);
1844
1845	if (mode->xres != rinfo->panel_info.xres) {
1846	hRatio = round_div(num: mode->xres * HORZ_STRETCH_RATIO_MAX,
1847	den: rinfo->panel_info.xres);
1848	newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1849	(newmode->fp_horz_stretch &
1850	(HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1851	HORZ_AUTO_RATIO_INC)));
1852	newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1853	HORZ_STRETCH_ENABLE);
1854	use_rmx = 1;
1855	}
1856	newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1857
1858	if (mode->yres != rinfo->panel_info.yres) {
1859	vRatio = round_div(num: mode->yres * VERT_STRETCH_RATIO_MAX,
1860	den: rinfo->panel_info.yres);
1861	newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1862	(newmode->fp_vert_stretch &
1863	(VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1864	newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1865	VERT_STRETCH_ENABLE);
1866	use_rmx = 1;
1867	}
1868	newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1869
1870	newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1871	~(FP_SEL_CRTC2 |
1872	FP_RMX_HVSYNC_CONTROL_EN |
1873	FP_DFP_SYNC_SEL |
1874	FP_CRT_SYNC_SEL |
1875	FP_CRTC_LOCK_8DOT |
1876	FP_USE_SHADOW_EN |
1877	FP_CRTC_USE_SHADOW_VEND |
1878	FP_CRT_SYNC_ALT));
1879
1880	newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1881	FP_CRTC_DONT_SHADOW_HEND |
1882	FP_PANEL_FORMAT);
1883
1884	if (IS_R300_VARIANT(rinfo) ||
1885	(rinfo->family == CHIP_FAMILY_R200)) {
1886	newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1887	if (use_rmx)
1888	newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1889	else
1890	newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1891	} else
1892	newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1893
1894	newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1895	newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1896	newmode->tmds_crc = rinfo->init_state.tmds_crc;
1897	newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1898
1899	if (primary_mon == MT_LCD) {
1900	newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1901	newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1902	} else {
1903	/* DFP */
1904	newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1905	newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1906	/* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1907	if (IS_R300_VARIANT(rinfo) ||
1908	(rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1909	newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1910	else
1911	newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1912	newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1913	}
1914
1915	newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1916	(((mode->xres / 8) - 1) << 16));
1917	newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1918	((mode->yres - 1) << 16);
1919	newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1920	(hsync_wid << 16) | (h_sync_pol << 23));
1921	newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1922	(vsync_wid << 16) | (v_sync_pol << 23));
1923	}
1924
1925	/* do it! */
1926	if (!rinfo->asleep) {
1927	memcpy(&rinfo->state, newmode, sizeof(*newmode));
1928	radeon_write_mode (rinfo, mode: newmode, regs_only: 0);
1929	/* (re)initialize the engine */
1930	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1931	radeonfb_engine_init (rinfo);
1932	}
1933	/* Update fix */
1934	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1935	info->fix.line_length = rinfo->pitch*64;
1936	else
1937	info->fix.line_length = mode->xres_virtual
1938	* ((mode->bits_per_pixel + 1) / 8);
1939	info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1940	: FB_VISUAL_DIRECTCOLOR;
1941
1942	#ifdef CONFIG_BOOTX_TEXT
1943	/* Update debug text engine */
1944	btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1945	rinfo->depth, info->fix.line_length);
1946	#endif
1947
1948	kfree(objp: newmode);
1949	return 0;
1950	}
1951
1952
1953	static const struct fb_ops radeonfb_ops = {
1954	.owner = THIS_MODULE,
1955	__FB_DEFAULT_IOMEM_OPS_RDWR,
1956	.fb_check_var = radeonfb_check_var,
1957	.fb_set_par = radeonfb_set_par,
1958	.fb_setcolreg = radeonfb_setcolreg,
1959	.fb_setcmap = radeonfb_setcmap,
1960	.fb_pan_display = radeonfb_pan_display,
1961	.fb_blank = radeonfb_blank,
1962	.fb_ioctl = radeonfb_ioctl,
1963	.fb_sync = radeonfb_sync,
1964	.fb_fillrect = radeonfb_fillrect,
1965	.fb_copyarea = radeonfb_copyarea,
1966	.fb_imageblit = radeonfb_imageblit,
1967	__FB_DEFAULT_IOMEM_OPS_MMAP,
1968	};
1969
1970
1971	static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1972	{
1973	struct fb_info *info = rinfo->info;
1974
1975	info->par = rinfo;
1976	info->pseudo_palette = rinfo->pseudo_palette;
1977	info->flags = FBINFO_HWACCEL_COPYAREA
1978	| FBINFO_HWACCEL_FILLRECT
1979	| FBINFO_HWACCEL_XPAN
1980	| FBINFO_HWACCEL_YPAN;
1981	info->fbops = &radeonfb_ops;
1982	info->screen_base = rinfo->fb_base;
1983	info->screen_size = rinfo->mapped_vram;
1984	/* Fill fix common fields */
1985	strscpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1986	info->fix.smem_start = rinfo->fb_base_phys;
1987	info->fix.smem_len = rinfo->video_ram;
1988	info->fix.type = FB_TYPE_PACKED_PIXELS;
1989	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1990	info->fix.xpanstep = 8;
1991	info->fix.ypanstep = 1;
1992	info->fix.ywrapstep = 0;
1993	info->fix.type_aux = 0;
1994	info->fix.mmio_start = rinfo->mmio_base_phys;
1995	info->fix.mmio_len = RADEON_REGSIZE;
1996	info->fix.accel = FB_ACCEL_ATI_RADEON;
1997
1998	fb_alloc_cmap(cmap: &info->cmap, len: 256, transp: 0);
1999
2000	if (noaccel)
2001	info->flags |= FBINFO_HWACCEL_DISABLED;
2002
2003	return 0;
2004	}
2005
2006	/*
2007	* This reconfigure the card's internal memory map. In theory, we'd like
2008	* to setup the card's memory at the same address as it's PCI bus address,
2009	* and the AGP aperture right after that so that system RAM on 32 bits
2010	* machines at least, is directly accessible. However, doing so would
2011	* conflict with the current XFree drivers...
2012	* Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2013	* on the proper way to set this up and duplicate this here. In the meantime,
2014	* I put the card's memory at 0 in card space and AGP at some random high
2015	* local (0xe0000000 for now) that will be changed by XFree/DRI anyway
2016	*/
2017	#ifdef CONFIG_PPC
2018	#undef SET_MC_FB_FROM_APERTURE
2019	static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2020	{
2021	u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
2022	u32 save_crtc_ext_cntl;
2023	u32 aper_base, aper_size;
2024	u32 agp_base;
2025
2026	/* First, we disable display to avoid interfering */
2027	if (rinfo->has_CRTC2) {
2028	save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
2029	OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
2030	}
2031	save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2032	save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2033
2034	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
2035	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
2036	mdelay(100);
2037
2038	aper_base = INREG(CNFG_APER_0_BASE);
2039	aper_size = INREG(CNFG_APER_SIZE);
2040
2041	#ifdef SET_MC_FB_FROM_APERTURE
2042	/* Set framebuffer to be at the same address as set in PCI BAR */
2043	OUTREG(MC_FB_LOCATION,
2044	((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
2045	rinfo->fb_local_base = aper_base;
2046	#else
2047	OUTREG(MC_FB_LOCATION, 0x7fff0000);
2048	rinfo->fb_local_base = 0;
2049	#endif
2050	agp_base = aper_base + aper_size;
2051	if (agp_base & 0xf0000000)
2052	agp_base = (aper_base | 0x0fffffff) + 1;
2053
2054	/* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2055	* assumes the FB isn't mapped to 0xf0000000 or above, but this is
2056	* always the case on PPCs afaik.
2057	*/
2058	#ifdef SET_MC_FB_FROM_APERTURE
2059	OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2060	#else
2061	OUTREG(MC_AGP_LOCATION, 0xffffe000);
2062	#endif
2063
2064	/* Fixup the display base addresses & engine offsets while we
2065	* are at it as well
2066	*/
2067	#ifdef SET_MC_FB_FROM_APERTURE
2068	OUTREG(DISPLAY_BASE_ADDR, aper_base);
2069	if (rinfo->has_CRTC2)
2070	OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2071	OUTREG(OV0_BASE_ADDR, aper_base);
2072	#else
2073	OUTREG(DISPLAY_BASE_ADDR, 0);
2074	if (rinfo->has_CRTC2)
2075	OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2076	OUTREG(OV0_BASE_ADDR, 0);
2077	#endif
2078	mdelay(100);
2079
2080	/* Restore display settings */
2081	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2082	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2083	if (rinfo->has_CRTC2)
2084	OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2085
2086	pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2087	aper_base,
2088	((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2089	0xffff0000 | (agp_base >> 16));
2090	}
2091	#endif /* CONFIG_PPC */
2092
2093
2094	static void radeon_identify_vram(struct radeonfb_info *rinfo)
2095	{
2096	u32 tmp;
2097
2098	/* framebuffer size */
2099	if ((rinfo->family == CHIP_FAMILY_RS100) ||
2100	(rinfo->family == CHIP_FAMILY_RS200) ||
2101	(rinfo->family == CHIP_FAMILY_RS300) ||
2102	(rinfo->family == CHIP_FAMILY_RC410) ||
2103	(rinfo->family == CHIP_FAMILY_RS400) ||
2104	(rinfo->family == CHIP_FAMILY_RS480) ) {
2105	u32 tom = INREG(NB_TOM);
2106
2107	tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2108	radeon_fifo_wait(6);
2109	OUTREG(MC_FB_LOCATION, tom);
2110	OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2111	OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2112	OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2113
2114	/* This is supposed to fix the crtc2 noise problem. */
2115	OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2116
2117	if ((rinfo->family == CHIP_FAMILY_RS100) ||
2118	(rinfo->family == CHIP_FAMILY_RS200)) {
2119	/* This is to workaround the asic bug for RMX, some versions
2120	* of BIOS doesn't have this register initialized correctly.
2121	*/
2122	OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2123	~CRTC_H_CUTOFF_ACTIVE_EN);
2124	}
2125	} else {
2126	tmp = INREG(CNFG_MEMSIZE);
2127	}
2128
2129	/* mem size is bits [28:0], mask off the rest */
2130	rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2131
2132	/*
2133	* Hack to get around some busted production M6's
2134	* reporting no ram
2135	*/
2136	if (rinfo->video_ram == 0) {
2137	switch (rinfo->pdev->device) {
2138	case PCI_CHIP_RADEON_LY:
2139	case PCI_CHIP_RADEON_LZ:
2140	rinfo->video_ram = 8192 * 1024;
2141	break;
2142	default:
2143	break;
2144	}
2145	}
2146
2147
2148	/*
2149	* Now try to identify VRAM type
2150	*/
2151	if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2152	(INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2153	rinfo->vram_ddr = 1;
2154	else
2155	rinfo->vram_ddr = 0;
2156
2157	tmp = INREG(MEM_CNTL);
2158	if (IS_R300_VARIANT(rinfo)) {
2159	tmp &= R300_MEM_NUM_CHANNELS_MASK;
2160	switch (tmp) {
2161	case 0: rinfo->vram_width = 64; break;
2162	case 1: rinfo->vram_width = 128; break;
2163	case 2: rinfo->vram_width = 256; break;
2164	default: rinfo->vram_width = 128; break;
2165	}
2166	} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2167	(rinfo->family == CHIP_FAMILY_RS100) ||
2168	(rinfo->family == CHIP_FAMILY_RS200)){
2169	if (tmp & RV100_MEM_HALF_MODE)
2170	rinfo->vram_width = 32;
2171	else
2172	rinfo->vram_width = 64;
2173	} else {
2174	if (tmp & MEM_NUM_CHANNELS_MASK)
2175	rinfo->vram_width = 128;
2176	else
2177	rinfo->vram_width = 64;
2178	}
2179
2180	/* This may not be correct, as some cards can have half of channel disabled
2181	* ToDo: identify these cases
2182	*/
2183
2184	pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2185	pci_name(rinfo->pdev),
2186	rinfo->video_ram / 1024,
2187	rinfo->vram_ddr ? "DDR" : "SDRAM",
2188	rinfo->vram_width);
2189	}
2190
2191	/*
2192	* Sysfs
2193	*/
2194
2195	static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2196	{
2197	return memory_read_from_buffer(to: buf, count, ppos: &off, from: edid, EDID_LENGTH);
2198	}
2199
2200
2201	static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
2202	struct bin_attribute *bin_attr,
2203	char *buf, loff_t off, size_t count)
2204	{
2205	struct device *dev = kobj_to_dev(kobj);
2206	struct fb_info *info = dev_get_drvdata(dev);
2207	struct radeonfb_info *rinfo = info->par;
2208
2209	return radeon_show_one_edid(buf, off, count, edid: rinfo->mon1_EDID);
2210	}
2211
2212
2213	static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
2214	struct bin_attribute *bin_attr,
2215	char *buf, loff_t off, size_t count)
2216	{
2217	struct device *dev = kobj_to_dev(kobj);
2218	struct fb_info *info = dev_get_drvdata(dev);
2219	struct radeonfb_info *rinfo = info->par;
2220
2221	return radeon_show_one_edid(buf, off, count, edid: rinfo->mon2_EDID);
2222	}
2223
2224	static const struct bin_attribute edid1_attr = {
2225	.attr = {
2226	.name = "edid1",
2227	.mode = 0444,
2228	},
2229	.size = EDID_LENGTH,
2230	.read = radeon_show_edid1,
2231	};
2232
2233	static const struct bin_attribute edid2_attr = {
2234	.attr = {
2235	.name = "edid2",
2236	.mode = 0444,
2237	},
2238	.size = EDID_LENGTH,
2239	.read = radeon_show_edid2,
2240	};
2241
2242	static int radeonfb_pci_register(struct pci_dev *pdev,
2243	const struct pci_device_id *ent)
2244	{
2245	struct fb_info *info;
2246	struct radeonfb_info *rinfo;
2247	int ret;
2248	unsigned char c1, c2;
2249	int err = 0;
2250
2251	pr_debug("radeonfb_pci_register BEGIN\n");
2252
2253	/* Enable device in PCI config */
2254	ret = pci_enable_device(dev: pdev);
2255	if (ret < 0) {
2256	printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2257	pci_name(pdev));
2258	goto err_out;
2259	}
2260
2261	info = framebuffer_alloc(size: sizeof(struct radeonfb_info), dev: &pdev->dev);
2262	if (!info) {
2263	ret = -ENOMEM;
2264	goto err_disable;
2265	}
2266	rinfo = info->par;
2267	rinfo->info = info;
2268	rinfo->pdev = pdev;
2269
2270	spin_lock_init(&rinfo->reg_lock);
2271	timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0);
2272
2273	c1 = ent->device >> 8;
2274	c2 = ent->device & 0xff;
2275	if (isprint(c1) && isprint(c2))
2276	snprintf(buf: rinfo->name, size: sizeof(rinfo->name),
2277	fmt: "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2278	else
2279	snprintf(buf: rinfo->name, size: sizeof(rinfo->name),
2280	fmt: "ATI Radeon %x", ent->device & 0xffff);
2281
2282	rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2283	rinfo->chipset = pdev->device;
2284	rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2285	rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2286	rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2287
2288	/* Set base addrs */
2289	rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2290	rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2291
2292	ret = aperture_remove_conflicting_pci_devices(pdev, KBUILD_MODNAME);
2293	if (ret)
2294	goto err_release_fb;
2295
2296	/* request the mem regions */
2297	ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2298	if (ret < 0) {
2299	printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2300	pci_name(rinfo->pdev));
2301	goto err_release_fb;
2302	}
2303
2304	ret = pci_request_region(pdev, 2, "radeonfb mmio");
2305	if (ret < 0) {
2306	printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2307	pci_name(rinfo->pdev));
2308	goto err_release_pci0;
2309	}
2310
2311	/* map the regions */
2312	rinfo->mmio_base = ioremap(offset: rinfo->mmio_base_phys, RADEON_REGSIZE);
2313	if (!rinfo->mmio_base) {
2314	printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2315	pci_name(rinfo->pdev));
2316	ret = -EIO;
2317	goto err_release_pci2;
2318	}
2319
2320	rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2321
2322	/*
2323	* Check for errata
2324	*/
2325	rinfo->errata = 0;
2326	if (rinfo->family == CHIP_FAMILY_R300 &&
2327	(INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
2328	== CFG_ATI_REV_A11)
2329	rinfo->errata |= CHIP_ERRATA_R300_CG;
2330
2331	if (rinfo->family == CHIP_FAMILY_RV200 ||
2332	rinfo->family == CHIP_FAMILY_RS200)
2333	rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2334
2335	if (rinfo->family == CHIP_FAMILY_RV100 ||
2336	rinfo->family == CHIP_FAMILY_RS100 ||
2337	rinfo->family == CHIP_FAMILY_RS200)
2338	rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2339
2340	#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
2341	/* On PPC, we obtain the OF device-node pointer to the firmware
2342	* data for this chip
2343	*/
2344	rinfo->of_node = pci_device_to_OF_node(pdev);
2345	if (rinfo->of_node == NULL)
2346	printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2347	pci_name(rinfo->pdev));
2348
2349	#endif /* CONFIG_PPC || CONFIG_SPARC */
2350	#ifdef CONFIG_PPC
2351	/* On PPC, the firmware sets up a memory mapping that tends
2352	* to cause lockups when enabling the engine. We reconfigure
2353	* the card internal memory mappings properly
2354	*/
2355	fixup_memory_mappings(rinfo);
2356	#endif /* CONFIG_PPC */
2357
2358	/* Get VRAM size and type */
2359	radeon_identify_vram(rinfo);
2360
2361	rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2362
2363	do {
2364	rinfo->fb_base = ioremap_wc(offset: rinfo->fb_base_phys,
2365	size: rinfo->mapped_vram);
2366	} while (rinfo->fb_base == NULL &&
2367	((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2368
2369	if (rinfo->fb_base == NULL) {
2370	printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2371	pci_name(rinfo->pdev));
2372	ret = -EIO;
2373	goto err_unmap_rom;
2374	}
2375
2376	pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2377	rinfo->mapped_vram/1024);
2378
2379	/*
2380	* Map the BIOS ROM if any and retrieve PLL parameters from
2381	* the BIOS. We skip that on mobility chips as the real panel
2382	* values we need aren't in the ROM but in the BIOS image in
2383	* memory. This is definitely not the best meacnism though,
2384	* we really need the arch code to tell us which is the "primary"
2385	* video adapter to use the memory image (or better, the arch
2386	* should provide us a copy of the BIOS image to shield us from
2387	* archs who would store that elsewhere and/or could initialize
2388	* more than one adapter during boot).
2389	*/
2390	if (!rinfo->is_mobility)
2391	radeon_map_ROM(rinfo, dev: pdev);
2392
2393	/*
2394	* On x86, the primary display on laptop may have it's BIOS
2395	* ROM elsewhere, try to locate it at the legacy memory hole.
2396	* We probably need to make sure this is the primary display,
2397	* but that is difficult without some arch support.
2398	*/
2399	#ifdef CONFIG_X86
2400	if (rinfo->bios_seg == NULL)
2401	radeon_find_mem_vbios(rinfo);
2402	#endif
2403
2404	/* If both above failed, try the BIOS ROM again for mobility
2405	* chips
2406	*/
2407	if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2408	radeon_map_ROM(rinfo, dev: pdev);
2409
2410	/* Get informations about the board's PLL */
2411	radeon_get_pllinfo(rinfo);
2412
2413	#ifdef CONFIG_FB_RADEON_I2C
2414	/* Register I2C bus */
2415	radeon_create_i2c_busses(rinfo);
2416	#endif
2417
2418	/* set all the vital stuff */
2419	radeon_set_fbinfo (rinfo);
2420
2421	/* Probe screen types */
2422	radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2423
2424	/* Build mode list, check out panel native model */
2425	radeon_check_modes(rinfo, mode_option);
2426
2427	/* Register some sysfs stuff (should be done better) */
2428	if (rinfo->mon1_EDID)
2429	err |= sysfs_create_bin_file(kobj: &rinfo->pdev->dev.kobj,
2430	attr: &edid1_attr);
2431	if (rinfo->mon2_EDID)
2432	err |= sysfs_create_bin_file(kobj: &rinfo->pdev->dev.kobj,
2433	attr: &edid2_attr);
2434	if (err)
2435	pr_warn("%s() Creating sysfs files failed, continuing\n",
2436	__func__);
2437
2438	/* save current mode regs before we switch into the new one
2439	* so we can restore this upon __exit
2440	*/
2441	radeon_save_state (rinfo, save: &rinfo->init_state);
2442	memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2443
2444	/* Setup Power Management capabilities */
2445	if (default_dynclk < -1) {
2446	/* -2 is special: means ON on mobility chips and do not
2447	* change on others
2448	*/
2449	radeonfb_pm_init(rinfo, dynclk: rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2450	} else
2451	radeonfb_pm_init(rinfo, dynclk: default_dynclk, ignore_devlist, force_sleep);
2452
2453	pci_set_drvdata(pdev, data: info);
2454
2455	/* Register with fbdev layer */
2456	ret = register_framebuffer(fb_info: info);
2457	if (ret < 0) {
2458	printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2459	pci_name(rinfo->pdev));
2460	goto err_unmap_fb;
2461	}
2462
2463	if (!nomtrr)
2464	rinfo->wc_cookie = arch_phys_wc_add(base: rinfo->fb_base_phys,
2465	size: rinfo->video_ram);
2466
2467	if (backlight)
2468	radeonfb_bl_init(rinfo);
2469
2470	printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2471
2472	if (rinfo->bios_seg)
2473	radeon_unmap_ROM(rinfo, dev: pdev);
2474	pr_debug("radeonfb_pci_register END\n");
2475
2476	return 0;
2477	err_unmap_fb:
2478	iounmap(addr: rinfo->fb_base);
2479	err_unmap_rom:
2480	kfree(objp: rinfo->mon1_EDID);
2481	kfree(objp: rinfo->mon2_EDID);
2482	if (rinfo->mon1_modedb)
2483	fb_destroy_modedb(modedb: rinfo->mon1_modedb);
2484	fb_dealloc_cmap(cmap: &info->cmap);
2485	#ifdef CONFIG_FB_RADEON_I2C
2486	radeon_delete_i2c_busses(rinfo);
2487	#endif
2488	if (rinfo->bios_seg)
2489	radeon_unmap_ROM(rinfo, dev: pdev);
2490	iounmap(addr: rinfo->mmio_base);
2491	err_release_pci2:
2492	pci_release_region(pdev, 2);
2493	err_release_pci0:
2494	pci_release_region(pdev, 0);
2495	err_release_fb:
2496	framebuffer_release(info);
2497	err_disable:
2498	err_out:
2499	return ret;
2500	}
2501
2502
2503
2504	static void radeonfb_pci_unregister(struct pci_dev *pdev)
2505	{
2506	struct fb_info *info = pci_get_drvdata(pdev);
2507	struct radeonfb_info *rinfo = info->par;
2508
2509	if (!rinfo)
2510	return;
2511
2512	radeonfb_pm_exit(rinfo);
2513
2514	if (rinfo->mon1_EDID)
2515	sysfs_remove_bin_file(kobj: &rinfo->pdev->dev.kobj, attr: &edid1_attr);
2516	if (rinfo->mon2_EDID)
2517	sysfs_remove_bin_file(kobj: &rinfo->pdev->dev.kobj, attr: &edid2_attr);
2518
2519	del_timer_sync(timer: &rinfo->lvds_timer);
2520	arch_phys_wc_del(handle: rinfo->wc_cookie);
2521	radeonfb_bl_exit(rinfo);
2522	unregister_framebuffer(fb_info: info);
2523
2524	iounmap(addr: rinfo->mmio_base);
2525	iounmap(addr: rinfo->fb_base);
2526
2527	pci_release_region(pdev, 2);
2528	pci_release_region(pdev, 0);
2529
2530	kfree(objp: rinfo->mon1_EDID);
2531	kfree(objp: rinfo->mon2_EDID);
2532	if (rinfo->mon1_modedb)
2533	fb_destroy_modedb(modedb: rinfo->mon1_modedb);
2534	#ifdef CONFIG_FB_RADEON_I2C
2535	radeon_delete_i2c_busses(rinfo);
2536	#endif
2537	fb_dealloc_cmap(cmap: &info->cmap);
2538	framebuffer_release(info);
2539	}
2540
2541	#ifdef CONFIG_PM
2542	#define RADEONFB_PCI_PM_OPS (&radeonfb_pci_pm_ops)
2543	#else
2544	#define RADEONFB_PCI_PM_OPS NULL
2545	#endif
2546
2547	static struct pci_driver radeonfb_driver = {
2548	.name = "radeonfb",
2549	.id_table = radeonfb_pci_table,
2550	.probe = radeonfb_pci_register,
2551	.remove = radeonfb_pci_unregister,
2552	.driver.pm = RADEONFB_PCI_PM_OPS,
2553	};
2554
2555	#ifndef MODULE
2556	static int __init radeonfb_setup (char *options)
2557	{
2558	char *this_opt;
2559
2560	if (!options || !*options)
2561	return 0;
2562
2563	while ((this_opt = strsep (&options, ",")) != NULL) {
2564	if (!*this_opt)
2565	continue;
2566
2567	if (!strncmp(this_opt, "noaccel", 7)) {
2568	noaccel = 1;
2569	} else if (!strncmp(this_opt, "mirror", 6)) {
2570	mirror = 1;
2571	} else if (!strncmp(this_opt, "force_dfp", 9)) {
2572	force_dfp = 1;
2573	} else if (!strncmp(this_opt, "panel_yres:", 11)) {
2574	panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2575	} else if (!strncmp(this_opt, "backlight:", 10)) {
2576	backlight = simple_strtoul(this_opt+10, NULL, 0);
2577	} else if (!strncmp(this_opt, "nomtrr", 6)) {
2578	nomtrr = 1;
2579	} else if (!strncmp(this_opt, "nomodeset", 9)) {
2580	nomodeset = 1;
2581	} else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2582	force_measure_pll = 1;
2583	} else if (!strncmp(this_opt, "ignore_edid", 11)) {
2584	ignore_edid = 1;
2585	#if defined(CONFIG_PM) && defined(CONFIG_X86)
2586	} else if (!strncmp(this_opt, "force_sleep", 11)) {
2587	force_sleep = 1;
2588	} else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2589	ignore_devlist = 1;
2590	#endif
2591	} else
2592	mode_option = this_opt;
2593	}
2594	return 0;
2595	}
2596	#endif /* MODULE */
2597
2598	static int __init radeonfb_init (void)
2599	{
2600	#ifndef MODULE
2601	char *option = NULL;
2602	#endif
2603
2604	if (fb_modesetting_disabled(drvname: "radeonfb"))
2605	return -ENODEV;
2606
2607	#ifndef MODULE
2608	if (fb_get_options(name: "radeonfb", option: &option))
2609	return -ENODEV;
2610	radeonfb_setup(options: option);
2611	#endif
2612	return pci_register_driver (&radeonfb_driver);
2613	}
2614
2615
2616	static void __exit radeonfb_exit (void)
2617	{
2618	pci_unregister_driver (dev: &radeonfb_driver);
2619	}
2620
2621	module_init(radeonfb_init);
2622	module_exit(radeonfb_exit);
2623
2624	MODULE_AUTHOR("Ani Joshi");
2625	MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2626	MODULE_LICENSE("GPL");
2627	module_param(noaccel, bool, 0);
2628	module_param(default_dynclk, int, 0);
2629	MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2630	MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2631	module_param(nomodeset, bool, 0);
2632	MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2633	module_param(mirror, bool, 0);
2634	MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2635	module_param(force_dfp, bool, 0);
2636	MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2637	module_param(ignore_edid, bool, 0);
2638	MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2639	module_param(monitor_layout, charp, 0);
2640	MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2641	module_param(force_measure_pll, bool, 0);
2642	MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2643	module_param(nomtrr, bool, 0);
2644	MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2645	module_param(panel_yres, int, 0);
2646	MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2647	module_param(mode_option, charp, 0);
2648	MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2649	#if defined(CONFIG_PM) && defined(CONFIG_X86)
2650	module_param(force_sleep, bool, 0);
2651	MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2652	module_param(ignore_devlist, bool, 0);
2653	MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2654	#endif
2655