1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * rt5645.c -- RT5645 ALSA SoC audio codec driver |
4 | * |
5 | * Copyright 2013 Realtek Semiconductor Corp. |
6 | * Author: Bard Liao <bardliao@realtek.com> |
7 | */ |
8 | |
9 | #include <linux/module.h> |
10 | #include <linux/moduleparam.h> |
11 | #include <linux/init.h> |
12 | #include <linux/delay.h> |
13 | #include <linux/pm.h> |
14 | #include <linux/i2c.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/spi/spi.h> |
17 | #include <linux/gpio/consumer.h> |
18 | #include <linux/acpi.h> |
19 | #include <linux/dmi.h> |
20 | #include <linux/regulator/consumer.h> |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> |
23 | #include <sound/pcm_params.h> |
24 | #include <sound/jack.h> |
25 | #include <sound/soc.h> |
26 | #include <sound/soc-dapm.h> |
27 | #include <sound/initval.h> |
28 | #include <sound/tlv.h> |
29 | |
30 | #include "rl6231.h" |
31 | #include "rt5645.h" |
32 | |
33 | #define QUIRK_INV_JD1_1(q) ((q) & 1) |
34 | #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1) |
35 | #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1) |
36 | #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1) |
37 | #define QUIRK_JD_MODE(q) (((q) >> 4) & 7) |
38 | #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3) |
39 | #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3) |
40 | |
41 | static unsigned int quirk = -1; |
42 | module_param(quirk, uint, 0444); |
43 | MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override" ); |
44 | |
45 | static const struct acpi_gpio_mapping *cht_rt5645_gpios; |
46 | |
47 | #define RT5645_DEVICE_ID 0x6308 |
48 | #define RT5650_DEVICE_ID 0x6419 |
49 | |
50 | #define RT5645_PR_RANGE_BASE (0xff + 1) |
51 | #define RT5645_PR_SPACING 0x100 |
52 | |
53 | #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) |
54 | |
55 | #define RT5645_HWEQ_NUM 57 |
56 | |
57 | #define TIME_TO_POWER_MS 400 |
58 | |
59 | static const struct regmap_range_cfg rt5645_ranges[] = { |
60 | { |
61 | .name = "PR" , |
62 | .range_min = RT5645_PR_BASE, |
63 | .range_max = RT5645_PR_BASE + 0xf8, |
64 | .selector_reg = RT5645_PRIV_INDEX, |
65 | .selector_mask = 0xff, |
66 | .selector_shift = 0x0, |
67 | .window_start = RT5645_PRIV_DATA, |
68 | .window_len = 0x1, |
69 | }, |
70 | }; |
71 | |
72 | static const struct reg_sequence init_list[] = { |
73 | {RT5645_PR_BASE + 0x3d, 0x3600}, |
74 | {RT5645_PR_BASE + 0x1c, 0xfd70}, |
75 | {RT5645_PR_BASE + 0x20, 0x611f}, |
76 | {RT5645_PR_BASE + 0x21, 0x4040}, |
77 | {RT5645_PR_BASE + 0x23, 0x0004}, |
78 | {RT5645_ASRC_4, 0x0120}, |
79 | }; |
80 | |
81 | static const struct reg_sequence rt5650_init_list[] = { |
82 | {0xf6, 0x0100}, |
83 | {RT5645_PWR_ANLG1, 0x02}, |
84 | }; |
85 | |
86 | static const struct reg_default rt5645_reg[] = { |
87 | { 0x00, 0x0000 }, |
88 | { 0x01, 0xc8c8 }, |
89 | { 0x02, 0xc8c8 }, |
90 | { 0x03, 0xc8c8 }, |
91 | { 0x0a, 0x0002 }, |
92 | { 0x0b, 0x2827 }, |
93 | { 0x0c, 0xe000 }, |
94 | { 0x0d, 0x0000 }, |
95 | { 0x0e, 0x0000 }, |
96 | { 0x0f, 0x0808 }, |
97 | { 0x14, 0x3333 }, |
98 | { 0x16, 0x4b00 }, |
99 | { 0x18, 0x018b }, |
100 | { 0x19, 0xafaf }, |
101 | { 0x1a, 0xafaf }, |
102 | { 0x1b, 0x0001 }, |
103 | { 0x1c, 0x2f2f }, |
104 | { 0x1d, 0x2f2f }, |
105 | { 0x1e, 0x0000 }, |
106 | { 0x20, 0x0000 }, |
107 | { 0x27, 0x7060 }, |
108 | { 0x28, 0x7070 }, |
109 | { 0x29, 0x8080 }, |
110 | { 0x2a, 0x5656 }, |
111 | { 0x2b, 0x5454 }, |
112 | { 0x2c, 0xaaa0 }, |
113 | { 0x2d, 0x0000 }, |
114 | { 0x2f, 0x1002 }, |
115 | { 0x31, 0x5000 }, |
116 | { 0x32, 0x0000 }, |
117 | { 0x33, 0x0000 }, |
118 | { 0x34, 0x0000 }, |
119 | { 0x35, 0x0000 }, |
120 | { 0x3b, 0x0000 }, |
121 | { 0x3c, 0x007f }, |
122 | { 0x3d, 0x0000 }, |
123 | { 0x3e, 0x007f }, |
124 | { 0x3f, 0x0000 }, |
125 | { 0x40, 0x001f }, |
126 | { 0x41, 0x0000 }, |
127 | { 0x42, 0x001f }, |
128 | { 0x45, 0x6000 }, |
129 | { 0x46, 0x003e }, |
130 | { 0x47, 0x003e }, |
131 | { 0x48, 0xf807 }, |
132 | { 0x4a, 0x0004 }, |
133 | { 0x4d, 0x0000 }, |
134 | { 0x4e, 0x0000 }, |
135 | { 0x4f, 0x01ff }, |
136 | { 0x50, 0x0000 }, |
137 | { 0x51, 0x0000 }, |
138 | { 0x52, 0x01ff }, |
139 | { 0x53, 0xf000 }, |
140 | { 0x56, 0x0111 }, |
141 | { 0x57, 0x0064 }, |
142 | { 0x58, 0xef0e }, |
143 | { 0x59, 0xf0f0 }, |
144 | { 0x5a, 0xef0e }, |
145 | { 0x5b, 0xf0f0 }, |
146 | { 0x5c, 0xef0e }, |
147 | { 0x5d, 0xf0f0 }, |
148 | { 0x5e, 0xf000 }, |
149 | { 0x5f, 0x0000 }, |
150 | { 0x61, 0x0300 }, |
151 | { 0x62, 0x0000 }, |
152 | { 0x63, 0x00c2 }, |
153 | { 0x64, 0x0000 }, |
154 | { 0x65, 0x0000 }, |
155 | { 0x66, 0x0000 }, |
156 | { 0x6a, 0x0000 }, |
157 | { 0x6c, 0x0aaa }, |
158 | { 0x70, 0x8000 }, |
159 | { 0x71, 0x8000 }, |
160 | { 0x72, 0x8000 }, |
161 | { 0x73, 0x7770 }, |
162 | { 0x74, 0x3e00 }, |
163 | { 0x75, 0x2409 }, |
164 | { 0x76, 0x000a }, |
165 | { 0x77, 0x0c00 }, |
166 | { 0x78, 0x0000 }, |
167 | { 0x79, 0x0123 }, |
168 | { 0x80, 0x0000 }, |
169 | { 0x81, 0x0000 }, |
170 | { 0x82, 0x0000 }, |
171 | { 0x83, 0x0000 }, |
172 | { 0x84, 0x0000 }, |
173 | { 0x85, 0x0000 }, |
174 | { 0x8a, 0x0120 }, |
175 | { 0x8e, 0x0004 }, |
176 | { 0x8f, 0x1100 }, |
177 | { 0x90, 0x0646 }, |
178 | { 0x91, 0x0c06 }, |
179 | { 0x93, 0x0000 }, |
180 | { 0x94, 0x0200 }, |
181 | { 0x95, 0x0000 }, |
182 | { 0x9a, 0x2184 }, |
183 | { 0x9b, 0x010a }, |
184 | { 0x9c, 0x0aea }, |
185 | { 0x9d, 0x000c }, |
186 | { 0x9e, 0x0400 }, |
187 | { 0xa0, 0xa0a8 }, |
188 | { 0xa1, 0x0059 }, |
189 | { 0xa2, 0x0001 }, |
190 | { 0xae, 0x6000 }, |
191 | { 0xaf, 0x0000 }, |
192 | { 0xb0, 0x6000 }, |
193 | { 0xb1, 0x0000 }, |
194 | { 0xb2, 0x0000 }, |
195 | { 0xb3, 0x001f }, |
196 | { 0xb4, 0x020c }, |
197 | { 0xb5, 0x1f00 }, |
198 | { 0xb6, 0x0000 }, |
199 | { 0xbb, 0x0000 }, |
200 | { 0xbc, 0x0000 }, |
201 | { 0xbd, 0x0000 }, |
202 | { 0xbe, 0x0000 }, |
203 | { 0xbf, 0x3100 }, |
204 | { 0xc0, 0x0000 }, |
205 | { 0xc1, 0x0000 }, |
206 | { 0xc2, 0x0000 }, |
207 | { 0xc3, 0x2000 }, |
208 | { 0xcd, 0x0000 }, |
209 | { 0xce, 0x0000 }, |
210 | { 0xcf, 0x1813 }, |
211 | { 0xd0, 0x0690 }, |
212 | { 0xd1, 0x1c17 }, |
213 | { 0xd3, 0xb320 }, |
214 | { 0xd4, 0x0000 }, |
215 | { 0xd6, 0x0400 }, |
216 | { 0xd9, 0x0809 }, |
217 | { 0xda, 0x0000 }, |
218 | { 0xdb, 0x0003 }, |
219 | { 0xdc, 0x0049 }, |
220 | { 0xdd, 0x001b }, |
221 | { 0xdf, 0x0008 }, |
222 | { 0xe0, 0x4000 }, |
223 | { 0xe6, 0x8000 }, |
224 | { 0xe7, 0x0200 }, |
225 | { 0xec, 0xb300 }, |
226 | { 0xed, 0x0000 }, |
227 | { 0xf0, 0x001f }, |
228 | { 0xf1, 0x020c }, |
229 | { 0xf2, 0x1f00 }, |
230 | { 0xf3, 0x0000 }, |
231 | { 0xf4, 0x4000 }, |
232 | { 0xf8, 0x0000 }, |
233 | { 0xf9, 0x0000 }, |
234 | { 0xfa, 0x2060 }, |
235 | { 0xfb, 0x4040 }, |
236 | { 0xfc, 0x0000 }, |
237 | { 0xfd, 0x0002 }, |
238 | { 0xfe, 0x10ec }, |
239 | { 0xff, 0x6308 }, |
240 | }; |
241 | |
242 | static const struct reg_default rt5650_reg[] = { |
243 | { 0x00, 0x0000 }, |
244 | { 0x01, 0xc8c8 }, |
245 | { 0x02, 0xc8c8 }, |
246 | { 0x03, 0xc8c8 }, |
247 | { 0x0a, 0x0002 }, |
248 | { 0x0b, 0x2827 }, |
249 | { 0x0c, 0xe000 }, |
250 | { 0x0d, 0x0000 }, |
251 | { 0x0e, 0x0000 }, |
252 | { 0x0f, 0x0808 }, |
253 | { 0x14, 0x3333 }, |
254 | { 0x16, 0x4b00 }, |
255 | { 0x18, 0x018b }, |
256 | { 0x19, 0xafaf }, |
257 | { 0x1a, 0xafaf }, |
258 | { 0x1b, 0x0001 }, |
259 | { 0x1c, 0x2f2f }, |
260 | { 0x1d, 0x2f2f }, |
261 | { 0x1e, 0x0000 }, |
262 | { 0x20, 0x0000 }, |
263 | { 0x27, 0x7060 }, |
264 | { 0x28, 0x7070 }, |
265 | { 0x29, 0x8080 }, |
266 | { 0x2a, 0x5656 }, |
267 | { 0x2b, 0x5454 }, |
268 | { 0x2c, 0xaaa0 }, |
269 | { 0x2d, 0x0000 }, |
270 | { 0x2f, 0x5002 }, |
271 | { 0x31, 0x5000 }, |
272 | { 0x32, 0x0000 }, |
273 | { 0x33, 0x0000 }, |
274 | { 0x34, 0x0000 }, |
275 | { 0x35, 0x0000 }, |
276 | { 0x3b, 0x0000 }, |
277 | { 0x3c, 0x007f }, |
278 | { 0x3d, 0x0000 }, |
279 | { 0x3e, 0x007f }, |
280 | { 0x3f, 0x0000 }, |
281 | { 0x40, 0x001f }, |
282 | { 0x41, 0x0000 }, |
283 | { 0x42, 0x001f }, |
284 | { 0x45, 0x6000 }, |
285 | { 0x46, 0x003e }, |
286 | { 0x47, 0x003e }, |
287 | { 0x48, 0xf807 }, |
288 | { 0x4a, 0x0004 }, |
289 | { 0x4d, 0x0000 }, |
290 | { 0x4e, 0x0000 }, |
291 | { 0x4f, 0x01ff }, |
292 | { 0x50, 0x0000 }, |
293 | { 0x51, 0x0000 }, |
294 | { 0x52, 0x01ff }, |
295 | { 0x53, 0xf000 }, |
296 | { 0x56, 0x0111 }, |
297 | { 0x57, 0x0064 }, |
298 | { 0x58, 0xef0e }, |
299 | { 0x59, 0xf0f0 }, |
300 | { 0x5a, 0xef0e }, |
301 | { 0x5b, 0xf0f0 }, |
302 | { 0x5c, 0xef0e }, |
303 | { 0x5d, 0xf0f0 }, |
304 | { 0x5e, 0xf000 }, |
305 | { 0x5f, 0x0000 }, |
306 | { 0x61, 0x0300 }, |
307 | { 0x62, 0x0000 }, |
308 | { 0x63, 0x00c2 }, |
309 | { 0x64, 0x0000 }, |
310 | { 0x65, 0x0000 }, |
311 | { 0x66, 0x0000 }, |
312 | { 0x6a, 0x0000 }, |
313 | { 0x6c, 0x0aaa }, |
314 | { 0x70, 0x8000 }, |
315 | { 0x71, 0x8000 }, |
316 | { 0x72, 0x8000 }, |
317 | { 0x73, 0x7770 }, |
318 | { 0x74, 0x3e00 }, |
319 | { 0x75, 0x2409 }, |
320 | { 0x76, 0x000a }, |
321 | { 0x77, 0x0c00 }, |
322 | { 0x78, 0x0000 }, |
323 | { 0x79, 0x0123 }, |
324 | { 0x7a, 0x0123 }, |
325 | { 0x80, 0x0000 }, |
326 | { 0x81, 0x0000 }, |
327 | { 0x82, 0x0000 }, |
328 | { 0x83, 0x0000 }, |
329 | { 0x84, 0x0000 }, |
330 | { 0x85, 0x0000 }, |
331 | { 0x8a, 0x0120 }, |
332 | { 0x8e, 0x0004 }, |
333 | { 0x8f, 0x1100 }, |
334 | { 0x90, 0x0646 }, |
335 | { 0x91, 0x0c06 }, |
336 | { 0x93, 0x0000 }, |
337 | { 0x94, 0x0200 }, |
338 | { 0x95, 0x0000 }, |
339 | { 0x9a, 0x2184 }, |
340 | { 0x9b, 0x010a }, |
341 | { 0x9c, 0x0aea }, |
342 | { 0x9d, 0x000c }, |
343 | { 0x9e, 0x0400 }, |
344 | { 0xa0, 0xa0a8 }, |
345 | { 0xa1, 0x0059 }, |
346 | { 0xa2, 0x0001 }, |
347 | { 0xae, 0x6000 }, |
348 | { 0xaf, 0x0000 }, |
349 | { 0xb0, 0x6000 }, |
350 | { 0xb1, 0x0000 }, |
351 | { 0xb2, 0x0000 }, |
352 | { 0xb3, 0x001f }, |
353 | { 0xb4, 0x020c }, |
354 | { 0xb5, 0x1f00 }, |
355 | { 0xb6, 0x0000 }, |
356 | { 0xbb, 0x0000 }, |
357 | { 0xbc, 0x0000 }, |
358 | { 0xbd, 0x0000 }, |
359 | { 0xbe, 0x0000 }, |
360 | { 0xbf, 0x3100 }, |
361 | { 0xc0, 0x0000 }, |
362 | { 0xc1, 0x0000 }, |
363 | { 0xc2, 0x0000 }, |
364 | { 0xc3, 0x2000 }, |
365 | { 0xcd, 0x0000 }, |
366 | { 0xce, 0x0000 }, |
367 | { 0xcf, 0x1813 }, |
368 | { 0xd0, 0x0690 }, |
369 | { 0xd1, 0x1c17 }, |
370 | { 0xd3, 0xb320 }, |
371 | { 0xd4, 0x0000 }, |
372 | { 0xd6, 0x0400 }, |
373 | { 0xd9, 0x0809 }, |
374 | { 0xda, 0x0000 }, |
375 | { 0xdb, 0x0003 }, |
376 | { 0xdc, 0x0049 }, |
377 | { 0xdd, 0x001b }, |
378 | { 0xdf, 0x0008 }, |
379 | { 0xe0, 0x4000 }, |
380 | { 0xe6, 0x8000 }, |
381 | { 0xe7, 0x0200 }, |
382 | { 0xec, 0xb300 }, |
383 | { 0xed, 0x0000 }, |
384 | { 0xf0, 0x001f }, |
385 | { 0xf1, 0x020c }, |
386 | { 0xf2, 0x1f00 }, |
387 | { 0xf3, 0x0000 }, |
388 | { 0xf4, 0x4000 }, |
389 | { 0xf8, 0x0000 }, |
390 | { 0xf9, 0x0000 }, |
391 | { 0xfa, 0x2060 }, |
392 | { 0xfb, 0x4040 }, |
393 | { 0xfc, 0x0000 }, |
394 | { 0xfd, 0x0002 }, |
395 | { 0xfe, 0x10ec }, |
396 | { 0xff, 0x6308 }, |
397 | }; |
398 | |
399 | struct rt5645_eq_param_s { |
400 | unsigned short reg; |
401 | unsigned short val; |
402 | }; |
403 | |
404 | struct rt5645_eq_param_s_be16 { |
405 | __be16 reg; |
406 | __be16 val; |
407 | }; |
408 | |
409 | static const char *const rt5645_supply_names[] = { |
410 | "avdd" , |
411 | "cpvdd" , |
412 | }; |
413 | |
414 | struct rt5645_platform_data { |
415 | /* IN2 can optionally be differential */ |
416 | bool in2_diff; |
417 | |
418 | unsigned int dmic1_data_pin; |
419 | /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */ |
420 | unsigned int dmic2_data_pin; |
421 | /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */ |
422 | |
423 | unsigned int jd_mode; |
424 | /* Use level triggered irq */ |
425 | bool level_trigger_irq; |
426 | /* Invert JD1_1 status polarity */ |
427 | bool inv_jd1_1; |
428 | /* Invert HP detect status polarity */ |
429 | bool inv_hp_pol; |
430 | |
431 | /* Only 1 speaker connected */ |
432 | bool mono_speaker; |
433 | |
434 | /* Value to assign to snd_soc_card.long_name */ |
435 | const char *long_name; |
436 | |
437 | /* Some (package) variants have the headset-mic pin not-connected */ |
438 | bool no_headset_mic; |
439 | }; |
440 | |
441 | struct rt5645_priv { |
442 | struct snd_soc_component *component; |
443 | struct rt5645_platform_data pdata; |
444 | struct regmap *regmap; |
445 | struct i2c_client *i2c; |
446 | struct gpio_desc *gpiod_hp_det; |
447 | struct snd_soc_jack *hp_jack; |
448 | struct snd_soc_jack *mic_jack; |
449 | struct snd_soc_jack *btn_jack; |
450 | struct delayed_work jack_detect_work, rcclock_work; |
451 | struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; |
452 | struct rt5645_eq_param_s *eq_param; |
453 | struct timer_list btn_check_timer; |
454 | struct mutex jd_mutex; |
455 | |
456 | int codec_type; |
457 | int sysclk; |
458 | int sysclk_src; |
459 | int lrck[RT5645_AIFS]; |
460 | int bclk[RT5645_AIFS]; |
461 | int master[RT5645_AIFS]; |
462 | |
463 | int pll_src; |
464 | int pll_in; |
465 | int pll_out; |
466 | |
467 | int jack_type; |
468 | bool en_button_func; |
469 | int v_id; |
470 | }; |
471 | |
472 | static int rt5645_reset(struct snd_soc_component *component) |
473 | { |
474 | return snd_soc_component_write(component, RT5645_RESET, val: 0); |
475 | } |
476 | |
477 | static bool rt5645_volatile_register(struct device *dev, unsigned int reg) |
478 | { |
479 | int i; |
480 | |
481 | for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { |
482 | if (reg >= rt5645_ranges[i].range_min && |
483 | reg <= rt5645_ranges[i].range_max) { |
484 | return true; |
485 | } |
486 | } |
487 | |
488 | switch (reg) { |
489 | case RT5645_RESET: |
490 | case RT5645_PRIV_INDEX: |
491 | case RT5645_PRIV_DATA: |
492 | case RT5645_IN1_CTRL1: |
493 | case RT5645_IN1_CTRL2: |
494 | case RT5645_IN1_CTRL3: |
495 | case RT5645_A_JD_CTRL1: |
496 | case RT5645_ADC_EQ_CTRL1: |
497 | case RT5645_EQ_CTRL1: |
498 | case RT5645_ALC_CTRL_1: |
499 | case RT5645_IRQ_CTRL2: |
500 | case RT5645_IRQ_CTRL3: |
501 | case RT5645_INT_IRQ_ST: |
502 | case RT5645_IL_CMD: |
503 | case RT5650_4BTN_IL_CMD1: |
504 | case RT5645_VENDOR_ID: |
505 | case RT5645_VENDOR_ID1: |
506 | case RT5645_VENDOR_ID2: |
507 | return true; |
508 | default: |
509 | return false; |
510 | } |
511 | } |
512 | |
513 | static bool rt5645_readable_register(struct device *dev, unsigned int reg) |
514 | { |
515 | int i; |
516 | |
517 | for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { |
518 | if (reg >= rt5645_ranges[i].range_min && |
519 | reg <= rt5645_ranges[i].range_max) { |
520 | return true; |
521 | } |
522 | } |
523 | |
524 | switch (reg) { |
525 | case RT5645_RESET: |
526 | case RT5645_SPK_VOL: |
527 | case RT5645_HP_VOL: |
528 | case RT5645_LOUT1: |
529 | case RT5645_IN1_CTRL1: |
530 | case RT5645_IN1_CTRL2: |
531 | case RT5645_IN1_CTRL3: |
532 | case RT5645_IN2_CTRL: |
533 | case RT5645_INL1_INR1_VOL: |
534 | case RT5645_SPK_FUNC_LIM: |
535 | case RT5645_ADJ_HPF_CTRL: |
536 | case RT5645_DAC1_DIG_VOL: |
537 | case RT5645_DAC2_DIG_VOL: |
538 | case RT5645_DAC_CTRL: |
539 | case RT5645_STO1_ADC_DIG_VOL: |
540 | case RT5645_MONO_ADC_DIG_VOL: |
541 | case RT5645_ADC_BST_VOL1: |
542 | case RT5645_ADC_BST_VOL2: |
543 | case RT5645_STO1_ADC_MIXER: |
544 | case RT5645_MONO_ADC_MIXER: |
545 | case RT5645_AD_DA_MIXER: |
546 | case RT5645_STO_DAC_MIXER: |
547 | case RT5645_MONO_DAC_MIXER: |
548 | case RT5645_DIG_MIXER: |
549 | case RT5650_A_DAC_SOUR: |
550 | case RT5645_DIG_INF1_DATA: |
551 | case RT5645_PDM_OUT_CTRL: |
552 | case RT5645_REC_L1_MIXER: |
553 | case RT5645_REC_L2_MIXER: |
554 | case RT5645_REC_R1_MIXER: |
555 | case RT5645_REC_R2_MIXER: |
556 | case RT5645_HPMIXL_CTRL: |
557 | case RT5645_HPOMIXL_CTRL: |
558 | case RT5645_HPMIXR_CTRL: |
559 | case RT5645_HPOMIXR_CTRL: |
560 | case RT5645_HPO_MIXER: |
561 | case RT5645_SPK_L_MIXER: |
562 | case RT5645_SPK_R_MIXER: |
563 | case RT5645_SPO_MIXER: |
564 | case RT5645_SPO_CLSD_RATIO: |
565 | case RT5645_OUT_L1_MIXER: |
566 | case RT5645_OUT_R1_MIXER: |
567 | case RT5645_OUT_L_GAIN1: |
568 | case RT5645_OUT_L_GAIN2: |
569 | case RT5645_OUT_R_GAIN1: |
570 | case RT5645_OUT_R_GAIN2: |
571 | case RT5645_LOUT_MIXER: |
572 | case RT5645_HAPTIC_CTRL1: |
573 | case RT5645_HAPTIC_CTRL2: |
574 | case RT5645_HAPTIC_CTRL3: |
575 | case RT5645_HAPTIC_CTRL4: |
576 | case RT5645_HAPTIC_CTRL5: |
577 | case RT5645_HAPTIC_CTRL6: |
578 | case RT5645_HAPTIC_CTRL7: |
579 | case RT5645_HAPTIC_CTRL8: |
580 | case RT5645_HAPTIC_CTRL9: |
581 | case RT5645_HAPTIC_CTRL10: |
582 | case RT5645_PWR_DIG1: |
583 | case RT5645_PWR_DIG2: |
584 | case RT5645_PWR_ANLG1: |
585 | case RT5645_PWR_ANLG2: |
586 | case RT5645_PWR_MIXER: |
587 | case RT5645_PWR_VOL: |
588 | case RT5645_PRIV_INDEX: |
589 | case RT5645_PRIV_DATA: |
590 | case RT5645_I2S1_SDP: |
591 | case RT5645_I2S2_SDP: |
592 | case RT5645_ADDA_CLK1: |
593 | case RT5645_ADDA_CLK2: |
594 | case RT5645_DMIC_CTRL1: |
595 | case RT5645_DMIC_CTRL2: |
596 | case RT5645_TDM_CTRL_1: |
597 | case RT5645_TDM_CTRL_2: |
598 | case RT5645_TDM_CTRL_3: |
599 | case RT5650_TDM_CTRL_4: |
600 | case RT5645_GLB_CLK: |
601 | case RT5645_PLL_CTRL1: |
602 | case RT5645_PLL_CTRL2: |
603 | case RT5645_ASRC_1: |
604 | case RT5645_ASRC_2: |
605 | case RT5645_ASRC_3: |
606 | case RT5645_ASRC_4: |
607 | case RT5645_DEPOP_M1: |
608 | case RT5645_DEPOP_M2: |
609 | case RT5645_DEPOP_M3: |
610 | case RT5645_CHARGE_PUMP: |
611 | case RT5645_MICBIAS: |
612 | case RT5645_A_JD_CTRL1: |
613 | case RT5645_VAD_CTRL4: |
614 | case RT5645_CLSD_OUT_CTRL: |
615 | case RT5645_ADC_EQ_CTRL1: |
616 | case RT5645_ADC_EQ_CTRL2: |
617 | case RT5645_EQ_CTRL1: |
618 | case RT5645_EQ_CTRL2: |
619 | case RT5645_ALC_CTRL_1: |
620 | case RT5645_ALC_CTRL_2: |
621 | case RT5645_ALC_CTRL_3: |
622 | case RT5645_ALC_CTRL_4: |
623 | case RT5645_ALC_CTRL_5: |
624 | case RT5645_JD_CTRL: |
625 | case RT5645_IRQ_CTRL1: |
626 | case RT5645_IRQ_CTRL2: |
627 | case RT5645_IRQ_CTRL3: |
628 | case RT5645_INT_IRQ_ST: |
629 | case RT5645_GPIO_CTRL1: |
630 | case RT5645_GPIO_CTRL2: |
631 | case RT5645_GPIO_CTRL3: |
632 | case RT5645_BASS_BACK: |
633 | case RT5645_MP3_PLUS1: |
634 | case RT5645_MP3_PLUS2: |
635 | case RT5645_ADJ_HPF1: |
636 | case RT5645_ADJ_HPF2: |
637 | case RT5645_HP_CALIB_AMP_DET: |
638 | case RT5645_SV_ZCD1: |
639 | case RT5645_SV_ZCD2: |
640 | case RT5645_IL_CMD: |
641 | case RT5645_IL_CMD2: |
642 | case RT5645_IL_CMD3: |
643 | case RT5650_4BTN_IL_CMD1: |
644 | case RT5650_4BTN_IL_CMD2: |
645 | case RT5645_DRC1_HL_CTRL1: |
646 | case RT5645_DRC2_HL_CTRL1: |
647 | case RT5645_ADC_MONO_HP_CTRL1: |
648 | case RT5645_ADC_MONO_HP_CTRL2: |
649 | case RT5645_DRC2_CTRL1: |
650 | case RT5645_DRC2_CTRL2: |
651 | case RT5645_DRC2_CTRL3: |
652 | case RT5645_DRC2_CTRL4: |
653 | case RT5645_DRC2_CTRL5: |
654 | case RT5645_JD_CTRL3: |
655 | case RT5645_JD_CTRL4: |
656 | case RT5645_GEN_CTRL1: |
657 | case RT5645_GEN_CTRL2: |
658 | case RT5645_GEN_CTRL3: |
659 | case RT5645_VENDOR_ID: |
660 | case RT5645_VENDOR_ID1: |
661 | case RT5645_VENDOR_ID2: |
662 | return true; |
663 | default: |
664 | return false; |
665 | } |
666 | } |
667 | |
668 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); |
669 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); |
670 | static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); |
671 | static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); |
672 | static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); |
673 | |
674 | /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ |
675 | static const DECLARE_TLV_DB_RANGE(bst_tlv, |
676 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
677 | 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), |
678 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), |
679 | 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), |
680 | 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), |
681 | 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), |
682 | 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) |
683 | ); |
684 | |
685 | /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ |
686 | static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, |
687 | 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), |
688 | 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), |
689 | 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), |
690 | 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) |
691 | ); |
692 | |
693 | static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, |
694 | struct snd_ctl_elem_info *uinfo) |
695 | { |
696 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
697 | uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); |
698 | |
699 | return 0; |
700 | } |
701 | |
702 | static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, |
703 | struct snd_ctl_elem_value *ucontrol) |
704 | { |
705 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); |
706 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
707 | struct rt5645_eq_param_s_be16 *eq_param = |
708 | (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; |
709 | int i; |
710 | |
711 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { |
712 | eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); |
713 | eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); |
714 | } |
715 | |
716 | return 0; |
717 | } |
718 | |
719 | static bool rt5645_validate_hweq(unsigned short reg) |
720 | { |
721 | if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) || |
722 | (reg == RT5645_EQ_CTRL2)) |
723 | return true; |
724 | |
725 | return false; |
726 | } |
727 | |
728 | static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, |
729 | struct snd_ctl_elem_value *ucontrol) |
730 | { |
731 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); |
732 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
733 | struct rt5645_eq_param_s_be16 *eq_param = |
734 | (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; |
735 | int i; |
736 | |
737 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { |
738 | rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg); |
739 | rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val); |
740 | } |
741 | |
742 | /* The final setting of the table should be RT5645_EQ_CTRL2 */ |
743 | for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { |
744 | if (rt5645->eq_param[i].reg == 0) |
745 | continue; |
746 | else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2) |
747 | return 0; |
748 | else |
749 | break; |
750 | } |
751 | |
752 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { |
753 | if (!rt5645_validate_hweq(reg: rt5645->eq_param[i].reg) && |
754 | rt5645->eq_param[i].reg != 0) |
755 | return 0; |
756 | else if (rt5645->eq_param[i].reg == 0) |
757 | break; |
758 | } |
759 | |
760 | return 0; |
761 | } |
762 | |
763 | #define RT5645_HWEQ(xname) \ |
764 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ |
765 | .info = rt5645_hweq_info, \ |
766 | .get = rt5645_hweq_get, \ |
767 | .put = rt5645_hweq_put \ |
768 | } |
769 | |
770 | static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, |
771 | struct snd_ctl_elem_value *ucontrol) |
772 | { |
773 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); |
774 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
775 | int ret; |
776 | |
777 | regmap_update_bits(map: rt5645->regmap, RT5645_MICBIAS, |
778 | RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); |
779 | |
780 | ret = snd_soc_put_volsw(kcontrol, ucontrol); |
781 | |
782 | mod_delayed_work(wq: system_power_efficient_wq, dwork: &rt5645->rcclock_work, |
783 | delay: msecs_to_jiffies(m: 200)); |
784 | |
785 | return ret; |
786 | } |
787 | |
788 | static const char * const rt5645_dac1_vol_ctrl_mode_text[] = { |
789 | "immediately" , "zero crossing" , "soft ramp" |
790 | }; |
791 | |
792 | static SOC_ENUM_SINGLE_DECL( |
793 | rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE, |
794 | RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text); |
795 | |
796 | static const struct snd_kcontrol_new rt5645_snd_controls[] = { |
797 | /* Speaker Output Volume */ |
798 | SOC_DOUBLE("Speaker Channel Switch" , RT5645_SPK_VOL, |
799 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), |
800 | SOC_DOUBLE_EXT_TLV("Speaker Playback Volume" , RT5645_SPK_VOL, |
801 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, |
802 | rt5645_spk_put_volsw, out_vol_tlv), |
803 | |
804 | /* ClassD modulator Speaker Gain Ratio */ |
805 | SOC_SINGLE_TLV("Speaker ClassD Playback Volume" , RT5645_SPO_CLSD_RATIO, |
806 | RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), |
807 | |
808 | /* Headphone Output Volume */ |
809 | SOC_DOUBLE("Headphone Channel Switch" , RT5645_HP_VOL, |
810 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), |
811 | SOC_DOUBLE_TLV("Headphone Playback Volume" , RT5645_HP_VOL, |
812 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), |
813 | |
814 | /* OUTPUT Control */ |
815 | SOC_DOUBLE("OUT Playback Switch" , RT5645_LOUT1, |
816 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), |
817 | SOC_DOUBLE("OUT Channel Switch" , RT5645_LOUT1, |
818 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), |
819 | SOC_DOUBLE_TLV("OUT Playback Volume" , RT5645_LOUT1, |
820 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), |
821 | |
822 | /* DAC Digital Volume */ |
823 | SOC_DOUBLE("DAC2 Playback Switch" , RT5645_DAC_CTRL, |
824 | RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), |
825 | SOC_DOUBLE_TLV("DAC1 Playback Volume" , RT5645_DAC1_DIG_VOL, |
826 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), |
827 | SOC_DOUBLE_TLV("Mono DAC Playback Volume" , RT5645_DAC2_DIG_VOL, |
828 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), |
829 | |
830 | /* IN1/IN2 Control */ |
831 | SOC_SINGLE_TLV("IN1 Boost" , RT5645_IN1_CTRL1, |
832 | RT5645_BST_SFT1, 12, 0, bst_tlv), |
833 | SOC_SINGLE_TLV("IN2 Boost" , RT5645_IN2_CTRL, |
834 | RT5645_BST_SFT2, 8, 0, bst_tlv), |
835 | |
836 | /* INL/INR Volume Control */ |
837 | SOC_DOUBLE_TLV("IN Capture Volume" , RT5645_INL1_INR1_VOL, |
838 | RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), |
839 | |
840 | /* ADC Digital Volume Control */ |
841 | SOC_DOUBLE("ADC Capture Switch" , RT5645_STO1_ADC_DIG_VOL, |
842 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), |
843 | SOC_DOUBLE_TLV("ADC Capture Volume" , RT5645_STO1_ADC_DIG_VOL, |
844 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), |
845 | SOC_DOUBLE("Mono ADC Capture Switch" , RT5645_MONO_ADC_DIG_VOL, |
846 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), |
847 | SOC_DOUBLE_TLV("Mono ADC Capture Volume" , RT5645_MONO_ADC_DIG_VOL, |
848 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), |
849 | |
850 | /* ADC Boost Volume Control */ |
851 | SOC_DOUBLE_TLV("ADC Boost Capture Volume" , RT5645_ADC_BST_VOL1, |
852 | RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, |
853 | adc_bst_tlv), |
854 | SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume" , RT5645_ADC_BST_VOL2, |
855 | RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, |
856 | adc_bst_tlv), |
857 | |
858 | /* I2S2 function select */ |
859 | SOC_SINGLE("I2S2 Func Switch" , RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, |
860 | 1, 1), |
861 | RT5645_HWEQ("Speaker HWEQ" ), |
862 | |
863 | /* Digital Soft Volume Control */ |
864 | SOC_ENUM("DAC1 Digital Volume Control Func" , rt5645_dac1_vol_ctrl_mode), |
865 | }; |
866 | |
867 | /** |
868 | * set_dmic_clk - Set parameter of dmic. |
869 | * |
870 | * @w: DAPM widget. |
871 | * @kcontrol: The kcontrol of this widget. |
872 | * @event: Event id. |
873 | * |
874 | */ |
875 | static int set_dmic_clk(struct snd_soc_dapm_widget *w, |
876 | struct snd_kcontrol *kcontrol, int event) |
877 | { |
878 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
879 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
880 | int idx, rate; |
881 | |
882 | rate = rt5645->sysclk / rl6231_get_pre_div(map: rt5645->regmap, |
883 | RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); |
884 | idx = rl6231_calc_dmic_clk(rate); |
885 | if (idx < 0) |
886 | dev_err(component->dev, "Failed to set DMIC clock\n" ); |
887 | else |
888 | snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1, |
889 | RT5645_DMIC_CLK_MASK, val: idx << RT5645_DMIC_CLK_SFT); |
890 | return idx; |
891 | } |
892 | |
893 | static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, |
894 | struct snd_soc_dapm_widget *sink) |
895 | { |
896 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: source->dapm); |
897 | unsigned int val; |
898 | |
899 | val = snd_soc_component_read(component, RT5645_GLB_CLK); |
900 | val &= RT5645_SCLK_SRC_MASK; |
901 | if (val == RT5645_SCLK_SRC_PLL1) |
902 | return 1; |
903 | else |
904 | return 0; |
905 | } |
906 | |
907 | static int is_using_asrc(struct snd_soc_dapm_widget *source, |
908 | struct snd_soc_dapm_widget *sink) |
909 | { |
910 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: source->dapm); |
911 | unsigned int reg, shift, val; |
912 | |
913 | switch (source->shift) { |
914 | case 0: |
915 | reg = RT5645_ASRC_3; |
916 | shift = 0; |
917 | break; |
918 | case 1: |
919 | reg = RT5645_ASRC_3; |
920 | shift = 4; |
921 | break; |
922 | case 3: |
923 | reg = RT5645_ASRC_2; |
924 | shift = 0; |
925 | break; |
926 | case 8: |
927 | reg = RT5645_ASRC_2; |
928 | shift = 4; |
929 | break; |
930 | case 9: |
931 | reg = RT5645_ASRC_2; |
932 | shift = 8; |
933 | break; |
934 | case 10: |
935 | reg = RT5645_ASRC_2; |
936 | shift = 12; |
937 | break; |
938 | default: |
939 | return 0; |
940 | } |
941 | |
942 | val = (snd_soc_component_read(component, reg) >> shift) & 0xf; |
943 | switch (val) { |
944 | case 1: |
945 | case 2: |
946 | case 3: |
947 | case 4: |
948 | return 1; |
949 | default: |
950 | return 0; |
951 | } |
952 | |
953 | } |
954 | |
955 | static int rt5645_enable_hweq(struct snd_soc_component *component) |
956 | { |
957 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
958 | int i; |
959 | |
960 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { |
961 | if (rt5645_validate_hweq(reg: rt5645->eq_param[i].reg)) |
962 | regmap_write(map: rt5645->regmap, reg: rt5645->eq_param[i].reg, |
963 | val: rt5645->eq_param[i].val); |
964 | else |
965 | break; |
966 | } |
967 | |
968 | return 0; |
969 | } |
970 | |
971 | /** |
972 | * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters |
973 | * @component: SoC audio component device. |
974 | * @filter_mask: mask of filters. |
975 | * @clk_src: clock source |
976 | * |
977 | * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can |
978 | * only support standard 32fs or 64fs i2s format, ASRC should be enabled to |
979 | * support special i2s clock format such as Intel's 100fs(100 * sampling rate). |
980 | * ASRC function will track i2s clock and generate a corresponding system clock |
981 | * for codec. This function provides an API to select the clock source for a |
982 | * set of filters specified by the mask. And the codec driver will turn on ASRC |
983 | * for these filters if ASRC is selected as their clock source. |
984 | */ |
985 | int rt5645_sel_asrc_clk_src(struct snd_soc_component *component, |
986 | unsigned int filter_mask, unsigned int clk_src) |
987 | { |
988 | unsigned int asrc2_mask = 0; |
989 | unsigned int asrc2_value = 0; |
990 | unsigned int asrc3_mask = 0; |
991 | unsigned int asrc3_value = 0; |
992 | |
993 | switch (clk_src) { |
994 | case RT5645_CLK_SEL_SYS: |
995 | case RT5645_CLK_SEL_I2S1_ASRC: |
996 | case RT5645_CLK_SEL_I2S2_ASRC: |
997 | case RT5645_CLK_SEL_SYS2: |
998 | break; |
999 | |
1000 | default: |
1001 | return -EINVAL; |
1002 | } |
1003 | |
1004 | if (filter_mask & RT5645_DA_STEREO_FILTER) { |
1005 | asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; |
1006 | asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) |
1007 | | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); |
1008 | } |
1009 | |
1010 | if (filter_mask & RT5645_DA_MONO_L_FILTER) { |
1011 | asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; |
1012 | asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) |
1013 | | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); |
1014 | } |
1015 | |
1016 | if (filter_mask & RT5645_DA_MONO_R_FILTER) { |
1017 | asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; |
1018 | asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) |
1019 | | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); |
1020 | } |
1021 | |
1022 | if (filter_mask & RT5645_AD_STEREO_FILTER) { |
1023 | asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; |
1024 | asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) |
1025 | | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); |
1026 | } |
1027 | |
1028 | if (filter_mask & RT5645_AD_MONO_L_FILTER) { |
1029 | asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; |
1030 | asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) |
1031 | | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); |
1032 | } |
1033 | |
1034 | if (filter_mask & RT5645_AD_MONO_R_FILTER) { |
1035 | asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; |
1036 | asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) |
1037 | | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); |
1038 | } |
1039 | |
1040 | if (asrc2_mask) |
1041 | snd_soc_component_update_bits(component, RT5645_ASRC_2, |
1042 | mask: asrc2_mask, val: asrc2_value); |
1043 | |
1044 | if (asrc3_mask) |
1045 | snd_soc_component_update_bits(component, RT5645_ASRC_3, |
1046 | mask: asrc3_mask, val: asrc3_value); |
1047 | |
1048 | return 0; |
1049 | } |
1050 | EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); |
1051 | |
1052 | /* Digital Mixer */ |
1053 | static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { |
1054 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5645_STO1_ADC_MIXER, |
1055 | RT5645_M_ADC_L1_SFT, 1, 1), |
1056 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5645_STO1_ADC_MIXER, |
1057 | RT5645_M_ADC_L2_SFT, 1, 1), |
1058 | }; |
1059 | |
1060 | static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { |
1061 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5645_STO1_ADC_MIXER, |
1062 | RT5645_M_ADC_R1_SFT, 1, 1), |
1063 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5645_STO1_ADC_MIXER, |
1064 | RT5645_M_ADC_R2_SFT, 1, 1), |
1065 | }; |
1066 | |
1067 | static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { |
1068 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5645_MONO_ADC_MIXER, |
1069 | RT5645_M_MONO_ADC_L1_SFT, 1, 1), |
1070 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5645_MONO_ADC_MIXER, |
1071 | RT5645_M_MONO_ADC_L2_SFT, 1, 1), |
1072 | }; |
1073 | |
1074 | static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { |
1075 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5645_MONO_ADC_MIXER, |
1076 | RT5645_M_MONO_ADC_R1_SFT, 1, 1), |
1077 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5645_MONO_ADC_MIXER, |
1078 | RT5645_M_MONO_ADC_R2_SFT, 1, 1), |
1079 | }; |
1080 | |
1081 | static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { |
1082 | SOC_DAPM_SINGLE("Stereo ADC Switch" , RT5645_AD_DA_MIXER, |
1083 | RT5645_M_ADCMIX_L_SFT, 1, 1), |
1084 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch" , RT5645_AD_DA_MIXER, |
1085 | RT5645_M_DAC1_L_SFT, 1, 1), |
1086 | }; |
1087 | |
1088 | static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { |
1089 | SOC_DAPM_SINGLE("Stereo ADC Switch" , RT5645_AD_DA_MIXER, |
1090 | RT5645_M_ADCMIX_R_SFT, 1, 1), |
1091 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch" , RT5645_AD_DA_MIXER, |
1092 | RT5645_M_DAC1_R_SFT, 1, 1), |
1093 | }; |
1094 | |
1095 | static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { |
1096 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5645_STO_DAC_MIXER, |
1097 | RT5645_M_DAC_L1_SFT, 1, 1), |
1098 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5645_STO_DAC_MIXER, |
1099 | RT5645_M_DAC_L2_SFT, 1, 1), |
1100 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_STO_DAC_MIXER, |
1101 | RT5645_M_DAC_R1_STO_L_SFT, 1, 1), |
1102 | }; |
1103 | |
1104 | static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { |
1105 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_STO_DAC_MIXER, |
1106 | RT5645_M_DAC_R1_SFT, 1, 1), |
1107 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5645_STO_DAC_MIXER, |
1108 | RT5645_M_DAC_R2_SFT, 1, 1), |
1109 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5645_STO_DAC_MIXER, |
1110 | RT5645_M_DAC_L1_STO_R_SFT, 1, 1), |
1111 | }; |
1112 | |
1113 | static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { |
1114 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5645_MONO_DAC_MIXER, |
1115 | RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), |
1116 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5645_MONO_DAC_MIXER, |
1117 | RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), |
1118 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5645_MONO_DAC_MIXER, |
1119 | RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), |
1120 | }; |
1121 | |
1122 | static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { |
1123 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_MONO_DAC_MIXER, |
1124 | RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), |
1125 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5645_MONO_DAC_MIXER, |
1126 | RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), |
1127 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5645_MONO_DAC_MIXER, |
1128 | RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), |
1129 | }; |
1130 | |
1131 | static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { |
1132 | SOC_DAPM_SINGLE("Sto DAC Mix L Switch" , RT5645_DIG_MIXER, |
1133 | RT5645_M_STO_L_DAC_L_SFT, 1, 1), |
1134 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5645_DIG_MIXER, |
1135 | RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), |
1136 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5645_DIG_MIXER, |
1137 | RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), |
1138 | }; |
1139 | |
1140 | static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { |
1141 | SOC_DAPM_SINGLE("Sto DAC Mix R Switch" , RT5645_DIG_MIXER, |
1142 | RT5645_M_STO_R_DAC_R_SFT, 1, 1), |
1143 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5645_DIG_MIXER, |
1144 | RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), |
1145 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5645_DIG_MIXER, |
1146 | RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), |
1147 | }; |
1148 | |
1149 | /* Analog Input Mixer */ |
1150 | static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { |
1151 | SOC_DAPM_SINGLE("HPOL Switch" , RT5645_REC_L2_MIXER, |
1152 | RT5645_M_HP_L_RM_L_SFT, 1, 1), |
1153 | SOC_DAPM_SINGLE("INL Switch" , RT5645_REC_L2_MIXER, |
1154 | RT5645_M_IN_L_RM_L_SFT, 1, 1), |
1155 | SOC_DAPM_SINGLE("BST2 Switch" , RT5645_REC_L2_MIXER, |
1156 | RT5645_M_BST2_RM_L_SFT, 1, 1), |
1157 | SOC_DAPM_SINGLE("BST1 Switch" , RT5645_REC_L2_MIXER, |
1158 | RT5645_M_BST1_RM_L_SFT, 1, 1), |
1159 | SOC_DAPM_SINGLE("OUT MIXL Switch" , RT5645_REC_L2_MIXER, |
1160 | RT5645_M_OM_L_RM_L_SFT, 1, 1), |
1161 | }; |
1162 | |
1163 | static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { |
1164 | SOC_DAPM_SINGLE("HPOR Switch" , RT5645_REC_R2_MIXER, |
1165 | RT5645_M_HP_R_RM_R_SFT, 1, 1), |
1166 | SOC_DAPM_SINGLE("INR Switch" , RT5645_REC_R2_MIXER, |
1167 | RT5645_M_IN_R_RM_R_SFT, 1, 1), |
1168 | SOC_DAPM_SINGLE("BST2 Switch" , RT5645_REC_R2_MIXER, |
1169 | RT5645_M_BST2_RM_R_SFT, 1, 1), |
1170 | SOC_DAPM_SINGLE("BST1 Switch" , RT5645_REC_R2_MIXER, |
1171 | RT5645_M_BST1_RM_R_SFT, 1, 1), |
1172 | SOC_DAPM_SINGLE("OUT MIXR Switch" , RT5645_REC_R2_MIXER, |
1173 | RT5645_M_OM_R_RM_R_SFT, 1, 1), |
1174 | }; |
1175 | |
1176 | static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { |
1177 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5645_SPK_L_MIXER, |
1178 | RT5645_M_DAC_L1_SM_L_SFT, 1, 1), |
1179 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5645_SPK_L_MIXER, |
1180 | RT5645_M_DAC_L2_SM_L_SFT, 1, 1), |
1181 | SOC_DAPM_SINGLE("INL Switch" , RT5645_SPK_L_MIXER, |
1182 | RT5645_M_IN_L_SM_L_SFT, 1, 1), |
1183 | SOC_DAPM_SINGLE("BST1 Switch" , RT5645_SPK_L_MIXER, |
1184 | RT5645_M_BST1_L_SM_L_SFT, 1, 1), |
1185 | }; |
1186 | |
1187 | static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { |
1188 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_SPK_R_MIXER, |
1189 | RT5645_M_DAC_R1_SM_R_SFT, 1, 1), |
1190 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5645_SPK_R_MIXER, |
1191 | RT5645_M_DAC_R2_SM_R_SFT, 1, 1), |
1192 | SOC_DAPM_SINGLE("INR Switch" , RT5645_SPK_R_MIXER, |
1193 | RT5645_M_IN_R_SM_R_SFT, 1, 1), |
1194 | SOC_DAPM_SINGLE("BST2 Switch" , RT5645_SPK_R_MIXER, |
1195 | RT5645_M_BST2_R_SM_R_SFT, 1, 1), |
1196 | }; |
1197 | |
1198 | static const struct snd_kcontrol_new rt5645_out_l_mix[] = { |
1199 | SOC_DAPM_SINGLE("BST1 Switch" , RT5645_OUT_L1_MIXER, |
1200 | RT5645_M_BST1_OM_L_SFT, 1, 1), |
1201 | SOC_DAPM_SINGLE("INL Switch" , RT5645_OUT_L1_MIXER, |
1202 | RT5645_M_IN_L_OM_L_SFT, 1, 1), |
1203 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5645_OUT_L1_MIXER, |
1204 | RT5645_M_DAC_L2_OM_L_SFT, 1, 1), |
1205 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5645_OUT_L1_MIXER, |
1206 | RT5645_M_DAC_L1_OM_L_SFT, 1, 1), |
1207 | }; |
1208 | |
1209 | static const struct snd_kcontrol_new rt5645_out_r_mix[] = { |
1210 | SOC_DAPM_SINGLE("BST2 Switch" , RT5645_OUT_R1_MIXER, |
1211 | RT5645_M_BST2_OM_R_SFT, 1, 1), |
1212 | SOC_DAPM_SINGLE("INR Switch" , RT5645_OUT_R1_MIXER, |
1213 | RT5645_M_IN_R_OM_R_SFT, 1, 1), |
1214 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5645_OUT_R1_MIXER, |
1215 | RT5645_M_DAC_R2_OM_R_SFT, 1, 1), |
1216 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_OUT_R1_MIXER, |
1217 | RT5645_M_DAC_R1_OM_R_SFT, 1, 1), |
1218 | }; |
1219 | |
1220 | static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { |
1221 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_SPO_MIXER, |
1222 | RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), |
1223 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5645_SPO_MIXER, |
1224 | RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), |
1225 | SOC_DAPM_SINGLE("SPKVOL R Switch" , RT5645_SPO_MIXER, |
1226 | RT5645_M_SV_R_SPM_L_SFT, 1, 1), |
1227 | SOC_DAPM_SINGLE("SPKVOL L Switch" , RT5645_SPO_MIXER, |
1228 | RT5645_M_SV_L_SPM_L_SFT, 1, 1), |
1229 | }; |
1230 | |
1231 | static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { |
1232 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_SPO_MIXER, |
1233 | RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), |
1234 | SOC_DAPM_SINGLE("SPKVOL R Switch" , RT5645_SPO_MIXER, |
1235 | RT5645_M_SV_R_SPM_R_SFT, 1, 1), |
1236 | }; |
1237 | |
1238 | static const struct snd_kcontrol_new rt5645_hpo_mix[] = { |
1239 | SOC_DAPM_SINGLE("DAC1 Switch" , RT5645_HPO_MIXER, |
1240 | RT5645_M_DAC1_HM_SFT, 1, 1), |
1241 | SOC_DAPM_SINGLE("HPVOL Switch" , RT5645_HPO_MIXER, |
1242 | RT5645_M_HPVOL_HM_SFT, 1, 1), |
1243 | }; |
1244 | |
1245 | static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { |
1246 | SOC_DAPM_SINGLE("DAC1 Switch" , RT5645_HPOMIXL_CTRL, |
1247 | RT5645_M_DAC1_HV_SFT, 1, 1), |
1248 | SOC_DAPM_SINGLE("DAC2 Switch" , RT5645_HPOMIXL_CTRL, |
1249 | RT5645_M_DAC2_HV_SFT, 1, 1), |
1250 | SOC_DAPM_SINGLE("INL Switch" , RT5645_HPOMIXL_CTRL, |
1251 | RT5645_M_IN_HV_SFT, 1, 1), |
1252 | SOC_DAPM_SINGLE("BST1 Switch" , RT5645_HPOMIXL_CTRL, |
1253 | RT5645_M_BST1_HV_SFT, 1, 1), |
1254 | }; |
1255 | |
1256 | static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { |
1257 | SOC_DAPM_SINGLE("DAC1 Switch" , RT5645_HPOMIXR_CTRL, |
1258 | RT5645_M_DAC1_HV_SFT, 1, 1), |
1259 | SOC_DAPM_SINGLE("DAC2 Switch" , RT5645_HPOMIXR_CTRL, |
1260 | RT5645_M_DAC2_HV_SFT, 1, 1), |
1261 | SOC_DAPM_SINGLE("INR Switch" , RT5645_HPOMIXR_CTRL, |
1262 | RT5645_M_IN_HV_SFT, 1, 1), |
1263 | SOC_DAPM_SINGLE("BST2 Switch" , RT5645_HPOMIXR_CTRL, |
1264 | RT5645_M_BST2_HV_SFT, 1, 1), |
1265 | }; |
1266 | |
1267 | static const struct snd_kcontrol_new rt5645_lout_mix[] = { |
1268 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5645_LOUT_MIXER, |
1269 | RT5645_M_DAC_L1_LM_SFT, 1, 1), |
1270 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5645_LOUT_MIXER, |
1271 | RT5645_M_DAC_R1_LM_SFT, 1, 1), |
1272 | SOC_DAPM_SINGLE("OUTMIX L Switch" , RT5645_LOUT_MIXER, |
1273 | RT5645_M_OV_L_LM_SFT, 1, 1), |
1274 | SOC_DAPM_SINGLE("OUTMIX R Switch" , RT5645_LOUT_MIXER, |
1275 | RT5645_M_OV_R_LM_SFT, 1, 1), |
1276 | }; |
1277 | |
1278 | /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ |
1279 | static const char * const rt5645_dac1_src[] = { |
1280 | "IF1 DAC" , "IF2 DAC" , "IF3 DAC" |
1281 | }; |
1282 | |
1283 | static SOC_ENUM_SINGLE_DECL( |
1284 | rt5645_dac1l_enum, RT5645_AD_DA_MIXER, |
1285 | RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); |
1286 | |
1287 | static const struct snd_kcontrol_new rt5645_dac1l_mux = |
1288 | SOC_DAPM_ENUM("DAC1 L source" , rt5645_dac1l_enum); |
1289 | |
1290 | static SOC_ENUM_SINGLE_DECL( |
1291 | rt5645_dac1r_enum, RT5645_AD_DA_MIXER, |
1292 | RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); |
1293 | |
1294 | static const struct snd_kcontrol_new rt5645_dac1r_mux = |
1295 | SOC_DAPM_ENUM("DAC1 R source" , rt5645_dac1r_enum); |
1296 | |
1297 | /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ |
1298 | static const char * const rt5645_dac12_src[] = { |
1299 | "IF1 DAC" , "IF2 DAC" , "IF3 DAC" , "Mono ADC" , "VAD_ADC" |
1300 | }; |
1301 | |
1302 | static SOC_ENUM_SINGLE_DECL( |
1303 | rt5645_dac2l_enum, RT5645_DAC_CTRL, |
1304 | RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); |
1305 | |
1306 | static const struct snd_kcontrol_new rt5645_dac_l2_mux = |
1307 | SOC_DAPM_ENUM("DAC2 L source" , rt5645_dac2l_enum); |
1308 | |
1309 | static const char * const rt5645_dacr2_src[] = { |
1310 | "IF1 DAC" , "IF2 DAC" , "IF3 DAC" , "Mono ADC" , "Haptic" |
1311 | }; |
1312 | |
1313 | static SOC_ENUM_SINGLE_DECL( |
1314 | rt5645_dac2r_enum, RT5645_DAC_CTRL, |
1315 | RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); |
1316 | |
1317 | static const struct snd_kcontrol_new rt5645_dac_r2_mux = |
1318 | SOC_DAPM_ENUM("DAC2 R source" , rt5645_dac2r_enum); |
1319 | |
1320 | /* Stereo1 ADC source */ |
1321 | /* MX-27 [12] */ |
1322 | static const char * const rt5645_stereo_adc1_src[] = { |
1323 | "DAC MIX" , "ADC" |
1324 | }; |
1325 | |
1326 | static SOC_ENUM_SINGLE_DECL( |
1327 | rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, |
1328 | RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); |
1329 | |
1330 | static const struct snd_kcontrol_new rt5645_sto_adc1_mux = |
1331 | SOC_DAPM_ENUM("Stereo1 ADC1 Mux" , rt5645_stereo1_adc1_enum); |
1332 | |
1333 | /* MX-27 [11] */ |
1334 | static const char * const rt5645_stereo_adc2_src[] = { |
1335 | "DAC MIX" , "DMIC" |
1336 | }; |
1337 | |
1338 | static SOC_ENUM_SINGLE_DECL( |
1339 | rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, |
1340 | RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); |
1341 | |
1342 | static const struct snd_kcontrol_new rt5645_sto_adc2_mux = |
1343 | SOC_DAPM_ENUM("Stereo1 ADC2 Mux" , rt5645_stereo1_adc2_enum); |
1344 | |
1345 | /* MX-27 [8] */ |
1346 | static const char * const rt5645_stereo_dmic_src[] = { |
1347 | "DMIC1" , "DMIC2" |
1348 | }; |
1349 | |
1350 | static SOC_ENUM_SINGLE_DECL( |
1351 | rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, |
1352 | RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); |
1353 | |
1354 | static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = |
1355 | SOC_DAPM_ENUM("Stereo1 DMIC source" , rt5645_stereo1_dmic_enum); |
1356 | |
1357 | /* Mono ADC source */ |
1358 | /* MX-28 [12] */ |
1359 | static const char * const rt5645_mono_adc_l1_src[] = { |
1360 | "Mono DAC MIXL" , "ADC" |
1361 | }; |
1362 | |
1363 | static SOC_ENUM_SINGLE_DECL( |
1364 | rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, |
1365 | RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); |
1366 | |
1367 | static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = |
1368 | SOC_DAPM_ENUM("Mono ADC1 left source" , rt5645_mono_adc_l1_enum); |
1369 | /* MX-28 [11] */ |
1370 | static const char * const rt5645_mono_adc_l2_src[] = { |
1371 | "Mono DAC MIXL" , "DMIC" |
1372 | }; |
1373 | |
1374 | static SOC_ENUM_SINGLE_DECL( |
1375 | rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, |
1376 | RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); |
1377 | |
1378 | static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = |
1379 | SOC_DAPM_ENUM("Mono ADC2 left source" , rt5645_mono_adc_l2_enum); |
1380 | |
1381 | /* MX-28 [8] */ |
1382 | static const char * const rt5645_mono_dmic_src[] = { |
1383 | "DMIC1" , "DMIC2" |
1384 | }; |
1385 | |
1386 | static SOC_ENUM_SINGLE_DECL( |
1387 | rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, |
1388 | RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); |
1389 | |
1390 | static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = |
1391 | SOC_DAPM_ENUM("Mono DMIC left source" , rt5645_mono_dmic_l_enum); |
1392 | /* MX-28 [1:0] */ |
1393 | static SOC_ENUM_SINGLE_DECL( |
1394 | rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, |
1395 | RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); |
1396 | |
1397 | static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = |
1398 | SOC_DAPM_ENUM("Mono DMIC Right source" , rt5645_mono_dmic_r_enum); |
1399 | /* MX-28 [4] */ |
1400 | static const char * const rt5645_mono_adc_r1_src[] = { |
1401 | "Mono DAC MIXR" , "ADC" |
1402 | }; |
1403 | |
1404 | static SOC_ENUM_SINGLE_DECL( |
1405 | rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, |
1406 | RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); |
1407 | |
1408 | static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = |
1409 | SOC_DAPM_ENUM("Mono ADC1 right source" , rt5645_mono_adc_r1_enum); |
1410 | /* MX-28 [3] */ |
1411 | static const char * const rt5645_mono_adc_r2_src[] = { |
1412 | "Mono DAC MIXR" , "DMIC" |
1413 | }; |
1414 | |
1415 | static SOC_ENUM_SINGLE_DECL( |
1416 | rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, |
1417 | RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); |
1418 | |
1419 | static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = |
1420 | SOC_DAPM_ENUM("Mono ADC2 right source" , rt5645_mono_adc_r2_enum); |
1421 | |
1422 | /* MX-77 [9:8] */ |
1423 | static const char * const rt5645_if1_adc_in_src[] = { |
1424 | "IF_ADC1/IF_ADC2/VAD_ADC" , "IF_ADC2/IF_ADC1/VAD_ADC" , |
1425 | "VAD_ADC/IF_ADC1/IF_ADC2" , "VAD_ADC/IF_ADC2/IF_ADC1" |
1426 | }; |
1427 | |
1428 | static SOC_ENUM_SINGLE_DECL( |
1429 | rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, |
1430 | RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); |
1431 | |
1432 | static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = |
1433 | SOC_DAPM_ENUM("IF1 ADC IN source" , rt5645_if1_adc_in_enum); |
1434 | |
1435 | /* MX-78 [4:0] */ |
1436 | static const char * const rt5650_if1_adc_in_src[] = { |
1437 | "IF_ADC1/IF_ADC2/DAC_REF/Null" , |
1438 | "IF_ADC1/IF_ADC2/Null/DAC_REF" , |
1439 | "IF_ADC1/DAC_REF/IF_ADC2/Null" , |
1440 | "IF_ADC1/DAC_REF/Null/IF_ADC2" , |
1441 | "IF_ADC1/Null/DAC_REF/IF_ADC2" , |
1442 | "IF_ADC1/Null/IF_ADC2/DAC_REF" , |
1443 | |
1444 | "IF_ADC2/IF_ADC1/DAC_REF/Null" , |
1445 | "IF_ADC2/IF_ADC1/Null/DAC_REF" , |
1446 | "IF_ADC2/DAC_REF/IF_ADC1/Null" , |
1447 | "IF_ADC2/DAC_REF/Null/IF_ADC1" , |
1448 | "IF_ADC2/Null/DAC_REF/IF_ADC1" , |
1449 | "IF_ADC2/Null/IF_ADC1/DAC_REF" , |
1450 | |
1451 | "DAC_REF/IF_ADC1/IF_ADC2/Null" , |
1452 | "DAC_REF/IF_ADC1/Null/IF_ADC2" , |
1453 | "DAC_REF/IF_ADC2/IF_ADC1/Null" , |
1454 | "DAC_REF/IF_ADC2/Null/IF_ADC1" , |
1455 | "DAC_REF/Null/IF_ADC1/IF_ADC2" , |
1456 | "DAC_REF/Null/IF_ADC2/IF_ADC1" , |
1457 | |
1458 | "Null/IF_ADC1/IF_ADC2/DAC_REF" , |
1459 | "Null/IF_ADC1/DAC_REF/IF_ADC2" , |
1460 | "Null/IF_ADC2/IF_ADC1/DAC_REF" , |
1461 | "Null/IF_ADC2/DAC_REF/IF_ADC1" , |
1462 | "Null/DAC_REF/IF_ADC1/IF_ADC2" , |
1463 | "Null/DAC_REF/IF_ADC2/IF_ADC1" , |
1464 | }; |
1465 | |
1466 | static SOC_ENUM_SINGLE_DECL( |
1467 | rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, |
1468 | 0, rt5650_if1_adc_in_src); |
1469 | |
1470 | static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = |
1471 | SOC_DAPM_ENUM("IF1 ADC IN source" , rt5650_if1_adc_in_enum); |
1472 | |
1473 | /* MX-78 [15:14][13:12][11:10] */ |
1474 | static const char * const rt5645_tdm_adc_swap_select[] = { |
1475 | "L/R" , "R/L" , "L/L" , "R/R" |
1476 | }; |
1477 | |
1478 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, |
1479 | RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); |
1480 | |
1481 | static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = |
1482 | SOC_DAPM_ENUM("IF1 ADC1 IN source" , rt5650_tdm_adc_slot0_1_enum); |
1483 | |
1484 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, |
1485 | RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); |
1486 | |
1487 | static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = |
1488 | SOC_DAPM_ENUM("IF1 ADC2 IN source" , rt5650_tdm_adc_slot2_3_enum); |
1489 | |
1490 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, |
1491 | RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); |
1492 | |
1493 | static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = |
1494 | SOC_DAPM_ENUM("IF1 ADC3 IN source" , rt5650_tdm_adc_slot4_5_enum); |
1495 | |
1496 | /* MX-77 [7:6][5:4][3:2] */ |
1497 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, |
1498 | RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); |
1499 | |
1500 | static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = |
1501 | SOC_DAPM_ENUM("IF1 ADC1 IN source" , rt5645_tdm_adc_slot0_1_enum); |
1502 | |
1503 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, |
1504 | RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); |
1505 | |
1506 | static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = |
1507 | SOC_DAPM_ENUM("IF1 ADC2 IN source" , rt5645_tdm_adc_slot2_3_enum); |
1508 | |
1509 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, |
1510 | RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); |
1511 | |
1512 | static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = |
1513 | SOC_DAPM_ENUM("IF1 ADC3 IN source" , rt5645_tdm_adc_slot4_5_enum); |
1514 | |
1515 | /* MX-79 [14:12][10:8][6:4][2:0] */ |
1516 | static const char * const rt5645_tdm_dac_swap_select[] = { |
1517 | "Slot0" , "Slot1" , "Slot2" , "Slot3" |
1518 | }; |
1519 | |
1520 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, |
1521 | RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); |
1522 | |
1523 | static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = |
1524 | SOC_DAPM_ENUM("IF1 DAC0 source" , rt5645_tdm_dac0_enum); |
1525 | |
1526 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, |
1527 | RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); |
1528 | |
1529 | static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = |
1530 | SOC_DAPM_ENUM("IF1 DAC1 source" , rt5645_tdm_dac1_enum); |
1531 | |
1532 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, |
1533 | RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); |
1534 | |
1535 | static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = |
1536 | SOC_DAPM_ENUM("IF1 DAC2 source" , rt5645_tdm_dac2_enum); |
1537 | |
1538 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, |
1539 | RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); |
1540 | |
1541 | static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = |
1542 | SOC_DAPM_ENUM("IF1 DAC3 source" , rt5645_tdm_dac3_enum); |
1543 | |
1544 | /* MX-7a [14:12][10:8][6:4][2:0] */ |
1545 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, |
1546 | RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); |
1547 | |
1548 | static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = |
1549 | SOC_DAPM_ENUM("IF1 DAC0 source" , rt5650_tdm_dac0_enum); |
1550 | |
1551 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, |
1552 | RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); |
1553 | |
1554 | static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = |
1555 | SOC_DAPM_ENUM("IF1 DAC1 source" , rt5650_tdm_dac1_enum); |
1556 | |
1557 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, |
1558 | RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); |
1559 | |
1560 | static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = |
1561 | SOC_DAPM_ENUM("IF1 DAC2 source" , rt5650_tdm_dac2_enum); |
1562 | |
1563 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, |
1564 | RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); |
1565 | |
1566 | static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = |
1567 | SOC_DAPM_ENUM("IF1 DAC3 source" , rt5650_tdm_dac3_enum); |
1568 | |
1569 | /* MX-2d [3] [2] */ |
1570 | static const char * const rt5650_a_dac1_src[] = { |
1571 | "DAC1" , "Stereo DAC Mixer" |
1572 | }; |
1573 | |
1574 | static SOC_ENUM_SINGLE_DECL( |
1575 | rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, |
1576 | RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); |
1577 | |
1578 | static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = |
1579 | SOC_DAPM_ENUM("A DAC1 L source" , rt5650_a_dac1_l_enum); |
1580 | |
1581 | static SOC_ENUM_SINGLE_DECL( |
1582 | rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, |
1583 | RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); |
1584 | |
1585 | static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = |
1586 | SOC_DAPM_ENUM("A DAC1 R source" , rt5650_a_dac1_r_enum); |
1587 | |
1588 | /* MX-2d [1] [0] */ |
1589 | static const char * const rt5650_a_dac2_src[] = { |
1590 | "Stereo DAC Mixer" , "Mono DAC Mixer" |
1591 | }; |
1592 | |
1593 | static SOC_ENUM_SINGLE_DECL( |
1594 | rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, |
1595 | RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); |
1596 | |
1597 | static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = |
1598 | SOC_DAPM_ENUM("A DAC2 L source" , rt5650_a_dac2_l_enum); |
1599 | |
1600 | static SOC_ENUM_SINGLE_DECL( |
1601 | rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, |
1602 | RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); |
1603 | |
1604 | static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = |
1605 | SOC_DAPM_ENUM("A DAC2 R source" , rt5650_a_dac2_r_enum); |
1606 | |
1607 | /* MX-2F [13:12] */ |
1608 | static const char * const rt5645_if2_adc_in_src[] = { |
1609 | "IF_ADC1" , "IF_ADC2" , "VAD_ADC" |
1610 | }; |
1611 | |
1612 | static SOC_ENUM_SINGLE_DECL( |
1613 | rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, |
1614 | RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); |
1615 | |
1616 | static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = |
1617 | SOC_DAPM_ENUM("IF2 ADC IN source" , rt5645_if2_adc_in_enum); |
1618 | |
1619 | /* MX-31 [15] [13] [11] [9] */ |
1620 | static const char * const rt5645_pdm_src[] = { |
1621 | "Mono DAC" , "Stereo DAC" |
1622 | }; |
1623 | |
1624 | static SOC_ENUM_SINGLE_DECL( |
1625 | rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, |
1626 | RT5645_PDM1_L_SFT, rt5645_pdm_src); |
1627 | |
1628 | static const struct snd_kcontrol_new rt5645_pdm1_l_mux = |
1629 | SOC_DAPM_ENUM("PDM1 L source" , rt5645_pdm1_l_enum); |
1630 | |
1631 | static SOC_ENUM_SINGLE_DECL( |
1632 | rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, |
1633 | RT5645_PDM1_R_SFT, rt5645_pdm_src); |
1634 | |
1635 | static const struct snd_kcontrol_new rt5645_pdm1_r_mux = |
1636 | SOC_DAPM_ENUM("PDM1 R source" , rt5645_pdm1_r_enum); |
1637 | |
1638 | /* MX-9D [9:8] */ |
1639 | static const char * const rt5645_vad_adc_src[] = { |
1640 | "Sto1 ADC L" , "Mono ADC L" , "Mono ADC R" |
1641 | }; |
1642 | |
1643 | static SOC_ENUM_SINGLE_DECL( |
1644 | rt5645_vad_adc_enum, RT5645_VAD_CTRL4, |
1645 | RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); |
1646 | |
1647 | static const struct snd_kcontrol_new rt5645_vad_adc_mux = |
1648 | SOC_DAPM_ENUM("VAD ADC source" , rt5645_vad_adc_enum); |
1649 | |
1650 | static const struct snd_kcontrol_new spk_l_vol_control = |
1651 | SOC_DAPM_SINGLE_AUTODISABLE("Switch" , RT5645_SPK_VOL, |
1652 | RT5645_L_MUTE_SFT, 1, 1); |
1653 | |
1654 | static const struct snd_kcontrol_new spk_r_vol_control = |
1655 | SOC_DAPM_SINGLE_AUTODISABLE("Switch" , RT5645_SPK_VOL, |
1656 | RT5645_R_MUTE_SFT, 1, 1); |
1657 | |
1658 | static const struct snd_kcontrol_new hp_l_vol_control = |
1659 | SOC_DAPM_SINGLE_AUTODISABLE("Switch" , RT5645_HP_VOL, |
1660 | RT5645_L_MUTE_SFT, 1, 1); |
1661 | |
1662 | static const struct snd_kcontrol_new hp_r_vol_control = |
1663 | SOC_DAPM_SINGLE_AUTODISABLE("Switch" , RT5645_HP_VOL, |
1664 | RT5645_R_MUTE_SFT, 1, 1); |
1665 | |
1666 | static const struct snd_kcontrol_new pdm1_l_vol_control = |
1667 | SOC_DAPM_SINGLE_AUTODISABLE("Switch" , RT5645_PDM_OUT_CTRL, |
1668 | RT5645_M_PDM1_L, 1, 1); |
1669 | |
1670 | static const struct snd_kcontrol_new pdm1_r_vol_control = |
1671 | SOC_DAPM_SINGLE_AUTODISABLE("Switch" , RT5645_PDM_OUT_CTRL, |
1672 | RT5645_M_PDM1_R, 1, 1); |
1673 | |
1674 | static void hp_amp_power(struct snd_soc_component *component, int on) |
1675 | { |
1676 | static int hp_amp_power_count; |
1677 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
1678 | int i, val; |
1679 | |
1680 | if (on) { |
1681 | if (hp_amp_power_count <= 0) { |
1682 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
1683 | snd_soc_component_write(component, RT5645_DEPOP_M2, val: 0x3100); |
1684 | snd_soc_component_write(component, RT5645_CHARGE_PUMP, |
1685 | val: 0x0e06); |
1686 | snd_soc_component_write(component, RT5645_DEPOP_M1, val: 0x000d); |
1687 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1688 | RT5645_HP_DCC_INT1, val: 0x9f01); |
1689 | for (i = 0; i < 20; i++) { |
1690 | usleep_range(min: 1000, max: 1500); |
1691 | regmap_read(map: rt5645->regmap, RT5645_PR_BASE + |
1692 | RT5645_HP_DCC_INT1, val: &val); |
1693 | if (!(val & 0x8000)) |
1694 | break; |
1695 | } |
1696 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1697 | RT5645_HP_CO_MASK, RT5645_HP_CO_EN); |
1698 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1699 | 0x3e, val: 0x7400); |
1700 | snd_soc_component_write(component, RT5645_DEPOP_M3, val: 0x0737); |
1701 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1702 | RT5645_MAMP_INT_REG2, val: 0xfc00); |
1703 | snd_soc_component_write(component, RT5645_DEPOP_M2, val: 0x1140); |
1704 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1705 | RT5645_PWR_HP_L | RT5645_PWR_HP_R, |
1706 | RT5645_PWR_HP_L | RT5645_PWR_HP_R); |
1707 | msleep(msecs: 90); |
1708 | } else { |
1709 | /* depop parameters */ |
1710 | snd_soc_component_update_bits(component, RT5645_DEPOP_M2, |
1711 | RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); |
1712 | snd_soc_component_write(component, RT5645_DEPOP_M1, val: 0x000d); |
1713 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1714 | RT5645_HP_DCC_INT1, val: 0x9f01); |
1715 | mdelay(150); |
1716 | /* headphone amp power on */ |
1717 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1718 | RT5645_PWR_FV1 | RT5645_PWR_FV2, val: 0); |
1719 | snd_soc_component_update_bits(component, RT5645_PWR_VOL, |
1720 | RT5645_PWR_HV_L | RT5645_PWR_HV_R, |
1721 | RT5645_PWR_HV_L | RT5645_PWR_HV_R); |
1722 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1723 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | |
1724 | RT5645_PWR_HA, |
1725 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | |
1726 | RT5645_PWR_HA); |
1727 | mdelay(5); |
1728 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1729 | RT5645_PWR_FV1 | RT5645_PWR_FV2, |
1730 | RT5645_PWR_FV1 | RT5645_PWR_FV2); |
1731 | |
1732 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1733 | RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, |
1734 | RT5645_HP_CO_EN | RT5645_HP_SG_EN); |
1735 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1736 | 0x14, val: 0x1aaa); |
1737 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1738 | 0x24, val: 0x0430); |
1739 | } |
1740 | } |
1741 | hp_amp_power_count++; |
1742 | } else { |
1743 | hp_amp_power_count--; |
1744 | if (hp_amp_power_count <= 0) { |
1745 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
1746 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1747 | 0x3e, val: 0x7400); |
1748 | snd_soc_component_write(component, RT5645_DEPOP_M3, val: 0x0737); |
1749 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1750 | RT5645_MAMP_INT_REG2, val: 0xfc00); |
1751 | snd_soc_component_write(component, RT5645_DEPOP_M2, val: 0x1140); |
1752 | msleep(msecs: 100); |
1753 | snd_soc_component_write(component, RT5645_DEPOP_M1, val: 0x0001); |
1754 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1755 | RT5645_PWR_HP_L | RT5645_PWR_HP_R, val: 0); |
1756 | } else { |
1757 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1758 | RT5645_HP_SG_MASK | |
1759 | RT5645_HP_L_SMT_MASK | |
1760 | RT5645_HP_R_SMT_MASK, |
1761 | RT5645_HP_SG_DIS | |
1762 | RT5645_HP_L_SMT_DIS | |
1763 | RT5645_HP_R_SMT_DIS); |
1764 | /* headphone amp power down */ |
1765 | snd_soc_component_write(component, RT5645_DEPOP_M1, val: 0x0000); |
1766 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1767 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | |
1768 | RT5645_PWR_HA, val: 0); |
1769 | snd_soc_component_update_bits(component, RT5645_DEPOP_M2, |
1770 | RT5645_DEPOP_MASK, val: 0); |
1771 | } |
1772 | } |
1773 | } |
1774 | } |
1775 | |
1776 | static int rt5645_hp_event(struct snd_soc_dapm_widget *w, |
1777 | struct snd_kcontrol *kcontrol, int event) |
1778 | { |
1779 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1780 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
1781 | |
1782 | switch (event) { |
1783 | case SND_SOC_DAPM_POST_PMU: |
1784 | hp_amp_power(component, on: 1); |
1785 | /* headphone unmute sequence */ |
1786 | if (rt5645->codec_type == CODEC_TYPE_RT5645) { |
1787 | snd_soc_component_update_bits(component, RT5645_DEPOP_M3, |
1788 | RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | |
1789 | RT5645_CP_FQ3_MASK, |
1790 | val: (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | |
1791 | (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | |
1792 | (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); |
1793 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1794 | RT5645_MAMP_INT_REG2, val: 0xfc00); |
1795 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1796 | RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); |
1797 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1798 | RT5645_RSTN_MASK, RT5645_RSTN_EN); |
1799 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1800 | RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | |
1801 | RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | |
1802 | RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); |
1803 | msleep(msecs: 40); |
1804 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1805 | RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | |
1806 | RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | |
1807 | RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); |
1808 | } |
1809 | break; |
1810 | |
1811 | case SND_SOC_DAPM_PRE_PMD: |
1812 | /* headphone mute sequence */ |
1813 | if (rt5645->codec_type == CODEC_TYPE_RT5645) { |
1814 | snd_soc_component_update_bits(component, RT5645_DEPOP_M3, |
1815 | RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | |
1816 | RT5645_CP_FQ3_MASK, |
1817 | val: (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | |
1818 | (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | |
1819 | (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); |
1820 | regmap_write(map: rt5645->regmap, RT5645_PR_BASE + |
1821 | RT5645_MAMP_INT_REG2, val: 0xfc00); |
1822 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1823 | RT5645_HP_SG_MASK, RT5645_HP_SG_EN); |
1824 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1825 | RT5645_RSTP_MASK, RT5645_RSTP_EN); |
1826 | snd_soc_component_update_bits(component, RT5645_DEPOP_M1, |
1827 | RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | |
1828 | RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | |
1829 | RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); |
1830 | msleep(msecs: 30); |
1831 | } |
1832 | hp_amp_power(component, on: 0); |
1833 | break; |
1834 | |
1835 | default: |
1836 | return 0; |
1837 | } |
1838 | |
1839 | return 0; |
1840 | } |
1841 | |
1842 | static int rt5645_spk_event(struct snd_soc_dapm_widget *w, |
1843 | struct snd_kcontrol *kcontrol, int event) |
1844 | { |
1845 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1846 | |
1847 | switch (event) { |
1848 | case SND_SOC_DAPM_POST_PMU: |
1849 | rt5645_enable_hweq(component); |
1850 | snd_soc_component_update_bits(component, RT5645_PWR_DIG1, |
1851 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | |
1852 | RT5645_PWR_CLS_D_L, |
1853 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | |
1854 | RT5645_PWR_CLS_D_L); |
1855 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, |
1856 | RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1); |
1857 | break; |
1858 | |
1859 | case SND_SOC_DAPM_PRE_PMD: |
1860 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, |
1861 | RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS); |
1862 | snd_soc_component_write(component, RT5645_EQ_CTRL2, val: 0); |
1863 | snd_soc_component_update_bits(component, RT5645_PWR_DIG1, |
1864 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | |
1865 | RT5645_PWR_CLS_D_L, val: 0); |
1866 | break; |
1867 | |
1868 | default: |
1869 | return 0; |
1870 | } |
1871 | |
1872 | return 0; |
1873 | } |
1874 | |
1875 | static int rt5645_lout_event(struct snd_soc_dapm_widget *w, |
1876 | struct snd_kcontrol *kcontrol, int event) |
1877 | { |
1878 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1879 | |
1880 | switch (event) { |
1881 | case SND_SOC_DAPM_POST_PMU: |
1882 | hp_amp_power(component, on: 1); |
1883 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1884 | RT5645_PWR_LM, RT5645_PWR_LM); |
1885 | snd_soc_component_update_bits(component, RT5645_LOUT1, |
1886 | RT5645_L_MUTE | RT5645_R_MUTE, val: 0); |
1887 | break; |
1888 | |
1889 | case SND_SOC_DAPM_PRE_PMD: |
1890 | snd_soc_component_update_bits(component, RT5645_LOUT1, |
1891 | RT5645_L_MUTE | RT5645_R_MUTE, |
1892 | RT5645_L_MUTE | RT5645_R_MUTE); |
1893 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
1894 | RT5645_PWR_LM, val: 0); |
1895 | hp_amp_power(component, on: 0); |
1896 | break; |
1897 | |
1898 | default: |
1899 | return 0; |
1900 | } |
1901 | |
1902 | return 0; |
1903 | } |
1904 | |
1905 | static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, |
1906 | struct snd_kcontrol *kcontrol, int event) |
1907 | { |
1908 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1909 | |
1910 | switch (event) { |
1911 | case SND_SOC_DAPM_POST_PMU: |
1912 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, |
1913 | RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); |
1914 | break; |
1915 | |
1916 | case SND_SOC_DAPM_PRE_PMD: |
1917 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, |
1918 | RT5645_PWR_BST2_P, val: 0); |
1919 | break; |
1920 | |
1921 | default: |
1922 | return 0; |
1923 | } |
1924 | |
1925 | return 0; |
1926 | } |
1927 | |
1928 | static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w, |
1929 | struct snd_kcontrol *k, int event) |
1930 | { |
1931 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1932 | |
1933 | switch (event) { |
1934 | case SND_SOC_DAPM_PRE_PMU: |
1935 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, |
1936 | RT5645_MICBIAS1_POW_CTRL_SEL_MASK, |
1937 | RT5645_MICBIAS1_POW_CTRL_SEL_M); |
1938 | break; |
1939 | |
1940 | case SND_SOC_DAPM_POST_PMD: |
1941 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, |
1942 | RT5645_MICBIAS1_POW_CTRL_SEL_MASK, |
1943 | RT5645_MICBIAS1_POW_CTRL_SEL_A); |
1944 | break; |
1945 | |
1946 | default: |
1947 | return 0; |
1948 | } |
1949 | |
1950 | return 0; |
1951 | } |
1952 | |
1953 | static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w, |
1954 | struct snd_kcontrol *k, int event) |
1955 | { |
1956 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1957 | |
1958 | switch (event) { |
1959 | case SND_SOC_DAPM_PRE_PMU: |
1960 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, |
1961 | RT5645_MICBIAS2_POW_CTRL_SEL_MASK, |
1962 | RT5645_MICBIAS2_POW_CTRL_SEL_M); |
1963 | break; |
1964 | |
1965 | case SND_SOC_DAPM_POST_PMD: |
1966 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, |
1967 | RT5645_MICBIAS2_POW_CTRL_SEL_MASK, |
1968 | RT5645_MICBIAS2_POW_CTRL_SEL_A); |
1969 | break; |
1970 | |
1971 | default: |
1972 | return 0; |
1973 | } |
1974 | |
1975 | return 0; |
1976 | } |
1977 | |
1978 | static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { |
1979 | SND_SOC_DAPM_SUPPLY("LDO2" , RT5645_PWR_MIXER, |
1980 | RT5645_PWR_LDO2_BIT, 0, NULL, 0), |
1981 | SND_SOC_DAPM_SUPPLY("PLL1" , RT5645_PWR_ANLG2, |
1982 | RT5645_PWR_PLL_BIT, 0, NULL, 0), |
1983 | |
1984 | SND_SOC_DAPM_SUPPLY("JD Power" , RT5645_PWR_ANLG2, |
1985 | RT5645_PWR_JD1_BIT, 0, NULL, 0), |
1986 | SND_SOC_DAPM_SUPPLY("Mic Det Power" , RT5645_PWR_VOL, |
1987 | RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), |
1988 | |
1989 | /* ASRC */ |
1990 | SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC" , 1, RT5645_ASRC_1, |
1991 | 11, 0, NULL, 0), |
1992 | SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC" , 1, RT5645_ASRC_1, |
1993 | 12, 0, NULL, 0), |
1994 | SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC" , 1, RT5645_ASRC_1, |
1995 | 10, 0, NULL, 0), |
1996 | SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC" , 1, RT5645_ASRC_1, |
1997 | 9, 0, NULL, 0), |
1998 | SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC" , 1, RT5645_ASRC_1, |
1999 | 8, 0, NULL, 0), |
2000 | SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC" , 1, RT5645_ASRC_1, |
2001 | 7, 0, NULL, 0), |
2002 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC" , 1, RT5645_ASRC_1, |
2003 | 5, 0, NULL, 0), |
2004 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC" , 1, RT5645_ASRC_1, |
2005 | 4, 0, NULL, 0), |
2006 | SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC" , 1, RT5645_ASRC_1, |
2007 | 3, 0, NULL, 0), |
2008 | SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC" , 1, RT5645_ASRC_1, |
2009 | 1, 0, NULL, 0), |
2010 | SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC" , 1, RT5645_ASRC_1, |
2011 | 0, 0, NULL, 0), |
2012 | |
2013 | /* Input Side */ |
2014 | /* micbias */ |
2015 | SND_SOC_DAPM_SUPPLY("micbias1" , RT5645_PWR_ANLG2, |
2016 | RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event, |
2017 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
2018 | SND_SOC_DAPM_SUPPLY("micbias2" , RT5645_PWR_ANLG2, |
2019 | RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event, |
2020 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
2021 | /* Input Lines */ |
2022 | SND_SOC_DAPM_INPUT("DMIC L1" ), |
2023 | SND_SOC_DAPM_INPUT("DMIC R1" ), |
2024 | SND_SOC_DAPM_INPUT("DMIC L2" ), |
2025 | SND_SOC_DAPM_INPUT("DMIC R2" ), |
2026 | |
2027 | SND_SOC_DAPM_INPUT("IN1P" ), |
2028 | SND_SOC_DAPM_INPUT("IN1N" ), |
2029 | SND_SOC_DAPM_INPUT("IN2P" ), |
2030 | SND_SOC_DAPM_INPUT("IN2N" ), |
2031 | |
2032 | SND_SOC_DAPM_INPUT("Haptic Generator" ), |
2033 | |
2034 | SND_SOC_DAPM_PGA("DMIC1" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2035 | SND_SOC_DAPM_PGA("DMIC2" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2036 | SND_SOC_DAPM_SUPPLY("DMIC CLK" , SND_SOC_NOPM, 0, 0, |
2037 | set_dmic_clk, SND_SOC_DAPM_PRE_PMU), |
2038 | SND_SOC_DAPM_SUPPLY("DMIC1 Power" , RT5645_DMIC_CTRL1, |
2039 | RT5645_DMIC_1_EN_SFT, 0, NULL, 0), |
2040 | SND_SOC_DAPM_SUPPLY("DMIC2 Power" , RT5645_DMIC_CTRL1, |
2041 | RT5645_DMIC_2_EN_SFT, 0, NULL, 0), |
2042 | /* Boost */ |
2043 | SND_SOC_DAPM_PGA("BST1" , RT5645_PWR_ANLG2, |
2044 | RT5645_PWR_BST1_BIT, 0, NULL, 0), |
2045 | SND_SOC_DAPM_PGA_E("BST2" , RT5645_PWR_ANLG2, |
2046 | RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, |
2047 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
2048 | /* Input Volume */ |
2049 | SND_SOC_DAPM_PGA("INL VOL" , RT5645_PWR_VOL, |
2050 | RT5645_PWR_IN_L_BIT, 0, NULL, 0), |
2051 | SND_SOC_DAPM_PGA("INR VOL" , RT5645_PWR_VOL, |
2052 | RT5645_PWR_IN_R_BIT, 0, NULL, 0), |
2053 | /* REC Mixer */ |
2054 | SND_SOC_DAPM_MIXER("RECMIXL" , RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, |
2055 | 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), |
2056 | SND_SOC_DAPM_MIXER("RECMIXR" , RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, |
2057 | 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), |
2058 | /* ADCs */ |
2059 | SND_SOC_DAPM_ADC("ADC L" , NULL, SND_SOC_NOPM, 0, 0), |
2060 | SND_SOC_DAPM_ADC("ADC R" , NULL, SND_SOC_NOPM, 0, 0), |
2061 | |
2062 | SND_SOC_DAPM_SUPPLY("ADC L power" , RT5645_PWR_DIG1, |
2063 | RT5645_PWR_ADC_L_BIT, 0, NULL, 0), |
2064 | SND_SOC_DAPM_SUPPLY("ADC R power" , RT5645_PWR_DIG1, |
2065 | RT5645_PWR_ADC_R_BIT, 0, NULL, 0), |
2066 | |
2067 | /* ADC Mux */ |
2068 | SND_SOC_DAPM_MUX("Stereo1 DMIC Mux" , SND_SOC_NOPM, 0, 0, |
2069 | &rt5645_sto1_dmic_mux), |
2070 | SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux" , SND_SOC_NOPM, 0, 0, |
2071 | &rt5645_sto_adc2_mux), |
2072 | SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux" , SND_SOC_NOPM, 0, 0, |
2073 | &rt5645_sto_adc2_mux), |
2074 | SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux" , SND_SOC_NOPM, 0, 0, |
2075 | &rt5645_sto_adc1_mux), |
2076 | SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux" , SND_SOC_NOPM, 0, 0, |
2077 | &rt5645_sto_adc1_mux), |
2078 | SND_SOC_DAPM_MUX("Mono DMIC L Mux" , SND_SOC_NOPM, 0, 0, |
2079 | &rt5645_mono_dmic_l_mux), |
2080 | SND_SOC_DAPM_MUX("Mono DMIC R Mux" , SND_SOC_NOPM, 0, 0, |
2081 | &rt5645_mono_dmic_r_mux), |
2082 | SND_SOC_DAPM_MUX("Mono ADC L2 Mux" , SND_SOC_NOPM, 0, 0, |
2083 | &rt5645_mono_adc_l2_mux), |
2084 | SND_SOC_DAPM_MUX("Mono ADC L1 Mux" , SND_SOC_NOPM, 0, 0, |
2085 | &rt5645_mono_adc_l1_mux), |
2086 | SND_SOC_DAPM_MUX("Mono ADC R1 Mux" , SND_SOC_NOPM, 0, 0, |
2087 | &rt5645_mono_adc_r1_mux), |
2088 | SND_SOC_DAPM_MUX("Mono ADC R2 Mux" , SND_SOC_NOPM, 0, 0, |
2089 | &rt5645_mono_adc_r2_mux), |
2090 | /* ADC Mixer */ |
2091 | |
2092 | SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter" , 1, RT5645_PWR_DIG2, |
2093 | RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), |
2094 | SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL" , SND_SOC_NOPM, 0, 0, |
2095 | rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), |
2096 | NULL, 0), |
2097 | SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR" , SND_SOC_NOPM, 0, 0, |
2098 | rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), |
2099 | NULL, 0), |
2100 | SND_SOC_DAPM_SUPPLY_S("adc mono left filter" , 1, RT5645_PWR_DIG2, |
2101 | RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), |
2102 | SND_SOC_DAPM_MIXER_E("Mono ADC MIXL" , SND_SOC_NOPM, 0, 0, |
2103 | rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), |
2104 | NULL, 0), |
2105 | SND_SOC_DAPM_SUPPLY_S("adc mono right filter" , 1, RT5645_PWR_DIG2, |
2106 | RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), |
2107 | SND_SOC_DAPM_MIXER_E("Mono ADC MIXR" , SND_SOC_NOPM, 0, 0, |
2108 | rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), |
2109 | NULL, 0), |
2110 | |
2111 | /* ADC PGA */ |
2112 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXL" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2113 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXR" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2114 | SND_SOC_DAPM_PGA("Sto2 ADC LR MIX" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2115 | SND_SOC_DAPM_PGA("VAD_ADC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2116 | SND_SOC_DAPM_PGA("IF_ADC1" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2117 | SND_SOC_DAPM_PGA("IF_ADC2" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2118 | SND_SOC_DAPM_PGA("IF1_ADC1" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2119 | SND_SOC_DAPM_PGA("IF1_ADC2" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2120 | SND_SOC_DAPM_PGA("IF1_ADC3" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2121 | SND_SOC_DAPM_PGA("IF1_ADC4" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2122 | |
2123 | /* IF1 2 Mux */ |
2124 | SND_SOC_DAPM_MUX("IF2 ADC Mux" , SND_SOC_NOPM, |
2125 | 0, 0, &rt5645_if2_adc_in_mux), |
2126 | |
2127 | /* Digital Interface */ |
2128 | SND_SOC_DAPM_SUPPLY("I2S1" , RT5645_PWR_DIG1, |
2129 | RT5645_PWR_I2S1_BIT, 0, NULL, 0), |
2130 | SND_SOC_DAPM_PGA("IF1 DAC0" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2131 | SND_SOC_DAPM_PGA("IF1 DAC1" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2132 | SND_SOC_DAPM_PGA("IF1 DAC2" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2133 | SND_SOC_DAPM_PGA("IF1 DAC3" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2134 | SND_SOC_DAPM_PGA("IF1 ADC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2135 | SND_SOC_DAPM_PGA("IF1 ADC L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2136 | SND_SOC_DAPM_PGA("IF1 ADC R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2137 | SND_SOC_DAPM_SUPPLY("I2S2" , RT5645_PWR_DIG1, |
2138 | RT5645_PWR_I2S2_BIT, 0, NULL, 0), |
2139 | SND_SOC_DAPM_PGA("IF2 DAC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2140 | SND_SOC_DAPM_PGA("IF2 DAC L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2141 | SND_SOC_DAPM_PGA("IF2 DAC R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2142 | SND_SOC_DAPM_PGA("IF2 ADC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2143 | |
2144 | /* Digital Interface Select */ |
2145 | SND_SOC_DAPM_MUX("VAD ADC Mux" , SND_SOC_NOPM, |
2146 | 0, 0, &rt5645_vad_adc_mux), |
2147 | |
2148 | /* Audio Interface */ |
2149 | SND_SOC_DAPM_AIF_IN("AIF1RX" , "AIF1 Playback" , 0, SND_SOC_NOPM, 0, 0), |
2150 | SND_SOC_DAPM_AIF_OUT("AIF1TX" , "AIF1 Capture" , 0, SND_SOC_NOPM, 0, 0), |
2151 | SND_SOC_DAPM_AIF_IN("AIF2RX" , "AIF2 Playback" , 0, SND_SOC_NOPM, 0, 0), |
2152 | SND_SOC_DAPM_AIF_OUT("AIF2TX" , "AIF2 Capture" , 0, SND_SOC_NOPM, 0, 0), |
2153 | |
2154 | /* Output Side */ |
2155 | /* DAC mixer before sound effect */ |
2156 | SND_SOC_DAPM_MIXER("DAC1 MIXL" , SND_SOC_NOPM, 0, 0, |
2157 | rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), |
2158 | SND_SOC_DAPM_MIXER("DAC1 MIXR" , SND_SOC_NOPM, 0, 0, |
2159 | rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), |
2160 | |
2161 | /* DAC2 channel Mux */ |
2162 | SND_SOC_DAPM_MUX("DAC L2 Mux" , SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), |
2163 | SND_SOC_DAPM_MUX("DAC R2 Mux" , SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), |
2164 | SND_SOC_DAPM_PGA("DAC L2 Volume" , RT5645_PWR_DIG1, |
2165 | RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), |
2166 | SND_SOC_DAPM_PGA("DAC R2 Volume" , RT5645_PWR_DIG1, |
2167 | RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), |
2168 | |
2169 | SND_SOC_DAPM_MUX("DAC1 L Mux" , SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), |
2170 | SND_SOC_DAPM_MUX("DAC1 R Mux" , SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), |
2171 | |
2172 | /* DAC Mixer */ |
2173 | SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter" , 1, RT5645_PWR_DIG2, |
2174 | RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), |
2175 | SND_SOC_DAPM_SUPPLY_S("dac mono left filter" , 1, RT5645_PWR_DIG2, |
2176 | RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), |
2177 | SND_SOC_DAPM_SUPPLY_S("dac mono right filter" , 1, RT5645_PWR_DIG2, |
2178 | RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), |
2179 | SND_SOC_DAPM_MIXER("Stereo DAC MIXL" , SND_SOC_NOPM, 0, 0, |
2180 | rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), |
2181 | SND_SOC_DAPM_MIXER("Stereo DAC MIXR" , SND_SOC_NOPM, 0, 0, |
2182 | rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), |
2183 | SND_SOC_DAPM_MIXER("Mono DAC MIXL" , SND_SOC_NOPM, 0, 0, |
2184 | rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), |
2185 | SND_SOC_DAPM_MIXER("Mono DAC MIXR" , SND_SOC_NOPM, 0, 0, |
2186 | rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), |
2187 | SND_SOC_DAPM_MIXER("DAC MIXL" , SND_SOC_NOPM, 0, 0, |
2188 | rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), |
2189 | SND_SOC_DAPM_MIXER("DAC MIXR" , SND_SOC_NOPM, 0, 0, |
2190 | rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), |
2191 | |
2192 | /* DACs */ |
2193 | SND_SOC_DAPM_DAC("DAC L1" , NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, |
2194 | 0), |
2195 | SND_SOC_DAPM_DAC("DAC L2" , NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, |
2196 | 0), |
2197 | SND_SOC_DAPM_DAC("DAC R1" , NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, |
2198 | 0), |
2199 | SND_SOC_DAPM_DAC("DAC R2" , NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, |
2200 | 0), |
2201 | /* OUT Mixer */ |
2202 | SND_SOC_DAPM_MIXER("SPK MIXL" , RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, |
2203 | 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), |
2204 | SND_SOC_DAPM_MIXER("SPK MIXR" , RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, |
2205 | 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), |
2206 | SND_SOC_DAPM_MIXER("OUT MIXL" , RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, |
2207 | 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), |
2208 | SND_SOC_DAPM_MIXER("OUT MIXR" , RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, |
2209 | 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), |
2210 | /* Ouput Volume */ |
2211 | SND_SOC_DAPM_SWITCH("SPKVOL L" , RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, |
2212 | &spk_l_vol_control), |
2213 | SND_SOC_DAPM_SWITCH("SPKVOL R" , RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, |
2214 | &spk_r_vol_control), |
2215 | SND_SOC_DAPM_MIXER("HPOVOL MIXL" , RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, |
2216 | 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), |
2217 | SND_SOC_DAPM_MIXER("HPOVOL MIXR" , RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, |
2218 | 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), |
2219 | SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power" , RT5645_PWR_MIXER, |
2220 | RT5645_PWR_HM_L_BIT, 0, NULL, 0), |
2221 | SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power" , RT5645_PWR_MIXER, |
2222 | RT5645_PWR_HM_R_BIT, 0, NULL, 0), |
2223 | SND_SOC_DAPM_PGA("DAC 1" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2224 | SND_SOC_DAPM_PGA("DAC 2" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2225 | SND_SOC_DAPM_PGA("HPOVOL" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2226 | SND_SOC_DAPM_SWITCH("HPOVOL L" , SND_SOC_NOPM, 0, 0, &hp_l_vol_control), |
2227 | SND_SOC_DAPM_SWITCH("HPOVOL R" , SND_SOC_NOPM, 0, 0, &hp_r_vol_control), |
2228 | |
2229 | /* HPO/LOUT/Mono Mixer */ |
2230 | SND_SOC_DAPM_MIXER("SPOL MIX" , SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, |
2231 | ARRAY_SIZE(rt5645_spo_l_mix)), |
2232 | SND_SOC_DAPM_MIXER("SPOR MIX" , SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, |
2233 | ARRAY_SIZE(rt5645_spo_r_mix)), |
2234 | SND_SOC_DAPM_MIXER("HPO MIX" , SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, |
2235 | ARRAY_SIZE(rt5645_hpo_mix)), |
2236 | SND_SOC_DAPM_MIXER("LOUT MIX" , SND_SOC_NOPM, 0, 0, rt5645_lout_mix, |
2237 | ARRAY_SIZE(rt5645_lout_mix)), |
2238 | |
2239 | SND_SOC_DAPM_PGA_S("HP amp" , 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, |
2240 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
2241 | SND_SOC_DAPM_PGA_S("LOUT amp" , 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, |
2242 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
2243 | SND_SOC_DAPM_PGA_S("SPK amp" , 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, |
2244 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
2245 | |
2246 | /* PDM */ |
2247 | SND_SOC_DAPM_SUPPLY("PDM1 Power" , RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, |
2248 | 0, NULL, 0), |
2249 | SND_SOC_DAPM_MUX("PDM1 L Mux" , SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), |
2250 | SND_SOC_DAPM_MUX("PDM1 R Mux" , SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), |
2251 | |
2252 | SND_SOC_DAPM_SWITCH("PDM1 L" , SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), |
2253 | SND_SOC_DAPM_SWITCH("PDM1 R" , SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), |
2254 | |
2255 | /* Output Lines */ |
2256 | SND_SOC_DAPM_OUTPUT("HPOL" ), |
2257 | SND_SOC_DAPM_OUTPUT("HPOR" ), |
2258 | SND_SOC_DAPM_OUTPUT("LOUTL" ), |
2259 | SND_SOC_DAPM_OUTPUT("LOUTR" ), |
2260 | SND_SOC_DAPM_OUTPUT("PDM1L" ), |
2261 | SND_SOC_DAPM_OUTPUT("PDM1R" ), |
2262 | SND_SOC_DAPM_OUTPUT("SPOL" ), |
2263 | SND_SOC_DAPM_OUTPUT("SPOR" ), |
2264 | }; |
2265 | |
2266 | static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { |
2267 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux" , SND_SOC_NOPM, 0, 0, |
2268 | &rt5645_if1_dac0_tdm_sel_mux), |
2269 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux" , SND_SOC_NOPM, 0, 0, |
2270 | &rt5645_if1_dac1_tdm_sel_mux), |
2271 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux" , SND_SOC_NOPM, 0, 0, |
2272 | &rt5645_if1_dac2_tdm_sel_mux), |
2273 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux" , SND_SOC_NOPM, 0, 0, |
2274 | &rt5645_if1_dac3_tdm_sel_mux), |
2275 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux" , SND_SOC_NOPM, |
2276 | 0, 0, &rt5645_if1_adc_in_mux), |
2277 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux" , SND_SOC_NOPM, |
2278 | 0, 0, &rt5645_if1_adc1_in_mux), |
2279 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux" , SND_SOC_NOPM, |
2280 | 0, 0, &rt5645_if1_adc2_in_mux), |
2281 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux" , SND_SOC_NOPM, |
2282 | 0, 0, &rt5645_if1_adc3_in_mux), |
2283 | }; |
2284 | |
2285 | static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { |
2286 | SND_SOC_DAPM_MUX("A DAC1 L Mux" , SND_SOC_NOPM, |
2287 | 0, 0, &rt5650_a_dac1_l_mux), |
2288 | SND_SOC_DAPM_MUX("A DAC1 R Mux" , SND_SOC_NOPM, |
2289 | 0, 0, &rt5650_a_dac1_r_mux), |
2290 | SND_SOC_DAPM_MUX("A DAC2 L Mux" , SND_SOC_NOPM, |
2291 | 0, 0, &rt5650_a_dac2_l_mux), |
2292 | SND_SOC_DAPM_MUX("A DAC2 R Mux" , SND_SOC_NOPM, |
2293 | 0, 0, &rt5650_a_dac2_r_mux), |
2294 | |
2295 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux" , SND_SOC_NOPM, |
2296 | 0, 0, &rt5650_if1_adc1_in_mux), |
2297 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux" , SND_SOC_NOPM, |
2298 | 0, 0, &rt5650_if1_adc2_in_mux), |
2299 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux" , SND_SOC_NOPM, |
2300 | 0, 0, &rt5650_if1_adc3_in_mux), |
2301 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux" , SND_SOC_NOPM, |
2302 | 0, 0, &rt5650_if1_adc_in_mux), |
2303 | |
2304 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux" , SND_SOC_NOPM, 0, 0, |
2305 | &rt5650_if1_dac0_tdm_sel_mux), |
2306 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux" , SND_SOC_NOPM, 0, 0, |
2307 | &rt5650_if1_dac1_tdm_sel_mux), |
2308 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux" , SND_SOC_NOPM, 0, 0, |
2309 | &rt5650_if1_dac2_tdm_sel_mux), |
2310 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux" , SND_SOC_NOPM, 0, 0, |
2311 | &rt5650_if1_dac3_tdm_sel_mux), |
2312 | }; |
2313 | |
2314 | static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { |
2315 | { "adc stereo1 filter" , NULL, "ADC STO1 ASRC" , is_using_asrc }, |
2316 | { "adc mono left filter" , NULL, "ADC MONO L ASRC" , is_using_asrc }, |
2317 | { "adc mono right filter" , NULL, "ADC MONO R ASRC" , is_using_asrc }, |
2318 | { "dac mono left filter" , NULL, "DAC MONO L ASRC" , is_using_asrc }, |
2319 | { "dac mono right filter" , NULL, "DAC MONO R ASRC" , is_using_asrc }, |
2320 | { "dac stereo1 filter" , NULL, "DAC STO ASRC" , is_using_asrc }, |
2321 | |
2322 | { "I2S1" , NULL, "I2S1 ASRC" }, |
2323 | { "I2S2" , NULL, "I2S2 ASRC" }, |
2324 | |
2325 | { "IN1P" , NULL, "LDO2" }, |
2326 | { "IN2P" , NULL, "LDO2" }, |
2327 | |
2328 | { "DMIC1" , NULL, "DMIC L1" }, |
2329 | { "DMIC1" , NULL, "DMIC R1" }, |
2330 | { "DMIC2" , NULL, "DMIC L2" }, |
2331 | { "DMIC2" , NULL, "DMIC R2" }, |
2332 | |
2333 | { "BST1" , NULL, "IN1P" }, |
2334 | { "BST1" , NULL, "IN1N" }, |
2335 | { "BST1" , NULL, "JD Power" }, |
2336 | { "BST1" , NULL, "Mic Det Power" }, |
2337 | { "BST2" , NULL, "IN2P" }, |
2338 | { "BST2" , NULL, "IN2N" }, |
2339 | |
2340 | { "INL VOL" , NULL, "IN2P" }, |
2341 | { "INR VOL" , NULL, "IN2N" }, |
2342 | |
2343 | { "RECMIXL" , "HPOL Switch" , "HPOL" }, |
2344 | { "RECMIXL" , "INL Switch" , "INL VOL" }, |
2345 | { "RECMIXL" , "BST2 Switch" , "BST2" }, |
2346 | { "RECMIXL" , "BST1 Switch" , "BST1" }, |
2347 | { "RECMIXL" , "OUT MIXL Switch" , "OUT MIXL" }, |
2348 | |
2349 | { "RECMIXR" , "HPOR Switch" , "HPOR" }, |
2350 | { "RECMIXR" , "INR Switch" , "INR VOL" }, |
2351 | { "RECMIXR" , "BST2 Switch" , "BST2" }, |
2352 | { "RECMIXR" , "BST1 Switch" , "BST1" }, |
2353 | { "RECMIXR" , "OUT MIXR Switch" , "OUT MIXR" }, |
2354 | |
2355 | { "ADC L" , NULL, "RECMIXL" }, |
2356 | { "ADC L" , NULL, "ADC L power" }, |
2357 | { "ADC R" , NULL, "RECMIXR" }, |
2358 | { "ADC R" , NULL, "ADC R power" }, |
2359 | |
2360 | {"DMIC L1" , NULL, "DMIC CLK" }, |
2361 | {"DMIC L1" , NULL, "DMIC1 Power" }, |
2362 | {"DMIC R1" , NULL, "DMIC CLK" }, |
2363 | {"DMIC R1" , NULL, "DMIC1 Power" }, |
2364 | {"DMIC L2" , NULL, "DMIC CLK" }, |
2365 | {"DMIC L2" , NULL, "DMIC2 Power" }, |
2366 | {"DMIC R2" , NULL, "DMIC CLK" }, |
2367 | {"DMIC R2" , NULL, "DMIC2 Power" }, |
2368 | |
2369 | { "Stereo1 DMIC Mux" , "DMIC1" , "DMIC1" }, |
2370 | { "Stereo1 DMIC Mux" , "DMIC2" , "DMIC2" }, |
2371 | { "Stereo1 DMIC Mux" , NULL, "DMIC STO1 ASRC" }, |
2372 | |
2373 | { "Mono DMIC L Mux" , "DMIC1" , "DMIC L1" }, |
2374 | { "Mono DMIC L Mux" , "DMIC2" , "DMIC L2" }, |
2375 | { "Mono DMIC L Mux" , NULL, "DMIC MONO L ASRC" }, |
2376 | |
2377 | { "Mono DMIC R Mux" , "DMIC1" , "DMIC R1" }, |
2378 | { "Mono DMIC R Mux" , "DMIC2" , "DMIC R2" }, |
2379 | { "Mono DMIC R Mux" , NULL, "DMIC MONO R ASRC" }, |
2380 | |
2381 | { "Stereo1 ADC L2 Mux" , "DMIC" , "Stereo1 DMIC Mux" }, |
2382 | { "Stereo1 ADC L2 Mux" , "DAC MIX" , "DAC MIXL" }, |
2383 | { "Stereo1 ADC L1 Mux" , "ADC" , "ADC L" }, |
2384 | { "Stereo1 ADC L1 Mux" , "DAC MIX" , "DAC MIXL" }, |
2385 | |
2386 | { "Stereo1 ADC R1 Mux" , "ADC" , "ADC R" }, |
2387 | { "Stereo1 ADC R1 Mux" , "DAC MIX" , "DAC MIXR" }, |
2388 | { "Stereo1 ADC R2 Mux" , "DMIC" , "Stereo1 DMIC Mux" }, |
2389 | { "Stereo1 ADC R2 Mux" , "DAC MIX" , "DAC MIXR" }, |
2390 | |
2391 | { "Mono ADC L2 Mux" , "DMIC" , "Mono DMIC L Mux" }, |
2392 | { "Mono ADC L2 Mux" , "Mono DAC MIXL" , "Mono DAC MIXL" }, |
2393 | { "Mono ADC L1 Mux" , "Mono DAC MIXL" , "Mono DAC MIXL" }, |
2394 | { "Mono ADC L1 Mux" , "ADC" , "ADC L" }, |
2395 | |
2396 | { "Mono ADC R1 Mux" , "Mono DAC MIXR" , "Mono DAC MIXR" }, |
2397 | { "Mono ADC R1 Mux" , "ADC" , "ADC R" }, |
2398 | { "Mono ADC R2 Mux" , "DMIC" , "Mono DMIC R Mux" }, |
2399 | { "Mono ADC R2 Mux" , "Mono DAC MIXR" , "Mono DAC MIXR" }, |
2400 | |
2401 | { "Sto1 ADC MIXL" , "ADC1 Switch" , "Stereo1 ADC L1 Mux" }, |
2402 | { "Sto1 ADC MIXL" , "ADC2 Switch" , "Stereo1 ADC L2 Mux" }, |
2403 | { "Sto1 ADC MIXR" , "ADC1 Switch" , "Stereo1 ADC R1 Mux" }, |
2404 | { "Sto1 ADC MIXR" , "ADC2 Switch" , "Stereo1 ADC R2 Mux" }, |
2405 | |
2406 | { "Stereo1 ADC MIXL" , NULL, "Sto1 ADC MIXL" }, |
2407 | { "Stereo1 ADC MIXL" , NULL, "adc stereo1 filter" }, |
2408 | { "adc stereo1 filter" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2409 | |
2410 | { "Stereo1 ADC MIXR" , NULL, "Sto1 ADC MIXR" }, |
2411 | { "Stereo1 ADC MIXR" , NULL, "adc stereo1 filter" }, |
2412 | { "adc stereo1 filter" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2413 | |
2414 | { "Mono ADC MIXL" , "ADC1 Switch" , "Mono ADC L1 Mux" }, |
2415 | { "Mono ADC MIXL" , "ADC2 Switch" , "Mono ADC L2 Mux" }, |
2416 | { "Mono ADC MIXL" , NULL, "adc mono left filter" }, |
2417 | { "adc mono left filter" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2418 | |
2419 | { "Mono ADC MIXR" , "ADC1 Switch" , "Mono ADC R1 Mux" }, |
2420 | { "Mono ADC MIXR" , "ADC2 Switch" , "Mono ADC R2 Mux" }, |
2421 | { "Mono ADC MIXR" , NULL, "adc mono right filter" }, |
2422 | { "adc mono right filter" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2423 | |
2424 | { "VAD ADC Mux" , "Sto1 ADC L" , "Stereo1 ADC MIXL" }, |
2425 | { "VAD ADC Mux" , "Mono ADC L" , "Mono ADC MIXL" }, |
2426 | { "VAD ADC Mux" , "Mono ADC R" , "Mono ADC MIXR" }, |
2427 | |
2428 | { "IF_ADC1" , NULL, "Stereo1 ADC MIXL" }, |
2429 | { "IF_ADC1" , NULL, "Stereo1 ADC MIXR" }, |
2430 | { "IF_ADC2" , NULL, "Mono ADC MIXL" }, |
2431 | { "IF_ADC2" , NULL, "Mono ADC MIXR" }, |
2432 | { "VAD_ADC" , NULL, "VAD ADC Mux" }, |
2433 | |
2434 | { "IF2 ADC Mux" , "IF_ADC1" , "IF_ADC1" }, |
2435 | { "IF2 ADC Mux" , "IF_ADC2" , "IF_ADC2" }, |
2436 | { "IF2 ADC Mux" , "VAD_ADC" , "VAD_ADC" }, |
2437 | |
2438 | { "IF1 ADC" , NULL, "I2S1" }, |
2439 | { "IF2 ADC" , NULL, "I2S2" }, |
2440 | { "IF2 ADC" , NULL, "IF2 ADC Mux" }, |
2441 | |
2442 | { "AIF2TX" , NULL, "IF2 ADC" }, |
2443 | |
2444 | { "IF1 DAC0" , NULL, "AIF1RX" }, |
2445 | { "IF1 DAC1" , NULL, "AIF1RX" }, |
2446 | { "IF1 DAC2" , NULL, "AIF1RX" }, |
2447 | { "IF1 DAC3" , NULL, "AIF1RX" }, |
2448 | { "IF2 DAC" , NULL, "AIF2RX" }, |
2449 | |
2450 | { "IF1 DAC0" , NULL, "I2S1" }, |
2451 | { "IF1 DAC1" , NULL, "I2S1" }, |
2452 | { "IF1 DAC2" , NULL, "I2S1" }, |
2453 | { "IF1 DAC3" , NULL, "I2S1" }, |
2454 | { "IF2 DAC" , NULL, "I2S2" }, |
2455 | |
2456 | { "IF2 DAC L" , NULL, "IF2 DAC" }, |
2457 | { "IF2 DAC R" , NULL, "IF2 DAC" }, |
2458 | |
2459 | { "DAC1 L Mux" , "IF2 DAC" , "IF2 DAC L" }, |
2460 | { "DAC1 R Mux" , "IF2 DAC" , "IF2 DAC R" }, |
2461 | |
2462 | { "DAC1 MIXL" , "Stereo ADC Switch" , "Stereo1 ADC MIXL" }, |
2463 | { "DAC1 MIXL" , "DAC1 Switch" , "DAC1 L Mux" }, |
2464 | { "DAC1 MIXL" , NULL, "dac stereo1 filter" }, |
2465 | { "DAC1 MIXR" , "Stereo ADC Switch" , "Stereo1 ADC MIXR" }, |
2466 | { "DAC1 MIXR" , "DAC1 Switch" , "DAC1 R Mux" }, |
2467 | { "DAC1 MIXR" , NULL, "dac stereo1 filter" }, |
2468 | |
2469 | { "DAC L2 Mux" , "IF2 DAC" , "IF2 DAC L" }, |
2470 | { "DAC L2 Mux" , "Mono ADC" , "Mono ADC MIXL" }, |
2471 | { "DAC L2 Mux" , "VAD_ADC" , "VAD_ADC" }, |
2472 | { "DAC L2 Volume" , NULL, "DAC L2 Mux" }, |
2473 | { "DAC L2 Volume" , NULL, "dac mono left filter" }, |
2474 | |
2475 | { "DAC R2 Mux" , "IF2 DAC" , "IF2 DAC R" }, |
2476 | { "DAC R2 Mux" , "Mono ADC" , "Mono ADC MIXR" }, |
2477 | { "DAC R2 Mux" , "Haptic" , "Haptic Generator" }, |
2478 | { "DAC R2 Volume" , NULL, "DAC R2 Mux" }, |
2479 | { "DAC R2 Volume" , NULL, "dac mono right filter" }, |
2480 | |
2481 | { "Stereo DAC MIXL" , "DAC L1 Switch" , "DAC1 MIXL" }, |
2482 | { "Stereo DAC MIXL" , "DAC R1 Switch" , "DAC1 MIXR" }, |
2483 | { "Stereo DAC MIXL" , "DAC L2 Switch" , "DAC L2 Volume" }, |
2484 | { "Stereo DAC MIXL" , NULL, "dac stereo1 filter" }, |
2485 | { "Stereo DAC MIXR" , "DAC R1 Switch" , "DAC1 MIXR" }, |
2486 | { "Stereo DAC MIXR" , "DAC L1 Switch" , "DAC1 MIXL" }, |
2487 | { "Stereo DAC MIXR" , "DAC R2 Switch" , "DAC R2 Volume" }, |
2488 | { "Stereo DAC MIXR" , NULL, "dac stereo1 filter" }, |
2489 | |
2490 | { "Mono DAC MIXL" , "DAC L1 Switch" , "DAC1 MIXL" }, |
2491 | { "Mono DAC MIXL" , "DAC L2 Switch" , "DAC L2 Volume" }, |
2492 | { "Mono DAC MIXL" , "DAC R2 Switch" , "DAC R2 Volume" }, |
2493 | { "Mono DAC MIXL" , NULL, "dac mono left filter" }, |
2494 | { "Mono DAC MIXR" , "DAC R1 Switch" , "DAC1 MIXR" }, |
2495 | { "Mono DAC MIXR" , "DAC R2 Switch" , "DAC R2 Volume" }, |
2496 | { "Mono DAC MIXR" , "DAC L2 Switch" , "DAC L2 Volume" }, |
2497 | { "Mono DAC MIXR" , NULL, "dac mono right filter" }, |
2498 | |
2499 | { "DAC MIXL" , "Sto DAC Mix L Switch" , "Stereo DAC MIXL" }, |
2500 | { "DAC MIXL" , "DAC L2 Switch" , "DAC L2 Volume" }, |
2501 | { "DAC MIXL" , "DAC R2 Switch" , "DAC R2 Volume" }, |
2502 | { "DAC MIXR" , "Sto DAC Mix R Switch" , "Stereo DAC MIXR" }, |
2503 | { "DAC MIXR" , "DAC R2 Switch" , "DAC R2 Volume" }, |
2504 | { "DAC MIXR" , "DAC L2 Switch" , "DAC L2 Volume" }, |
2505 | |
2506 | { "DAC L1" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2507 | { "DAC R1" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2508 | { "DAC L2" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2509 | { "DAC R2" , NULL, "PLL1" , is_sys_clk_from_pll }, |
2510 | |
2511 | { "SPK MIXL" , "BST1 Switch" , "BST1" }, |
2512 | { "SPK MIXL" , "INL Switch" , "INL VOL" }, |
2513 | { "SPK MIXL" , "DAC L1 Switch" , "DAC L1" }, |
2514 | { "SPK MIXL" , "DAC L2 Switch" , "DAC L2" }, |
2515 | { "SPK MIXR" , "BST2 Switch" , "BST2" }, |
2516 | { "SPK MIXR" , "INR Switch" , "INR VOL" }, |
2517 | { "SPK MIXR" , "DAC R1 Switch" , "DAC R1" }, |
2518 | { "SPK MIXR" , "DAC R2 Switch" , "DAC R2" }, |
2519 | |
2520 | { "OUT MIXL" , "BST1 Switch" , "BST1" }, |
2521 | { "OUT MIXL" , "INL Switch" , "INL VOL" }, |
2522 | { "OUT MIXL" , "DAC L2 Switch" , "DAC L2" }, |
2523 | { "OUT MIXL" , "DAC L1 Switch" , "DAC L1" }, |
2524 | |
2525 | { "OUT MIXR" , "BST2 Switch" , "BST2" }, |
2526 | { "OUT MIXR" , "INR Switch" , "INR VOL" }, |
2527 | { "OUT MIXR" , "DAC R2 Switch" , "DAC R2" }, |
2528 | { "OUT MIXR" , "DAC R1 Switch" , "DAC R1" }, |
2529 | |
2530 | { "HPOVOL MIXL" , "DAC1 Switch" , "DAC L1" }, |
2531 | { "HPOVOL MIXL" , "DAC2 Switch" , "DAC L2" }, |
2532 | { "HPOVOL MIXL" , "INL Switch" , "INL VOL" }, |
2533 | { "HPOVOL MIXL" , "BST1 Switch" , "BST1" }, |
2534 | { "HPOVOL MIXL" , NULL, "HPOVOL MIXL Power" }, |
2535 | { "HPOVOL MIXR" , "DAC1 Switch" , "DAC R1" }, |
2536 | { "HPOVOL MIXR" , "DAC2 Switch" , "DAC R2" }, |
2537 | { "HPOVOL MIXR" , "INR Switch" , "INR VOL" }, |
2538 | { "HPOVOL MIXR" , "BST2 Switch" , "BST2" }, |
2539 | { "HPOVOL MIXR" , NULL, "HPOVOL MIXR Power" }, |
2540 | |
2541 | { "DAC 2" , NULL, "DAC L2" }, |
2542 | { "DAC 2" , NULL, "DAC R2" }, |
2543 | { "DAC 1" , NULL, "DAC L1" }, |
2544 | { "DAC 1" , NULL, "DAC R1" }, |
2545 | { "HPOVOL L" , "Switch" , "HPOVOL MIXL" }, |
2546 | { "HPOVOL R" , "Switch" , "HPOVOL MIXR" }, |
2547 | { "HPOVOL" , NULL, "HPOVOL L" }, |
2548 | { "HPOVOL" , NULL, "HPOVOL R" }, |
2549 | { "HPO MIX" , "DAC1 Switch" , "DAC 1" }, |
2550 | { "HPO MIX" , "HPVOL Switch" , "HPOVOL" }, |
2551 | |
2552 | { "SPKVOL L" , "Switch" , "SPK MIXL" }, |
2553 | { "SPKVOL R" , "Switch" , "SPK MIXR" }, |
2554 | |
2555 | { "SPOL MIX" , "DAC L1 Switch" , "DAC L1" }, |
2556 | { "SPOL MIX" , "SPKVOL L Switch" , "SPKVOL L" }, |
2557 | { "SPOR MIX" , "DAC R1 Switch" , "DAC R1" }, |
2558 | { "SPOR MIX" , "SPKVOL R Switch" , "SPKVOL R" }, |
2559 | |
2560 | { "LOUT MIX" , "DAC L1 Switch" , "DAC L1" }, |
2561 | { "LOUT MIX" , "DAC R1 Switch" , "DAC R1" }, |
2562 | { "LOUT MIX" , "OUTMIX L Switch" , "OUT MIXL" }, |
2563 | { "LOUT MIX" , "OUTMIX R Switch" , "OUT MIXR" }, |
2564 | |
2565 | { "PDM1 L Mux" , "Stereo DAC" , "Stereo DAC MIXL" }, |
2566 | { "PDM1 L Mux" , "Mono DAC" , "Mono DAC MIXL" }, |
2567 | { "PDM1 L Mux" , NULL, "PDM1 Power" }, |
2568 | { "PDM1 R Mux" , "Stereo DAC" , "Stereo DAC MIXR" }, |
2569 | { "PDM1 R Mux" , "Mono DAC" , "Mono DAC MIXR" }, |
2570 | { "PDM1 R Mux" , NULL, "PDM1 Power" }, |
2571 | |
2572 | { "HP amp" , NULL, "HPO MIX" }, |
2573 | { "HP amp" , NULL, "JD Power" }, |
2574 | { "HP amp" , NULL, "Mic Det Power" }, |
2575 | { "HP amp" , NULL, "LDO2" }, |
2576 | { "HPOL" , NULL, "HP amp" }, |
2577 | { "HPOR" , NULL, "HP amp" }, |
2578 | |
2579 | { "LOUT amp" , NULL, "LOUT MIX" }, |
2580 | { "LOUTL" , NULL, "LOUT amp" }, |
2581 | { "LOUTR" , NULL, "LOUT amp" }, |
2582 | |
2583 | { "PDM1 L" , "Switch" , "PDM1 L Mux" }, |
2584 | { "PDM1 R" , "Switch" , "PDM1 R Mux" }, |
2585 | |
2586 | { "PDM1L" , NULL, "PDM1 L" }, |
2587 | { "PDM1R" , NULL, "PDM1 R" }, |
2588 | |
2589 | { "SPK amp" , NULL, "SPOL MIX" }, |
2590 | { "SPK amp" , NULL, "SPOR MIX" }, |
2591 | { "SPOL" , NULL, "SPK amp" }, |
2592 | { "SPOR" , NULL, "SPK amp" }, |
2593 | }; |
2594 | |
2595 | static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { |
2596 | { "A DAC1 L Mux" , "DAC1" , "DAC1 MIXL" }, |
2597 | { "A DAC1 L Mux" , "Stereo DAC Mixer" , "Stereo DAC MIXL" }, |
2598 | { "A DAC1 R Mux" , "DAC1" , "DAC1 MIXR" }, |
2599 | { "A DAC1 R Mux" , "Stereo DAC Mixer" , "Stereo DAC MIXR" }, |
2600 | |
2601 | { "A DAC2 L Mux" , "Stereo DAC Mixer" , "Stereo DAC MIXL" }, |
2602 | { "A DAC2 L Mux" , "Mono DAC Mixer" , "Mono DAC MIXL" }, |
2603 | { "A DAC2 R Mux" , "Stereo DAC Mixer" , "Stereo DAC MIXR" }, |
2604 | { "A DAC2 R Mux" , "Mono DAC Mixer" , "Mono DAC MIXR" }, |
2605 | |
2606 | { "DAC L1" , NULL, "A DAC1 L Mux" }, |
2607 | { "DAC R1" , NULL, "A DAC1 R Mux" }, |
2608 | { "DAC L2" , NULL, "A DAC2 L Mux" }, |
2609 | { "DAC R2" , NULL, "A DAC2 R Mux" }, |
2610 | |
2611 | { "RT5650 IF1 ADC1 Swap Mux" , "L/R" , "IF_ADC1" }, |
2612 | { "RT5650 IF1 ADC1 Swap Mux" , "R/L" , "IF_ADC1" }, |
2613 | { "RT5650 IF1 ADC1 Swap Mux" , "L/L" , "IF_ADC1" }, |
2614 | { "RT5650 IF1 ADC1 Swap Mux" , "R/R" , "IF_ADC1" }, |
2615 | |
2616 | { "RT5650 IF1 ADC2 Swap Mux" , "L/R" , "IF_ADC2" }, |
2617 | { "RT5650 IF1 ADC2 Swap Mux" , "R/L" , "IF_ADC2" }, |
2618 | { "RT5650 IF1 ADC2 Swap Mux" , "L/L" , "IF_ADC2" }, |
2619 | { "RT5650 IF1 ADC2 Swap Mux" , "R/R" , "IF_ADC2" }, |
2620 | |
2621 | { "RT5650 IF1 ADC3 Swap Mux" , "L/R" , "VAD_ADC" }, |
2622 | { "RT5650 IF1 ADC3 Swap Mux" , "R/L" , "VAD_ADC" }, |
2623 | { "RT5650 IF1 ADC3 Swap Mux" , "L/L" , "VAD_ADC" }, |
2624 | { "RT5650 IF1 ADC3 Swap Mux" , "R/R" , "VAD_ADC" }, |
2625 | |
2626 | { "IF1 ADC" , NULL, "RT5650 IF1 ADC1 Swap Mux" }, |
2627 | { "IF1 ADC" , NULL, "RT5650 IF1 ADC2 Swap Mux" }, |
2628 | { "IF1 ADC" , NULL, "RT5650 IF1 ADC3 Swap Mux" }, |
2629 | |
2630 | { "RT5650 IF1 ADC Mux" , "IF_ADC1/IF_ADC2/DAC_REF/Null" , "IF1 ADC" }, |
2631 | { "RT5650 IF1 ADC Mux" , "IF_ADC1/IF_ADC2/Null/DAC_REF" , "IF1 ADC" }, |
2632 | { "RT5650 IF1 ADC Mux" , "IF_ADC1/DAC_REF/IF_ADC2/Null" , "IF1 ADC" }, |
2633 | { "RT5650 IF1 ADC Mux" , "IF_ADC1/DAC_REF/Null/IF_ADC2" , "IF1 ADC" }, |
2634 | { "RT5650 IF1 ADC Mux" , "IF_ADC1/Null/DAC_REF/IF_ADC2" , "IF1 ADC" }, |
2635 | { "RT5650 IF1 ADC Mux" , "IF_ADC1/Null/IF_ADC2/DAC_REF" , "IF1 ADC" }, |
2636 | |
2637 | { "RT5650 IF1 ADC Mux" , "IF_ADC2/IF_ADC1/DAC_REF/Null" , "IF1 ADC" }, |
2638 | { "RT5650 IF1 ADC Mux" , "IF_ADC2/IF_ADC1/Null/DAC_REF" , "IF1 ADC" }, |
2639 | { "RT5650 IF1 ADC Mux" , "IF_ADC2/DAC_REF/IF_ADC1/Null" , "IF1 ADC" }, |
2640 | { "RT5650 IF1 ADC Mux" , "IF_ADC2/DAC_REF/Null/IF_ADC1" , "IF1 ADC" }, |
2641 | { "RT5650 IF1 ADC Mux" , "IF_ADC2/Null/DAC_REF/IF_ADC1" , "IF1 ADC" }, |
2642 | { "RT5650 IF1 ADC Mux" , "IF_ADC2/Null/IF_ADC1/DAC_REF" , "IF1 ADC" }, |
2643 | |
2644 | { "RT5650 IF1 ADC Mux" , "DAC_REF/IF_ADC1/IF_ADC2/Null" , "IF1 ADC" }, |
2645 | { "RT5650 IF1 ADC Mux" , "DAC_REF/IF_ADC1/Null/IF_ADC2" , "IF1 ADC" }, |
2646 | { "RT5650 IF1 ADC Mux" , "DAC_REF/IF_ADC2/IF_ADC1/Null" , "IF1 ADC" }, |
2647 | { "RT5650 IF1 ADC Mux" , "DAC_REF/IF_ADC2/Null/IF_ADC1" , "IF1 ADC" }, |
2648 | { "RT5650 IF1 ADC Mux" , "DAC_REF/Null/IF_ADC1/IF_ADC2" , "IF1 ADC" }, |
2649 | { "RT5650 IF1 ADC Mux" , "DAC_REF/Null/IF_ADC2/IF_ADC1" , "IF1 ADC" }, |
2650 | |
2651 | { "RT5650 IF1 ADC Mux" , "Null/IF_ADC1/IF_ADC2/DAC_REF" , "IF1 ADC" }, |
2652 | { "RT5650 IF1 ADC Mux" , "Null/IF_ADC1/DAC_REF/IF_ADC2" , "IF1 ADC" }, |
2653 | { "RT5650 IF1 ADC Mux" , "Null/IF_ADC2/IF_ADC1/DAC_REF" , "IF1 ADC" }, |
2654 | { "RT5650 IF1 ADC Mux" , "Null/IF_ADC2/DAC_REF/IF_ADC1" , "IF1 ADC" }, |
2655 | { "RT5650 IF1 ADC Mux" , "Null/DAC_REF/IF_ADC1/IF_ADC2" , "IF1 ADC" }, |
2656 | { "RT5650 IF1 ADC Mux" , "Null/DAC_REF/IF_ADC2/IF_ADC1" , "IF1 ADC" }, |
2657 | { "AIF1TX" , NULL, "RT5650 IF1 ADC Mux" }, |
2658 | |
2659 | { "RT5650 IF1 DAC1 L Mux" , "Slot0" , "IF1 DAC0" }, |
2660 | { "RT5650 IF1 DAC1 L Mux" , "Slot1" , "IF1 DAC1" }, |
2661 | { "RT5650 IF1 DAC1 L Mux" , "Slot2" , "IF1 DAC2" }, |
2662 | { "RT5650 IF1 DAC1 L Mux" , "Slot3" , "IF1 DAC3" }, |
2663 | |
2664 | { "RT5650 IF1 DAC1 R Mux" , "Slot0" , "IF1 DAC0" }, |
2665 | { "RT5650 IF1 DAC1 R Mux" , "Slot1" , "IF1 DAC1" }, |
2666 | { "RT5650 IF1 DAC1 R Mux" , "Slot2" , "IF1 DAC2" }, |
2667 | { "RT5650 IF1 DAC1 R Mux" , "Slot3" , "IF1 DAC3" }, |
2668 | |
2669 | { "RT5650 IF1 DAC2 L Mux" , "Slot0" , "IF1 DAC0" }, |
2670 | { "RT5650 IF1 DAC2 L Mux" , "Slot1" , "IF1 DAC1" }, |
2671 | { "RT5650 IF1 DAC2 L Mux" , "Slot2" , "IF1 DAC2" }, |
2672 | { "RT5650 IF1 DAC2 L Mux" , "Slot3" , "IF1 DAC3" }, |
2673 | |
2674 | { "RT5650 IF1 DAC2 R Mux" , "Slot0" , "IF1 DAC0" }, |
2675 | { "RT5650 IF1 DAC2 R Mux" , "Slot1" , "IF1 DAC1" }, |
2676 | { "RT5650 IF1 DAC2 R Mux" , "Slot2" , "IF1 DAC2" }, |
2677 | { "RT5650 IF1 DAC2 R Mux" , "Slot3" , "IF1 DAC3" }, |
2678 | |
2679 | { "DAC1 L Mux" , "IF1 DAC" , "RT5650 IF1 DAC1 L Mux" }, |
2680 | { "DAC1 R Mux" , "IF1 DAC" , "RT5650 IF1 DAC1 R Mux" }, |
2681 | |
2682 | { "DAC L2 Mux" , "IF1 DAC" , "RT5650 IF1 DAC2 L Mux" }, |
2683 | { "DAC R2 Mux" , "IF1 DAC" , "RT5650 IF1 DAC2 R Mux" }, |
2684 | }; |
2685 | |
2686 | static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { |
2687 | { "DAC L1" , NULL, "Stereo DAC MIXL" }, |
2688 | { "DAC R1" , NULL, "Stereo DAC MIXR" }, |
2689 | { "DAC L2" , NULL, "Mono DAC MIXL" }, |
2690 | { "DAC R2" , NULL, "Mono DAC MIXR" }, |
2691 | |
2692 | { "RT5645 IF1 ADC1 Swap Mux" , "L/R" , "IF_ADC1" }, |
2693 | { "RT5645 IF1 ADC1 Swap Mux" , "R/L" , "IF_ADC1" }, |
2694 | { "RT5645 IF1 ADC1 Swap Mux" , "L/L" , "IF_ADC1" }, |
2695 | { "RT5645 IF1 ADC1 Swap Mux" , "R/R" , "IF_ADC1" }, |
2696 | |
2697 | { "RT5645 IF1 ADC2 Swap Mux" , "L/R" , "IF_ADC2" }, |
2698 | { "RT5645 IF1 ADC2 Swap Mux" , "R/L" , "IF_ADC2" }, |
2699 | { "RT5645 IF1 ADC2 Swap Mux" , "L/L" , "IF_ADC2" }, |
2700 | { "RT5645 IF1 ADC2 Swap Mux" , "R/R" , "IF_ADC2" }, |
2701 | |
2702 | { "RT5645 IF1 ADC3 Swap Mux" , "L/R" , "VAD_ADC" }, |
2703 | { "RT5645 IF1 ADC3 Swap Mux" , "R/L" , "VAD_ADC" }, |
2704 | { "RT5645 IF1 ADC3 Swap Mux" , "L/L" , "VAD_ADC" }, |
2705 | { "RT5645 IF1 ADC3 Swap Mux" , "R/R" , "VAD_ADC" }, |
2706 | |
2707 | { "IF1 ADC" , NULL, "RT5645 IF1 ADC1 Swap Mux" }, |
2708 | { "IF1 ADC" , NULL, "RT5645 IF1 ADC2 Swap Mux" }, |
2709 | { "IF1 ADC" , NULL, "RT5645 IF1 ADC3 Swap Mux" }, |
2710 | |
2711 | { "RT5645 IF1 ADC Mux" , "IF_ADC1/IF_ADC2/VAD_ADC" , "IF1 ADC" }, |
2712 | { "RT5645 IF1 ADC Mux" , "IF_ADC2/IF_ADC1/VAD_ADC" , "IF1 ADC" }, |
2713 | { "RT5645 IF1 ADC Mux" , "VAD_ADC/IF_ADC1/IF_ADC2" , "IF1 ADC" }, |
2714 | { "RT5645 IF1 ADC Mux" , "VAD_ADC/IF_ADC2/IF_ADC1" , "IF1 ADC" }, |
2715 | { "AIF1TX" , NULL, "RT5645 IF1 ADC Mux" }, |
2716 | |
2717 | { "RT5645 IF1 DAC1 L Mux" , "Slot0" , "IF1 DAC0" }, |
2718 | { "RT5645 IF1 DAC1 L Mux" , "Slot1" , "IF1 DAC1" }, |
2719 | { "RT5645 IF1 DAC1 L Mux" , "Slot2" , "IF1 DAC2" }, |
2720 | { "RT5645 IF1 DAC1 L Mux" , "Slot3" , "IF1 DAC3" }, |
2721 | |
2722 | { "RT5645 IF1 DAC1 R Mux" , "Slot0" , "IF1 DAC0" }, |
2723 | { "RT5645 IF1 DAC1 R Mux" , "Slot1" , "IF1 DAC1" }, |
2724 | { "RT5645 IF1 DAC1 R Mux" , "Slot2" , "IF1 DAC2" }, |
2725 | { "RT5645 IF1 DAC1 R Mux" , "Slot3" , "IF1 DAC3" }, |
2726 | |
2727 | { "RT5645 IF1 DAC2 L Mux" , "Slot0" , "IF1 DAC0" }, |
2728 | { "RT5645 IF1 DAC2 L Mux" , "Slot1" , "IF1 DAC1" }, |
2729 | { "RT5645 IF1 DAC2 L Mux" , "Slot2" , "IF1 DAC2" }, |
2730 | { "RT5645 IF1 DAC2 L Mux" , "Slot3" , "IF1 DAC3" }, |
2731 | |
2732 | { "RT5645 IF1 DAC2 R Mux" , "Slot0" , "IF1 DAC0" }, |
2733 | { "RT5645 IF1 DAC2 R Mux" , "Slot1" , "IF1 DAC1" }, |
2734 | { "RT5645 IF1 DAC2 R Mux" , "Slot2" , "IF1 DAC2" }, |
2735 | { "RT5645 IF1 DAC2 R Mux" , "Slot3" , "IF1 DAC3" }, |
2736 | |
2737 | { "DAC1 L Mux" , "IF1 DAC" , "RT5645 IF1 DAC1 L Mux" }, |
2738 | { "DAC1 R Mux" , "IF1 DAC" , "RT5645 IF1 DAC1 R Mux" }, |
2739 | |
2740 | { "DAC L2 Mux" , "IF1 DAC" , "RT5645 IF1 DAC2 L Mux" }, |
2741 | { "DAC R2 Mux" , "IF1 DAC" , "RT5645 IF1 DAC2 R Mux" }, |
2742 | }; |
2743 | |
2744 | static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = { |
2745 | { "SPOL MIX" , "DAC R1 Switch" , "DAC R1" }, |
2746 | { "SPOL MIX" , "SPKVOL R Switch" , "SPKVOL R" }, |
2747 | }; |
2748 | |
2749 | static int rt5645_hw_params(struct snd_pcm_substream *substream, |
2750 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
2751 | { |
2752 | struct snd_soc_component *component = dai->component; |
2753 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
2754 | unsigned int val_len = 0, val_clk, mask_clk, dl_sft; |
2755 | int pre_div, bclk_ms, frame_size; |
2756 | |
2757 | rt5645->lrck[dai->id] = params_rate(p: params); |
2758 | pre_div = rl6231_get_clk_info(sclk: rt5645->sysclk, rate: rt5645->lrck[dai->id]); |
2759 | if (pre_div < 0) { |
2760 | dev_err(component->dev, "Unsupported clock setting\n" ); |
2761 | return -EINVAL; |
2762 | } |
2763 | frame_size = snd_soc_params_to_frame_size(params); |
2764 | if (frame_size < 0) { |
2765 | dev_err(component->dev, "Unsupported frame size: %d\n" , frame_size); |
2766 | return -EINVAL; |
2767 | } |
2768 | |
2769 | switch (rt5645->codec_type) { |
2770 | case CODEC_TYPE_RT5650: |
2771 | dl_sft = 4; |
2772 | break; |
2773 | default: |
2774 | dl_sft = 2; |
2775 | break; |
2776 | } |
2777 | |
2778 | bclk_ms = frame_size > 32; |
2779 | rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); |
2780 | |
2781 | dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n" , |
2782 | rt5645->bclk[dai->id], rt5645->lrck[dai->id]); |
2783 | dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n" , |
2784 | bclk_ms, pre_div, dai->id); |
2785 | |
2786 | switch (params_width(p: params)) { |
2787 | case 16: |
2788 | break; |
2789 | case 20: |
2790 | val_len = 0x1; |
2791 | break; |
2792 | case 24: |
2793 | val_len = 0x2; |
2794 | break; |
2795 | case 8: |
2796 | val_len = 0x3; |
2797 | break; |
2798 | default: |
2799 | return -EINVAL; |
2800 | } |
2801 | |
2802 | switch (dai->id) { |
2803 | case RT5645_AIF1: |
2804 | mask_clk = RT5645_I2S_PD1_MASK; |
2805 | val_clk = pre_div << RT5645_I2S_PD1_SFT; |
2806 | snd_soc_component_update_bits(component, RT5645_I2S1_SDP, |
2807 | mask: (0x3 << dl_sft), val: (val_len << dl_sft)); |
2808 | snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask: mask_clk, val: val_clk); |
2809 | break; |
2810 | case RT5645_AIF2: |
2811 | mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; |
2812 | val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | |
2813 | pre_div << RT5645_I2S_PD2_SFT; |
2814 | snd_soc_component_update_bits(component, RT5645_I2S2_SDP, |
2815 | mask: (0x3 << dl_sft), val: (val_len << dl_sft)); |
2816 | snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask: mask_clk, val: val_clk); |
2817 | break; |
2818 | default: |
2819 | dev_err(component->dev, "Invalid dai->id: %d\n" , dai->id); |
2820 | return -EINVAL; |
2821 | } |
2822 | |
2823 | return 0; |
2824 | } |
2825 | |
2826 | static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
2827 | { |
2828 | struct snd_soc_component *component = dai->component; |
2829 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
2830 | unsigned int reg_val = 0, pol_sft; |
2831 | |
2832 | switch (rt5645->codec_type) { |
2833 | case CODEC_TYPE_RT5650: |
2834 | pol_sft = 8; |
2835 | break; |
2836 | default: |
2837 | pol_sft = 7; |
2838 | break; |
2839 | } |
2840 | |
2841 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
2842 | case SND_SOC_DAIFMT_CBM_CFM: |
2843 | rt5645->master[dai->id] = 1; |
2844 | break; |
2845 | case SND_SOC_DAIFMT_CBS_CFS: |
2846 | reg_val |= RT5645_I2S_MS_S; |
2847 | rt5645->master[dai->id] = 0; |
2848 | break; |
2849 | default: |
2850 | return -EINVAL; |
2851 | } |
2852 | |
2853 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
2854 | case SND_SOC_DAIFMT_NB_NF: |
2855 | break; |
2856 | case SND_SOC_DAIFMT_IB_NF: |
2857 | reg_val |= (1 << pol_sft); |
2858 | break; |
2859 | default: |
2860 | return -EINVAL; |
2861 | } |
2862 | |
2863 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
2864 | case SND_SOC_DAIFMT_I2S: |
2865 | break; |
2866 | case SND_SOC_DAIFMT_LEFT_J: |
2867 | reg_val |= RT5645_I2S_DF_LEFT; |
2868 | break; |
2869 | case SND_SOC_DAIFMT_DSP_A: |
2870 | reg_val |= RT5645_I2S_DF_PCM_A; |
2871 | break; |
2872 | case SND_SOC_DAIFMT_DSP_B: |
2873 | reg_val |= RT5645_I2S_DF_PCM_B; |
2874 | break; |
2875 | default: |
2876 | return -EINVAL; |
2877 | } |
2878 | switch (dai->id) { |
2879 | case RT5645_AIF1: |
2880 | snd_soc_component_update_bits(component, RT5645_I2S1_SDP, |
2881 | RT5645_I2S_MS_MASK | (1 << pol_sft) | |
2882 | RT5645_I2S_DF_MASK, val: reg_val); |
2883 | break; |
2884 | case RT5645_AIF2: |
2885 | snd_soc_component_update_bits(component, RT5645_I2S2_SDP, |
2886 | RT5645_I2S_MS_MASK | (1 << pol_sft) | |
2887 | RT5645_I2S_DF_MASK, val: reg_val); |
2888 | break; |
2889 | default: |
2890 | dev_err(component->dev, "Invalid dai->id: %d\n" , dai->id); |
2891 | return -EINVAL; |
2892 | } |
2893 | return 0; |
2894 | } |
2895 | |
2896 | static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, |
2897 | int clk_id, unsigned int freq, int dir) |
2898 | { |
2899 | struct snd_soc_component *component = dai->component; |
2900 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
2901 | unsigned int reg_val = 0; |
2902 | |
2903 | if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) |
2904 | return 0; |
2905 | |
2906 | switch (clk_id) { |
2907 | case RT5645_SCLK_S_MCLK: |
2908 | reg_val |= RT5645_SCLK_SRC_MCLK; |
2909 | break; |
2910 | case RT5645_SCLK_S_PLL1: |
2911 | reg_val |= RT5645_SCLK_SRC_PLL1; |
2912 | break; |
2913 | case RT5645_SCLK_S_RCCLK: |
2914 | reg_val |= RT5645_SCLK_SRC_RCCLK; |
2915 | break; |
2916 | default: |
2917 | dev_err(component->dev, "Invalid clock id (%d)\n" , clk_id); |
2918 | return -EINVAL; |
2919 | } |
2920 | snd_soc_component_update_bits(component, RT5645_GLB_CLK, |
2921 | RT5645_SCLK_SRC_MASK, val: reg_val); |
2922 | rt5645->sysclk = freq; |
2923 | rt5645->sysclk_src = clk_id; |
2924 | |
2925 | dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n" , freq, clk_id); |
2926 | |
2927 | return 0; |
2928 | } |
2929 | |
2930 | static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, |
2931 | unsigned int freq_in, unsigned int freq_out) |
2932 | { |
2933 | struct snd_soc_component *component = dai->component; |
2934 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
2935 | struct rl6231_pll_code pll_code; |
2936 | int ret; |
2937 | |
2938 | if (source == rt5645->pll_src && freq_in == rt5645->pll_in && |
2939 | freq_out == rt5645->pll_out) |
2940 | return 0; |
2941 | |
2942 | if (!freq_in || !freq_out) { |
2943 | dev_dbg(component->dev, "PLL disabled\n" ); |
2944 | |
2945 | rt5645->pll_in = 0; |
2946 | rt5645->pll_out = 0; |
2947 | snd_soc_component_update_bits(component, RT5645_GLB_CLK, |
2948 | RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); |
2949 | return 0; |
2950 | } |
2951 | |
2952 | switch (source) { |
2953 | case RT5645_PLL1_S_MCLK: |
2954 | snd_soc_component_update_bits(component, RT5645_GLB_CLK, |
2955 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); |
2956 | break; |
2957 | case RT5645_PLL1_S_BCLK1: |
2958 | case RT5645_PLL1_S_BCLK2: |
2959 | switch (dai->id) { |
2960 | case RT5645_AIF1: |
2961 | snd_soc_component_update_bits(component, RT5645_GLB_CLK, |
2962 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); |
2963 | break; |
2964 | case RT5645_AIF2: |
2965 | snd_soc_component_update_bits(component, RT5645_GLB_CLK, |
2966 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); |
2967 | break; |
2968 | default: |
2969 | dev_err(component->dev, "Invalid dai->id: %d\n" , dai->id); |
2970 | return -EINVAL; |
2971 | } |
2972 | break; |
2973 | default: |
2974 | dev_err(component->dev, "Unknown PLL source %d\n" , source); |
2975 | return -EINVAL; |
2976 | } |
2977 | |
2978 | ret = rl6231_pll_calc(freq_in, freq_out, pll_code: &pll_code); |
2979 | if (ret < 0) { |
2980 | dev_err(component->dev, "Unsupported input clock %d\n" , freq_in); |
2981 | return ret; |
2982 | } |
2983 | |
2984 | dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n" , |
2985 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), |
2986 | pll_code.n_code, pll_code.k_code); |
2987 | |
2988 | snd_soc_component_write(component, RT5645_PLL_CTRL1, |
2989 | val: pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); |
2990 | snd_soc_component_write(component, RT5645_PLL_CTRL2, |
2991 | val: ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) | |
2992 | (pll_code.m_bp << RT5645_PLL_M_BP_SFT)); |
2993 | |
2994 | rt5645->pll_in = freq_in; |
2995 | rt5645->pll_out = freq_out; |
2996 | rt5645->pll_src = source; |
2997 | |
2998 | return 0; |
2999 | } |
3000 | |
3001 | static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, |
3002 | unsigned int rx_mask, int slots, int slot_width) |
3003 | { |
3004 | struct snd_soc_component *component = dai->component; |
3005 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
3006 | unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; |
3007 | unsigned int mask, val = 0; |
3008 | |
3009 | switch (rt5645->codec_type) { |
3010 | case CODEC_TYPE_RT5650: |
3011 | en_sft = 15; |
3012 | i_slot_sft = 10; |
3013 | o_slot_sft = 8; |
3014 | i_width_sht = 6; |
3015 | o_width_sht = 4; |
3016 | mask = 0x8ff0; |
3017 | break; |
3018 | default: |
3019 | en_sft = 14; |
3020 | i_slot_sft = o_slot_sft = 12; |
3021 | i_width_sht = o_width_sht = 10; |
3022 | mask = 0x7c00; |
3023 | break; |
3024 | } |
3025 | if (rx_mask || tx_mask) { |
3026 | val |= (1 << en_sft); |
3027 | if (rt5645->codec_type == CODEC_TYPE_RT5645) |
3028 | snd_soc_component_update_bits(component, RT5645_BASS_BACK, |
3029 | RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); |
3030 | } |
3031 | |
3032 | switch (slots) { |
3033 | case 4: |
3034 | val |= (1 << i_slot_sft) | (1 << o_slot_sft); |
3035 | break; |
3036 | case 6: |
3037 | val |= (2 << i_slot_sft) | (2 << o_slot_sft); |
3038 | break; |
3039 | case 8: |
3040 | val |= (3 << i_slot_sft) | (3 << o_slot_sft); |
3041 | break; |
3042 | case 2: |
3043 | default: |
3044 | break; |
3045 | } |
3046 | |
3047 | switch (slot_width) { |
3048 | case 20: |
3049 | val |= (1 << i_width_sht) | (1 << o_width_sht); |
3050 | break; |
3051 | case 24: |
3052 | val |= (2 << i_width_sht) | (2 << o_width_sht); |
3053 | break; |
3054 | case 32: |
3055 | val |= (3 << i_width_sht) | (3 << o_width_sht); |
3056 | break; |
3057 | case 16: |
3058 | default: |
3059 | break; |
3060 | } |
3061 | |
3062 | snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); |
3063 | |
3064 | return 0; |
3065 | } |
3066 | |
3067 | static int rt5645_set_bias_level(struct snd_soc_component *component, |
3068 | enum snd_soc_bias_level level) |
3069 | { |
3070 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
3071 | |
3072 | switch (level) { |
3073 | case SND_SOC_BIAS_PREPARE: |
3074 | if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) { |
3075 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
3076 | RT5645_PWR_VREF1 | RT5645_PWR_MB | |
3077 | RT5645_PWR_BG | RT5645_PWR_VREF2, |
3078 | RT5645_PWR_VREF1 | RT5645_PWR_MB | |
3079 | RT5645_PWR_BG | RT5645_PWR_VREF2); |
3080 | mdelay(10); |
3081 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
3082 | RT5645_PWR_FV1 | RT5645_PWR_FV2, |
3083 | RT5645_PWR_FV1 | RT5645_PWR_FV2); |
3084 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, |
3085 | RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); |
3086 | } |
3087 | break; |
3088 | |
3089 | case SND_SOC_BIAS_STANDBY: |
3090 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
3091 | RT5645_PWR_VREF1 | RT5645_PWR_MB | |
3092 | RT5645_PWR_BG | RT5645_PWR_VREF2, |
3093 | RT5645_PWR_VREF1 | RT5645_PWR_MB | |
3094 | RT5645_PWR_BG | RT5645_PWR_VREF2); |
3095 | mdelay(10); |
3096 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
3097 | RT5645_PWR_FV1 | RT5645_PWR_FV2, |
3098 | RT5645_PWR_FV1 | RT5645_PWR_FV2); |
3099 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
3100 | snd_soc_component_write(component, RT5645_DEPOP_M2, val: 0x1140); |
3101 | msleep(msecs: 40); |
3102 | if (rt5645->en_button_func) |
3103 | queue_delayed_work(wq: system_power_efficient_wq, |
3104 | dwork: &rt5645->jack_detect_work, |
3105 | delay: msecs_to_jiffies(m: 0)); |
3106 | } |
3107 | break; |
3108 | |
3109 | case SND_SOC_BIAS_OFF: |
3110 | snd_soc_component_write(component, RT5645_DEPOP_M2, val: 0x1100); |
3111 | if (!rt5645->en_button_func) |
3112 | snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, |
3113 | RT5645_DIG_GATE_CTRL, val: 0); |
3114 | snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, |
3115 | RT5645_PWR_VREF1 | RT5645_PWR_MB | |
3116 | RT5645_PWR_BG | RT5645_PWR_VREF2 | |
3117 | RT5645_PWR_FV1 | RT5645_PWR_FV2, val: 0x0); |
3118 | break; |
3119 | |
3120 | default: |
3121 | break; |
3122 | } |
3123 | |
3124 | return 0; |
3125 | } |
3126 | |
3127 | static void rt5645_enable_push_button_irq(struct snd_soc_component *component, |
3128 | bool enable) |
3129 | { |
3130 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
3131 | |
3132 | if (enable) { |
3133 | snd_soc_dapm_force_enable_pin(dapm, pin: "ADC L power" ); |
3134 | snd_soc_dapm_force_enable_pin(dapm, pin: "ADC R power" ); |
3135 | snd_soc_dapm_sync(dapm); |
3136 | |
3137 | snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, mask: 0x3, val: 0x3); |
3138 | snd_soc_component_update_bits(component, |
3139 | RT5645_INT_IRQ_ST, mask: 0x8, val: 0x8); |
3140 | snd_soc_component_update_bits(component, |
3141 | RT5650_4BTN_IL_CMD2, mask: 0x8000, val: 0x8000); |
3142 | snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); |
3143 | pr_debug("%s read %x = %x\n" , __func__, RT5650_4BTN_IL_CMD1, |
3144 | snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); |
3145 | } else { |
3146 | snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, mask: 0x8000, val: 0x0); |
3147 | snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, mask: 0x8, val: 0x0); |
3148 | |
3149 | snd_soc_dapm_disable_pin(dapm, pin: "ADC L power" ); |
3150 | snd_soc_dapm_disable_pin(dapm, pin: "ADC R power" ); |
3151 | snd_soc_dapm_sync(dapm); |
3152 | } |
3153 | } |
3154 | |
3155 | static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert) |
3156 | { |
3157 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
3158 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
3159 | unsigned int val; |
3160 | |
3161 | if (jack_insert) { |
3162 | regmap_write(map: rt5645->regmap, RT5645_CHARGE_PUMP, val: 0x0206); |
3163 | |
3164 | /* for jack type detect */ |
3165 | snd_soc_dapm_force_enable_pin(dapm, pin: "LDO2" ); |
3166 | snd_soc_dapm_force_enable_pin(dapm, pin: "Mic Det Power" ); |
3167 | snd_soc_dapm_sync(dapm); |
3168 | if (!snd_soc_card_is_instantiated(card: dapm->card)) { |
3169 | /* Power up necessary bits for JD if dapm is |
3170 | not ready yet */ |
3171 | regmap_update_bits(map: rt5645->regmap, RT5645_PWR_ANLG1, |
3172 | RT5645_PWR_MB | RT5645_PWR_VREF2, |
3173 | RT5645_PWR_MB | RT5645_PWR_VREF2); |
3174 | regmap_update_bits(map: rt5645->regmap, RT5645_PWR_MIXER, |
3175 | RT5645_PWR_LDO2, RT5645_PWR_LDO2); |
3176 | regmap_update_bits(map: rt5645->regmap, RT5645_PWR_VOL, |
3177 | RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); |
3178 | } |
3179 | |
3180 | regmap_write(map: rt5645->regmap, RT5645_JD_CTRL3, val: 0x00f0); |
3181 | regmap_update_bits(map: rt5645->regmap, RT5645_IN1_CTRL2, |
3182 | RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); |
3183 | regmap_update_bits(map: rt5645->regmap, RT5645_IN1_CTRL1, |
3184 | RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); |
3185 | msleep(msecs: 100); |
3186 | regmap_update_bits(map: rt5645->regmap, RT5645_IN1_CTRL2, |
3187 | RT5645_CBJ_MN_JD, val: 0); |
3188 | |
3189 | msleep(msecs: 600); |
3190 | regmap_read(map: rt5645->regmap, RT5645_IN1_CTRL3, val: &val); |
3191 | val &= 0x7; |
3192 | dev_dbg(component->dev, "val = %d\n" , val); |
3193 | |
3194 | if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) { |
3195 | rt5645->jack_type = SND_JACK_HEADSET; |
3196 | if (rt5645->en_button_func) { |
3197 | rt5645_enable_push_button_irq(component, enable: true); |
3198 | } |
3199 | } else { |
3200 | if (rt5645->en_button_func) |
3201 | rt5645_enable_push_button_irq(component, enable: false); |
3202 | snd_soc_dapm_disable_pin(dapm, pin: "Mic Det Power" ); |
3203 | snd_soc_dapm_sync(dapm); |
3204 | rt5645->jack_type = SND_JACK_HEADPHONE; |
3205 | } |
3206 | if (rt5645->pdata.level_trigger_irq) |
3207 | regmap_update_bits(map: rt5645->regmap, RT5645_IRQ_CTRL2, |
3208 | RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); |
3209 | |
3210 | regmap_write(map: rt5645->regmap, RT5645_CHARGE_PUMP, val: 0x0e06); |
3211 | } else { /* jack out */ |
3212 | rt5645->jack_type = 0; |
3213 | |
3214 | regmap_update_bits(map: rt5645->regmap, RT5645_HP_VOL, |
3215 | RT5645_L_MUTE | RT5645_R_MUTE, |
3216 | RT5645_L_MUTE | RT5645_R_MUTE); |
3217 | regmap_update_bits(map: rt5645->regmap, RT5645_IN1_CTRL2, |
3218 | RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); |
3219 | regmap_update_bits(map: rt5645->regmap, RT5645_IN1_CTRL1, |
3220 | RT5645_CBJ_BST1_EN, val: 0); |
3221 | |
3222 | if (rt5645->en_button_func) |
3223 | rt5645_enable_push_button_irq(component, enable: false); |
3224 | |
3225 | if (rt5645->pdata.jd_mode == 0) |
3226 | snd_soc_dapm_disable_pin(dapm, pin: "LDO2" ); |
3227 | snd_soc_dapm_disable_pin(dapm, pin: "Mic Det Power" ); |
3228 | snd_soc_dapm_sync(dapm); |
3229 | if (rt5645->pdata.level_trigger_irq) |
3230 | regmap_update_bits(map: rt5645->regmap, RT5645_IRQ_CTRL2, |
3231 | RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); |
3232 | } |
3233 | |
3234 | return rt5645->jack_type; |
3235 | } |
3236 | |
3237 | static int rt5645_button_detect(struct snd_soc_component *component) |
3238 | { |
3239 | int btn_type, val; |
3240 | |
3241 | val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); |
3242 | pr_debug("val=0x%x\n" , val); |
3243 | btn_type = val & 0xfff0; |
3244 | snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val); |
3245 | |
3246 | return btn_type; |
3247 | } |
3248 | |
3249 | static irqreturn_t rt5645_irq(int irq, void *data); |
3250 | |
3251 | int rt5645_set_jack_detect(struct snd_soc_component *component, |
3252 | struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, |
3253 | struct snd_soc_jack *btn_jack) |
3254 | { |
3255 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
3256 | |
3257 | rt5645->hp_jack = hp_jack; |
3258 | rt5645->mic_jack = mic_jack; |
3259 | rt5645->btn_jack = btn_jack; |
3260 | if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { |
3261 | rt5645->en_button_func = true; |
3262 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
3263 | RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); |
3264 | regmap_update_bits(map: rt5645->regmap, RT5645_GEN_CTRL1, |
3265 | RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); |
3266 | regmap_update_bits(map: rt5645->regmap, RT5645_DEPOP_M1, |
3267 | RT5645_HP_CB_MASK, RT5645_HP_CB_PU); |
3268 | } |
3269 | rt5645_irq(irq: 0, data: rt5645); |
3270 | |
3271 | return 0; |
3272 | } |
3273 | EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); |
3274 | |
3275 | static int rt5645_component_set_jack(struct snd_soc_component *component, |
3276 | struct snd_soc_jack *hs_jack, void *data) |
3277 | { |
3278 | struct snd_soc_jack *mic_jack = NULL; |
3279 | struct snd_soc_jack *btn_jack = NULL; |
3280 | int type; |
3281 | |
3282 | if (hs_jack) { |
3283 | type = *(int *)data; |
3284 | |
3285 | if (type & SND_JACK_MICROPHONE) |
3286 | mic_jack = hs_jack; |
3287 | if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
3288 | SND_JACK_BTN_2 | SND_JACK_BTN_3)) |
3289 | btn_jack = hs_jack; |
3290 | } |
3291 | |
3292 | return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack); |
3293 | } |
3294 | |
3295 | static void rt5645_jack_detect_work(struct work_struct *work) |
3296 | { |
3297 | struct rt5645_priv *rt5645 = |
3298 | container_of(work, struct rt5645_priv, jack_detect_work.work); |
3299 | int val, btn_type, gpio_state = 0, report = 0; |
3300 | |
3301 | if (!rt5645->component) |
3302 | return; |
3303 | |
3304 | mutex_lock(&rt5645->jd_mutex); |
3305 | |
3306 | switch (rt5645->pdata.jd_mode) { |
3307 | case 0: /* Not using rt5645 JD */ |
3308 | if (rt5645->gpiod_hp_det) { |
3309 | gpio_state = gpiod_get_value(desc: rt5645->gpiod_hp_det); |
3310 | if (rt5645->pdata.inv_hp_pol) |
3311 | gpio_state ^= 1; |
3312 | dev_dbg(rt5645->component->dev, "gpio_state = %d\n" , |
3313 | gpio_state); |
3314 | report = rt5645_jack_detect(component: rt5645->component, jack_insert: gpio_state); |
3315 | } |
3316 | snd_soc_jack_report(jack: rt5645->hp_jack, |
3317 | status: report, mask: SND_JACK_HEADPHONE); |
3318 | snd_soc_jack_report(jack: rt5645->mic_jack, |
3319 | status: report, mask: SND_JACK_MICROPHONE); |
3320 | mutex_unlock(lock: &rt5645->jd_mutex); |
3321 | return; |
3322 | case 4: |
3323 | val = snd_soc_component_read(component: rt5645->component, RT5645_A_JD_CTRL1) & 0x0020; |
3324 | break; |
3325 | default: /* read rt5645 jd1_1 status */ |
3326 | val = snd_soc_component_read(component: rt5645->component, RT5645_INT_IRQ_ST) & 0x1000; |
3327 | break; |
3328 | |
3329 | } |
3330 | |
3331 | if (!val && (rt5645->jack_type == 0)) { /* jack in */ |
3332 | report = rt5645_jack_detect(component: rt5645->component, jack_insert: 1); |
3333 | } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) { |
3334 | /* for push button and jack out */ |
3335 | btn_type = 0; |
3336 | if (snd_soc_component_read(component: rt5645->component, RT5645_INT_IRQ_ST) & 0x4) { |
3337 | /* button pressed */ |
3338 | report = SND_JACK_HEADSET; |
3339 | btn_type = rt5645_button_detect(component: rt5645->component); |
3340 | /* rt5650 can report three kinds of button behavior, |
3341 | one click, double click and hold. However, |
3342 | currently we will report button pressed/released |
3343 | event. So all the three button behaviors are |
3344 | treated as button pressed. */ |
3345 | switch (btn_type) { |
3346 | case 0x8000: |
3347 | case 0x4000: |
3348 | case 0x2000: |
3349 | report |= SND_JACK_BTN_0; |
3350 | break; |
3351 | case 0x1000: |
3352 | case 0x0800: |
3353 | case 0x0400: |
3354 | report |= SND_JACK_BTN_1; |
3355 | break; |
3356 | case 0x0200: |
3357 | case 0x0100: |
3358 | case 0x0080: |
3359 | report |= SND_JACK_BTN_2; |
3360 | break; |
3361 | case 0x0040: |
3362 | case 0x0020: |
3363 | case 0x0010: |
3364 | report |= SND_JACK_BTN_3; |
3365 | break; |
3366 | case 0x0000: /* unpressed */ |
3367 | break; |
3368 | default: |
3369 | dev_err(rt5645->component->dev, |
3370 | "Unexpected button code 0x%04x\n" , |
3371 | btn_type); |
3372 | break; |
3373 | } |
3374 | } |
3375 | if (btn_type == 0)/* button release */ |
3376 | report = rt5645->jack_type; |
3377 | else { |
3378 | mod_timer(timer: &rt5645->btn_check_timer, |
3379 | expires: msecs_to_jiffies(m: 100)); |
3380 | } |
3381 | } else { |
3382 | /* jack out */ |
3383 | report = 0; |
3384 | snd_soc_component_update_bits(component: rt5645->component, |
3385 | RT5645_INT_IRQ_ST, mask: 0x1, val: 0x0); |
3386 | rt5645_jack_detect(component: rt5645->component, jack_insert: 0); |
3387 | } |
3388 | |
3389 | mutex_unlock(lock: &rt5645->jd_mutex); |
3390 | |
3391 | snd_soc_jack_report(jack: rt5645->hp_jack, status: report, mask: SND_JACK_HEADPHONE); |
3392 | snd_soc_jack_report(jack: rt5645->mic_jack, status: report, mask: SND_JACK_MICROPHONE); |
3393 | if (rt5645->en_button_func) |
3394 | snd_soc_jack_report(jack: rt5645->btn_jack, |
3395 | status: report, mask: SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
3396 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
3397 | } |
3398 | |
3399 | static void rt5645_rcclock_work(struct work_struct *work) |
3400 | { |
3401 | struct rt5645_priv *rt5645 = |
3402 | container_of(work, struct rt5645_priv, rcclock_work.work); |
3403 | |
3404 | regmap_update_bits(map: rt5645->regmap, RT5645_MICBIAS, |
3405 | RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); |
3406 | } |
3407 | |
3408 | static irqreturn_t rt5645_irq(int irq, void *data) |
3409 | { |
3410 | struct rt5645_priv *rt5645 = data; |
3411 | |
3412 | queue_delayed_work(wq: system_power_efficient_wq, |
3413 | dwork: &rt5645->jack_detect_work, delay: msecs_to_jiffies(m: 250)); |
3414 | |
3415 | return IRQ_HANDLED; |
3416 | } |
3417 | |
3418 | static void rt5645_btn_check_callback(struct timer_list *t) |
3419 | { |
3420 | struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer); |
3421 | |
3422 | queue_delayed_work(wq: system_power_efficient_wq, |
3423 | dwork: &rt5645->jack_detect_work, delay: msecs_to_jiffies(m: 5)); |
3424 | } |
3425 | |
3426 | static int rt5645_probe(struct snd_soc_component *component) |
3427 | { |
3428 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
3429 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
3430 | |
3431 | rt5645->component = component; |
3432 | |
3433 | switch (rt5645->codec_type) { |
3434 | case CODEC_TYPE_RT5645: |
3435 | snd_soc_dapm_new_controls(dapm, |
3436 | widget: rt5645_specific_dapm_widgets, |
3437 | ARRAY_SIZE(rt5645_specific_dapm_widgets)); |
3438 | snd_soc_dapm_add_routes(dapm, |
3439 | route: rt5645_specific_dapm_routes, |
3440 | ARRAY_SIZE(rt5645_specific_dapm_routes)); |
3441 | if (rt5645->v_id < 3) { |
3442 | snd_soc_dapm_add_routes(dapm, |
3443 | route: rt5645_old_dapm_routes, |
3444 | ARRAY_SIZE(rt5645_old_dapm_routes)); |
3445 | } |
3446 | break; |
3447 | case CODEC_TYPE_RT5650: |
3448 | snd_soc_dapm_new_controls(dapm, |
3449 | widget: rt5650_specific_dapm_widgets, |
3450 | ARRAY_SIZE(rt5650_specific_dapm_widgets)); |
3451 | snd_soc_dapm_add_routes(dapm, |
3452 | route: rt5650_specific_dapm_routes, |
3453 | ARRAY_SIZE(rt5650_specific_dapm_routes)); |
3454 | break; |
3455 | } |
3456 | |
3457 | snd_soc_component_force_bias_level(component, level: SND_SOC_BIAS_OFF); |
3458 | |
3459 | /* for JD function */ |
3460 | if (rt5645->pdata.jd_mode) { |
3461 | snd_soc_dapm_force_enable_pin(dapm, pin: "JD Power" ); |
3462 | snd_soc_dapm_force_enable_pin(dapm, pin: "LDO2" ); |
3463 | snd_soc_dapm_sync(dapm); |
3464 | } |
3465 | |
3466 | if (rt5645->pdata.long_name) |
3467 | component->card->long_name = rt5645->pdata.long_name; |
3468 | |
3469 | rt5645->eq_param = devm_kcalloc(dev: component->dev, |
3470 | RT5645_HWEQ_NUM, size: sizeof(struct rt5645_eq_param_s), |
3471 | GFP_KERNEL); |
3472 | |
3473 | if (!rt5645->eq_param) |
3474 | return -ENOMEM; |
3475 | |
3476 | return 0; |
3477 | } |
3478 | |
3479 | static void rt5645_remove(struct snd_soc_component *component) |
3480 | { |
3481 | rt5645_reset(component); |
3482 | } |
3483 | |
3484 | #ifdef CONFIG_PM |
3485 | static int rt5645_suspend(struct snd_soc_component *component) |
3486 | { |
3487 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
3488 | |
3489 | regcache_cache_only(map: rt5645->regmap, enable: true); |
3490 | regcache_mark_dirty(map: rt5645->regmap); |
3491 | |
3492 | return 0; |
3493 | } |
3494 | |
3495 | static int rt5645_resume(struct snd_soc_component *component) |
3496 | { |
3497 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(c: component); |
3498 | |
3499 | regcache_cache_only(map: rt5645->regmap, enable: false); |
3500 | regcache_sync(map: rt5645->regmap); |
3501 | |
3502 | return 0; |
3503 | } |
3504 | #else |
3505 | #define rt5645_suspend NULL |
3506 | #define rt5645_resume NULL |
3507 | #endif |
3508 | |
3509 | #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 |
3510 | #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
3511 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) |
3512 | |
3513 | static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { |
3514 | .hw_params = rt5645_hw_params, |
3515 | .set_fmt = rt5645_set_dai_fmt, |
3516 | .set_sysclk = rt5645_set_dai_sysclk, |
3517 | .set_tdm_slot = rt5645_set_tdm_slot, |
3518 | .set_pll = rt5645_set_dai_pll, |
3519 | }; |
3520 | |
3521 | static struct snd_soc_dai_driver rt5645_dai[] = { |
3522 | { |
3523 | .name = "rt5645-aif1" , |
3524 | .id = RT5645_AIF1, |
3525 | .playback = { |
3526 | .stream_name = "AIF1 Playback" , |
3527 | .channels_min = 1, |
3528 | .channels_max = 2, |
3529 | .rates = RT5645_STEREO_RATES, |
3530 | .formats = RT5645_FORMATS, |
3531 | }, |
3532 | .capture = { |
3533 | .stream_name = "AIF1 Capture" , |
3534 | .channels_min = 1, |
3535 | .channels_max = 4, |
3536 | .rates = RT5645_STEREO_RATES, |
3537 | .formats = RT5645_FORMATS, |
3538 | }, |
3539 | .ops = &rt5645_aif_dai_ops, |
3540 | }, |
3541 | { |
3542 | .name = "rt5645-aif2" , |
3543 | .id = RT5645_AIF2, |
3544 | .playback = { |
3545 | .stream_name = "AIF2 Playback" , |
3546 | .channels_min = 1, |
3547 | .channels_max = 2, |
3548 | .rates = RT5645_STEREO_RATES, |
3549 | .formats = RT5645_FORMATS, |
3550 | }, |
3551 | .capture = { |
3552 | .stream_name = "AIF2 Capture" , |
3553 | .channels_min = 1, |
3554 | .channels_max = 2, |
3555 | .rates = RT5645_STEREO_RATES, |
3556 | .formats = RT5645_FORMATS, |
3557 | }, |
3558 | .ops = &rt5645_aif_dai_ops, |
3559 | }, |
3560 | }; |
3561 | |
3562 | static const struct snd_soc_component_driver soc_component_dev_rt5645 = { |
3563 | .probe = rt5645_probe, |
3564 | .remove = rt5645_remove, |
3565 | .suspend = rt5645_suspend, |
3566 | .resume = rt5645_resume, |
3567 | .set_bias_level = rt5645_set_bias_level, |
3568 | .controls = rt5645_snd_controls, |
3569 | .num_controls = ARRAY_SIZE(rt5645_snd_controls), |
3570 | .dapm_widgets = rt5645_dapm_widgets, |
3571 | .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), |
3572 | .dapm_routes = rt5645_dapm_routes, |
3573 | .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), |
3574 | .set_jack = rt5645_component_set_jack, |
3575 | .use_pmdown_time = 1, |
3576 | .endianness = 1, |
3577 | }; |
3578 | |
3579 | static const struct regmap_config rt5645_regmap = { |
3580 | .reg_bits = 8, |
3581 | .val_bits = 16, |
3582 | .use_single_read = true, |
3583 | .use_single_write = true, |
3584 | .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * |
3585 | RT5645_PR_SPACING), |
3586 | .volatile_reg = rt5645_volatile_register, |
3587 | .readable_reg = rt5645_readable_register, |
3588 | |
3589 | .cache_type = REGCACHE_MAPLE, |
3590 | .reg_defaults = rt5645_reg, |
3591 | .num_reg_defaults = ARRAY_SIZE(rt5645_reg), |
3592 | .ranges = rt5645_ranges, |
3593 | .num_ranges = ARRAY_SIZE(rt5645_ranges), |
3594 | }; |
3595 | |
3596 | static const struct regmap_config rt5650_regmap = { |
3597 | .reg_bits = 8, |
3598 | .val_bits = 16, |
3599 | .use_single_read = true, |
3600 | .use_single_write = true, |
3601 | .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * |
3602 | RT5645_PR_SPACING), |
3603 | .volatile_reg = rt5645_volatile_register, |
3604 | .readable_reg = rt5645_readable_register, |
3605 | |
3606 | .cache_type = REGCACHE_MAPLE, |
3607 | .reg_defaults = rt5650_reg, |
3608 | .num_reg_defaults = ARRAY_SIZE(rt5650_reg), |
3609 | .ranges = rt5645_ranges, |
3610 | .num_ranges = ARRAY_SIZE(rt5645_ranges), |
3611 | }; |
3612 | |
3613 | static const struct regmap_config temp_regmap = { |
3614 | .name="nocache" , |
3615 | .reg_bits = 8, |
3616 | .val_bits = 16, |
3617 | .use_single_read = true, |
3618 | .use_single_write = true, |
3619 | .max_register = RT5645_VENDOR_ID2 + 1, |
3620 | .cache_type = REGCACHE_NONE, |
3621 | }; |
3622 | |
3623 | static const struct i2c_device_id rt5645_i2c_id[] = { |
3624 | { "rt5645" , 0 }, |
3625 | { "rt5650" , 0 }, |
3626 | { } |
3627 | }; |
3628 | MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); |
3629 | |
3630 | #ifdef CONFIG_OF |
3631 | static const struct of_device_id rt5645_of_match[] = { |
3632 | { .compatible = "realtek,rt5645" , }, |
3633 | { .compatible = "realtek,rt5650" , }, |
3634 | { } |
3635 | }; |
3636 | MODULE_DEVICE_TABLE(of, rt5645_of_match); |
3637 | #endif |
3638 | |
3639 | #ifdef CONFIG_ACPI |
3640 | static const struct acpi_device_id rt5645_acpi_match[] = { |
3641 | { "10EC5645" , 0 }, |
3642 | { "10EC5648" , 0 }, |
3643 | { "10EC5650" , 0 }, |
3644 | { "10EC5640" , 0 }, |
3645 | { "10EC3270" , 0 }, |
3646 | {}, |
3647 | }; |
3648 | MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); |
3649 | #endif |
3650 | |
3651 | static const struct rt5645_platform_data intel_braswell_platform_data = { |
3652 | .dmic1_data_pin = RT5645_DMIC1_DISABLE, |
3653 | .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, |
3654 | .jd_mode = 3, |
3655 | }; |
3656 | |
3657 | static const struct rt5645_platform_data buddy_platform_data = { |
3658 | .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, |
3659 | .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, |
3660 | .jd_mode = 4, |
3661 | .level_trigger_irq = true, |
3662 | }; |
3663 | |
3664 | static const struct rt5645_platform_data gpd_win_platform_data = { |
3665 | .jd_mode = 3, |
3666 | .inv_jd1_1 = true, |
3667 | .mono_speaker = true, |
3668 | .long_name = "gpd-win-pocket-rt5645" , |
3669 | /* The GPD pocket has a diff. mic, for the win this does not matter. */ |
3670 | .in2_diff = true, |
3671 | }; |
3672 | |
3673 | static const struct rt5645_platform_data asus_t100ha_platform_data = { |
3674 | .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, |
3675 | .dmic2_data_pin = RT5645_DMIC2_DISABLE, |
3676 | .jd_mode = 3, |
3677 | .inv_jd1_1 = true, |
3678 | }; |
3679 | |
3680 | static const struct rt5645_platform_data asus_t101ha_platform_data = { |
3681 | .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, |
3682 | .dmic2_data_pin = RT5645_DMIC2_DISABLE, |
3683 | .jd_mode = 3, |
3684 | }; |
3685 | |
3686 | static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = { |
3687 | .jd_mode = 3, |
3688 | .in2_diff = true, |
3689 | }; |
3690 | |
3691 | static const struct rt5645_platform_data jd_mode3_monospk_platform_data = { |
3692 | .jd_mode = 3, |
3693 | .mono_speaker = true, |
3694 | }; |
3695 | |
3696 | static const struct rt5645_platform_data jd_mode3_inv_data = { |
3697 | .jd_mode = 3, |
3698 | .inv_jd1_1 = true, |
3699 | }; |
3700 | |
3701 | static const struct rt5645_platform_data jd_mode3_platform_data = { |
3702 | .jd_mode = 3, |
3703 | }; |
3704 | |
3705 | static const struct rt5645_platform_data lattepanda_board_platform_data = { |
3706 | .jd_mode = 2, |
3707 | .inv_jd1_1 = true |
3708 | }; |
3709 | |
3710 | static const struct rt5645_platform_data kahlee_platform_data = { |
3711 | .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, |
3712 | .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, |
3713 | .jd_mode = 3, |
3714 | }; |
3715 | |
3716 | static const struct rt5645_platform_data ecs_ef20_platform_data = { |
3717 | .dmic1_data_pin = RT5645_DMIC1_DISABLE, |
3718 | .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, |
3719 | .inv_hp_pol = 1, |
3720 | }; |
3721 | |
3722 | static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false }; |
3723 | |
3724 | static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = { |
3725 | { .name: "hp-detect-gpios" , .data: &ef20_hp_detect, .size: 1 }, |
3726 | { }, |
3727 | }; |
3728 | |
3729 | static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id) |
3730 | { |
3731 | cht_rt5645_gpios = cht_rt5645_ef20_gpios; |
3732 | return 1; |
3733 | } |
3734 | |
3735 | static const struct dmi_system_id dmi_platform_data[] = { |
3736 | { |
3737 | .ident = "Chrome Buddy" , |
3738 | .matches = { |
3739 | DMI_MATCH(DMI_PRODUCT_NAME, "Buddy" ), |
3740 | }, |
3741 | .driver_data = (void *)&buddy_platform_data, |
3742 | }, |
3743 | { |
3744 | .ident = "Intel Strago" , |
3745 | .matches = { |
3746 | DMI_MATCH(DMI_PRODUCT_NAME, "Strago" ), |
3747 | }, |
3748 | .driver_data = (void *)&intel_braswell_platform_data, |
3749 | }, |
3750 | { |
3751 | .ident = "Google Chrome" , |
3752 | .matches = { |
3753 | DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE" ), |
3754 | }, |
3755 | .driver_data = (void *)&intel_braswell_platform_data, |
3756 | }, |
3757 | { |
3758 | .ident = "Google Setzer" , |
3759 | .matches = { |
3760 | DMI_MATCH(DMI_PRODUCT_NAME, "Setzer" ), |
3761 | }, |
3762 | .driver_data = (void *)&intel_braswell_platform_data, |
3763 | }, |
3764 | { |
3765 | .ident = "Microsoft Surface 3" , |
3766 | .matches = { |
3767 | DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3" ), |
3768 | }, |
3769 | .driver_data = (void *)&intel_braswell_platform_data, |
3770 | }, |
3771 | { |
3772 | /* |
3773 | * Match for the GPDwin which unfortunately uses somewhat |
3774 | * generic dmi strings, which is why we test for 4 strings. |
3775 | * Comparing against 23 other byt/cht boards, board_vendor |
3776 | * and board_name are unique to the GPDwin, where as only one |
3777 | * other board has the same board_serial and 3 others have |
3778 | * the same default product_name. Also the GPDwin is the |
3779 | * only device to have both board_ and product_name not set. |
3780 | */ |
3781 | .ident = "GPD Win / Pocket" , |
3782 | .matches = { |
3783 | DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation" ), |
3784 | DMI_MATCH(DMI_BOARD_NAME, "Default string" ), |
3785 | DMI_MATCH(DMI_BOARD_SERIAL, "Default string" ), |
3786 | DMI_MATCH(DMI_PRODUCT_NAME, "Default string" ), |
3787 | }, |
3788 | .driver_data = (void *)&gpd_win_platform_data, |
3789 | }, |
3790 | { |
3791 | .ident = "ASUS T100HAN" , |
3792 | .matches = { |
3793 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC." ), |
3794 | DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN" ), |
3795 | }, |
3796 | .driver_data = (void *)&asus_t100ha_platform_data, |
3797 | }, |
3798 | { |
3799 | .ident = "ASUS T101HA" , |
3800 | .matches = { |
3801 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC." ), |
3802 | DMI_MATCH(DMI_PRODUCT_NAME, "T101HA" ), |
3803 | }, |
3804 | .driver_data = (void *)&asus_t101ha_platform_data, |
3805 | }, |
3806 | { |
3807 | .ident = "MINIX Z83-4" , |
3808 | .matches = { |
3809 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX" ), |
3810 | DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4" ), |
3811 | }, |
3812 | .driver_data = (void *)&jd_mode3_platform_data, |
3813 | }, |
3814 | { |
3815 | .ident = "Teclast X80 Pro" , |
3816 | .matches = { |
3817 | DMI_MATCH(DMI_SYS_VENDOR, "TECLAST" ), |
3818 | DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro" ), |
3819 | }, |
3820 | .driver_data = (void *)&jd_mode3_monospk_platform_data, |
3821 | }, |
3822 | { |
3823 | .ident = "Lenovo Ideapad Miix 310" , |
3824 | .matches = { |
3825 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO" ), |
3826 | DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG" ), |
3827 | DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR" ), |
3828 | }, |
3829 | .driver_data = (void *)&lenovo_ideapad_miix_310_pdata, |
3830 | }, |
3831 | { |
3832 | .ident = "Lenovo Ideapad Miix 320" , |
3833 | .matches = { |
3834 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO" ), |
3835 | DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF" ), |
3836 | DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR" ), |
3837 | }, |
3838 | .driver_data = (void *)&intel_braswell_platform_data, |
3839 | }, |
3840 | { |
3841 | .ident = "LattePanda board" , |
3842 | .matches = { |
3843 | DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation" ), |
3844 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR" ), |
3845 | DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string" ), |
3846 | /* |
3847 | * Above strings are too generic, LattePanda BIOS versions for |
3848 | * all 4 hw revisions are: |
3849 | * DF-BI-7-S70CR100-* |
3850 | * DF-BI-7-S70CR110-* |
3851 | * DF-BI-7-S70CR200-* |
3852 | * LP-BS-7-S70CR700-* |
3853 | * Do a partial match for S70CR to avoid false positive matches. |
3854 | */ |
3855 | DMI_MATCH(DMI_BIOS_VERSION, "S70CR" ), |
3856 | }, |
3857 | .driver_data = (void *)&lattepanda_board_platform_data, |
3858 | }, |
3859 | { |
3860 | .ident = "Chrome Kahlee" , |
3861 | .matches = { |
3862 | DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee" ), |
3863 | }, |
3864 | .driver_data = (void *)&kahlee_platform_data, |
3865 | }, |
3866 | { |
3867 | .ident = "Medion E1239T" , |
3868 | .matches = { |
3869 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION" ), |
3870 | DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568" ), |
3871 | }, |
3872 | .driver_data = (void *)&intel_braswell_platform_data, |
3873 | }, |
3874 | { |
3875 | .ident = "EF20" , |
3876 | .callback = cht_rt5645_ef20_quirk_cb, |
3877 | .matches = { |
3878 | DMI_MATCH(DMI_PRODUCT_NAME, "EF20" ), |
3879 | }, |
3880 | .driver_data = (void *)&ecs_ef20_platform_data, |
3881 | }, |
3882 | { |
3883 | .ident = "Acer Switch V 10 (SW5-017)" , |
3884 | .matches = { |
3885 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer" ), |
3886 | DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017" ), |
3887 | }, |
3888 | .driver_data = (void *)&intel_braswell_platform_data, |
3889 | }, |
3890 | { |
3891 | .ident = "Meegopad T08" , |
3892 | .matches = { |
3893 | DMI_MATCH(DMI_SYS_VENDOR, "Default string" ), |
3894 | DMI_MATCH(DMI_PRODUCT_NAME, "Default string" ), |
3895 | DMI_MATCH(DMI_BOARD_NAME, "T3 MRD" ), |
3896 | DMI_MATCH(DMI_BOARD_VERSION, "V1.1" ), |
3897 | }, |
3898 | .driver_data = (void *)&jd_mode3_inv_data, |
3899 | }, |
3900 | { } |
3901 | }; |
3902 | |
3903 | static bool rt5645_check_dp(struct device *dev) |
3904 | { |
3905 | if (device_property_present(dev, propname: "realtek,in2-differential" ) || |
3906 | device_property_present(dev, propname: "realtek,dmic1-data-pin" ) || |
3907 | device_property_present(dev, propname: "realtek,dmic2-data-pin" ) || |
3908 | device_property_present(dev, propname: "realtek,jd-mode" )) |
3909 | return true; |
3910 | |
3911 | return false; |
3912 | } |
3913 | |
3914 | static void rt5645_parse_dt(struct device *dev, struct rt5645_platform_data *pdata) |
3915 | { |
3916 | pdata->in2_diff = device_property_read_bool(dev, propname: "realtek,in2-differential" ); |
3917 | device_property_read_u32(dev, propname: "realtek,dmic1-data-pin" , val: &pdata->dmic1_data_pin); |
3918 | device_property_read_u32(dev, propname: "realtek,dmic2-data-pin" , val: &pdata->dmic2_data_pin); |
3919 | device_property_read_u32(dev, propname: "realtek,jd-mode" , val: &pdata->jd_mode); |
3920 | } |
3921 | |
3922 | static void rt5645_get_pdata(struct device *codec_dev, struct rt5645_platform_data *pdata) |
3923 | { |
3924 | const struct dmi_system_id *dmi_data; |
3925 | |
3926 | dmi_data = dmi_first_match(list: dmi_platform_data); |
3927 | if (dmi_data) { |
3928 | dev_info(codec_dev, "Detected %s platform\n" , dmi_data->ident); |
3929 | *pdata = *((struct rt5645_platform_data *)dmi_data->driver_data); |
3930 | } else if (rt5645_check_dp(dev: codec_dev)) { |
3931 | rt5645_parse_dt(dev: codec_dev, pdata); |
3932 | } else { |
3933 | *pdata = jd_mode3_platform_data; |
3934 | } |
3935 | |
3936 | if (quirk != -1) { |
3937 | pdata->in2_diff = QUIRK_IN2_DIFF(quirk); |
3938 | pdata->level_trigger_irq = QUIRK_LEVEL_IRQ(quirk); |
3939 | pdata->inv_jd1_1 = QUIRK_INV_JD1_1(quirk); |
3940 | pdata->inv_hp_pol = QUIRK_INV_HP_POL(quirk); |
3941 | pdata->jd_mode = QUIRK_JD_MODE(quirk); |
3942 | pdata->dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk); |
3943 | pdata->dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk); |
3944 | } |
3945 | } |
3946 | |
3947 | const char *rt5645_components(struct device *codec_dev) |
3948 | { |
3949 | struct rt5645_platform_data pdata = { }; |
3950 | static char buf[32]; |
3951 | const char *mic; |
3952 | int spk = 2; |
3953 | |
3954 | rt5645_get_pdata(codec_dev, pdata: &pdata); |
3955 | |
3956 | if (pdata.mono_speaker) |
3957 | spk = 1; |
3958 | |
3959 | if (pdata.dmic1_data_pin && pdata.dmic2_data_pin) |
3960 | mic = "dmics12" ; |
3961 | else if (pdata.dmic1_data_pin) |
3962 | mic = "dmic1" ; |
3963 | else if (pdata.dmic2_data_pin) |
3964 | mic = "dmic2" ; |
3965 | else |
3966 | mic = "in2" ; |
3967 | |
3968 | snprintf(buf, size: sizeof(buf), fmt: "cfg-spk:%d cfg-mic:%s" , spk, mic); |
3969 | |
3970 | return buf; |
3971 | } |
3972 | EXPORT_SYMBOL_GPL(rt5645_components); |
3973 | |
3974 | static int rt5645_i2c_probe(struct i2c_client *i2c) |
3975 | { |
3976 | struct rt5645_priv *rt5645; |
3977 | int ret, i; |
3978 | unsigned int val; |
3979 | struct regmap *regmap; |
3980 | |
3981 | rt5645 = devm_kzalloc(dev: &i2c->dev, size: sizeof(struct rt5645_priv), |
3982 | GFP_KERNEL); |
3983 | if (rt5645 == NULL) |
3984 | return -ENOMEM; |
3985 | |
3986 | rt5645->i2c = i2c; |
3987 | i2c_set_clientdata(client: i2c, data: rt5645); |
3988 | rt5645_get_pdata(codec_dev: &i2c->dev, pdata: &rt5645->pdata); |
3989 | |
3990 | if (has_acpi_companion(dev: &i2c->dev)) { |
3991 | if (cht_rt5645_gpios) { |
3992 | if (devm_acpi_dev_add_driver_gpios(dev: &i2c->dev, gpios: cht_rt5645_gpios)) |
3993 | dev_dbg(&i2c->dev, "Failed to add driver gpios\n" ); |
3994 | } |
3995 | |
3996 | /* The ALC3270 package has the headset-mic pin not-connected */ |
3997 | if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270" , NULL)) |
3998 | rt5645->pdata.no_headset_mic = true; |
3999 | } |
4000 | |
4001 | rt5645->gpiod_hp_det = devm_gpiod_get_optional(dev: &i2c->dev, con_id: "hp-detect" , |
4002 | flags: GPIOD_IN); |
4003 | |
4004 | if (IS_ERR(ptr: rt5645->gpiod_hp_det)) { |
4005 | dev_info(&i2c->dev, "failed to initialize gpiod\n" ); |
4006 | ret = PTR_ERR(ptr: rt5645->gpiod_hp_det); |
4007 | /* |
4008 | * Continue if optional gpiod is missing, bail for all other |
4009 | * errors, including -EPROBE_DEFER |
4010 | */ |
4011 | if (ret != -ENOENT) |
4012 | return ret; |
4013 | } |
4014 | |
4015 | for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) |
4016 | rt5645->supplies[i].supply = rt5645_supply_names[i]; |
4017 | |
4018 | ret = devm_regulator_bulk_get(dev: &i2c->dev, |
4019 | ARRAY_SIZE(rt5645->supplies), |
4020 | consumers: rt5645->supplies); |
4021 | if (ret) { |
4022 | dev_err(&i2c->dev, "Failed to request supplies: %d\n" , ret); |
4023 | return ret; |
4024 | } |
4025 | |
4026 | ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), |
4027 | consumers: rt5645->supplies); |
4028 | if (ret) { |
4029 | dev_err(&i2c->dev, "Failed to enable supplies: %d\n" , ret); |
4030 | return ret; |
4031 | } |
4032 | |
4033 | regmap = devm_regmap_init_i2c(i2c, &temp_regmap); |
4034 | if (IS_ERR(ptr: regmap)) { |
4035 | ret = PTR_ERR(ptr: regmap); |
4036 | dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n" , |
4037 | ret); |
4038 | goto err_enable; |
4039 | } |
4040 | |
4041 | /* |
4042 | * Read after 400msec, as it is the interval required between |
4043 | * read and power On. |
4044 | */ |
4045 | msleep(TIME_TO_POWER_MS); |
4046 | ret = regmap_read(map: regmap, RT5645_VENDOR_ID2, val: &val); |
4047 | if (ret < 0) { |
4048 | dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d" , RT5645_VENDOR_ID2, ret); |
4049 | goto err_enable; |
4050 | } |
4051 | |
4052 | switch (val) { |
4053 | case RT5645_DEVICE_ID: |
4054 | rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); |
4055 | rt5645->codec_type = CODEC_TYPE_RT5645; |
4056 | break; |
4057 | case RT5650_DEVICE_ID: |
4058 | rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap); |
4059 | rt5645->codec_type = CODEC_TYPE_RT5650; |
4060 | break; |
4061 | default: |
4062 | dev_err(&i2c->dev, |
4063 | "Device with ID register %#x is not rt5645 or rt5650\n" , |
4064 | val); |
4065 | ret = -ENODEV; |
4066 | goto err_enable; |
4067 | } |
4068 | |
4069 | if (IS_ERR(ptr: rt5645->regmap)) { |
4070 | ret = PTR_ERR(ptr: rt5645->regmap); |
4071 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n" , |
4072 | ret); |
4073 | goto err_enable; |
4074 | } |
4075 | |
4076 | regmap_write(map: rt5645->regmap, RT5645_RESET, val: 0); |
4077 | |
4078 | regmap_read(map: regmap, RT5645_VENDOR_ID, val: &val); |
4079 | rt5645->v_id = val & 0xff; |
4080 | |
4081 | regmap_write(map: rt5645->regmap, RT5645_AD_DA_MIXER, val: 0x8080); |
4082 | |
4083 | ret = regmap_multi_reg_write(map: rt5645->regmap, regs: init_list, |
4084 | ARRAY_SIZE(init_list)); |
4085 | if (ret != 0) |
4086 | dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n" , ret); |
4087 | |
4088 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
4089 | ret = regmap_multi_reg_write(map: rt5645->regmap, regs: rt5650_init_list, |
4090 | ARRAY_SIZE(rt5650_init_list)); |
4091 | if (ret != 0) |
4092 | dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n" , |
4093 | ret); |
4094 | } |
4095 | |
4096 | regmap_update_bits(map: rt5645->regmap, RT5645_CLSD_OUT_CTRL, mask: 0xc0, val: 0xc0); |
4097 | |
4098 | if (rt5645->pdata.in2_diff) |
4099 | regmap_update_bits(map: rt5645->regmap, RT5645_IN2_CTRL, |
4100 | RT5645_IN_DF2, RT5645_IN_DF2); |
4101 | |
4102 | if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { |
4103 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4104 | RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); |
4105 | } |
4106 | switch (rt5645->pdata.dmic1_data_pin) { |
4107 | case RT5645_DMIC_DATA_IN2N: |
4108 | regmap_update_bits(map: rt5645->regmap, RT5645_DMIC_CTRL1, |
4109 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); |
4110 | break; |
4111 | |
4112 | case RT5645_DMIC_DATA_GPIO5: |
4113 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4114 | RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); |
4115 | regmap_update_bits(map: rt5645->regmap, RT5645_DMIC_CTRL1, |
4116 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); |
4117 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4118 | RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); |
4119 | break; |
4120 | |
4121 | case RT5645_DMIC_DATA_GPIO11: |
4122 | regmap_update_bits(map: rt5645->regmap, RT5645_DMIC_CTRL1, |
4123 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); |
4124 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4125 | RT5645_GP11_PIN_MASK, |
4126 | RT5645_GP11_PIN_DMIC1_SDA); |
4127 | break; |
4128 | |
4129 | default: |
4130 | break; |
4131 | } |
4132 | |
4133 | switch (rt5645->pdata.dmic2_data_pin) { |
4134 | case RT5645_DMIC_DATA_IN2P: |
4135 | regmap_update_bits(map: rt5645->regmap, RT5645_DMIC_CTRL1, |
4136 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); |
4137 | break; |
4138 | |
4139 | case RT5645_DMIC_DATA_GPIO6: |
4140 | regmap_update_bits(map: rt5645->regmap, RT5645_DMIC_CTRL1, |
4141 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); |
4142 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4143 | RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); |
4144 | break; |
4145 | |
4146 | case RT5645_DMIC_DATA_GPIO10: |
4147 | regmap_update_bits(map: rt5645->regmap, RT5645_DMIC_CTRL1, |
4148 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); |
4149 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4150 | RT5645_GP10_PIN_MASK, |
4151 | RT5645_GP10_PIN_DMIC2_SDA); |
4152 | break; |
4153 | |
4154 | case RT5645_DMIC_DATA_GPIO12: |
4155 | regmap_update_bits(map: rt5645->regmap, RT5645_DMIC_CTRL1, |
4156 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); |
4157 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4158 | RT5645_GP12_PIN_MASK, |
4159 | RT5645_GP12_PIN_DMIC2_SDA); |
4160 | break; |
4161 | |
4162 | default: |
4163 | break; |
4164 | } |
4165 | |
4166 | if (rt5645->pdata.jd_mode) { |
4167 | regmap_update_bits(map: rt5645->regmap, RT5645_GEN_CTRL3, |
4168 | RT5645_IRQ_CLK_GATE_CTRL, |
4169 | RT5645_IRQ_CLK_GATE_CTRL); |
4170 | regmap_update_bits(map: rt5645->regmap, RT5645_MICBIAS, |
4171 | RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); |
4172 | regmap_update_bits(map: rt5645->regmap, RT5645_IRQ_CTRL2, |
4173 | RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); |
4174 | regmap_update_bits(map: rt5645->regmap, RT5645_GEN_CTRL3, |
4175 | RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); |
4176 | regmap_update_bits(map: rt5645->regmap, RT5645_HPO_MIXER, |
4177 | RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); |
4178 | regmap_update_bits(map: rt5645->regmap, RT5645_MICBIAS, |
4179 | RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); |
4180 | regmap_update_bits(map: rt5645->regmap, RT5645_GPIO_CTRL1, |
4181 | RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); |
4182 | switch (rt5645->pdata.jd_mode) { |
4183 | case 1: |
4184 | regmap_update_bits(map: rt5645->regmap, RT5645_A_JD_CTRL1, |
4185 | RT5645_JD1_MODE_MASK, |
4186 | RT5645_JD1_MODE_0); |
4187 | break; |
4188 | case 2: |
4189 | regmap_update_bits(map: rt5645->regmap, RT5645_A_JD_CTRL1, |
4190 | RT5645_JD1_MODE_MASK, |
4191 | RT5645_JD1_MODE_1); |
4192 | break; |
4193 | case 3: |
4194 | case 4: |
4195 | regmap_update_bits(map: rt5645->regmap, RT5645_A_JD_CTRL1, |
4196 | RT5645_JD1_MODE_MASK, |
4197 | RT5645_JD1_MODE_2); |
4198 | break; |
4199 | default: |
4200 | break; |
4201 | } |
4202 | if (rt5645->pdata.inv_jd1_1) { |
4203 | regmap_update_bits(map: rt5645->regmap, RT5645_IRQ_CTRL2, |
4204 | RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); |
4205 | } |
4206 | } |
4207 | |
4208 | regmap_update_bits(map: rt5645->regmap, RT5645_ADDA_CLK1, |
4209 | RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2); |
4210 | |
4211 | if (rt5645->pdata.level_trigger_irq) { |
4212 | regmap_update_bits(map: rt5645->regmap, RT5645_IRQ_CTRL2, |
4213 | RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); |
4214 | } |
4215 | timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0); |
4216 | |
4217 | mutex_init(&rt5645->jd_mutex); |
4218 | INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); |
4219 | INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); |
4220 | |
4221 | if (rt5645->i2c->irq) { |
4222 | ret = request_threaded_irq(irq: rt5645->i2c->irq, NULL, thread_fn: rt5645_irq, |
4223 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
4224 | | IRQF_ONESHOT, name: "rt5645" , dev: rt5645); |
4225 | if (ret) { |
4226 | dev_err(&i2c->dev, "Failed to request IRQ: %d\n" , ret); |
4227 | goto err_enable; |
4228 | } |
4229 | } |
4230 | |
4231 | ret = devm_snd_soc_register_component(dev: &i2c->dev, component_driver: &soc_component_dev_rt5645, |
4232 | dai_drv: rt5645_dai, ARRAY_SIZE(rt5645_dai)); |
4233 | if (ret) |
4234 | goto err_irq; |
4235 | |
4236 | return 0; |
4237 | |
4238 | err_irq: |
4239 | if (rt5645->i2c->irq) |
4240 | free_irq(rt5645->i2c->irq, rt5645); |
4241 | err_enable: |
4242 | regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), consumers: rt5645->supplies); |
4243 | return ret; |
4244 | } |
4245 | |
4246 | static void rt5645_i2c_remove(struct i2c_client *i2c) |
4247 | { |
4248 | struct rt5645_priv *rt5645 = i2c_get_clientdata(client: i2c); |
4249 | |
4250 | if (i2c->irq) |
4251 | free_irq(i2c->irq, rt5645); |
4252 | |
4253 | /* |
4254 | * Since the rt5645_btn_check_callback() can queue jack_detect_work, |
4255 | * the timer need to be delted first |
4256 | */ |
4257 | del_timer_sync(timer: &rt5645->btn_check_timer); |
4258 | |
4259 | cancel_delayed_work_sync(dwork: &rt5645->jack_detect_work); |
4260 | cancel_delayed_work_sync(dwork: &rt5645->rcclock_work); |
4261 | |
4262 | regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), consumers: rt5645->supplies); |
4263 | } |
4264 | |
4265 | static void rt5645_i2c_shutdown(struct i2c_client *i2c) |
4266 | { |
4267 | struct rt5645_priv *rt5645 = i2c_get_clientdata(client: i2c); |
4268 | |
4269 | regmap_update_bits(map: rt5645->regmap, RT5645_GEN_CTRL3, |
4270 | RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); |
4271 | regmap_update_bits(map: rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, |
4272 | RT5645_CBJ_MN_JD); |
4273 | regmap_update_bits(map: rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, |
4274 | val: 0); |
4275 | msleep(msecs: 20); |
4276 | regmap_write(map: rt5645->regmap, RT5645_RESET, val: 0); |
4277 | } |
4278 | |
4279 | static int __maybe_unused rt5645_sys_suspend(struct device *dev) |
4280 | { |
4281 | struct rt5645_priv *rt5645 = dev_get_drvdata(dev); |
4282 | |
4283 | del_timer_sync(timer: &rt5645->btn_check_timer); |
4284 | cancel_delayed_work_sync(dwork: &rt5645->jack_detect_work); |
4285 | cancel_delayed_work_sync(dwork: &rt5645->rcclock_work); |
4286 | |
4287 | regcache_cache_only(map: rt5645->regmap, enable: true); |
4288 | regcache_mark_dirty(map: rt5645->regmap); |
4289 | return 0; |
4290 | } |
4291 | |
4292 | static int __maybe_unused rt5645_sys_resume(struct device *dev) |
4293 | { |
4294 | struct rt5645_priv *rt5645 = dev_get_drvdata(dev); |
4295 | |
4296 | regcache_cache_only(map: rt5645->regmap, enable: false); |
4297 | regcache_sync(map: rt5645->regmap); |
4298 | |
4299 | if (rt5645->hp_jack) { |
4300 | rt5645->jack_type = 0; |
4301 | rt5645_jack_detect_work(work: &rt5645->jack_detect_work.work); |
4302 | } |
4303 | return 0; |
4304 | } |
4305 | |
4306 | static const struct dev_pm_ops rt5645_pm = { |
4307 | SET_SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume) |
4308 | }; |
4309 | |
4310 | static struct i2c_driver rt5645_i2c_driver = { |
4311 | .driver = { |
4312 | .name = "rt5645" , |
4313 | .of_match_table = of_match_ptr(rt5645_of_match), |
4314 | .acpi_match_table = ACPI_PTR(rt5645_acpi_match), |
4315 | .pm = &rt5645_pm, |
4316 | }, |
4317 | .probe = rt5645_i2c_probe, |
4318 | .remove = rt5645_i2c_remove, |
4319 | .shutdown = rt5645_i2c_shutdown, |
4320 | .id_table = rt5645_i2c_id, |
4321 | }; |
4322 | module_i2c_driver(rt5645_i2c_driver); |
4323 | |
4324 | MODULE_DESCRIPTION("ASoC RT5645 driver" ); |
4325 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>" ); |
4326 | MODULE_LICENSE("GPL v2" ); |
4327 | |