1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver |
4 | * |
5 | * Copyright 2016 Realtek Semiconductor Corp. |
6 | * Author: Bard Liao <bardliao@realtek.com> |
7 | */ |
8 | |
9 | #include <linux/module.h> |
10 | #include <linux/moduleparam.h> |
11 | #include <linux/init.h> |
12 | #include <linux/delay.h> |
13 | #include <linux/pm.h> |
14 | #include <linux/i2c.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/spi/spi.h> |
17 | #include <linux/acpi.h> |
18 | #include <linux/gpio/consumer.h> |
19 | #include <linux/regulator/consumer.h> |
20 | #include <linux/mutex.h> |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> |
23 | #include <sound/pcm_params.h> |
24 | #include <sound/jack.h> |
25 | #include <sound/soc.h> |
26 | #include <sound/soc-dapm.h> |
27 | #include <sound/initval.h> |
28 | #include <sound/tlv.h> |
29 | #include <sound/rt5665.h> |
30 | |
31 | #include "rl6231.h" |
32 | #include "rt5665.h" |
33 | |
34 | #define RT5665_NUM_SUPPLIES 3 |
35 | |
36 | static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = { |
37 | "AVDD" , |
38 | "MICVDD" , |
39 | "VBAT" , |
40 | }; |
41 | |
42 | struct rt5665_priv { |
43 | struct snd_soc_component *component; |
44 | struct rt5665_platform_data pdata; |
45 | struct regmap *regmap; |
46 | struct gpio_desc *gpiod_ldo1_en; |
47 | struct gpio_desc *gpiod_reset; |
48 | struct snd_soc_jack *hs_jack; |
49 | struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES]; |
50 | struct delayed_work jack_detect_work; |
51 | struct delayed_work calibrate_work; |
52 | struct delayed_work jd_check_work; |
53 | struct mutex calibrate_mutex; |
54 | |
55 | int sysclk; |
56 | int sysclk_src; |
57 | int lrck[RT5665_AIFS]; |
58 | int bclk[RT5665_AIFS]; |
59 | int master[RT5665_AIFS]; |
60 | int id; |
61 | |
62 | int pll_src; |
63 | int pll_in; |
64 | int pll_out; |
65 | |
66 | int jack_type; |
67 | int irq_work_delay_time; |
68 | unsigned int sar_adc_value; |
69 | bool calibration_done; |
70 | }; |
71 | |
72 | static const struct reg_default rt5665_reg[] = { |
73 | {0x0000, 0x0000}, |
74 | {0x0001, 0xc8c8}, |
75 | {0x0002, 0x8080}, |
76 | {0x0003, 0x8000}, |
77 | {0x0004, 0xc80a}, |
78 | {0x0005, 0x0000}, |
79 | {0x0006, 0x0000}, |
80 | {0x0007, 0x0000}, |
81 | {0x000a, 0x0000}, |
82 | {0x000b, 0x0000}, |
83 | {0x000c, 0x0000}, |
84 | {0x000d, 0x0000}, |
85 | {0x000f, 0x0808}, |
86 | {0x0010, 0x4040}, |
87 | {0x0011, 0x0000}, |
88 | {0x0012, 0x1404}, |
89 | {0x0013, 0x1000}, |
90 | {0x0014, 0xa00a}, |
91 | {0x0015, 0x0404}, |
92 | {0x0016, 0x0404}, |
93 | {0x0017, 0x0011}, |
94 | {0x0018, 0xafaf}, |
95 | {0x0019, 0xafaf}, |
96 | {0x001a, 0xafaf}, |
97 | {0x001b, 0x0011}, |
98 | {0x001c, 0x2f2f}, |
99 | {0x001d, 0x2f2f}, |
100 | {0x001e, 0x2f2f}, |
101 | {0x001f, 0x0000}, |
102 | {0x0020, 0x0000}, |
103 | {0x0021, 0x0000}, |
104 | {0x0022, 0x5757}, |
105 | {0x0023, 0x0039}, |
106 | {0x0026, 0xc0c0}, |
107 | {0x0027, 0xc0c0}, |
108 | {0x0028, 0xc0c0}, |
109 | {0x0029, 0x8080}, |
110 | {0x002a, 0xaaaa}, |
111 | {0x002b, 0xaaaa}, |
112 | {0x002c, 0xaba8}, |
113 | {0x002d, 0x0000}, |
114 | {0x002e, 0x0000}, |
115 | {0x002f, 0x0000}, |
116 | {0x0030, 0x0000}, |
117 | {0x0031, 0x5000}, |
118 | {0x0032, 0x0000}, |
119 | {0x0033, 0x0000}, |
120 | {0x0034, 0x0000}, |
121 | {0x0035, 0x0000}, |
122 | {0x003a, 0x0000}, |
123 | {0x003b, 0x0000}, |
124 | {0x003c, 0x00ff}, |
125 | {0x003d, 0x0000}, |
126 | {0x003e, 0x00ff}, |
127 | {0x003f, 0x0000}, |
128 | {0x0040, 0x0000}, |
129 | {0x0041, 0x00ff}, |
130 | {0x0042, 0x0000}, |
131 | {0x0043, 0x00ff}, |
132 | {0x0044, 0x0c0c}, |
133 | {0x0049, 0xc00b}, |
134 | {0x004a, 0x0000}, |
135 | {0x004b, 0x031f}, |
136 | {0x004d, 0x0000}, |
137 | {0x004e, 0x001f}, |
138 | {0x004f, 0x0000}, |
139 | {0x0050, 0x001f}, |
140 | {0x0052, 0xf000}, |
141 | {0x0061, 0x0000}, |
142 | {0x0062, 0x0000}, |
143 | {0x0063, 0x003e}, |
144 | {0x0064, 0x0000}, |
145 | {0x0065, 0x0000}, |
146 | {0x0066, 0x003f}, |
147 | {0x0067, 0x0000}, |
148 | {0x006b, 0x0000}, |
149 | {0x006d, 0xff00}, |
150 | {0x006e, 0x2808}, |
151 | {0x006f, 0x000a}, |
152 | {0x0070, 0x8000}, |
153 | {0x0071, 0x8000}, |
154 | {0x0072, 0x8000}, |
155 | {0x0073, 0x7000}, |
156 | {0x0074, 0x7770}, |
157 | {0x0075, 0x0002}, |
158 | {0x0076, 0x0001}, |
159 | {0x0078, 0x00f0}, |
160 | {0x0079, 0x0000}, |
161 | {0x007a, 0x0000}, |
162 | {0x007b, 0x0000}, |
163 | {0x007c, 0x0000}, |
164 | {0x007d, 0x0123}, |
165 | {0x007e, 0x4500}, |
166 | {0x007f, 0x8003}, |
167 | {0x0080, 0x0000}, |
168 | {0x0081, 0x0000}, |
169 | {0x0082, 0x0000}, |
170 | {0x0083, 0x0000}, |
171 | {0x0084, 0x0000}, |
172 | {0x0085, 0x0000}, |
173 | {0x0086, 0x0008}, |
174 | {0x0087, 0x0000}, |
175 | {0x0088, 0x0000}, |
176 | {0x0089, 0x0000}, |
177 | {0x008a, 0x0000}, |
178 | {0x008b, 0x0000}, |
179 | {0x008c, 0x0003}, |
180 | {0x008e, 0x0060}, |
181 | {0x008f, 0x1000}, |
182 | {0x0091, 0x0c26}, |
183 | {0x0092, 0x0073}, |
184 | {0x0093, 0x0000}, |
185 | {0x0094, 0x0080}, |
186 | {0x0098, 0x0000}, |
187 | {0x0099, 0x0000}, |
188 | {0x009a, 0x0007}, |
189 | {0x009f, 0x0000}, |
190 | {0x00a0, 0x0000}, |
191 | {0x00a1, 0x0002}, |
192 | {0x00a2, 0x0001}, |
193 | {0x00a3, 0x0002}, |
194 | {0x00a4, 0x0001}, |
195 | {0x00ae, 0x2040}, |
196 | {0x00af, 0x0000}, |
197 | {0x00b6, 0x0000}, |
198 | {0x00b7, 0x0000}, |
199 | {0x00b8, 0x0000}, |
200 | {0x00b9, 0x0000}, |
201 | {0x00ba, 0x0002}, |
202 | {0x00bb, 0x0000}, |
203 | {0x00be, 0x0000}, |
204 | {0x00c0, 0x0000}, |
205 | {0x00c1, 0x0aaa}, |
206 | {0x00c2, 0xaa80}, |
207 | {0x00c3, 0x0003}, |
208 | {0x00c4, 0x0000}, |
209 | {0x00d0, 0x0000}, |
210 | {0x00d1, 0x2244}, |
211 | {0x00d3, 0x3300}, |
212 | {0x00d4, 0x2200}, |
213 | {0x00d9, 0x0809}, |
214 | {0x00da, 0x0000}, |
215 | {0x00db, 0x0008}, |
216 | {0x00dc, 0x00c0}, |
217 | {0x00dd, 0x6724}, |
218 | {0x00de, 0x3131}, |
219 | {0x00df, 0x0008}, |
220 | {0x00e0, 0x4000}, |
221 | {0x00e1, 0x3131}, |
222 | {0x00e2, 0x600c}, |
223 | {0x00ea, 0xb320}, |
224 | {0x00eb, 0x0000}, |
225 | {0x00ec, 0xb300}, |
226 | {0x00ed, 0x0000}, |
227 | {0x00ee, 0xb320}, |
228 | {0x00ef, 0x0000}, |
229 | {0x00f0, 0x0201}, |
230 | {0x00f1, 0x0ddd}, |
231 | {0x00f2, 0x0ddd}, |
232 | {0x00f6, 0x0000}, |
233 | {0x00f7, 0x0000}, |
234 | {0x00f8, 0x0000}, |
235 | {0x00fa, 0x0000}, |
236 | {0x00fb, 0x0000}, |
237 | {0x00fc, 0x0000}, |
238 | {0x00fd, 0x0000}, |
239 | {0x00fe, 0x10ec}, |
240 | {0x00ff, 0x6451}, |
241 | {0x0100, 0xaaaa}, |
242 | {0x0101, 0x000a}, |
243 | {0x010a, 0xaaaa}, |
244 | {0x010b, 0xa0a0}, |
245 | {0x010c, 0xaeae}, |
246 | {0x010d, 0xaaaa}, |
247 | {0x010e, 0xaaaa}, |
248 | {0x010f, 0xaaaa}, |
249 | {0x0110, 0xe002}, |
250 | {0x0111, 0xa402}, |
251 | {0x0112, 0xaaaa}, |
252 | {0x0113, 0x2000}, |
253 | {0x0117, 0x0f00}, |
254 | {0x0125, 0x0410}, |
255 | {0x0132, 0x0000}, |
256 | {0x0133, 0x0000}, |
257 | {0x0137, 0x5540}, |
258 | {0x0138, 0x3700}, |
259 | {0x0139, 0x79a1}, |
260 | {0x013a, 0x2020}, |
261 | {0x013b, 0x2020}, |
262 | {0x013c, 0x2005}, |
263 | {0x013f, 0x0000}, |
264 | {0x0145, 0x0002}, |
265 | {0x0146, 0x0000}, |
266 | {0x0147, 0x0000}, |
267 | {0x0148, 0x0000}, |
268 | {0x0150, 0x0000}, |
269 | {0x0160, 0x4eff}, |
270 | {0x0161, 0x0080}, |
271 | {0x0162, 0x0200}, |
272 | {0x0163, 0x0800}, |
273 | {0x0164, 0x0000}, |
274 | {0x0165, 0x0000}, |
275 | {0x0166, 0x0000}, |
276 | {0x0167, 0x000f}, |
277 | {0x0170, 0x4e87}, |
278 | {0x0171, 0x0080}, |
279 | {0x0172, 0x0200}, |
280 | {0x0173, 0x0800}, |
281 | {0x0174, 0x00ff}, |
282 | {0x0175, 0x0000}, |
283 | {0x0190, 0x413d}, |
284 | {0x0191, 0x4139}, |
285 | {0x0192, 0x4135}, |
286 | {0x0193, 0x413d}, |
287 | {0x0194, 0x0000}, |
288 | {0x0195, 0x0000}, |
289 | {0x0196, 0x0000}, |
290 | {0x0197, 0x0000}, |
291 | {0x0198, 0x0000}, |
292 | {0x0199, 0x0000}, |
293 | {0x01a0, 0x1e64}, |
294 | {0x01a1, 0x06a3}, |
295 | {0x01a2, 0x0000}, |
296 | {0x01a3, 0x0000}, |
297 | {0x01a4, 0x0000}, |
298 | {0x01a5, 0x0000}, |
299 | {0x01a6, 0x0000}, |
300 | {0x01a7, 0x8000}, |
301 | {0x01a8, 0x0000}, |
302 | {0x01a9, 0x0000}, |
303 | {0x01aa, 0x0000}, |
304 | {0x01ab, 0x0000}, |
305 | {0x01b5, 0x0000}, |
306 | {0x01b6, 0x01c3}, |
307 | {0x01b7, 0x02a0}, |
308 | {0x01b8, 0x03e9}, |
309 | {0x01b9, 0x1389}, |
310 | {0x01ba, 0xc351}, |
311 | {0x01bb, 0x0009}, |
312 | {0x01bc, 0x0018}, |
313 | {0x01bd, 0x002a}, |
314 | {0x01be, 0x004c}, |
315 | {0x01bf, 0x0097}, |
316 | {0x01c0, 0x433d}, |
317 | {0x01c1, 0x0000}, |
318 | {0x01c2, 0x0000}, |
319 | {0x01c3, 0x0000}, |
320 | {0x01c4, 0x0000}, |
321 | {0x01c5, 0x0000}, |
322 | {0x01c6, 0x0000}, |
323 | {0x01c7, 0x0000}, |
324 | {0x01c8, 0x40af}, |
325 | {0x01c9, 0x0702}, |
326 | {0x01ca, 0x0000}, |
327 | {0x01cb, 0x0000}, |
328 | {0x01cc, 0x5757}, |
329 | {0x01cd, 0x5757}, |
330 | {0x01ce, 0x5757}, |
331 | {0x01cf, 0x5757}, |
332 | {0x01d0, 0x5757}, |
333 | {0x01d1, 0x5757}, |
334 | {0x01d2, 0x5757}, |
335 | {0x01d3, 0x5757}, |
336 | {0x01d4, 0x5757}, |
337 | {0x01d5, 0x5757}, |
338 | {0x01d6, 0x003c}, |
339 | {0x01da, 0x0000}, |
340 | {0x01db, 0x0000}, |
341 | {0x01dc, 0x0000}, |
342 | {0x01de, 0x7c00}, |
343 | {0x01df, 0x0320}, |
344 | {0x01e0, 0x06a1}, |
345 | {0x01e1, 0x0000}, |
346 | {0x01e2, 0x0000}, |
347 | {0x01e3, 0x0000}, |
348 | {0x01e4, 0x0000}, |
349 | {0x01e6, 0x0001}, |
350 | {0x01e7, 0x0000}, |
351 | {0x01e8, 0x0000}, |
352 | {0x01ea, 0xbf3f}, |
353 | {0x01eb, 0x0000}, |
354 | {0x01ec, 0x0000}, |
355 | {0x01ed, 0x0000}, |
356 | {0x01ee, 0x0000}, |
357 | {0x01ef, 0x0000}, |
358 | {0x01f0, 0x0000}, |
359 | {0x01f1, 0x0000}, |
360 | {0x01f2, 0x0000}, |
361 | {0x01f3, 0x0000}, |
362 | {0x01f4, 0x0000}, |
363 | {0x0200, 0x0000}, |
364 | {0x0201, 0x0000}, |
365 | {0x0202, 0x0000}, |
366 | {0x0203, 0x0000}, |
367 | {0x0204, 0x0000}, |
368 | {0x0205, 0x0000}, |
369 | {0x0206, 0x0000}, |
370 | {0x0207, 0x0000}, |
371 | {0x0208, 0x0000}, |
372 | {0x0210, 0x60b1}, |
373 | {0x0211, 0xa005}, |
374 | {0x0212, 0x024c}, |
375 | {0x0213, 0xf7ff}, |
376 | {0x0214, 0x024c}, |
377 | {0x0215, 0x0102}, |
378 | {0x0216, 0x00a3}, |
379 | {0x0217, 0x0048}, |
380 | {0x0218, 0xa2c0}, |
381 | {0x0219, 0x0400}, |
382 | {0x021a, 0x00c8}, |
383 | {0x021b, 0x00c0}, |
384 | {0x02ff, 0x0110}, |
385 | {0x0300, 0x001f}, |
386 | {0x0301, 0x032c}, |
387 | {0x0302, 0x5f21}, |
388 | {0x0303, 0x4000}, |
389 | {0x0304, 0x4000}, |
390 | {0x0305, 0x06d5}, |
391 | {0x0306, 0x8000}, |
392 | {0x0307, 0x0700}, |
393 | {0x0310, 0x4560}, |
394 | {0x0311, 0xa4a8}, |
395 | {0x0312, 0x7418}, |
396 | {0x0313, 0x0000}, |
397 | {0x0314, 0x0006}, |
398 | {0x0315, 0xffff}, |
399 | {0x0316, 0xc400}, |
400 | {0x0317, 0x0000}, |
401 | {0x0330, 0x00a6}, |
402 | {0x0331, 0x04c3}, |
403 | {0x0332, 0x27c8}, |
404 | {0x0333, 0xbf50}, |
405 | {0x0334, 0x0045}, |
406 | {0x0335, 0x0007}, |
407 | {0x0336, 0x7418}, |
408 | {0x0337, 0x0501}, |
409 | {0x0338, 0x0000}, |
410 | {0x0339, 0x0010}, |
411 | {0x033a, 0x1010}, |
412 | {0x03c0, 0x7e00}, |
413 | {0x03c1, 0x8000}, |
414 | {0x03c2, 0x8000}, |
415 | {0x03c3, 0x8000}, |
416 | {0x03c4, 0x8000}, |
417 | {0x03c5, 0x8000}, |
418 | {0x03c6, 0x8000}, |
419 | {0x03c7, 0x8000}, |
420 | {0x03c8, 0x8000}, |
421 | {0x03c9, 0x8000}, |
422 | {0x03ca, 0x8000}, |
423 | {0x03cb, 0x8000}, |
424 | {0x03cc, 0x8000}, |
425 | {0x03d0, 0x0000}, |
426 | {0x03d1, 0x0000}, |
427 | {0x03d2, 0x0000}, |
428 | {0x03d3, 0x0000}, |
429 | {0x03d4, 0x2000}, |
430 | {0x03d5, 0x2000}, |
431 | {0x03d6, 0x0000}, |
432 | {0x03d7, 0x0000}, |
433 | {0x03d8, 0x2000}, |
434 | {0x03d9, 0x2000}, |
435 | {0x03da, 0x2000}, |
436 | {0x03db, 0x2000}, |
437 | {0x03dc, 0x0000}, |
438 | {0x03dd, 0x0000}, |
439 | {0x03de, 0x0000}, |
440 | {0x03df, 0x2000}, |
441 | {0x03e0, 0x0000}, |
442 | {0x03e1, 0x0000}, |
443 | {0x03e2, 0x0000}, |
444 | {0x03e3, 0x0000}, |
445 | {0x03e4, 0x0000}, |
446 | {0x03e5, 0x0000}, |
447 | {0x03e6, 0x0000}, |
448 | {0x03e7, 0x0000}, |
449 | {0x03e8, 0x0000}, |
450 | {0x03e9, 0x0000}, |
451 | {0x03ea, 0x0000}, |
452 | {0x03eb, 0x0000}, |
453 | {0x03ec, 0x0000}, |
454 | {0x03ed, 0x0000}, |
455 | {0x03ee, 0x0000}, |
456 | {0x03ef, 0x0000}, |
457 | {0x03f0, 0x0800}, |
458 | {0x03f1, 0x0800}, |
459 | {0x03f2, 0x0800}, |
460 | {0x03f3, 0x0800}, |
461 | }; |
462 | |
463 | static bool rt5665_volatile_register(struct device *dev, unsigned int reg) |
464 | { |
465 | switch (reg) { |
466 | case RT5665_RESET: |
467 | case RT5665_EJD_CTRL_2: |
468 | case RT5665_GPIO_STA: |
469 | case RT5665_INT_ST_1: |
470 | case RT5665_IL_CMD_1: |
471 | case RT5665_4BTN_IL_CMD_1: |
472 | case RT5665_PSV_IL_CMD_1: |
473 | case RT5665_AJD1_CTRL: |
474 | case RT5665_JD_CTRL_3: |
475 | case RT5665_STO_NG2_CTRL_1: |
476 | case RT5665_SAR_IL_CMD_4: |
477 | case RT5665_DEVICE_ID: |
478 | case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET: |
479 | case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6: |
480 | case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15: |
481 | case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11: |
482 | return true; |
483 | default: |
484 | return false; |
485 | } |
486 | } |
487 | |
488 | static bool rt5665_readable_register(struct device *dev, unsigned int reg) |
489 | { |
490 | switch (reg) { |
491 | case RT5665_RESET: |
492 | case RT5665_VENDOR_ID: |
493 | case RT5665_VENDOR_ID_1: |
494 | case RT5665_DEVICE_ID: |
495 | case RT5665_LOUT: |
496 | case RT5665_HP_CTRL_1: |
497 | case RT5665_HP_CTRL_2: |
498 | case RT5665_MONO_OUT: |
499 | case RT5665_HPL_GAIN: |
500 | case RT5665_HPR_GAIN: |
501 | case RT5665_MONO_GAIN: |
502 | case RT5665_CAL_BST_CTRL: |
503 | case RT5665_CBJ_BST_CTRL: |
504 | case RT5665_IN1_IN2: |
505 | case RT5665_IN3_IN4: |
506 | case RT5665_INL1_INR1_VOL: |
507 | case RT5665_EJD_CTRL_1: |
508 | case RT5665_EJD_CTRL_2: |
509 | case RT5665_EJD_CTRL_3: |
510 | case RT5665_EJD_CTRL_4: |
511 | case RT5665_EJD_CTRL_5: |
512 | case RT5665_EJD_CTRL_6: |
513 | case RT5665_EJD_CTRL_7: |
514 | case RT5665_DAC2_CTRL: |
515 | case RT5665_DAC2_DIG_VOL: |
516 | case RT5665_DAC1_DIG_VOL: |
517 | case RT5665_DAC3_DIG_VOL: |
518 | case RT5665_DAC3_CTRL: |
519 | case RT5665_STO1_ADC_DIG_VOL: |
520 | case RT5665_MONO_ADC_DIG_VOL: |
521 | case RT5665_STO2_ADC_DIG_VOL: |
522 | case RT5665_STO1_ADC_BOOST: |
523 | case RT5665_MONO_ADC_BOOST: |
524 | case RT5665_STO2_ADC_BOOST: |
525 | case RT5665_HP_IMP_GAIN_1: |
526 | case RT5665_HP_IMP_GAIN_2: |
527 | case RT5665_STO1_ADC_MIXER: |
528 | case RT5665_MONO_ADC_MIXER: |
529 | case RT5665_STO2_ADC_MIXER: |
530 | case RT5665_AD_DA_MIXER: |
531 | case RT5665_STO1_DAC_MIXER: |
532 | case RT5665_MONO_DAC_MIXER: |
533 | case RT5665_STO2_DAC_MIXER: |
534 | case RT5665_A_DAC1_MUX: |
535 | case RT5665_A_DAC2_MUX: |
536 | case RT5665_DIG_INF2_DATA: |
537 | case RT5665_DIG_INF3_DATA: |
538 | case RT5665_PDM_OUT_CTRL: |
539 | case RT5665_PDM_DATA_CTRL_1: |
540 | case RT5665_PDM_DATA_CTRL_2: |
541 | case RT5665_PDM_DATA_CTRL_3: |
542 | case RT5665_PDM_DATA_CTRL_4: |
543 | case RT5665_REC1_GAIN: |
544 | case RT5665_REC1_L1_MIXER: |
545 | case RT5665_REC1_L2_MIXER: |
546 | case RT5665_REC1_R1_MIXER: |
547 | case RT5665_REC1_R2_MIXER: |
548 | case RT5665_REC2_GAIN: |
549 | case RT5665_REC2_L1_MIXER: |
550 | case RT5665_REC2_L2_MIXER: |
551 | case RT5665_REC2_R1_MIXER: |
552 | case RT5665_REC2_R2_MIXER: |
553 | case RT5665_CAL_REC: |
554 | case RT5665_ALC_BACK_GAIN: |
555 | case RT5665_MONOMIX_GAIN: |
556 | case RT5665_MONOMIX_IN_GAIN: |
557 | case RT5665_OUT_L_GAIN: |
558 | case RT5665_OUT_L_MIXER: |
559 | case RT5665_OUT_R_GAIN: |
560 | case RT5665_OUT_R_MIXER: |
561 | case RT5665_LOUT_MIXER: |
562 | case RT5665_PWR_DIG_1: |
563 | case RT5665_PWR_DIG_2: |
564 | case RT5665_PWR_ANLG_1: |
565 | case RT5665_PWR_ANLG_2: |
566 | case RT5665_PWR_ANLG_3: |
567 | case RT5665_PWR_MIXER: |
568 | case RT5665_PWR_VOL: |
569 | case RT5665_CLK_DET: |
570 | case RT5665_HPF_CTRL1: |
571 | case RT5665_DMIC_CTRL_1: |
572 | case RT5665_DMIC_CTRL_2: |
573 | case RT5665_I2S1_SDP: |
574 | case RT5665_I2S2_SDP: |
575 | case RT5665_I2S3_SDP: |
576 | case RT5665_ADDA_CLK_1: |
577 | case RT5665_ADDA_CLK_2: |
578 | case RT5665_I2S1_F_DIV_CTRL_1: |
579 | case RT5665_I2S1_F_DIV_CTRL_2: |
580 | case RT5665_TDM_CTRL_1: |
581 | case RT5665_TDM_CTRL_2: |
582 | case RT5665_TDM_CTRL_3: |
583 | case RT5665_TDM_CTRL_4: |
584 | case RT5665_TDM_CTRL_5: |
585 | case RT5665_TDM_CTRL_6: |
586 | case RT5665_TDM_CTRL_7: |
587 | case RT5665_TDM_CTRL_8: |
588 | case RT5665_GLB_CLK: |
589 | case RT5665_PLL_CTRL_1: |
590 | case RT5665_PLL_CTRL_2: |
591 | case RT5665_ASRC_1: |
592 | case RT5665_ASRC_2: |
593 | case RT5665_ASRC_3: |
594 | case RT5665_ASRC_4: |
595 | case RT5665_ASRC_5: |
596 | case RT5665_ASRC_6: |
597 | case RT5665_ASRC_7: |
598 | case RT5665_ASRC_8: |
599 | case RT5665_ASRC_9: |
600 | case RT5665_ASRC_10: |
601 | case RT5665_DEPOP_1: |
602 | case RT5665_DEPOP_2: |
603 | case RT5665_HP_CHARGE_PUMP_1: |
604 | case RT5665_HP_CHARGE_PUMP_2: |
605 | case RT5665_MICBIAS_1: |
606 | case RT5665_MICBIAS_2: |
607 | case RT5665_ASRC_12: |
608 | case RT5665_ASRC_13: |
609 | case RT5665_ASRC_14: |
610 | case RT5665_RC_CLK_CTRL: |
611 | case RT5665_I2S_M_CLK_CTRL_1: |
612 | case RT5665_I2S2_F_DIV_CTRL_1: |
613 | case RT5665_I2S2_F_DIV_CTRL_2: |
614 | case RT5665_I2S3_F_DIV_CTRL_1: |
615 | case RT5665_I2S3_F_DIV_CTRL_2: |
616 | case RT5665_EQ_CTRL_1: |
617 | case RT5665_EQ_CTRL_2: |
618 | case RT5665_IRQ_CTRL_1: |
619 | case RT5665_IRQ_CTRL_2: |
620 | case RT5665_IRQ_CTRL_3: |
621 | case RT5665_IRQ_CTRL_4: |
622 | case RT5665_IRQ_CTRL_5: |
623 | case RT5665_IRQ_CTRL_6: |
624 | case RT5665_INT_ST_1: |
625 | case RT5665_GPIO_CTRL_1: |
626 | case RT5665_GPIO_CTRL_2: |
627 | case RT5665_GPIO_CTRL_3: |
628 | case RT5665_GPIO_CTRL_4: |
629 | case RT5665_GPIO_STA: |
630 | case RT5665_HP_AMP_DET_CTRL_1: |
631 | case RT5665_HP_AMP_DET_CTRL_2: |
632 | case RT5665_MID_HP_AMP_DET: |
633 | case RT5665_LOW_HP_AMP_DET: |
634 | case RT5665_SV_ZCD_1: |
635 | case RT5665_SV_ZCD_2: |
636 | case RT5665_IL_CMD_1: |
637 | case RT5665_IL_CMD_2: |
638 | case RT5665_IL_CMD_3: |
639 | case RT5665_IL_CMD_4: |
640 | case RT5665_4BTN_IL_CMD_1: |
641 | case RT5665_4BTN_IL_CMD_2: |
642 | case RT5665_4BTN_IL_CMD_3: |
643 | case RT5665_PSV_IL_CMD_1: |
644 | case RT5665_ADC_STO1_HP_CTRL_1: |
645 | case RT5665_ADC_STO1_HP_CTRL_2: |
646 | case RT5665_ADC_MONO_HP_CTRL_1: |
647 | case RT5665_ADC_MONO_HP_CTRL_2: |
648 | case RT5665_ADC_STO2_HP_CTRL_1: |
649 | case RT5665_ADC_STO2_HP_CTRL_2: |
650 | case RT5665_AJD1_CTRL: |
651 | case RT5665_JD1_THD: |
652 | case RT5665_JD2_THD: |
653 | case RT5665_JD_CTRL_1: |
654 | case RT5665_JD_CTRL_2: |
655 | case RT5665_JD_CTRL_3: |
656 | case RT5665_DIG_MISC: |
657 | case RT5665_DUMMY_2: |
658 | case RT5665_DUMMY_3: |
659 | case RT5665_DAC_ADC_DIG_VOL1: |
660 | case RT5665_DAC_ADC_DIG_VOL2: |
661 | case RT5665_BIAS_CUR_CTRL_1: |
662 | case RT5665_BIAS_CUR_CTRL_2: |
663 | case RT5665_BIAS_CUR_CTRL_3: |
664 | case RT5665_BIAS_CUR_CTRL_4: |
665 | case RT5665_BIAS_CUR_CTRL_5: |
666 | case RT5665_BIAS_CUR_CTRL_6: |
667 | case RT5665_BIAS_CUR_CTRL_7: |
668 | case RT5665_BIAS_CUR_CTRL_8: |
669 | case RT5665_BIAS_CUR_CTRL_9: |
670 | case RT5665_BIAS_CUR_CTRL_10: |
671 | case RT5665_VREF_REC_OP_FB_CAP_CTRL: |
672 | case RT5665_CHARGE_PUMP_1: |
673 | case RT5665_DIG_IN_CTRL_1: |
674 | case RT5665_DIG_IN_CTRL_2: |
675 | case RT5665_PAD_DRIVING_CTRL: |
676 | case RT5665_SOFT_RAMP_DEPOP: |
677 | case RT5665_PLL: |
678 | case RT5665_CHOP_DAC: |
679 | case RT5665_CHOP_ADC: |
680 | case RT5665_CALIB_ADC_CTRL: |
681 | case RT5665_VOL_TEST: |
682 | case RT5665_TEST_MODE_CTRL_1: |
683 | case RT5665_TEST_MODE_CTRL_2: |
684 | case RT5665_TEST_MODE_CTRL_3: |
685 | case RT5665_TEST_MODE_CTRL_4: |
686 | case RT5665_BASSBACK_CTRL: |
687 | case RT5665_STO_NG2_CTRL_1: |
688 | case RT5665_STO_NG2_CTRL_2: |
689 | case RT5665_STO_NG2_CTRL_3: |
690 | case RT5665_STO_NG2_CTRL_4: |
691 | case RT5665_STO_NG2_CTRL_5: |
692 | case RT5665_STO_NG2_CTRL_6: |
693 | case RT5665_STO_NG2_CTRL_7: |
694 | case RT5665_STO_NG2_CTRL_8: |
695 | case RT5665_MONO_NG2_CTRL_1: |
696 | case RT5665_MONO_NG2_CTRL_2: |
697 | case RT5665_MONO_NG2_CTRL_3: |
698 | case RT5665_MONO_NG2_CTRL_4: |
699 | case RT5665_MONO_NG2_CTRL_5: |
700 | case RT5665_MONO_NG2_CTRL_6: |
701 | case RT5665_STO1_DAC_SIL_DET: |
702 | case RT5665_MONOL_DAC_SIL_DET: |
703 | case RT5665_MONOR_DAC_SIL_DET: |
704 | case RT5665_STO2_DAC_SIL_DET: |
705 | case RT5665_SIL_PSV_CTRL1: |
706 | case RT5665_SIL_PSV_CTRL2: |
707 | case RT5665_SIL_PSV_CTRL3: |
708 | case RT5665_SIL_PSV_CTRL4: |
709 | case RT5665_SIL_PSV_CTRL5: |
710 | case RT5665_SIL_PSV_CTRL6: |
711 | case RT5665_MONO_AMP_CALIB_CTRL_1: |
712 | case RT5665_MONO_AMP_CALIB_CTRL_2: |
713 | case RT5665_MONO_AMP_CALIB_CTRL_3: |
714 | case RT5665_MONO_AMP_CALIB_CTRL_4: |
715 | case RT5665_MONO_AMP_CALIB_CTRL_5: |
716 | case RT5665_MONO_AMP_CALIB_CTRL_6: |
717 | case RT5665_MONO_AMP_CALIB_CTRL_7: |
718 | case RT5665_MONO_AMP_CALIB_STA1: |
719 | case RT5665_MONO_AMP_CALIB_STA2: |
720 | case RT5665_MONO_AMP_CALIB_STA3: |
721 | case RT5665_MONO_AMP_CALIB_STA4: |
722 | case RT5665_MONO_AMP_CALIB_STA6: |
723 | case RT5665_HP_IMP_SENS_CTRL_01: |
724 | case RT5665_HP_IMP_SENS_CTRL_02: |
725 | case RT5665_HP_IMP_SENS_CTRL_03: |
726 | case RT5665_HP_IMP_SENS_CTRL_04: |
727 | case RT5665_HP_IMP_SENS_CTRL_05: |
728 | case RT5665_HP_IMP_SENS_CTRL_06: |
729 | case RT5665_HP_IMP_SENS_CTRL_07: |
730 | case RT5665_HP_IMP_SENS_CTRL_08: |
731 | case RT5665_HP_IMP_SENS_CTRL_09: |
732 | case RT5665_HP_IMP_SENS_CTRL_10: |
733 | case RT5665_HP_IMP_SENS_CTRL_11: |
734 | case RT5665_HP_IMP_SENS_CTRL_12: |
735 | case RT5665_HP_IMP_SENS_CTRL_13: |
736 | case RT5665_HP_IMP_SENS_CTRL_14: |
737 | case RT5665_HP_IMP_SENS_CTRL_15: |
738 | case RT5665_HP_IMP_SENS_CTRL_16: |
739 | case RT5665_HP_IMP_SENS_CTRL_17: |
740 | case RT5665_HP_IMP_SENS_CTRL_18: |
741 | case RT5665_HP_IMP_SENS_CTRL_19: |
742 | case RT5665_HP_IMP_SENS_CTRL_20: |
743 | case RT5665_HP_IMP_SENS_CTRL_21: |
744 | case RT5665_HP_IMP_SENS_CTRL_22: |
745 | case RT5665_HP_IMP_SENS_CTRL_23: |
746 | case RT5665_HP_IMP_SENS_CTRL_24: |
747 | case RT5665_HP_IMP_SENS_CTRL_25: |
748 | case RT5665_HP_IMP_SENS_CTRL_26: |
749 | case RT5665_HP_IMP_SENS_CTRL_27: |
750 | case RT5665_HP_IMP_SENS_CTRL_28: |
751 | case RT5665_HP_IMP_SENS_CTRL_29: |
752 | case RT5665_HP_IMP_SENS_CTRL_30: |
753 | case RT5665_HP_IMP_SENS_CTRL_31: |
754 | case RT5665_HP_IMP_SENS_CTRL_32: |
755 | case RT5665_HP_IMP_SENS_CTRL_33: |
756 | case RT5665_HP_IMP_SENS_CTRL_34: |
757 | case RT5665_HP_LOGIC_CTRL_1: |
758 | case RT5665_HP_LOGIC_CTRL_2: |
759 | case RT5665_HP_LOGIC_CTRL_3: |
760 | case RT5665_HP_CALIB_CTRL_1: |
761 | case RT5665_HP_CALIB_CTRL_2: |
762 | case RT5665_HP_CALIB_CTRL_3: |
763 | case RT5665_HP_CALIB_CTRL_4: |
764 | case RT5665_HP_CALIB_CTRL_5: |
765 | case RT5665_HP_CALIB_CTRL_6: |
766 | case RT5665_HP_CALIB_CTRL_7: |
767 | case RT5665_HP_CALIB_CTRL_9: |
768 | case RT5665_HP_CALIB_CTRL_10: |
769 | case RT5665_HP_CALIB_CTRL_11: |
770 | case RT5665_HP_CALIB_STA_1: |
771 | case RT5665_HP_CALIB_STA_2: |
772 | case RT5665_HP_CALIB_STA_3: |
773 | case RT5665_HP_CALIB_STA_4: |
774 | case RT5665_HP_CALIB_STA_5: |
775 | case RT5665_HP_CALIB_STA_6: |
776 | case RT5665_HP_CALIB_STA_7: |
777 | case RT5665_HP_CALIB_STA_8: |
778 | case RT5665_HP_CALIB_STA_9: |
779 | case RT5665_HP_CALIB_STA_10: |
780 | case RT5665_HP_CALIB_STA_11: |
781 | case RT5665_PGM_TAB_CTRL1: |
782 | case RT5665_PGM_TAB_CTRL2: |
783 | case RT5665_PGM_TAB_CTRL3: |
784 | case RT5665_PGM_TAB_CTRL4: |
785 | case RT5665_PGM_TAB_CTRL5: |
786 | case RT5665_PGM_TAB_CTRL6: |
787 | case RT5665_PGM_TAB_CTRL7: |
788 | case RT5665_PGM_TAB_CTRL8: |
789 | case RT5665_PGM_TAB_CTRL9: |
790 | case RT5665_SAR_IL_CMD_1: |
791 | case RT5665_SAR_IL_CMD_2: |
792 | case RT5665_SAR_IL_CMD_3: |
793 | case RT5665_SAR_IL_CMD_4: |
794 | case RT5665_SAR_IL_CMD_5: |
795 | case RT5665_SAR_IL_CMD_6: |
796 | case RT5665_SAR_IL_CMD_7: |
797 | case RT5665_SAR_IL_CMD_8: |
798 | case RT5665_SAR_IL_CMD_9: |
799 | case RT5665_SAR_IL_CMD_10: |
800 | case RT5665_SAR_IL_CMD_11: |
801 | case RT5665_SAR_IL_CMD_12: |
802 | case RT5665_DRC1_CTRL_0: |
803 | case RT5665_DRC1_CTRL_1: |
804 | case RT5665_DRC1_CTRL_2: |
805 | case RT5665_DRC1_CTRL_3: |
806 | case RT5665_DRC1_CTRL_4: |
807 | case RT5665_DRC1_CTRL_5: |
808 | case RT5665_DRC1_CTRL_6: |
809 | case RT5665_DRC1_HARD_LMT_CTRL_1: |
810 | case RT5665_DRC1_HARD_LMT_CTRL_2: |
811 | case RT5665_DRC1_PRIV_1: |
812 | case RT5665_DRC1_PRIV_2: |
813 | case RT5665_DRC1_PRIV_3: |
814 | case RT5665_DRC1_PRIV_4: |
815 | case RT5665_DRC1_PRIV_5: |
816 | case RT5665_DRC1_PRIV_6: |
817 | case RT5665_DRC1_PRIV_7: |
818 | case RT5665_DRC1_PRIV_8: |
819 | case RT5665_ALC_PGA_CTRL_1: |
820 | case RT5665_ALC_PGA_CTRL_2: |
821 | case RT5665_ALC_PGA_CTRL_3: |
822 | case RT5665_ALC_PGA_CTRL_4: |
823 | case RT5665_ALC_PGA_CTRL_5: |
824 | case RT5665_ALC_PGA_CTRL_6: |
825 | case RT5665_ALC_PGA_CTRL_7: |
826 | case RT5665_ALC_PGA_CTRL_8: |
827 | case RT5665_ALC_PGA_STA_1: |
828 | case RT5665_ALC_PGA_STA_2: |
829 | case RT5665_ALC_PGA_STA_3: |
830 | case RT5665_EQ_AUTO_RCV_CTRL1: |
831 | case RT5665_EQ_AUTO_RCV_CTRL2: |
832 | case RT5665_EQ_AUTO_RCV_CTRL3: |
833 | case RT5665_EQ_AUTO_RCV_CTRL4: |
834 | case RT5665_EQ_AUTO_RCV_CTRL5: |
835 | case RT5665_EQ_AUTO_RCV_CTRL6: |
836 | case RT5665_EQ_AUTO_RCV_CTRL7: |
837 | case RT5665_EQ_AUTO_RCV_CTRL8: |
838 | case RT5665_EQ_AUTO_RCV_CTRL9: |
839 | case RT5665_EQ_AUTO_RCV_CTRL10: |
840 | case RT5665_EQ_AUTO_RCV_CTRL11: |
841 | case RT5665_EQ_AUTO_RCV_CTRL12: |
842 | case RT5665_EQ_AUTO_RCV_CTRL13: |
843 | case RT5665_ADC_L_EQ_LPF1_A1: |
844 | case RT5665_R_EQ_LPF1_A1: |
845 | case RT5665_L_EQ_LPF1_H0: |
846 | case RT5665_R_EQ_LPF1_H0: |
847 | case RT5665_L_EQ_BPF1_A1: |
848 | case RT5665_R_EQ_BPF1_A1: |
849 | case RT5665_L_EQ_BPF1_A2: |
850 | case RT5665_R_EQ_BPF1_A2: |
851 | case RT5665_L_EQ_BPF1_H0: |
852 | case RT5665_R_EQ_BPF1_H0: |
853 | case RT5665_L_EQ_BPF2_A1: |
854 | case RT5665_R_EQ_BPF2_A1: |
855 | case RT5665_L_EQ_BPF2_A2: |
856 | case RT5665_R_EQ_BPF2_A2: |
857 | case RT5665_L_EQ_BPF2_H0: |
858 | case RT5665_R_EQ_BPF2_H0: |
859 | case RT5665_L_EQ_BPF3_A1: |
860 | case RT5665_R_EQ_BPF3_A1: |
861 | case RT5665_L_EQ_BPF3_A2: |
862 | case RT5665_R_EQ_BPF3_A2: |
863 | case RT5665_L_EQ_BPF3_H0: |
864 | case RT5665_R_EQ_BPF3_H0: |
865 | case RT5665_L_EQ_BPF4_A1: |
866 | case RT5665_R_EQ_BPF4_A1: |
867 | case RT5665_L_EQ_BPF4_A2: |
868 | case RT5665_R_EQ_BPF4_A2: |
869 | case RT5665_L_EQ_BPF4_H0: |
870 | case RT5665_R_EQ_BPF4_H0: |
871 | case RT5665_L_EQ_HPF1_A1: |
872 | case RT5665_R_EQ_HPF1_A1: |
873 | case RT5665_L_EQ_HPF1_H0: |
874 | case RT5665_R_EQ_HPF1_H0: |
875 | case RT5665_L_EQ_PRE_VOL: |
876 | case RT5665_R_EQ_PRE_VOL: |
877 | case RT5665_L_EQ_POST_VOL: |
878 | case RT5665_R_EQ_POST_VOL: |
879 | case RT5665_SCAN_MODE_CTRL: |
880 | case RT5665_I2C_MODE: |
881 | return true; |
882 | default: |
883 | return false; |
884 | } |
885 | } |
886 | |
887 | static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0); |
888 | static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0); |
889 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); |
890 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); |
891 | static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); |
892 | static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); |
893 | static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); |
894 | static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0); |
895 | |
896 | /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ |
897 | static const DECLARE_TLV_DB_RANGE(bst_tlv, |
898 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
899 | 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), |
900 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), |
901 | 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), |
902 | 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), |
903 | 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), |
904 | 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) |
905 | ); |
906 | |
907 | /* Interface data select */ |
908 | static const char * const rt5665_data_select[] = { |
909 | "L/R" , "R/L" , "L/L" , "R/R" |
910 | }; |
911 | |
912 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum, |
913 | RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select); |
914 | |
915 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum, |
916 | RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select); |
917 | |
918 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum, |
919 | RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select); |
920 | |
921 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum, |
922 | RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select); |
923 | |
924 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum, |
925 | RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select); |
926 | |
927 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum, |
928 | RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select); |
929 | |
930 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum, |
931 | RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select); |
932 | |
933 | static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum, |
934 | RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select); |
935 | |
936 | static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum, |
937 | RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select); |
938 | |
939 | static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum, |
940 | RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select); |
941 | |
942 | static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum, |
943 | RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select); |
944 | |
945 | static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum, |
946 | RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select); |
947 | |
948 | static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum, |
949 | RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select); |
950 | |
951 | static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum, |
952 | RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select); |
953 | |
954 | static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux = |
955 | SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux" , rt5665_if1_1_01_adc_enum); |
956 | |
957 | static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux = |
958 | SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux" , rt5665_if1_1_23_adc_enum); |
959 | |
960 | static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux = |
961 | SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux" , rt5665_if1_1_45_adc_enum); |
962 | |
963 | static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux = |
964 | SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux" , rt5665_if1_1_67_adc_enum); |
965 | |
966 | static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux = |
967 | SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux" , rt5665_if1_2_01_adc_enum); |
968 | |
969 | static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux = |
970 | SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux" , rt5665_if1_2_23_adc_enum); |
971 | |
972 | static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux = |
973 | SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux" , rt5665_if1_2_45_adc_enum); |
974 | |
975 | static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux = |
976 | SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux" , rt5665_if1_2_67_adc_enum); |
977 | |
978 | static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux = |
979 | SOC_DAPM_ENUM("IF2_1 DAC Swap Source" , rt5665_if2_1_dac_enum); |
980 | |
981 | static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux = |
982 | SOC_DAPM_ENUM("IF2_1 ADC Swap Source" , rt5665_if2_1_adc_enum); |
983 | |
984 | static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux = |
985 | SOC_DAPM_ENUM("IF2_2 DAC Swap Source" , rt5665_if2_2_dac_enum); |
986 | |
987 | static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux = |
988 | SOC_DAPM_ENUM("IF2_2 ADC Swap Source" , rt5665_if2_2_adc_enum); |
989 | |
990 | static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux = |
991 | SOC_DAPM_ENUM("IF3 DAC Swap Source" , rt5665_if3_dac_enum); |
992 | |
993 | static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux = |
994 | SOC_DAPM_ENUM("IF3 ADC Swap Source" , rt5665_if3_adc_enum); |
995 | |
996 | static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol, |
997 | struct snd_ctl_elem_value *ucontrol) |
998 | { |
999 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
1000 | int ret = snd_soc_put_volsw(kcontrol, ucontrol); |
1001 | |
1002 | if (snd_soc_component_read(component, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) { |
1003 | snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, |
1004 | RT5665_NG2_EN_MASK, RT5665_NG2_DIS); |
1005 | snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, |
1006 | RT5665_NG2_EN_MASK, RT5665_NG2_EN); |
1007 | } |
1008 | |
1009 | return ret; |
1010 | } |
1011 | |
1012 | static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol, |
1013 | struct snd_ctl_elem_value *ucontrol) |
1014 | { |
1015 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
1016 | int ret = snd_soc_put_volsw(kcontrol, ucontrol); |
1017 | |
1018 | if (snd_soc_component_read(component, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) { |
1019 | snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, |
1020 | RT5665_NG2_EN_MASK, RT5665_NG2_DIS); |
1021 | snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, |
1022 | RT5665_NG2_EN_MASK, RT5665_NG2_EN); |
1023 | } |
1024 | |
1025 | return ret; |
1026 | } |
1027 | |
1028 | /** |
1029 | * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters |
1030 | * @component: SoC audio component device. |
1031 | * @filter_mask: mask of filters. |
1032 | * @clk_src: clock source |
1033 | * |
1034 | * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can |
1035 | * only support standard 32fs or 64fs i2s format, ASRC should be enabled to |
1036 | * support special i2s clock format such as Intel's 100fs(100 * sampling rate). |
1037 | * ASRC function will track i2s clock and generate a corresponding system clock |
1038 | * for codec. This function provides an API to select the clock source for a |
1039 | * set of filters specified by the mask. And the codec driver will turn on ASRC |
1040 | * for these filters if ASRC is selected as their clock source. |
1041 | */ |
1042 | int rt5665_sel_asrc_clk_src(struct snd_soc_component *component, |
1043 | unsigned int filter_mask, unsigned int clk_src) |
1044 | { |
1045 | unsigned int asrc2_mask = 0; |
1046 | unsigned int asrc2_value = 0; |
1047 | unsigned int asrc3_mask = 0; |
1048 | unsigned int asrc3_value = 0; |
1049 | |
1050 | switch (clk_src) { |
1051 | case RT5665_CLK_SEL_SYS: |
1052 | case RT5665_CLK_SEL_I2S1_ASRC: |
1053 | case RT5665_CLK_SEL_I2S2_ASRC: |
1054 | case RT5665_CLK_SEL_I2S3_ASRC: |
1055 | case RT5665_CLK_SEL_SYS2: |
1056 | case RT5665_CLK_SEL_SYS3: |
1057 | case RT5665_CLK_SEL_SYS4: |
1058 | break; |
1059 | |
1060 | default: |
1061 | return -EINVAL; |
1062 | } |
1063 | |
1064 | if (filter_mask & RT5665_DA_STEREO1_FILTER) { |
1065 | asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK; |
1066 | asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK) |
1067 | | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT); |
1068 | } |
1069 | |
1070 | if (filter_mask & RT5665_DA_STEREO2_FILTER) { |
1071 | asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK; |
1072 | asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK) |
1073 | | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT); |
1074 | } |
1075 | |
1076 | if (filter_mask & RT5665_DA_MONO_L_FILTER) { |
1077 | asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK; |
1078 | asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK) |
1079 | | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT); |
1080 | } |
1081 | |
1082 | if (filter_mask & RT5665_DA_MONO_R_FILTER) { |
1083 | asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK; |
1084 | asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK) |
1085 | | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT); |
1086 | } |
1087 | |
1088 | if (filter_mask & RT5665_AD_STEREO1_FILTER) { |
1089 | asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK; |
1090 | asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK) |
1091 | | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT); |
1092 | } |
1093 | |
1094 | if (filter_mask & RT5665_AD_STEREO2_FILTER) { |
1095 | asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK; |
1096 | asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK) |
1097 | | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT); |
1098 | } |
1099 | |
1100 | if (filter_mask & RT5665_AD_MONO_L_FILTER) { |
1101 | asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK; |
1102 | asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK) |
1103 | | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT); |
1104 | } |
1105 | |
1106 | if (filter_mask & RT5665_AD_MONO_R_FILTER) { |
1107 | asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK; |
1108 | asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK) |
1109 | | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT); |
1110 | } |
1111 | |
1112 | if (asrc2_mask) |
1113 | snd_soc_component_update_bits(component, RT5665_ASRC_2, |
1114 | mask: asrc2_mask, val: asrc2_value); |
1115 | |
1116 | if (asrc3_mask) |
1117 | snd_soc_component_update_bits(component, RT5665_ASRC_3, |
1118 | mask: asrc3_mask, val: asrc3_value); |
1119 | |
1120 | return 0; |
1121 | } |
1122 | EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src); |
1123 | |
1124 | static int rt5665_button_detect(struct snd_soc_component *component) |
1125 | { |
1126 | int btn_type, val; |
1127 | |
1128 | val = snd_soc_component_read(component, RT5665_4BTN_IL_CMD_1); |
1129 | btn_type = val & 0xfff0; |
1130 | snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val); |
1131 | |
1132 | return btn_type; |
1133 | } |
1134 | |
1135 | static void rt5665_enable_push_button_irq(struct snd_soc_component *component, |
1136 | bool enable) |
1137 | { |
1138 | if (enable) { |
1139 | snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val: 0x0003); |
1140 | snd_soc_component_update_bits(component, RT5665_SAR_IL_CMD_9, mask: 0x1, val: 0x1); |
1141 | snd_soc_component_write(component, RT5665_IL_CMD_1, val: 0x0048); |
1142 | snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2, |
1143 | RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK, |
1144 | RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR); |
1145 | snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3, |
1146 | RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN); |
1147 | } else { |
1148 | snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3, |
1149 | RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS); |
1150 | snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2, |
1151 | RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS); |
1152 | snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2, |
1153 | RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST); |
1154 | } |
1155 | } |
1156 | |
1157 | /** |
1158 | * rt5665_headset_detect - Detect headset. |
1159 | * @component: SoC audio component device. |
1160 | * @jack_insert: Jack insert or not. |
1161 | * |
1162 | * Detect whether is headset or not when jack inserted. |
1163 | * |
1164 | * Returns detect status. |
1165 | */ |
1166 | static int rt5665_headset_detect(struct snd_soc_component *component, int jack_insert) |
1167 | { |
1168 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
1169 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
1170 | unsigned int sar_hs_type, val; |
1171 | |
1172 | if (jack_insert) { |
1173 | snd_soc_dapm_force_enable_pin(dapm, pin: "MICBIAS1" ); |
1174 | snd_soc_dapm_sync(dapm); |
1175 | |
1176 | regmap_update_bits(map: rt5665->regmap, RT5665_MICBIAS_2, mask: 0x100, |
1177 | val: 0x100); |
1178 | |
1179 | regmap_read(map: rt5665->regmap, RT5665_GPIO_STA, val: &val); |
1180 | if (val & 0x4) { |
1181 | regmap_update_bits(map: rt5665->regmap, RT5665_EJD_CTRL_1, |
1182 | mask: 0x100, val: 0); |
1183 | |
1184 | regmap_read(map: rt5665->regmap, RT5665_GPIO_STA, val: &val); |
1185 | while (val & 0x4) { |
1186 | usleep_range(min: 10000, max: 15000); |
1187 | regmap_read(map: rt5665->regmap, RT5665_GPIO_STA, |
1188 | val: &val); |
1189 | } |
1190 | } |
1191 | |
1192 | regmap_update_bits(map: rt5665->regmap, RT5665_EJD_CTRL_1, |
1193 | mask: 0x1a0, val: 0x120); |
1194 | regmap_write(map: rt5665->regmap, RT5665_EJD_CTRL_3, val: 0x3424); |
1195 | regmap_write(map: rt5665->regmap, RT5665_IL_CMD_1, val: 0x0048); |
1196 | regmap_write(map: rt5665->regmap, RT5665_SAR_IL_CMD_1, val: 0xa291); |
1197 | |
1198 | usleep_range(min: 10000, max: 15000); |
1199 | |
1200 | rt5665->sar_adc_value = snd_soc_component_read(component: rt5665->component, |
1201 | RT5665_SAR_IL_CMD_4) & 0x7ff; |
1202 | |
1203 | sar_hs_type = rt5665->pdata.sar_hs_type ? |
1204 | rt5665->pdata.sar_hs_type : 729; |
1205 | |
1206 | if (rt5665->sar_adc_value > sar_hs_type) { |
1207 | rt5665->jack_type = SND_JACK_HEADSET; |
1208 | rt5665_enable_push_button_irq(component, enable: true); |
1209 | } else { |
1210 | rt5665->jack_type = SND_JACK_HEADPHONE; |
1211 | regmap_write(map: rt5665->regmap, RT5665_SAR_IL_CMD_1, |
1212 | val: 0x2291); |
1213 | regmap_update_bits(map: rt5665->regmap, RT5665_MICBIAS_2, |
1214 | mask: 0x100, val: 0); |
1215 | snd_soc_dapm_disable_pin(dapm, pin: "MICBIAS1" ); |
1216 | snd_soc_dapm_sync(dapm); |
1217 | } |
1218 | } else { |
1219 | regmap_write(map: rt5665->regmap, RT5665_SAR_IL_CMD_1, val: 0x2291); |
1220 | regmap_update_bits(map: rt5665->regmap, RT5665_MICBIAS_2, mask: 0x100, val: 0); |
1221 | snd_soc_dapm_disable_pin(dapm, pin: "MICBIAS1" ); |
1222 | snd_soc_dapm_sync(dapm); |
1223 | if (rt5665->jack_type == SND_JACK_HEADSET) |
1224 | rt5665_enable_push_button_irq(component, enable: false); |
1225 | rt5665->jack_type = 0; |
1226 | } |
1227 | |
1228 | dev_dbg(component->dev, "jack_type = %d\n" , rt5665->jack_type); |
1229 | return rt5665->jack_type; |
1230 | } |
1231 | |
1232 | static irqreturn_t rt5665_irq(int irq, void *data) |
1233 | { |
1234 | struct rt5665_priv *rt5665 = data; |
1235 | |
1236 | mod_delayed_work(wq: system_power_efficient_wq, |
1237 | dwork: &rt5665->jack_detect_work, delay: msecs_to_jiffies(m: 250)); |
1238 | |
1239 | return IRQ_HANDLED; |
1240 | } |
1241 | |
1242 | static void rt5665_jd_check_handler(struct work_struct *work) |
1243 | { |
1244 | struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv, |
1245 | jd_check_work.work); |
1246 | |
1247 | if (snd_soc_component_read(component: rt5665->component, RT5665_AJD1_CTRL) & 0x0010) { |
1248 | /* jack out */ |
1249 | rt5665->jack_type = rt5665_headset_detect(component: rt5665->component, jack_insert: 0); |
1250 | |
1251 | snd_soc_jack_report(jack: rt5665->hs_jack, status: rt5665->jack_type, |
1252 | mask: SND_JACK_HEADSET | |
1253 | SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1254 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
1255 | } else { |
1256 | schedule_delayed_work(dwork: &rt5665->jd_check_work, delay: 500); |
1257 | } |
1258 | } |
1259 | |
1260 | static int rt5665_set_jack_detect(struct snd_soc_component *component, |
1261 | struct snd_soc_jack *hs_jack, void *data) |
1262 | { |
1263 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
1264 | |
1265 | switch (rt5665->pdata.jd_src) { |
1266 | case RT5665_JD1: |
1267 | regmap_update_bits(map: rt5665->regmap, RT5665_GPIO_CTRL_1, |
1268 | RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ); |
1269 | regmap_update_bits(map: rt5665->regmap, RT5665_RC_CLK_CTRL, |
1270 | mask: 0xc000, val: 0xc000); |
1271 | regmap_update_bits(map: rt5665->regmap, RT5665_PWR_ANLG_2, |
1272 | RT5665_PWR_JD1, RT5665_PWR_JD1); |
1273 | regmap_update_bits(map: rt5665->regmap, RT5665_IRQ_CTRL_1, mask: 0x8, val: 0x8); |
1274 | break; |
1275 | |
1276 | case RT5665_JD_NULL: |
1277 | break; |
1278 | |
1279 | default: |
1280 | dev_warn(component->dev, "Wrong JD source\n" ); |
1281 | break; |
1282 | } |
1283 | |
1284 | rt5665->hs_jack = hs_jack; |
1285 | |
1286 | return 0; |
1287 | } |
1288 | |
1289 | static void rt5665_jack_detect_handler(struct work_struct *work) |
1290 | { |
1291 | struct rt5665_priv *rt5665 = |
1292 | container_of(work, struct rt5665_priv, jack_detect_work.work); |
1293 | int val, btn_type; |
1294 | |
1295 | while (!rt5665->component) { |
1296 | pr_debug("%s codec = null\n" , __func__); |
1297 | usleep_range(min: 10000, max: 15000); |
1298 | } |
1299 | |
1300 | while (!snd_soc_card_is_instantiated(card: rt5665->component->card)) { |
1301 | pr_debug("%s\n" , __func__); |
1302 | usleep_range(min: 10000, max: 15000); |
1303 | } |
1304 | |
1305 | while (!rt5665->calibration_done) { |
1306 | pr_debug("%s calibration not ready\n" , __func__); |
1307 | usleep_range(min: 10000, max: 15000); |
1308 | } |
1309 | |
1310 | mutex_lock(&rt5665->calibrate_mutex); |
1311 | |
1312 | val = snd_soc_component_read(component: rt5665->component, RT5665_AJD1_CTRL) & 0x0010; |
1313 | if (!val) { |
1314 | /* jack in */ |
1315 | if (rt5665->jack_type == 0) { |
1316 | /* jack was out, report jack type */ |
1317 | rt5665->jack_type = |
1318 | rt5665_headset_detect(component: rt5665->component, jack_insert: 1); |
1319 | } else { |
1320 | /* jack is already in, report button event */ |
1321 | rt5665->jack_type = SND_JACK_HEADSET; |
1322 | btn_type = rt5665_button_detect(component: rt5665->component); |
1323 | /** |
1324 | * rt5665 can report three kinds of button behavior, |
1325 | * one click, double click and hold. However, |
1326 | * currently we will report button pressed/released |
1327 | * event. So all the three button behaviors are |
1328 | * treated as button pressed. |
1329 | */ |
1330 | switch (btn_type) { |
1331 | case 0x8000: |
1332 | case 0x4000: |
1333 | case 0x2000: |
1334 | rt5665->jack_type |= SND_JACK_BTN_0; |
1335 | break; |
1336 | case 0x1000: |
1337 | case 0x0800: |
1338 | case 0x0400: |
1339 | rt5665->jack_type |= SND_JACK_BTN_1; |
1340 | break; |
1341 | case 0x0200: |
1342 | case 0x0100: |
1343 | case 0x0080: |
1344 | rt5665->jack_type |= SND_JACK_BTN_2; |
1345 | break; |
1346 | case 0x0040: |
1347 | case 0x0020: |
1348 | case 0x0010: |
1349 | rt5665->jack_type |= SND_JACK_BTN_3; |
1350 | break; |
1351 | case 0x0000: /* unpressed */ |
1352 | break; |
1353 | default: |
1354 | btn_type = 0; |
1355 | dev_err(rt5665->component->dev, |
1356 | "Unexpected button code 0x%04x\n" , |
1357 | btn_type); |
1358 | break; |
1359 | } |
1360 | } |
1361 | } else { |
1362 | /* jack out */ |
1363 | rt5665->jack_type = rt5665_headset_detect(component: rt5665->component, jack_insert: 0); |
1364 | } |
1365 | |
1366 | snd_soc_jack_report(jack: rt5665->hs_jack, status: rt5665->jack_type, |
1367 | mask: SND_JACK_HEADSET | |
1368 | SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1369 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
1370 | |
1371 | if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1372 | SND_JACK_BTN_2 | SND_JACK_BTN_3)) |
1373 | schedule_delayed_work(dwork: &rt5665->jd_check_work, delay: 0); |
1374 | else |
1375 | cancel_delayed_work_sync(dwork: &rt5665->jd_check_work); |
1376 | |
1377 | mutex_unlock(lock: &rt5665->calibrate_mutex); |
1378 | } |
1379 | |
1380 | static const char * const rt5665_clk_sync[] = { |
1381 | "I2S1_1" , "I2S1_2" , "I2S2" , "I2S3" , "IF2 Slave" , "IF3 Slave" |
1382 | }; |
1383 | |
1384 | static const struct soc_enum rt5665_enum[] = { |
1385 | SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync), |
1386 | SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync), |
1387 | SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync), |
1388 | }; |
1389 | |
1390 | static const struct snd_kcontrol_new rt5665_snd_controls[] = { |
1391 | /* Headphone Output Volume */ |
1392 | SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume" , RT5665_HPL_GAIN, |
1393 | RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw, |
1394 | rt5665_hp_vol_put, hp_vol_tlv), |
1395 | |
1396 | /* Mono Output Volume */ |
1397 | SOC_SINGLE_EXT_TLV("Mono Playback Volume" , RT5665_MONO_GAIN, |
1398 | RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw, |
1399 | rt5665_mono_vol_put, mono_vol_tlv), |
1400 | |
1401 | SOC_SINGLE_TLV("MONOVOL Playback Volume" , RT5665_MONO_OUT, |
1402 | RT5665_L_VOL_SFT, 39, 1, out_vol_tlv), |
1403 | |
1404 | /* Output Volume */ |
1405 | SOC_DOUBLE_TLV("OUT Playback Volume" , RT5665_LOUT, RT5665_L_VOL_SFT, |
1406 | RT5665_R_VOL_SFT, 39, 1, out_vol_tlv), |
1407 | |
1408 | /* DAC Digital Volume */ |
1409 | SOC_DOUBLE_TLV("DAC1 Playback Volume" , RT5665_DAC1_DIG_VOL, |
1410 | RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv), |
1411 | SOC_DOUBLE_TLV("DAC2 Playback Volume" , RT5665_DAC2_DIG_VOL, |
1412 | RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv), |
1413 | SOC_DOUBLE("DAC2 Playback Switch" , RT5665_DAC2_CTRL, |
1414 | RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1), |
1415 | |
1416 | /* IN1/IN2/IN3/IN4 Volume */ |
1417 | SOC_SINGLE_TLV("IN1 Boost Volume" , RT5665_IN1_IN2, |
1418 | RT5665_BST1_SFT, 69, 0, in_bst_tlv), |
1419 | SOC_SINGLE_TLV("IN2 Boost Volume" , RT5665_IN1_IN2, |
1420 | RT5665_BST2_SFT, 69, 0, in_bst_tlv), |
1421 | SOC_SINGLE_TLV("IN3 Boost Volume" , RT5665_IN3_IN4, |
1422 | RT5665_BST3_SFT, 69, 0, in_bst_tlv), |
1423 | SOC_SINGLE_TLV("IN4 Boost Volume" , RT5665_IN3_IN4, |
1424 | RT5665_BST4_SFT, 69, 0, in_bst_tlv), |
1425 | SOC_SINGLE_TLV("CBJ Boost Volume" , RT5665_CBJ_BST_CTRL, |
1426 | RT5665_BST_CBJ_SFT, 8, 0, bst_tlv), |
1427 | |
1428 | /* INL/INR Volume Control */ |
1429 | SOC_DOUBLE_TLV("IN Capture Volume" , RT5665_INL1_INR1_VOL, |
1430 | RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv), |
1431 | |
1432 | /* ADC Digital Volume Control */ |
1433 | SOC_DOUBLE("STO1 ADC Capture Switch" , RT5665_STO1_ADC_DIG_VOL, |
1434 | RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1), |
1435 | SOC_DOUBLE_TLV("STO1 ADC Capture Volume" , RT5665_STO1_ADC_DIG_VOL, |
1436 | RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv), |
1437 | SOC_DOUBLE("Mono ADC Capture Switch" , RT5665_MONO_ADC_DIG_VOL, |
1438 | RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1), |
1439 | SOC_DOUBLE_TLV("Mono ADC Capture Volume" , RT5665_MONO_ADC_DIG_VOL, |
1440 | RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv), |
1441 | SOC_DOUBLE("STO2 ADC Capture Switch" , RT5665_STO2_ADC_DIG_VOL, |
1442 | RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1), |
1443 | SOC_DOUBLE_TLV("STO2 ADC Capture Volume" , RT5665_STO2_ADC_DIG_VOL, |
1444 | RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv), |
1445 | |
1446 | /* ADC Boost Volume Control */ |
1447 | SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume" , RT5665_STO1_ADC_BOOST, |
1448 | RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT, |
1449 | 3, 0, adc_bst_tlv), |
1450 | |
1451 | SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume" , RT5665_MONO_ADC_BOOST, |
1452 | RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT, |
1453 | 3, 0, adc_bst_tlv), |
1454 | |
1455 | SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume" , RT5665_STO2_ADC_BOOST, |
1456 | RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT, |
1457 | 3, 0, adc_bst_tlv), |
1458 | |
1459 | /* I2S3 CLK Source */ |
1460 | SOC_ENUM("I2S1 Master Clk Sel" , rt5665_enum[0]), |
1461 | SOC_ENUM("I2S2 Master Clk Sel" , rt5665_enum[1]), |
1462 | SOC_ENUM("I2S3 Master Clk Sel" , rt5665_enum[2]), |
1463 | }; |
1464 | |
1465 | /** |
1466 | * set_dmic_clk - Set parameter of dmic. |
1467 | * |
1468 | * @w: DAPM widget. |
1469 | * @kcontrol: The kcontrol of this widget. |
1470 | * @event: Event id. |
1471 | * |
1472 | * Choose dmic clock between 1MHz and 3MHz. |
1473 | * It is better for clock to approximate 3MHz. |
1474 | */ |
1475 | static int set_dmic_clk(struct snd_soc_dapm_widget *w, |
1476 | struct snd_kcontrol *kcontrol, int event) |
1477 | { |
1478 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1479 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
1480 | int pd, idx; |
1481 | |
1482 | pd = rl6231_get_pre_div(map: rt5665->regmap, |
1483 | RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT); |
1484 | idx = rl6231_calc_dmic_clk(rate: rt5665->sysclk / pd); |
1485 | |
1486 | if (idx < 0) |
1487 | dev_err(component->dev, "Failed to set DMIC clock\n" ); |
1488 | else { |
1489 | snd_soc_component_update_bits(component, RT5665_DMIC_CTRL_1, |
1490 | RT5665_DMIC_CLK_MASK, val: idx << RT5665_DMIC_CLK_SFT); |
1491 | } |
1492 | return idx; |
1493 | } |
1494 | |
1495 | static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w, |
1496 | struct snd_kcontrol *kcontrol, int event) |
1497 | { |
1498 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1499 | |
1500 | switch (event) { |
1501 | case SND_SOC_DAPM_PRE_PMU: |
1502 | snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1, |
1503 | RT5665_PM_HP_MASK | RT5665_OSW_L_MASK, |
1504 | RT5665_PM_HP_HV | RT5665_OSW_L_EN); |
1505 | break; |
1506 | case SND_SOC_DAPM_POST_PMD: |
1507 | snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1, |
1508 | RT5665_PM_HP_MASK | RT5665_OSW_L_MASK, |
1509 | RT5665_PM_HP_LV | RT5665_OSW_L_DIS); |
1510 | break; |
1511 | default: |
1512 | return 0; |
1513 | } |
1514 | |
1515 | return 0; |
1516 | } |
1517 | |
1518 | static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, |
1519 | struct snd_soc_dapm_widget *sink) |
1520 | { |
1521 | unsigned int val; |
1522 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1523 | |
1524 | val = snd_soc_component_read(component, RT5665_GLB_CLK); |
1525 | val &= RT5665_SCLK_SRC_MASK; |
1526 | if (val == RT5665_SCLK_SRC_PLL1) |
1527 | return 1; |
1528 | else |
1529 | return 0; |
1530 | } |
1531 | |
1532 | static int is_using_asrc(struct snd_soc_dapm_widget *w, |
1533 | struct snd_soc_dapm_widget *sink) |
1534 | { |
1535 | unsigned int reg, shift, val; |
1536 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1537 | |
1538 | switch (w->shift) { |
1539 | case RT5665_ADC_MONO_R_ASRC_SFT: |
1540 | reg = RT5665_ASRC_3; |
1541 | shift = RT5665_AD_MONOR_CLK_SEL_SFT; |
1542 | break; |
1543 | case RT5665_ADC_MONO_L_ASRC_SFT: |
1544 | reg = RT5665_ASRC_3; |
1545 | shift = RT5665_AD_MONOL_CLK_SEL_SFT; |
1546 | break; |
1547 | case RT5665_ADC_STO1_ASRC_SFT: |
1548 | reg = RT5665_ASRC_3; |
1549 | shift = RT5665_AD_STO1_CLK_SEL_SFT; |
1550 | break; |
1551 | case RT5665_ADC_STO2_ASRC_SFT: |
1552 | reg = RT5665_ASRC_3; |
1553 | shift = RT5665_AD_STO2_CLK_SEL_SFT; |
1554 | break; |
1555 | case RT5665_DAC_MONO_R_ASRC_SFT: |
1556 | reg = RT5665_ASRC_2; |
1557 | shift = RT5665_DA_MONOR_CLK_SEL_SFT; |
1558 | break; |
1559 | case RT5665_DAC_MONO_L_ASRC_SFT: |
1560 | reg = RT5665_ASRC_2; |
1561 | shift = RT5665_DA_MONOL_CLK_SEL_SFT; |
1562 | break; |
1563 | case RT5665_DAC_STO1_ASRC_SFT: |
1564 | reg = RT5665_ASRC_2; |
1565 | shift = RT5665_DA_STO1_CLK_SEL_SFT; |
1566 | break; |
1567 | case RT5665_DAC_STO2_ASRC_SFT: |
1568 | reg = RT5665_ASRC_2; |
1569 | shift = RT5665_DA_STO2_CLK_SEL_SFT; |
1570 | break; |
1571 | default: |
1572 | return 0; |
1573 | } |
1574 | |
1575 | val = (snd_soc_component_read(component, reg) >> shift) & 0xf; |
1576 | switch (val) { |
1577 | case RT5665_CLK_SEL_I2S1_ASRC: |
1578 | case RT5665_CLK_SEL_I2S2_ASRC: |
1579 | case RT5665_CLK_SEL_I2S3_ASRC: |
1580 | /* I2S_Pre_Div1 should be 1 in asrc mode */ |
1581 | snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, |
1582 | RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2); |
1583 | return 1; |
1584 | default: |
1585 | return 0; |
1586 | } |
1587 | |
1588 | } |
1589 | |
1590 | /* Digital Mixer */ |
1591 | static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = { |
1592 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5665_STO1_ADC_MIXER, |
1593 | RT5665_M_STO1_ADC_L1_SFT, 1, 1), |
1594 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5665_STO1_ADC_MIXER, |
1595 | RT5665_M_STO1_ADC_L2_SFT, 1, 1), |
1596 | }; |
1597 | |
1598 | static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = { |
1599 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5665_STO1_ADC_MIXER, |
1600 | RT5665_M_STO1_ADC_R1_SFT, 1, 1), |
1601 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5665_STO1_ADC_MIXER, |
1602 | RT5665_M_STO1_ADC_R2_SFT, 1, 1), |
1603 | }; |
1604 | |
1605 | static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = { |
1606 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5665_STO2_ADC_MIXER, |
1607 | RT5665_M_STO2_ADC_L1_SFT, 1, 1), |
1608 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5665_STO2_ADC_MIXER, |
1609 | RT5665_M_STO2_ADC_L2_SFT, 1, 1), |
1610 | }; |
1611 | |
1612 | static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = { |
1613 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5665_STO2_ADC_MIXER, |
1614 | RT5665_M_STO2_ADC_R1_SFT, 1, 1), |
1615 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5665_STO2_ADC_MIXER, |
1616 | RT5665_M_STO2_ADC_R2_SFT, 1, 1), |
1617 | }; |
1618 | |
1619 | static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = { |
1620 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5665_MONO_ADC_MIXER, |
1621 | RT5665_M_MONO_ADC_L1_SFT, 1, 1), |
1622 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5665_MONO_ADC_MIXER, |
1623 | RT5665_M_MONO_ADC_L2_SFT, 1, 1), |
1624 | }; |
1625 | |
1626 | static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = { |
1627 | SOC_DAPM_SINGLE("ADC1 Switch" , RT5665_MONO_ADC_MIXER, |
1628 | RT5665_M_MONO_ADC_R1_SFT, 1, 1), |
1629 | SOC_DAPM_SINGLE("ADC2 Switch" , RT5665_MONO_ADC_MIXER, |
1630 | RT5665_M_MONO_ADC_R2_SFT, 1, 1), |
1631 | }; |
1632 | |
1633 | static const struct snd_kcontrol_new rt5665_dac_l_mix[] = { |
1634 | SOC_DAPM_SINGLE("Stereo ADC Switch" , RT5665_AD_DA_MIXER, |
1635 | RT5665_M_ADCMIX_L_SFT, 1, 1), |
1636 | SOC_DAPM_SINGLE("DAC1 Switch" , RT5665_AD_DA_MIXER, |
1637 | RT5665_M_DAC1_L_SFT, 1, 1), |
1638 | }; |
1639 | |
1640 | static const struct snd_kcontrol_new rt5665_dac_r_mix[] = { |
1641 | SOC_DAPM_SINGLE("Stereo ADC Switch" , RT5665_AD_DA_MIXER, |
1642 | RT5665_M_ADCMIX_R_SFT, 1, 1), |
1643 | SOC_DAPM_SINGLE("DAC1 Switch" , RT5665_AD_DA_MIXER, |
1644 | RT5665_M_DAC1_R_SFT, 1, 1), |
1645 | }; |
1646 | |
1647 | static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = { |
1648 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5665_STO1_DAC_MIXER, |
1649 | RT5665_M_DAC_L1_STO_L_SFT, 1, 1), |
1650 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5665_STO1_DAC_MIXER, |
1651 | RT5665_M_DAC_R1_STO_L_SFT, 1, 1), |
1652 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_STO1_DAC_MIXER, |
1653 | RT5665_M_DAC_L2_STO_L_SFT, 1, 1), |
1654 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5665_STO1_DAC_MIXER, |
1655 | RT5665_M_DAC_R2_STO_L_SFT, 1, 1), |
1656 | }; |
1657 | |
1658 | static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = { |
1659 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5665_STO1_DAC_MIXER, |
1660 | RT5665_M_DAC_L1_STO_R_SFT, 1, 1), |
1661 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5665_STO1_DAC_MIXER, |
1662 | RT5665_M_DAC_R1_STO_R_SFT, 1, 1), |
1663 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_STO1_DAC_MIXER, |
1664 | RT5665_M_DAC_L2_STO_R_SFT, 1, 1), |
1665 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5665_STO1_DAC_MIXER, |
1666 | RT5665_M_DAC_R2_STO_R_SFT, 1, 1), |
1667 | }; |
1668 | |
1669 | static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = { |
1670 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5665_STO2_DAC_MIXER, |
1671 | RT5665_M_DAC_L1_STO2_L_SFT, 1, 1), |
1672 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_STO2_DAC_MIXER, |
1673 | RT5665_M_DAC_L2_STO2_L_SFT, 1, 1), |
1674 | SOC_DAPM_SINGLE("DAC L3 Switch" , RT5665_STO2_DAC_MIXER, |
1675 | RT5665_M_DAC_L3_STO2_L_SFT, 1, 1), |
1676 | }; |
1677 | |
1678 | static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = { |
1679 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5665_STO2_DAC_MIXER, |
1680 | RT5665_M_DAC_R1_STO2_R_SFT, 1, 1), |
1681 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5665_STO2_DAC_MIXER, |
1682 | RT5665_M_DAC_R2_STO2_R_SFT, 1, 1), |
1683 | SOC_DAPM_SINGLE("DAC R3 Switch" , RT5665_STO2_DAC_MIXER, |
1684 | RT5665_M_DAC_R3_STO2_R_SFT, 1, 1), |
1685 | }; |
1686 | |
1687 | static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = { |
1688 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5665_MONO_DAC_MIXER, |
1689 | RT5665_M_DAC_L1_MONO_L_SFT, 1, 1), |
1690 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5665_MONO_DAC_MIXER, |
1691 | RT5665_M_DAC_R1_MONO_L_SFT, 1, 1), |
1692 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_MONO_DAC_MIXER, |
1693 | RT5665_M_DAC_L2_MONO_L_SFT, 1, 1), |
1694 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5665_MONO_DAC_MIXER, |
1695 | RT5665_M_DAC_R2_MONO_L_SFT, 1, 1), |
1696 | }; |
1697 | |
1698 | static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = { |
1699 | SOC_DAPM_SINGLE("DAC L1 Switch" , RT5665_MONO_DAC_MIXER, |
1700 | RT5665_M_DAC_L1_MONO_R_SFT, 1, 1), |
1701 | SOC_DAPM_SINGLE("DAC R1 Switch" , RT5665_MONO_DAC_MIXER, |
1702 | RT5665_M_DAC_R1_MONO_R_SFT, 1, 1), |
1703 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_MONO_DAC_MIXER, |
1704 | RT5665_M_DAC_L2_MONO_R_SFT, 1, 1), |
1705 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5665_MONO_DAC_MIXER, |
1706 | RT5665_M_DAC_R2_MONO_R_SFT, 1, 1), |
1707 | }; |
1708 | |
1709 | /* Analog Input Mixer */ |
1710 | static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = { |
1711 | SOC_DAPM_SINGLE("CBJ Switch" , RT5665_REC1_L2_MIXER, |
1712 | RT5665_M_CBJ_RM1_L_SFT, 1, 1), |
1713 | SOC_DAPM_SINGLE("INL Switch" , RT5665_REC1_L2_MIXER, |
1714 | RT5665_M_INL_RM1_L_SFT, 1, 1), |
1715 | SOC_DAPM_SINGLE("INR Switch" , RT5665_REC1_L2_MIXER, |
1716 | RT5665_M_INR_RM1_L_SFT, 1, 1), |
1717 | SOC_DAPM_SINGLE("BST4 Switch" , RT5665_REC1_L2_MIXER, |
1718 | RT5665_M_BST4_RM1_L_SFT, 1, 1), |
1719 | SOC_DAPM_SINGLE("BST3 Switch" , RT5665_REC1_L2_MIXER, |
1720 | RT5665_M_BST3_RM1_L_SFT, 1, 1), |
1721 | SOC_DAPM_SINGLE("BST2 Switch" , RT5665_REC1_L2_MIXER, |
1722 | RT5665_M_BST2_RM1_L_SFT, 1, 1), |
1723 | SOC_DAPM_SINGLE("BST1 Switch" , RT5665_REC1_L2_MIXER, |
1724 | RT5665_M_BST1_RM1_L_SFT, 1, 1), |
1725 | }; |
1726 | |
1727 | static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = { |
1728 | SOC_DAPM_SINGLE("MONOVOL Switch" , RT5665_REC1_R2_MIXER, |
1729 | RT5665_M_AEC_REF_RM1_R_SFT, 1, 1), |
1730 | SOC_DAPM_SINGLE("INR Switch" , RT5665_REC1_R2_MIXER, |
1731 | RT5665_M_INR_RM1_R_SFT, 1, 1), |
1732 | SOC_DAPM_SINGLE("BST4 Switch" , RT5665_REC1_R2_MIXER, |
1733 | RT5665_M_BST4_RM1_R_SFT, 1, 1), |
1734 | SOC_DAPM_SINGLE("BST3 Switch" , RT5665_REC1_R2_MIXER, |
1735 | RT5665_M_BST3_RM1_R_SFT, 1, 1), |
1736 | SOC_DAPM_SINGLE("BST2 Switch" , RT5665_REC1_R2_MIXER, |
1737 | RT5665_M_BST2_RM1_R_SFT, 1, 1), |
1738 | SOC_DAPM_SINGLE("BST1 Switch" , RT5665_REC1_R2_MIXER, |
1739 | RT5665_M_BST1_RM1_R_SFT, 1, 1), |
1740 | }; |
1741 | |
1742 | static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = { |
1743 | SOC_DAPM_SINGLE("INL Switch" , RT5665_REC2_L2_MIXER, |
1744 | RT5665_M_INL_RM2_L_SFT, 1, 1), |
1745 | SOC_DAPM_SINGLE("INR Switch" , RT5665_REC2_L2_MIXER, |
1746 | RT5665_M_INR_RM2_L_SFT, 1, 1), |
1747 | SOC_DAPM_SINGLE("CBJ Switch" , RT5665_REC2_L2_MIXER, |
1748 | RT5665_M_CBJ_RM2_L_SFT, 1, 1), |
1749 | SOC_DAPM_SINGLE("BST4 Switch" , RT5665_REC2_L2_MIXER, |
1750 | RT5665_M_BST4_RM2_L_SFT, 1, 1), |
1751 | SOC_DAPM_SINGLE("BST3 Switch" , RT5665_REC2_L2_MIXER, |
1752 | RT5665_M_BST3_RM2_L_SFT, 1, 1), |
1753 | SOC_DAPM_SINGLE("BST2 Switch" , RT5665_REC2_L2_MIXER, |
1754 | RT5665_M_BST2_RM2_L_SFT, 1, 1), |
1755 | SOC_DAPM_SINGLE("BST1 Switch" , RT5665_REC2_L2_MIXER, |
1756 | RT5665_M_BST1_RM2_L_SFT, 1, 1), |
1757 | }; |
1758 | |
1759 | static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = { |
1760 | SOC_DAPM_SINGLE("MONOVOL Switch" , RT5665_REC2_R2_MIXER, |
1761 | RT5665_M_MONOVOL_RM2_R_SFT, 1, 1), |
1762 | SOC_DAPM_SINGLE("INL Switch" , RT5665_REC2_R2_MIXER, |
1763 | RT5665_M_INL_RM2_R_SFT, 1, 1), |
1764 | SOC_DAPM_SINGLE("INR Switch" , RT5665_REC2_R2_MIXER, |
1765 | RT5665_M_INR_RM2_R_SFT, 1, 1), |
1766 | SOC_DAPM_SINGLE("BST4 Switch" , RT5665_REC2_R2_MIXER, |
1767 | RT5665_M_BST4_RM2_R_SFT, 1, 1), |
1768 | SOC_DAPM_SINGLE("BST3 Switch" , RT5665_REC2_R2_MIXER, |
1769 | RT5665_M_BST3_RM2_R_SFT, 1, 1), |
1770 | SOC_DAPM_SINGLE("BST2 Switch" , RT5665_REC2_R2_MIXER, |
1771 | RT5665_M_BST2_RM2_R_SFT, 1, 1), |
1772 | SOC_DAPM_SINGLE("BST1 Switch" , RT5665_REC2_R2_MIXER, |
1773 | RT5665_M_BST1_RM2_R_SFT, 1, 1), |
1774 | }; |
1775 | |
1776 | static const struct snd_kcontrol_new rt5665_monovol_mix[] = { |
1777 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_MONOMIX_IN_GAIN, |
1778 | RT5665_M_DAC_L2_MM_SFT, 1, 1), |
1779 | SOC_DAPM_SINGLE("RECMIX2L Switch" , RT5665_MONOMIX_IN_GAIN, |
1780 | RT5665_M_RECMIC2L_MM_SFT, 1, 1), |
1781 | SOC_DAPM_SINGLE("BST1 Switch" , RT5665_MONOMIX_IN_GAIN, |
1782 | RT5665_M_BST1_MM_SFT, 1, 1), |
1783 | SOC_DAPM_SINGLE("BST2 Switch" , RT5665_MONOMIX_IN_GAIN, |
1784 | RT5665_M_BST2_MM_SFT, 1, 1), |
1785 | SOC_DAPM_SINGLE("BST3 Switch" , RT5665_MONOMIX_IN_GAIN, |
1786 | RT5665_M_BST3_MM_SFT, 1, 1), |
1787 | }; |
1788 | |
1789 | static const struct snd_kcontrol_new rt5665_out_l_mix[] = { |
1790 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_OUT_L_MIXER, |
1791 | RT5665_M_DAC_L2_OM_L_SFT, 1, 1), |
1792 | SOC_DAPM_SINGLE("INL Switch" , RT5665_OUT_L_MIXER, |
1793 | RT5665_M_IN_L_OM_L_SFT, 1, 1), |
1794 | SOC_DAPM_SINGLE("BST1 Switch" , RT5665_OUT_L_MIXER, |
1795 | RT5665_M_BST1_OM_L_SFT, 1, 1), |
1796 | SOC_DAPM_SINGLE("BST2 Switch" , RT5665_OUT_L_MIXER, |
1797 | RT5665_M_BST2_OM_L_SFT, 1, 1), |
1798 | SOC_DAPM_SINGLE("BST3 Switch" , RT5665_OUT_L_MIXER, |
1799 | RT5665_M_BST3_OM_L_SFT, 1, 1), |
1800 | }; |
1801 | |
1802 | static const struct snd_kcontrol_new rt5665_out_r_mix[] = { |
1803 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5665_OUT_R_MIXER, |
1804 | RT5665_M_DAC_R2_OM_R_SFT, 1, 1), |
1805 | SOC_DAPM_SINGLE("INR Switch" , RT5665_OUT_R_MIXER, |
1806 | RT5665_M_IN_R_OM_R_SFT, 1, 1), |
1807 | SOC_DAPM_SINGLE("BST2 Switch" , RT5665_OUT_R_MIXER, |
1808 | RT5665_M_BST2_OM_R_SFT, 1, 1), |
1809 | SOC_DAPM_SINGLE("BST3 Switch" , RT5665_OUT_R_MIXER, |
1810 | RT5665_M_BST3_OM_R_SFT, 1, 1), |
1811 | SOC_DAPM_SINGLE("BST4 Switch" , RT5665_OUT_R_MIXER, |
1812 | RT5665_M_BST4_OM_R_SFT, 1, 1), |
1813 | }; |
1814 | |
1815 | static const struct snd_kcontrol_new rt5665_mono_mix[] = { |
1816 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_MONOMIX_IN_GAIN, |
1817 | RT5665_M_DAC_L2_MA_SFT, 1, 1), |
1818 | SOC_DAPM_SINGLE("MONOVOL Switch" , RT5665_MONOMIX_IN_GAIN, |
1819 | RT5665_M_MONOVOL_MA_SFT, 1, 1), |
1820 | }; |
1821 | |
1822 | static const struct snd_kcontrol_new rt5665_lout_l_mix[] = { |
1823 | SOC_DAPM_SINGLE("DAC L2 Switch" , RT5665_LOUT_MIXER, |
1824 | RT5665_M_DAC_L2_LM_SFT, 1, 1), |
1825 | SOC_DAPM_SINGLE("OUTVOL L Switch" , RT5665_LOUT_MIXER, |
1826 | RT5665_M_OV_L_LM_SFT, 1, 1), |
1827 | }; |
1828 | |
1829 | static const struct snd_kcontrol_new rt5665_lout_r_mix[] = { |
1830 | SOC_DAPM_SINGLE("DAC R2 Switch" , RT5665_LOUT_MIXER, |
1831 | RT5665_M_DAC_R2_LM_SFT, 1, 1), |
1832 | SOC_DAPM_SINGLE("OUTVOL R Switch" , RT5665_LOUT_MIXER, |
1833 | RT5665_M_OV_R_LM_SFT, 1, 1), |
1834 | }; |
1835 | |
1836 | /*DAC L2, DAC R2*/ |
1837 | /*MX-17 [6:4], MX-17 [2:0]*/ |
1838 | static const char * const rt5665_dac2_src[] = { |
1839 | "IF1 DAC2" , "IF2_1 DAC" , "IF2_2 DAC" , "IF3 DAC" , "Mono ADC MIX" |
1840 | }; |
1841 | |
1842 | static SOC_ENUM_SINGLE_DECL( |
1843 | rt5665_dac_l2_enum, RT5665_DAC2_CTRL, |
1844 | RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src); |
1845 | |
1846 | static const struct snd_kcontrol_new rt5665_dac_l2_mux = |
1847 | SOC_DAPM_ENUM("Digital DAC L2 Source" , rt5665_dac_l2_enum); |
1848 | |
1849 | static SOC_ENUM_SINGLE_DECL( |
1850 | rt5665_dac_r2_enum, RT5665_DAC2_CTRL, |
1851 | RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src); |
1852 | |
1853 | static const struct snd_kcontrol_new rt5665_dac_r2_mux = |
1854 | SOC_DAPM_ENUM("Digital DAC R2 Source" , rt5665_dac_r2_enum); |
1855 | |
1856 | /*DAC L3, DAC R3*/ |
1857 | /*MX-1B [6:4], MX-1B [2:0]*/ |
1858 | static const char * const rt5665_dac3_src[] = { |
1859 | "IF1 DAC2" , "IF2_1 DAC" , "IF2_2 DAC" , "IF3 DAC" , "STO2 ADC MIX" |
1860 | }; |
1861 | |
1862 | static SOC_ENUM_SINGLE_DECL( |
1863 | rt5665_dac_l3_enum, RT5665_DAC3_CTRL, |
1864 | RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src); |
1865 | |
1866 | static const struct snd_kcontrol_new rt5665_dac_l3_mux = |
1867 | SOC_DAPM_ENUM("Digital DAC L3 Source" , rt5665_dac_l3_enum); |
1868 | |
1869 | static SOC_ENUM_SINGLE_DECL( |
1870 | rt5665_dac_r3_enum, RT5665_DAC3_CTRL, |
1871 | RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src); |
1872 | |
1873 | static const struct snd_kcontrol_new rt5665_dac_r3_mux = |
1874 | SOC_DAPM_ENUM("Digital DAC R3 Source" , rt5665_dac_r3_enum); |
1875 | |
1876 | /* STO1 ADC1 Source */ |
1877 | /* MX-26 [13] [5] */ |
1878 | static const char * const rt5665_sto1_adc1_src[] = { |
1879 | "DD Mux" , "ADC" |
1880 | }; |
1881 | |
1882 | static SOC_ENUM_SINGLE_DECL( |
1883 | rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER, |
1884 | RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src); |
1885 | |
1886 | static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux = |
1887 | SOC_DAPM_ENUM("Stereo1 ADC1L Source" , rt5665_sto1_adc1l_enum); |
1888 | |
1889 | static SOC_ENUM_SINGLE_DECL( |
1890 | rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER, |
1891 | RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src); |
1892 | |
1893 | static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux = |
1894 | SOC_DAPM_ENUM("Stereo1 ADC1L Source" , rt5665_sto1_adc1r_enum); |
1895 | |
1896 | /* STO1 ADC Source */ |
1897 | /* MX-26 [11:10] [3:2] */ |
1898 | static const char * const rt5665_sto1_adc_src[] = { |
1899 | "ADC1 L" , "ADC1 R" , "ADC2 L" , "ADC2 R" |
1900 | }; |
1901 | |
1902 | static SOC_ENUM_SINGLE_DECL( |
1903 | rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER, |
1904 | RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src); |
1905 | |
1906 | static const struct snd_kcontrol_new rt5665_sto1_adcl_mux = |
1907 | SOC_DAPM_ENUM("Stereo1 ADCL Source" , rt5665_sto1_adcl_enum); |
1908 | |
1909 | static SOC_ENUM_SINGLE_DECL( |
1910 | rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER, |
1911 | RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src); |
1912 | |
1913 | static const struct snd_kcontrol_new rt5665_sto1_adcr_mux = |
1914 | SOC_DAPM_ENUM("Stereo1 ADCR Source" , rt5665_sto1_adcr_enum); |
1915 | |
1916 | /* STO1 ADC2 Source */ |
1917 | /* MX-26 [12] [4] */ |
1918 | static const char * const rt5665_sto1_adc2_src[] = { |
1919 | "DAC MIX" , "DMIC" |
1920 | }; |
1921 | |
1922 | static SOC_ENUM_SINGLE_DECL( |
1923 | rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER, |
1924 | RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src); |
1925 | |
1926 | static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux = |
1927 | SOC_DAPM_ENUM("Stereo1 ADC2L Source" , rt5665_sto1_adc2l_enum); |
1928 | |
1929 | static SOC_ENUM_SINGLE_DECL( |
1930 | rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER, |
1931 | RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src); |
1932 | |
1933 | static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux = |
1934 | SOC_DAPM_ENUM("Stereo1 ADC2R Source" , rt5665_sto1_adc2r_enum); |
1935 | |
1936 | /* STO1 DMIC Source */ |
1937 | /* MX-26 [8] */ |
1938 | static const char * const rt5665_sto1_dmic_src[] = { |
1939 | "DMIC1" , "DMIC2" |
1940 | }; |
1941 | |
1942 | static SOC_ENUM_SINGLE_DECL( |
1943 | rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER, |
1944 | RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src); |
1945 | |
1946 | static const struct snd_kcontrol_new rt5665_sto1_dmic_mux = |
1947 | SOC_DAPM_ENUM("Stereo1 DMIC Mux" , rt5665_sto1_dmic_enum); |
1948 | |
1949 | /* MX-26 [9] */ |
1950 | static const char * const rt5665_sto1_dd_l_src[] = { |
1951 | "STO2 DAC" , "MONO DAC" |
1952 | }; |
1953 | |
1954 | static SOC_ENUM_SINGLE_DECL( |
1955 | rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER, |
1956 | RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src); |
1957 | |
1958 | static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux = |
1959 | SOC_DAPM_ENUM("Stereo1 DD L Source" , rt5665_sto1_dd_l_enum); |
1960 | |
1961 | /* MX-26 [1:0] */ |
1962 | static const char * const rt5665_sto1_dd_r_src[] = { |
1963 | "STO2 DAC" , "MONO DAC" , "AEC REF" |
1964 | }; |
1965 | |
1966 | static SOC_ENUM_SINGLE_DECL( |
1967 | rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER, |
1968 | RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src); |
1969 | |
1970 | static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux = |
1971 | SOC_DAPM_ENUM("Stereo1 DD R Source" , rt5665_sto1_dd_r_enum); |
1972 | |
1973 | /* MONO ADC L2 Source */ |
1974 | /* MX-27 [12] */ |
1975 | static const char * const rt5665_mono_adc_l2_src[] = { |
1976 | "DAC MIXL" , "DMIC" |
1977 | }; |
1978 | |
1979 | static SOC_ENUM_SINGLE_DECL( |
1980 | rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER, |
1981 | RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src); |
1982 | |
1983 | static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux = |
1984 | SOC_DAPM_ENUM("Mono ADC L2 Source" , rt5665_mono_adc_l2_enum); |
1985 | |
1986 | |
1987 | /* MONO ADC L1 Source */ |
1988 | /* MX-27 [13] */ |
1989 | static const char * const rt5665_mono_adc_l1_src[] = { |
1990 | "DD Mux" , "ADC" |
1991 | }; |
1992 | |
1993 | static SOC_ENUM_SINGLE_DECL( |
1994 | rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER, |
1995 | RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src); |
1996 | |
1997 | static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux = |
1998 | SOC_DAPM_ENUM("Mono ADC L1 Source" , rt5665_mono_adc_l1_enum); |
1999 | |
2000 | /* MX-27 [9][1]*/ |
2001 | static const char * const rt5665_mono_dd_src[] = { |
2002 | "STO2 DAC" , "MONO DAC" |
2003 | }; |
2004 | |
2005 | static SOC_ENUM_SINGLE_DECL( |
2006 | rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER, |
2007 | RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src); |
2008 | |
2009 | static const struct snd_kcontrol_new rt5665_mono_dd_l_mux = |
2010 | SOC_DAPM_ENUM("Mono DD L Source" , rt5665_mono_dd_l_enum); |
2011 | |
2012 | static SOC_ENUM_SINGLE_DECL( |
2013 | rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER, |
2014 | RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src); |
2015 | |
2016 | static const struct snd_kcontrol_new rt5665_mono_dd_r_mux = |
2017 | SOC_DAPM_ENUM("Mono DD R Source" , rt5665_mono_dd_r_enum); |
2018 | |
2019 | /* MONO ADC L Source, MONO ADC R Source*/ |
2020 | /* MX-27 [11:10], MX-27 [3:2] */ |
2021 | static const char * const rt5665_mono_adc_src[] = { |
2022 | "ADC1 L" , "ADC1 R" , "ADC2 L" , "ADC2 R" |
2023 | }; |
2024 | |
2025 | static SOC_ENUM_SINGLE_DECL( |
2026 | rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER, |
2027 | RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src); |
2028 | |
2029 | static const struct snd_kcontrol_new rt5665_mono_adc_l_mux = |
2030 | SOC_DAPM_ENUM("Mono ADC L Source" , rt5665_mono_adc_l_enum); |
2031 | |
2032 | static SOC_ENUM_SINGLE_DECL( |
2033 | rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER, |
2034 | RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src); |
2035 | |
2036 | static const struct snd_kcontrol_new rt5665_mono_adc_r_mux = |
2037 | SOC_DAPM_ENUM("Mono ADC R Source" , rt5665_mono_adcr_enum); |
2038 | |
2039 | /* MONO DMIC L Source */ |
2040 | /* MX-27 [8] */ |
2041 | static const char * const rt5665_mono_dmic_l_src[] = { |
2042 | "DMIC1 L" , "DMIC2 L" |
2043 | }; |
2044 | |
2045 | static SOC_ENUM_SINGLE_DECL( |
2046 | rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER, |
2047 | RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src); |
2048 | |
2049 | static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux = |
2050 | SOC_DAPM_ENUM("Mono DMIC L Source" , rt5665_mono_dmic_l_enum); |
2051 | |
2052 | /* MONO ADC R2 Source */ |
2053 | /* MX-27 [4] */ |
2054 | static const char * const rt5665_mono_adc_r2_src[] = { |
2055 | "DAC MIXR" , "DMIC" |
2056 | }; |
2057 | |
2058 | static SOC_ENUM_SINGLE_DECL( |
2059 | rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER, |
2060 | RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src); |
2061 | |
2062 | static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux = |
2063 | SOC_DAPM_ENUM("Mono ADC R2 Source" , rt5665_mono_adc_r2_enum); |
2064 | |
2065 | /* MONO ADC R1 Source */ |
2066 | /* MX-27 [5] */ |
2067 | static const char * const rt5665_mono_adc_r1_src[] = { |
2068 | "DD Mux" , "ADC" |
2069 | }; |
2070 | |
2071 | static SOC_ENUM_SINGLE_DECL( |
2072 | rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER, |
2073 | RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src); |
2074 | |
2075 | static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux = |
2076 | SOC_DAPM_ENUM("Mono ADC R1 Source" , rt5665_mono_adc_r1_enum); |
2077 | |
2078 | /* MONO DMIC R Source */ |
2079 | /* MX-27 [0] */ |
2080 | static const char * const rt5665_mono_dmic_r_src[] = { |
2081 | "DMIC1 R" , "DMIC2 R" |
2082 | }; |
2083 | |
2084 | static SOC_ENUM_SINGLE_DECL( |
2085 | rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER, |
2086 | RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src); |
2087 | |
2088 | static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux = |
2089 | SOC_DAPM_ENUM("Mono DMIC R Source" , rt5665_mono_dmic_r_enum); |
2090 | |
2091 | |
2092 | /* STO2 ADC1 Source */ |
2093 | /* MX-28 [13] [5] */ |
2094 | static const char * const rt5665_sto2_adc1_src[] = { |
2095 | "DD Mux" , "ADC" |
2096 | }; |
2097 | |
2098 | static SOC_ENUM_SINGLE_DECL( |
2099 | rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER, |
2100 | RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src); |
2101 | |
2102 | static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux = |
2103 | SOC_DAPM_ENUM("Stereo2 ADC1L Source" , rt5665_sto2_adc1l_enum); |
2104 | |
2105 | static SOC_ENUM_SINGLE_DECL( |
2106 | rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER, |
2107 | RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src); |
2108 | |
2109 | static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux = |
2110 | SOC_DAPM_ENUM("Stereo2 ADC1L Source" , rt5665_sto2_adc1r_enum); |
2111 | |
2112 | /* STO2 ADC Source */ |
2113 | /* MX-28 [11:10] [3:2] */ |
2114 | static const char * const rt5665_sto2_adc_src[] = { |
2115 | "ADC1 L" , "ADC1 R" , "ADC2 L" |
2116 | }; |
2117 | |
2118 | static SOC_ENUM_SINGLE_DECL( |
2119 | rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER, |
2120 | RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src); |
2121 | |
2122 | static const struct snd_kcontrol_new rt5665_sto2_adcl_mux = |
2123 | SOC_DAPM_ENUM("Stereo2 ADCL Source" , rt5665_sto2_adcl_enum); |
2124 | |
2125 | static SOC_ENUM_SINGLE_DECL( |
2126 | rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER, |
2127 | RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src); |
2128 | |
2129 | static const struct snd_kcontrol_new rt5665_sto2_adcr_mux = |
2130 | SOC_DAPM_ENUM("Stereo2 ADCR Source" , rt5665_sto2_adcr_enum); |
2131 | |
2132 | /* STO2 ADC2 Source */ |
2133 | /* MX-28 [12] [4] */ |
2134 | static const char * const rt5665_sto2_adc2_src[] = { |
2135 | "DAC MIX" , "DMIC" |
2136 | }; |
2137 | |
2138 | static SOC_ENUM_SINGLE_DECL( |
2139 | rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER, |
2140 | RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src); |
2141 | |
2142 | static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux = |
2143 | SOC_DAPM_ENUM("Stereo2 ADC2L Source" , rt5665_sto2_adc2l_enum); |
2144 | |
2145 | static SOC_ENUM_SINGLE_DECL( |
2146 | rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER, |
2147 | RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src); |
2148 | |
2149 | static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux = |
2150 | SOC_DAPM_ENUM("Stereo2 ADC2R Source" , rt5665_sto2_adc2r_enum); |
2151 | |
2152 | /* STO2 DMIC Source */ |
2153 | /* MX-28 [8] */ |
2154 | static const char * const rt5665_sto2_dmic_src[] = { |
2155 | "DMIC1" , "DMIC2" |
2156 | }; |
2157 | |
2158 | static SOC_ENUM_SINGLE_DECL( |
2159 | rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER, |
2160 | RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src); |
2161 | |
2162 | static const struct snd_kcontrol_new rt5665_sto2_dmic_mux = |
2163 | SOC_DAPM_ENUM("Stereo2 DMIC Source" , rt5665_sto2_dmic_enum); |
2164 | |
2165 | /* MX-28 [9] */ |
2166 | static const char * const rt5665_sto2_dd_l_src[] = { |
2167 | "STO2 DAC" , "MONO DAC" |
2168 | }; |
2169 | |
2170 | static SOC_ENUM_SINGLE_DECL( |
2171 | rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER, |
2172 | RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src); |
2173 | |
2174 | static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux = |
2175 | SOC_DAPM_ENUM("Stereo2 DD L Source" , rt5665_sto2_dd_l_enum); |
2176 | |
2177 | /* MX-28 [1] */ |
2178 | static const char * const rt5665_sto2_dd_r_src[] = { |
2179 | "STO2 DAC" , "MONO DAC" |
2180 | }; |
2181 | |
2182 | static SOC_ENUM_SINGLE_DECL( |
2183 | rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER, |
2184 | RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src); |
2185 | |
2186 | static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux = |
2187 | SOC_DAPM_ENUM("Stereo2 DD R Source" , rt5665_sto2_dd_r_enum); |
2188 | |
2189 | /* DAC R1 Source, DAC L1 Source*/ |
2190 | /* MX-29 [11:10], MX-29 [9:8]*/ |
2191 | static const char * const rt5665_dac1_src[] = { |
2192 | "IF1 DAC1" , "IF2_1 DAC" , "IF2_2 DAC" , "IF3 DAC" |
2193 | }; |
2194 | |
2195 | static SOC_ENUM_SINGLE_DECL( |
2196 | rt5665_dac_r1_enum, RT5665_AD_DA_MIXER, |
2197 | RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src); |
2198 | |
2199 | static const struct snd_kcontrol_new rt5665_dac_r1_mux = |
2200 | SOC_DAPM_ENUM("DAC R1 Source" , rt5665_dac_r1_enum); |
2201 | |
2202 | static SOC_ENUM_SINGLE_DECL( |
2203 | rt5665_dac_l1_enum, RT5665_AD_DA_MIXER, |
2204 | RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src); |
2205 | |
2206 | static const struct snd_kcontrol_new rt5665_dac_l1_mux = |
2207 | SOC_DAPM_ENUM("DAC L1 Source" , rt5665_dac_l1_enum); |
2208 | |
2209 | /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/ |
2210 | /* MX-2D [13:12], MX-2D [9:8]*/ |
2211 | static const char * const rt5665_dig_dac_mix_src[] = { |
2212 | "Stereo1 DAC Mixer" , "Stereo2 DAC Mixer" , "Mono DAC Mixer" |
2213 | }; |
2214 | |
2215 | static SOC_ENUM_SINGLE_DECL( |
2216 | rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX, |
2217 | RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src); |
2218 | |
2219 | static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux = |
2220 | SOC_DAPM_ENUM("DAC Digital Mixer L Source" , rt5665_dig_dac_mixl_enum); |
2221 | |
2222 | static SOC_ENUM_SINGLE_DECL( |
2223 | rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX, |
2224 | RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src); |
2225 | |
2226 | static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux = |
2227 | SOC_DAPM_ENUM("DAC Digital Mixer R Source" , rt5665_dig_dac_mixr_enum); |
2228 | |
2229 | /* Analog DAC L1 Source, Analog DAC R1 Source*/ |
2230 | /* MX-2D [5:4], MX-2D [1:0]*/ |
2231 | static const char * const rt5665_alg_dac1_src[] = { |
2232 | "Stereo1 DAC Mixer" , "DAC1" , "DMIC1" |
2233 | }; |
2234 | |
2235 | static SOC_ENUM_SINGLE_DECL( |
2236 | rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX, |
2237 | RT5665_A_DACL1_SFT, rt5665_alg_dac1_src); |
2238 | |
2239 | static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux = |
2240 | SOC_DAPM_ENUM("Analog DAC L1 Source" , rt5665_alg_dac_l1_enum); |
2241 | |
2242 | static SOC_ENUM_SINGLE_DECL( |
2243 | rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX, |
2244 | RT5665_A_DACR1_SFT, rt5665_alg_dac1_src); |
2245 | |
2246 | static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux = |
2247 | SOC_DAPM_ENUM("Analog DAC R1 Source" , rt5665_alg_dac_r1_enum); |
2248 | |
2249 | /* Analog DAC LR Source, Analog DAC R2 Source*/ |
2250 | /* MX-2E [5:4], MX-2E [0]*/ |
2251 | static const char * const rt5665_alg_dac2_src[] = { |
2252 | "Mono DAC Mixer" , "DAC2" |
2253 | }; |
2254 | |
2255 | static SOC_ENUM_SINGLE_DECL( |
2256 | rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX, |
2257 | RT5665_A_DACL2_SFT, rt5665_alg_dac2_src); |
2258 | |
2259 | static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux = |
2260 | SOC_DAPM_ENUM("Analog DAC L2 Source" , rt5665_alg_dac_l2_enum); |
2261 | |
2262 | static SOC_ENUM_SINGLE_DECL( |
2263 | rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX, |
2264 | RT5665_A_DACR2_SFT, rt5665_alg_dac2_src); |
2265 | |
2266 | static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux = |
2267 | SOC_DAPM_ENUM("Analog DAC R2 Source" , rt5665_alg_dac_r2_enum); |
2268 | |
2269 | /* Interface2 ADC Data Input*/ |
2270 | /* MX-2F [14:12] */ |
2271 | static const char * const rt5665_if2_1_adc_in_src[] = { |
2272 | "STO1 ADC" , "STO2 ADC" , "MONO ADC" , "IF1 DAC1" , |
2273 | "IF1 DAC2" , "IF2_2 DAC" , "IF3 DAC" , "DAC1 MIX" |
2274 | }; |
2275 | |
2276 | static SOC_ENUM_SINGLE_DECL( |
2277 | rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA, |
2278 | RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src); |
2279 | |
2280 | static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux = |
2281 | SOC_DAPM_ENUM("IF2_1 ADC IN Source" , rt5665_if2_1_adc_in_enum); |
2282 | |
2283 | /* MX-2F [6:4] */ |
2284 | static const char * const rt5665_if2_2_adc_in_src[] = { |
2285 | "STO1 ADC" , "STO2 ADC" , "MONO ADC" , "IF1 DAC1" , |
2286 | "IF1 DAC2" , "IF2_1 DAC" , "IF3 DAC" , "DAC1 MIX" |
2287 | }; |
2288 | |
2289 | static SOC_ENUM_SINGLE_DECL( |
2290 | rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA, |
2291 | RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src); |
2292 | |
2293 | static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux = |
2294 | SOC_DAPM_ENUM("IF2_1 ADC IN Source" , rt5665_if2_2_adc_in_enum); |
2295 | |
2296 | /* Interface3 ADC Data Input*/ |
2297 | /* MX-30 [6:4] */ |
2298 | static const char * const rt5665_if3_adc_in_src[] = { |
2299 | "STO1 ADC" , "STO2 ADC" , "MONO ADC" , "IF1 DAC1" , |
2300 | "IF1 DAC2" , "IF2_1 DAC" , "IF2_2 DAC" , "DAC1 MIX" |
2301 | }; |
2302 | |
2303 | static SOC_ENUM_SINGLE_DECL( |
2304 | rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA, |
2305 | RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src); |
2306 | |
2307 | static const struct snd_kcontrol_new rt5665_if3_adc_in_mux = |
2308 | SOC_DAPM_ENUM("IF3 ADC IN Source" , rt5665_if3_adc_in_enum); |
2309 | |
2310 | /* PDM 1 L/R*/ |
2311 | /* MX-31 [11:10] [9:8] */ |
2312 | static const char * const rt5665_pdm_src[] = { |
2313 | "Stereo1 DAC" , "Stereo2 DAC" , "Mono DAC" |
2314 | }; |
2315 | |
2316 | static SOC_ENUM_SINGLE_DECL( |
2317 | rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL, |
2318 | RT5665_PDM1_L_SFT, rt5665_pdm_src); |
2319 | |
2320 | static const struct snd_kcontrol_new rt5665_pdm_l_mux = |
2321 | SOC_DAPM_ENUM("PDM L Source" , rt5665_pdm_l_enum); |
2322 | |
2323 | static SOC_ENUM_SINGLE_DECL( |
2324 | rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL, |
2325 | RT5665_PDM1_R_SFT, rt5665_pdm_src); |
2326 | |
2327 | static const struct snd_kcontrol_new rt5665_pdm_r_mux = |
2328 | SOC_DAPM_ENUM("PDM R Source" , rt5665_pdm_r_enum); |
2329 | |
2330 | |
2331 | /* I2S1 TDM ADCDAT Source */ |
2332 | /* MX-7a[10] */ |
2333 | static const char * const rt5665_if1_1_adc1_data_src[] = { |
2334 | "STO1 ADC" , "IF2_1 DAC" , |
2335 | }; |
2336 | |
2337 | static SOC_ENUM_SINGLE_DECL( |
2338 | rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3, |
2339 | RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src); |
2340 | |
2341 | static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux = |
2342 | SOC_DAPM_ENUM("IF1_1 ADC1 Source" , rt5665_if1_1_adc1_data_enum); |
2343 | |
2344 | /* MX-7a[9] */ |
2345 | static const char * const rt5665_if1_1_adc2_data_src[] = { |
2346 | "STO2 ADC" , "IF2_2 DAC" , |
2347 | }; |
2348 | |
2349 | static SOC_ENUM_SINGLE_DECL( |
2350 | rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3, |
2351 | RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src); |
2352 | |
2353 | static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux = |
2354 | SOC_DAPM_ENUM("IF1_1 ADC2 Source" , rt5665_if1_1_adc2_data_enum); |
2355 | |
2356 | /* MX-7a[8] */ |
2357 | static const char * const rt5665_if1_1_adc3_data_src[] = { |
2358 | "MONO ADC" , "IF3 DAC" , |
2359 | }; |
2360 | |
2361 | static SOC_ENUM_SINGLE_DECL( |
2362 | rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3, |
2363 | RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src); |
2364 | |
2365 | static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux = |
2366 | SOC_DAPM_ENUM("IF1_1 ADC3 Source" , rt5665_if1_1_adc3_data_enum); |
2367 | |
2368 | /* MX-7b[10] */ |
2369 | static const char * const rt5665_if1_2_adc1_data_src[] = { |
2370 | "STO1 ADC" , "IF1 DAC" , |
2371 | }; |
2372 | |
2373 | static SOC_ENUM_SINGLE_DECL( |
2374 | rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4, |
2375 | RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src); |
2376 | |
2377 | static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux = |
2378 | SOC_DAPM_ENUM("IF1_2 ADC1 Source" , rt5665_if1_2_adc1_data_enum); |
2379 | |
2380 | /* MX-7b[9] */ |
2381 | static const char * const rt5665_if1_2_adc2_data_src[] = { |
2382 | "STO2 ADC" , "IF2_1 DAC" , |
2383 | }; |
2384 | |
2385 | static SOC_ENUM_SINGLE_DECL( |
2386 | rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4, |
2387 | RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src); |
2388 | |
2389 | static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux = |
2390 | SOC_DAPM_ENUM("IF1_2 ADC2 Source" , rt5665_if1_2_adc2_data_enum); |
2391 | |
2392 | /* MX-7b[8] */ |
2393 | static const char * const rt5665_if1_2_adc3_data_src[] = { |
2394 | "MONO ADC" , "IF2_2 DAC" , |
2395 | }; |
2396 | |
2397 | static SOC_ENUM_SINGLE_DECL( |
2398 | rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4, |
2399 | RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src); |
2400 | |
2401 | static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux = |
2402 | SOC_DAPM_ENUM("IF1_2 ADC3 Source" , rt5665_if1_2_adc3_data_enum); |
2403 | |
2404 | /* MX-7b[7] */ |
2405 | static const char * const rt5665_if1_2_adc4_data_src[] = { |
2406 | "DAC1" , "IF3 DAC" , |
2407 | }; |
2408 | |
2409 | static SOC_ENUM_SINGLE_DECL( |
2410 | rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4, |
2411 | RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src); |
2412 | |
2413 | static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux = |
2414 | SOC_DAPM_ENUM("IF1_2 ADC4 Source" , rt5665_if1_2_adc4_data_enum); |
2415 | |
2416 | /* MX-7a[4:0] MX-7b[4:0] */ |
2417 | static const char * const rt5665_tdm_adc_data_src[] = { |
2418 | "1234" , "1243" , "1324" , "1342" , "1432" , "1423" , |
2419 | "2134" , "2143" , "2314" , "2341" , "2431" , "2413" , |
2420 | "3124" , "3142" , "3214" , "3241" , "3412" , "3421" , |
2421 | "4123" , "4132" , "4213" , "4231" , "4312" , "4321" |
2422 | }; |
2423 | |
2424 | static SOC_ENUM_SINGLE_DECL( |
2425 | rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3, |
2426 | RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src); |
2427 | |
2428 | static const struct snd_kcontrol_new rt5665_tdm1_adc_mux = |
2429 | SOC_DAPM_ENUM("TDM1 ADC Mux" , rt5665_tdm1_adc_data_enum); |
2430 | |
2431 | static SOC_ENUM_SINGLE_DECL( |
2432 | rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4, |
2433 | RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src); |
2434 | |
2435 | static const struct snd_kcontrol_new rt5665_tdm2_adc_mux = |
2436 | SOC_DAPM_ENUM("TDM2 ADCDAT Source" , rt5665_tdm2_adc_data_enum); |
2437 | |
2438 | /* Out Volume Switch */ |
2439 | static const struct snd_kcontrol_new monovol_switch = |
2440 | SOC_DAPM_SINGLE("Switch" , RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1); |
2441 | |
2442 | static const struct snd_kcontrol_new outvol_l_switch = |
2443 | SOC_DAPM_SINGLE("Switch" , RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1); |
2444 | |
2445 | static const struct snd_kcontrol_new outvol_r_switch = |
2446 | SOC_DAPM_SINGLE("Switch" , RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1); |
2447 | |
2448 | /* Out Switch */ |
2449 | static const struct snd_kcontrol_new mono_switch = |
2450 | SOC_DAPM_SINGLE("Switch" , RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1); |
2451 | |
2452 | static const struct snd_kcontrol_new hpo_switch = |
2453 | SOC_DAPM_SINGLE_AUTODISABLE("Switch" , RT5665_HP_CTRL_2, |
2454 | RT5665_VOL_L_SFT, 1, 0); |
2455 | |
2456 | static const struct snd_kcontrol_new lout_l_switch = |
2457 | SOC_DAPM_SINGLE("Switch" , RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1); |
2458 | |
2459 | static const struct snd_kcontrol_new lout_r_switch = |
2460 | SOC_DAPM_SINGLE("Switch" , RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1); |
2461 | |
2462 | static const struct snd_kcontrol_new pdm_l_switch = |
2463 | SOC_DAPM_SINGLE("Switch" , RT5665_PDM_OUT_CTRL, |
2464 | RT5665_M_PDM1_L_SFT, 1, 1); |
2465 | |
2466 | static const struct snd_kcontrol_new pdm_r_switch = |
2467 | SOC_DAPM_SINGLE("Switch" , RT5665_PDM_OUT_CTRL, |
2468 | RT5665_M_PDM1_R_SFT, 1, 1); |
2469 | |
2470 | static int rt5665_mono_event(struct snd_soc_dapm_widget *w, |
2471 | struct snd_kcontrol *kcontrol, int event) |
2472 | { |
2473 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
2474 | |
2475 | switch (event) { |
2476 | case SND_SOC_DAPM_PRE_PMU: |
2477 | snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, |
2478 | RT5665_NG2_EN_MASK, RT5665_NG2_EN); |
2479 | snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, mask: 0x40, |
2480 | val: 0x0); |
2481 | snd_soc_component_update_bits(component, RT5665_MONO_OUT, mask: 0x10, val: 0x10); |
2482 | snd_soc_component_update_bits(component, RT5665_MONO_OUT, mask: 0x20, val: 0x20); |
2483 | break; |
2484 | |
2485 | case SND_SOC_DAPM_POST_PMD: |
2486 | snd_soc_component_update_bits(component, RT5665_MONO_OUT, mask: 0x20, val: 0); |
2487 | snd_soc_component_update_bits(component, RT5665_MONO_OUT, mask: 0x10, val: 0); |
2488 | snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, mask: 0x40, |
2489 | val: 0x40); |
2490 | snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1, |
2491 | RT5665_NG2_EN_MASK, RT5665_NG2_DIS); |
2492 | break; |
2493 | |
2494 | default: |
2495 | return 0; |
2496 | } |
2497 | |
2498 | return 0; |
2499 | |
2500 | } |
2501 | |
2502 | static int rt5665_hp_event(struct snd_soc_dapm_widget *w, |
2503 | struct snd_kcontrol *kcontrol, int event) |
2504 | { |
2505 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
2506 | |
2507 | switch (event) { |
2508 | case SND_SOC_DAPM_PRE_PMU: |
2509 | snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, |
2510 | RT5665_NG2_EN_MASK, RT5665_NG2_EN); |
2511 | snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, val: 0x0003); |
2512 | break; |
2513 | |
2514 | case SND_SOC_DAPM_POST_PMD: |
2515 | snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, val: 0x0002); |
2516 | snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1, |
2517 | RT5665_NG2_EN_MASK, RT5665_NG2_DIS); |
2518 | break; |
2519 | |
2520 | default: |
2521 | return 0; |
2522 | } |
2523 | |
2524 | return 0; |
2525 | |
2526 | } |
2527 | |
2528 | static int rt5665_lout_event(struct snd_soc_dapm_widget *w, |
2529 | struct snd_kcontrol *kcontrol, int event) |
2530 | { |
2531 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
2532 | |
2533 | switch (event) { |
2534 | case SND_SOC_DAPM_POST_PMU: |
2535 | snd_soc_component_update_bits(component, RT5665_DEPOP_1, |
2536 | RT5665_PUMP_EN, RT5665_PUMP_EN); |
2537 | break; |
2538 | |
2539 | case SND_SOC_DAPM_PRE_PMD: |
2540 | snd_soc_component_update_bits(component, RT5665_DEPOP_1, |
2541 | RT5665_PUMP_EN, val: 0); |
2542 | break; |
2543 | |
2544 | default: |
2545 | return 0; |
2546 | } |
2547 | |
2548 | return 0; |
2549 | |
2550 | } |
2551 | |
2552 | static int set_dmic_power(struct snd_soc_dapm_widget *w, |
2553 | struct snd_kcontrol *kcontrol, int event) |
2554 | { |
2555 | switch (event) { |
2556 | case SND_SOC_DAPM_POST_PMU: |
2557 | /*Add delay to avoid pop noise*/ |
2558 | msleep(msecs: 150); |
2559 | break; |
2560 | |
2561 | default: |
2562 | return 0; |
2563 | } |
2564 | |
2565 | return 0; |
2566 | } |
2567 | |
2568 | static int rt5665_set_verf(struct snd_soc_dapm_widget *w, |
2569 | struct snd_kcontrol *kcontrol, int event) |
2570 | { |
2571 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
2572 | |
2573 | switch (event) { |
2574 | case SND_SOC_DAPM_PRE_PMU: |
2575 | switch (w->shift) { |
2576 | case RT5665_PWR_VREF1_BIT: |
2577 | snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, |
2578 | RT5665_PWR_FV1, val: 0); |
2579 | break; |
2580 | |
2581 | case RT5665_PWR_VREF2_BIT: |
2582 | snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, |
2583 | RT5665_PWR_FV2, val: 0); |
2584 | break; |
2585 | |
2586 | case RT5665_PWR_VREF3_BIT: |
2587 | snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, |
2588 | RT5665_PWR_FV3, val: 0); |
2589 | break; |
2590 | |
2591 | default: |
2592 | break; |
2593 | } |
2594 | break; |
2595 | |
2596 | case SND_SOC_DAPM_POST_PMU: |
2597 | usleep_range(min: 15000, max: 20000); |
2598 | switch (w->shift) { |
2599 | case RT5665_PWR_VREF1_BIT: |
2600 | snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, |
2601 | RT5665_PWR_FV1, RT5665_PWR_FV1); |
2602 | break; |
2603 | |
2604 | case RT5665_PWR_VREF2_BIT: |
2605 | snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, |
2606 | RT5665_PWR_FV2, RT5665_PWR_FV2); |
2607 | break; |
2608 | |
2609 | case RT5665_PWR_VREF3_BIT: |
2610 | snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1, |
2611 | RT5665_PWR_FV3, RT5665_PWR_FV3); |
2612 | break; |
2613 | |
2614 | default: |
2615 | break; |
2616 | } |
2617 | break; |
2618 | |
2619 | default: |
2620 | return 0; |
2621 | } |
2622 | |
2623 | return 0; |
2624 | } |
2625 | |
2626 | static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w, |
2627 | struct snd_kcontrol *kcontrol, int event) |
2628 | { |
2629 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
2630 | unsigned int val1, val2, mask1 = 0, mask2 = 0; |
2631 | |
2632 | switch (w->shift) { |
2633 | case RT5665_PWR_I2S2_1_BIT: |
2634 | mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK | |
2635 | RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK; |
2636 | val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 | |
2637 | RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1; |
2638 | break; |
2639 | case RT5665_PWR_I2S2_2_BIT: |
2640 | mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK | |
2641 | RT5665_GP8_PIN_MASK; |
2642 | val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 | |
2643 | RT5665_GP8_PIN_DACDAT2_2; |
2644 | mask2 = RT5665_GP9_PIN_MASK; |
2645 | val2 = RT5665_GP9_PIN_ADCDAT2_2; |
2646 | break; |
2647 | case RT5665_PWR_I2S3_BIT: |
2648 | mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK | |
2649 | RT5665_GP8_PIN_MASK; |
2650 | val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 | |
2651 | RT5665_GP8_PIN_DACDAT3; |
2652 | mask2 = RT5665_GP9_PIN_MASK; |
2653 | val2 = RT5665_GP9_PIN_ADCDAT3; |
2654 | break; |
2655 | } |
2656 | switch (event) { |
2657 | case SND_SOC_DAPM_PRE_PMU: |
2658 | if (mask1) |
2659 | snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1, |
2660 | mask: mask1, val: val1); |
2661 | if (mask2) |
2662 | snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2, |
2663 | mask: mask2, val: val2); |
2664 | break; |
2665 | case SND_SOC_DAPM_POST_PMD: |
2666 | if (mask1) |
2667 | snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1, |
2668 | mask: mask1, val: 0); |
2669 | if (mask2) |
2670 | snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2, |
2671 | mask: mask2, val: 0); |
2672 | break; |
2673 | default: |
2674 | return 0; |
2675 | } |
2676 | |
2677 | return 0; |
2678 | } |
2679 | |
2680 | static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = { |
2681 | SND_SOC_DAPM_SUPPLY("LDO2" , RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0, |
2682 | NULL, 0), |
2683 | SND_SOC_DAPM_SUPPLY("PLL" , RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0, |
2684 | NULL, 0), |
2685 | SND_SOC_DAPM_SUPPLY("Mic Det Power" , RT5665_PWR_VOL, |
2686 | RT5665_PWR_MIC_DET_BIT, 0, NULL, 0), |
2687 | SND_SOC_DAPM_SUPPLY("Vref1" , RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0, |
2688 | rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), |
2689 | SND_SOC_DAPM_SUPPLY("Vref2" , RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0, |
2690 | rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), |
2691 | SND_SOC_DAPM_SUPPLY("Vref3" , RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0, |
2692 | rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), |
2693 | |
2694 | /* ASRC */ |
2695 | SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC" , 1, RT5665_ASRC_1, |
2696 | RT5665_I2S1_ASRC_SFT, 0, NULL, 0), |
2697 | SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC" , 1, RT5665_ASRC_1, |
2698 | RT5665_I2S2_ASRC_SFT, 0, NULL, 0), |
2699 | SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC" , 1, RT5665_ASRC_1, |
2700 | RT5665_I2S3_ASRC_SFT, 0, NULL, 0), |
2701 | SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC" , 1, RT5665_ASRC_1, |
2702 | RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0), |
2703 | SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC" , 1, RT5665_ASRC_1, |
2704 | RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0), |
2705 | SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC" , 1, RT5665_ASRC_1, |
2706 | RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0), |
2707 | SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC" , 1, RT5665_ASRC_1, |
2708 | RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0), |
2709 | SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC" , 1, RT5665_ASRC_1, |
2710 | RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0), |
2711 | SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC" , 1, RT5665_ASRC_1, |
2712 | RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0), |
2713 | SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC" , 1, RT5665_ASRC_1, |
2714 | RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0), |
2715 | SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC" , 1, RT5665_ASRC_1, |
2716 | RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0), |
2717 | SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC" , 1, RT5665_ASRC_1, |
2718 | RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0), |
2719 | SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC" , 1, RT5665_ASRC_1, |
2720 | RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0), |
2721 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC" , 1, RT5665_ASRC_1, |
2722 | RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0), |
2723 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC" , 1, RT5665_ASRC_1, |
2724 | RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0), |
2725 | |
2726 | /* Input Side */ |
2727 | SND_SOC_DAPM_SUPPLY("MICBIAS1" , RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT, |
2728 | 0, NULL, 0), |
2729 | SND_SOC_DAPM_SUPPLY("MICBIAS2" , RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT, |
2730 | 0, NULL, 0), |
2731 | SND_SOC_DAPM_SUPPLY("MICBIAS3" , RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT, |
2732 | 0, NULL, 0), |
2733 | |
2734 | /* Input Lines */ |
2735 | SND_SOC_DAPM_INPUT("DMIC L1" ), |
2736 | SND_SOC_DAPM_INPUT("DMIC R1" ), |
2737 | SND_SOC_DAPM_INPUT("DMIC L2" ), |
2738 | SND_SOC_DAPM_INPUT("DMIC R2" ), |
2739 | |
2740 | SND_SOC_DAPM_INPUT("IN1P" ), |
2741 | SND_SOC_DAPM_INPUT("IN1N" ), |
2742 | SND_SOC_DAPM_INPUT("IN2P" ), |
2743 | SND_SOC_DAPM_INPUT("IN2N" ), |
2744 | SND_SOC_DAPM_INPUT("IN3P" ), |
2745 | SND_SOC_DAPM_INPUT("IN3N" ), |
2746 | SND_SOC_DAPM_INPUT("IN4P" ), |
2747 | SND_SOC_DAPM_INPUT("IN4N" ), |
2748 | |
2749 | SND_SOC_DAPM_PGA("DMIC1" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2750 | SND_SOC_DAPM_PGA("DMIC2" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2751 | |
2752 | SND_SOC_DAPM_SUPPLY("DMIC CLK" , SND_SOC_NOPM, 0, 0, |
2753 | set_dmic_clk, SND_SOC_DAPM_PRE_PMU), |
2754 | SND_SOC_DAPM_SUPPLY("DMIC1 Power" , RT5665_DMIC_CTRL_1, |
2755 | RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), |
2756 | SND_SOC_DAPM_SUPPLY("DMIC2 Power" , RT5665_DMIC_CTRL_1, |
2757 | RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), |
2758 | |
2759 | /* Boost */ |
2760 | SND_SOC_DAPM_PGA("BST1" , SND_SOC_NOPM, |
2761 | 0, 0, NULL, 0), |
2762 | SND_SOC_DAPM_PGA("BST2" , SND_SOC_NOPM, |
2763 | 0, 0, NULL, 0), |
2764 | SND_SOC_DAPM_PGA("BST3" , SND_SOC_NOPM, |
2765 | 0, 0, NULL, 0), |
2766 | SND_SOC_DAPM_PGA("BST4" , SND_SOC_NOPM, |
2767 | 0, 0, NULL, 0), |
2768 | SND_SOC_DAPM_PGA("BST1 CBJ" , SND_SOC_NOPM, |
2769 | 0, 0, NULL, 0), |
2770 | SND_SOC_DAPM_SUPPLY("BST1 Power" , RT5665_PWR_ANLG_2, |
2771 | RT5665_PWR_BST1_BIT, 0, NULL, 0), |
2772 | SND_SOC_DAPM_SUPPLY("BST2 Power" , RT5665_PWR_ANLG_2, |
2773 | RT5665_PWR_BST2_BIT, 0, NULL, 0), |
2774 | SND_SOC_DAPM_SUPPLY("BST3 Power" , RT5665_PWR_ANLG_2, |
2775 | RT5665_PWR_BST3_BIT, 0, NULL, 0), |
2776 | SND_SOC_DAPM_SUPPLY("BST4 Power" , RT5665_PWR_ANLG_2, |
2777 | RT5665_PWR_BST4_BIT, 0, NULL, 0), |
2778 | SND_SOC_DAPM_SUPPLY("BST1P Power" , RT5665_PWR_ANLG_2, |
2779 | RT5665_PWR_BST1_P_BIT, 0, NULL, 0), |
2780 | SND_SOC_DAPM_SUPPLY("BST2P Power" , RT5665_PWR_ANLG_2, |
2781 | RT5665_PWR_BST2_P_BIT, 0, NULL, 0), |
2782 | SND_SOC_DAPM_SUPPLY("BST3P Power" , RT5665_PWR_ANLG_2, |
2783 | RT5665_PWR_BST3_P_BIT, 0, NULL, 0), |
2784 | SND_SOC_DAPM_SUPPLY("BST4P Power" , RT5665_PWR_ANLG_2, |
2785 | RT5665_PWR_BST4_P_BIT, 0, NULL, 0), |
2786 | SND_SOC_DAPM_SUPPLY("CBJ Power" , RT5665_PWR_ANLG_3, |
2787 | RT5665_PWR_CBJ_BIT, 0, NULL, 0), |
2788 | |
2789 | |
2790 | /* Input Volume */ |
2791 | SND_SOC_DAPM_PGA("INL VOL" , RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT, |
2792 | 0, NULL, 0), |
2793 | SND_SOC_DAPM_PGA("INR VOL" , RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT, |
2794 | 0, NULL, 0), |
2795 | |
2796 | /* REC Mixer */ |
2797 | SND_SOC_DAPM_MIXER("RECMIX1L" , SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix, |
2798 | ARRAY_SIZE(rt5665_rec1_l_mix)), |
2799 | SND_SOC_DAPM_MIXER("RECMIX1R" , SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix, |
2800 | ARRAY_SIZE(rt5665_rec1_r_mix)), |
2801 | SND_SOC_DAPM_MIXER("RECMIX2L" , SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix, |
2802 | ARRAY_SIZE(rt5665_rec2_l_mix)), |
2803 | SND_SOC_DAPM_MIXER("RECMIX2R" , SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix, |
2804 | ARRAY_SIZE(rt5665_rec2_r_mix)), |
2805 | SND_SOC_DAPM_SUPPLY("RECMIX1L Power" , RT5665_PWR_ANLG_2, |
2806 | RT5665_PWR_RM1_L_BIT, 0, NULL, 0), |
2807 | SND_SOC_DAPM_SUPPLY("RECMIX1R Power" , RT5665_PWR_ANLG_2, |
2808 | RT5665_PWR_RM1_R_BIT, 0, NULL, 0), |
2809 | SND_SOC_DAPM_SUPPLY("RECMIX2L Power" , RT5665_PWR_MIXER, |
2810 | RT5665_PWR_RM2_L_BIT, 0, NULL, 0), |
2811 | SND_SOC_DAPM_SUPPLY("RECMIX2R Power" , RT5665_PWR_MIXER, |
2812 | RT5665_PWR_RM2_R_BIT, 0, NULL, 0), |
2813 | |
2814 | /* ADCs */ |
2815 | SND_SOC_DAPM_ADC("ADC1 L" , NULL, SND_SOC_NOPM, 0, 0), |
2816 | SND_SOC_DAPM_ADC("ADC1 R" , NULL, SND_SOC_NOPM, 0, 0), |
2817 | SND_SOC_DAPM_ADC("ADC2 L" , NULL, SND_SOC_NOPM, 0, 0), |
2818 | SND_SOC_DAPM_ADC("ADC2 R" , NULL, SND_SOC_NOPM, 0, 0), |
2819 | |
2820 | SND_SOC_DAPM_SUPPLY("ADC1 L Power" , RT5665_PWR_DIG_1, |
2821 | RT5665_PWR_ADC_L1_BIT, 0, NULL, 0), |
2822 | SND_SOC_DAPM_SUPPLY("ADC1 R Power" , RT5665_PWR_DIG_1, |
2823 | RT5665_PWR_ADC_R1_BIT, 0, NULL, 0), |
2824 | SND_SOC_DAPM_SUPPLY("ADC2 L Power" , RT5665_PWR_DIG_1, |
2825 | RT5665_PWR_ADC_L2_BIT, 0, NULL, 0), |
2826 | SND_SOC_DAPM_SUPPLY("ADC2 R Power" , RT5665_PWR_DIG_1, |
2827 | RT5665_PWR_ADC_R2_BIT, 0, NULL, 0), |
2828 | SND_SOC_DAPM_SUPPLY("ADC1 clock" , RT5665_CHOP_ADC, |
2829 | RT5665_CKGEN_ADC1_SFT, 0, NULL, 0), |
2830 | SND_SOC_DAPM_SUPPLY("ADC2 clock" , RT5665_CHOP_ADC, |
2831 | RT5665_CKGEN_ADC2_SFT, 0, NULL, 0), |
2832 | |
2833 | /* ADC Mux */ |
2834 | SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux" , SND_SOC_NOPM, 0, 0, |
2835 | &rt5665_sto1_dmic_mux), |
2836 | SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux" , SND_SOC_NOPM, 0, 0, |
2837 | &rt5665_sto1_dmic_mux), |
2838 | SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux" , SND_SOC_NOPM, 0, 0, |
2839 | &rt5665_sto1_adc1l_mux), |
2840 | SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux" , SND_SOC_NOPM, 0, 0, |
2841 | &rt5665_sto1_adc1r_mux), |
2842 | SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux" , SND_SOC_NOPM, 0, 0, |
2843 | &rt5665_sto1_adc2l_mux), |
2844 | SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux" , SND_SOC_NOPM, 0, 0, |
2845 | &rt5665_sto1_adc2r_mux), |
2846 | SND_SOC_DAPM_MUX("Stereo1 ADC L Mux" , SND_SOC_NOPM, 0, 0, |
2847 | &rt5665_sto1_adcl_mux), |
2848 | SND_SOC_DAPM_MUX("Stereo1 ADC R Mux" , SND_SOC_NOPM, 0, 0, |
2849 | &rt5665_sto1_adcr_mux), |
2850 | SND_SOC_DAPM_MUX("Stereo1 DD L Mux" , SND_SOC_NOPM, 0, 0, |
2851 | &rt5665_sto1_dd_l_mux), |
2852 | SND_SOC_DAPM_MUX("Stereo1 DD R Mux" , SND_SOC_NOPM, 0, 0, |
2853 | &rt5665_sto1_dd_r_mux), |
2854 | SND_SOC_DAPM_MUX("Mono ADC L2 Mux" , SND_SOC_NOPM, 0, 0, |
2855 | &rt5665_mono_adc_l2_mux), |
2856 | SND_SOC_DAPM_MUX("Mono ADC R2 Mux" , SND_SOC_NOPM, 0, 0, |
2857 | &rt5665_mono_adc_r2_mux), |
2858 | SND_SOC_DAPM_MUX("Mono ADC L1 Mux" , SND_SOC_NOPM, 0, 0, |
2859 | &rt5665_mono_adc_l1_mux), |
2860 | SND_SOC_DAPM_MUX("Mono ADC R1 Mux" , SND_SOC_NOPM, 0, 0, |
2861 | &rt5665_mono_adc_r1_mux), |
2862 | SND_SOC_DAPM_MUX("Mono DMIC L Mux" , SND_SOC_NOPM, 0, 0, |
2863 | &rt5665_mono_dmic_l_mux), |
2864 | SND_SOC_DAPM_MUX("Mono DMIC R Mux" , SND_SOC_NOPM, 0, 0, |
2865 | &rt5665_mono_dmic_r_mux), |
2866 | SND_SOC_DAPM_MUX("Mono ADC L Mux" , SND_SOC_NOPM, 0, 0, |
2867 | &rt5665_mono_adc_l_mux), |
2868 | SND_SOC_DAPM_MUX("Mono ADC R Mux" , SND_SOC_NOPM, 0, 0, |
2869 | &rt5665_mono_adc_r_mux), |
2870 | SND_SOC_DAPM_MUX("Mono DD L Mux" , SND_SOC_NOPM, 0, 0, |
2871 | &rt5665_mono_dd_l_mux), |
2872 | SND_SOC_DAPM_MUX("Mono DD R Mux" , SND_SOC_NOPM, 0, 0, |
2873 | &rt5665_mono_dd_r_mux), |
2874 | SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux" , SND_SOC_NOPM, 0, 0, |
2875 | &rt5665_sto2_dmic_mux), |
2876 | SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux" , SND_SOC_NOPM, 0, 0, |
2877 | &rt5665_sto2_dmic_mux), |
2878 | SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux" , SND_SOC_NOPM, 0, 0, |
2879 | &rt5665_sto2_adc1l_mux), |
2880 | SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux" , SND_SOC_NOPM, 0, 0, |
2881 | &rt5665_sto2_adc1r_mux), |
2882 | SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux" , SND_SOC_NOPM, 0, 0, |
2883 | &rt5665_sto2_adc2l_mux), |
2884 | SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux" , SND_SOC_NOPM, 0, 0, |
2885 | &rt5665_sto2_adc2r_mux), |
2886 | SND_SOC_DAPM_MUX("Stereo2 ADC L Mux" , SND_SOC_NOPM, 0, 0, |
2887 | &rt5665_sto2_adcl_mux), |
2888 | SND_SOC_DAPM_MUX("Stereo2 ADC R Mux" , SND_SOC_NOPM, 0, 0, |
2889 | &rt5665_sto2_adcr_mux), |
2890 | SND_SOC_DAPM_MUX("Stereo2 DD L Mux" , SND_SOC_NOPM, 0, 0, |
2891 | &rt5665_sto2_dd_l_mux), |
2892 | SND_SOC_DAPM_MUX("Stereo2 DD R Mux" , SND_SOC_NOPM, 0, 0, |
2893 | &rt5665_sto2_dd_r_mux), |
2894 | /* ADC Mixer */ |
2895 | SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter" , RT5665_PWR_DIG_2, |
2896 | RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0), |
2897 | SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter" , RT5665_PWR_DIG_2, |
2898 | RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0), |
2899 | SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL" , RT5665_STO1_ADC_DIG_VOL, |
2900 | RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix, |
2901 | ARRAY_SIZE(rt5665_sto1_adc_l_mix)), |
2902 | SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR" , RT5665_STO1_ADC_DIG_VOL, |
2903 | RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix, |
2904 | ARRAY_SIZE(rt5665_sto1_adc_r_mix)), |
2905 | SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL" , RT5665_STO2_ADC_DIG_VOL, |
2906 | RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix, |
2907 | ARRAY_SIZE(rt5665_sto2_adc_l_mix)), |
2908 | SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR" , RT5665_STO2_ADC_DIG_VOL, |
2909 | RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix, |
2910 | ARRAY_SIZE(rt5665_sto2_adc_r_mix)), |
2911 | SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter" , RT5665_PWR_DIG_2, |
2912 | RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0), |
2913 | SND_SOC_DAPM_MIXER("Mono ADC MIXL" , RT5665_MONO_ADC_DIG_VOL, |
2914 | RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix, |
2915 | ARRAY_SIZE(rt5665_mono_adc_l_mix)), |
2916 | SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter" , RT5665_PWR_DIG_2, |
2917 | RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0), |
2918 | SND_SOC_DAPM_MIXER("Mono ADC MIXR" , RT5665_MONO_ADC_DIG_VOL, |
2919 | RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix, |
2920 | ARRAY_SIZE(rt5665_mono_adc_r_mix)), |
2921 | |
2922 | /* ADC PGA */ |
2923 | SND_SOC_DAPM_PGA("Stereo1 ADC MIX" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2924 | SND_SOC_DAPM_PGA("Stereo2 ADC MIX" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2925 | SND_SOC_DAPM_PGA("Mono ADC MIX" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2926 | |
2927 | /* Digital Interface */ |
2928 | SND_SOC_DAPM_SUPPLY("I2S1_1" , RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT, |
2929 | 0, NULL, 0), |
2930 | SND_SOC_DAPM_SUPPLY("I2S1_2" , RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT, |
2931 | 0, NULL, 0), |
2932 | SND_SOC_DAPM_SUPPLY("I2S2_1" , RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT, |
2933 | 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU | |
2934 | SND_SOC_DAPM_POST_PMD), |
2935 | SND_SOC_DAPM_SUPPLY("I2S2_2" , RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT, |
2936 | 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU | |
2937 | SND_SOC_DAPM_POST_PMD), |
2938 | SND_SOC_DAPM_SUPPLY("I2S3" , RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT, |
2939 | 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU | |
2940 | SND_SOC_DAPM_POST_PMD), |
2941 | SND_SOC_DAPM_PGA("IF1 DAC1" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2942 | SND_SOC_DAPM_PGA("IF1 DAC2" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2943 | SND_SOC_DAPM_PGA("IF1 DAC3" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2944 | SND_SOC_DAPM_PGA("IF1 DAC1 L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2945 | SND_SOC_DAPM_PGA("IF1 DAC1 R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2946 | SND_SOC_DAPM_PGA("IF1 DAC2 L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2947 | SND_SOC_DAPM_PGA("IF1 DAC2 R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2948 | SND_SOC_DAPM_PGA("IF1 DAC3 L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2949 | SND_SOC_DAPM_PGA("IF1 DAC3 R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2950 | |
2951 | SND_SOC_DAPM_PGA("IF2_1 DAC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2952 | SND_SOC_DAPM_PGA("IF2_2 DAC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2953 | SND_SOC_DAPM_PGA("IF2_1 DAC L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2954 | SND_SOC_DAPM_PGA("IF2_1 DAC R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2955 | SND_SOC_DAPM_PGA("IF2_2 DAC L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2956 | SND_SOC_DAPM_PGA("IF2_2 DAC R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2957 | SND_SOC_DAPM_PGA("IF2_1 ADC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2958 | SND_SOC_DAPM_PGA("IF2_2 ADC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2959 | |
2960 | SND_SOC_DAPM_PGA("IF3 DAC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2961 | SND_SOC_DAPM_PGA("IF3 DAC L" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2962 | SND_SOC_DAPM_PGA("IF3 DAC R" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2963 | SND_SOC_DAPM_PGA("IF3 ADC" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2964 | |
2965 | /* Digital Interface Select */ |
2966 | SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux" , SND_SOC_NOPM, 0, 0, |
2967 | &rt5665_if1_1_adc1_mux), |
2968 | SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux" , SND_SOC_NOPM, 0, 0, |
2969 | &rt5665_if1_1_adc2_mux), |
2970 | SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux" , SND_SOC_NOPM, 0, 0, |
2971 | &rt5665_if1_1_adc3_mux), |
2972 | SND_SOC_DAPM_PGA("IF1_1_ADC4" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2973 | SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux" , SND_SOC_NOPM, 0, 0, |
2974 | &rt5665_if1_2_adc1_mux), |
2975 | SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux" , SND_SOC_NOPM, 0, 0, |
2976 | &rt5665_if1_2_adc2_mux), |
2977 | SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux" , SND_SOC_NOPM, 0, 0, |
2978 | &rt5665_if1_2_adc3_mux), |
2979 | SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux" , SND_SOC_NOPM, 0, 0, |
2980 | &rt5665_if1_2_adc4_mux), |
2981 | SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux" , SND_SOC_NOPM, 0, 0, |
2982 | &rt5665_tdm1_adc_mux), |
2983 | SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux" , SND_SOC_NOPM, 0, 0, |
2984 | &rt5665_tdm1_adc_mux), |
2985 | SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux" , SND_SOC_NOPM, 0, 0, |
2986 | &rt5665_tdm1_adc_mux), |
2987 | SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux" , SND_SOC_NOPM, 0, 0, |
2988 | &rt5665_tdm1_adc_mux), |
2989 | SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux" , SND_SOC_NOPM, 0, 0, |
2990 | &rt5665_tdm2_adc_mux), |
2991 | SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux" , SND_SOC_NOPM, 0, 0, |
2992 | &rt5665_tdm2_adc_mux), |
2993 | SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux" , SND_SOC_NOPM, 0, 0, |
2994 | &rt5665_tdm2_adc_mux), |
2995 | SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux" , SND_SOC_NOPM, 0, 0, |
2996 | &rt5665_tdm2_adc_mux), |
2997 | SND_SOC_DAPM_MUX("IF2_1 ADC Mux" , SND_SOC_NOPM, 0, 0, |
2998 | &rt5665_if2_1_adc_in_mux), |
2999 | SND_SOC_DAPM_MUX("IF2_2 ADC Mux" , SND_SOC_NOPM, 0, 0, |
3000 | &rt5665_if2_2_adc_in_mux), |
3001 | SND_SOC_DAPM_MUX("IF3 ADC Mux" , SND_SOC_NOPM, 0, 0, |
3002 | &rt5665_if3_adc_in_mux), |
3003 | SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3004 | &rt5665_if1_1_01_adc_swap_mux), |
3005 | SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3006 | &rt5665_if1_1_01_adc_swap_mux), |
3007 | SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3008 | &rt5665_if1_1_23_adc_swap_mux), |
3009 | SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3010 | &rt5665_if1_1_23_adc_swap_mux), |
3011 | SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3012 | &rt5665_if1_1_45_adc_swap_mux), |
3013 | SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3014 | &rt5665_if1_1_45_adc_swap_mux), |
3015 | SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3016 | &rt5665_if1_1_67_adc_swap_mux), |
3017 | SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3018 | &rt5665_if1_1_67_adc_swap_mux), |
3019 | SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3020 | &rt5665_if1_2_01_adc_swap_mux), |
3021 | SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3022 | &rt5665_if1_2_01_adc_swap_mux), |
3023 | SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3024 | &rt5665_if1_2_23_adc_swap_mux), |
3025 | SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3026 | &rt5665_if1_2_23_adc_swap_mux), |
3027 | SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3028 | &rt5665_if1_2_45_adc_swap_mux), |
3029 | SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3030 | &rt5665_if1_2_45_adc_swap_mux), |
3031 | SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3032 | &rt5665_if1_2_67_adc_swap_mux), |
3033 | SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3034 | &rt5665_if1_2_67_adc_swap_mux), |
3035 | SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3036 | &rt5665_if2_1_dac_swap_mux), |
3037 | SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3038 | &rt5665_if2_1_adc_swap_mux), |
3039 | SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3040 | &rt5665_if2_2_dac_swap_mux), |
3041 | SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3042 | &rt5665_if2_2_adc_swap_mux), |
3043 | SND_SOC_DAPM_MUX("IF3 DAC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3044 | &rt5665_if3_dac_swap_mux), |
3045 | SND_SOC_DAPM_MUX("IF3 ADC Swap Mux" , SND_SOC_NOPM, 0, 0, |
3046 | &rt5665_if3_adc_swap_mux), |
3047 | |
3048 | /* Audio Interface */ |
3049 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0" , "AIF1_1 Capture" , |
3050 | 0, SND_SOC_NOPM, 0, 0), |
3051 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1" , "AIF1_1 Capture" , |
3052 | 1, SND_SOC_NOPM, 0, 0), |
3053 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2" , "AIF1_1 Capture" , |
3054 | 2, SND_SOC_NOPM, 0, 0), |
3055 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3" , "AIF1_1 Capture" , |
3056 | 3, SND_SOC_NOPM, 0, 0), |
3057 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4" , "AIF1_1 Capture" , |
3058 | 4, SND_SOC_NOPM, 0, 0), |
3059 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5" , "AIF1_1 Capture" , |
3060 | 5, SND_SOC_NOPM, 0, 0), |
3061 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6" , "AIF1_1 Capture" , |
3062 | 6, SND_SOC_NOPM, 0, 0), |
3063 | SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7" , "AIF1_1 Capture" , |
3064 | 7, SND_SOC_NOPM, 0, 0), |
3065 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0" , "AIF1_2 Capture" , |
3066 | 0, SND_SOC_NOPM, 0, 0), |
3067 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1" , "AIF1_2 Capture" , |
3068 | 1, SND_SOC_NOPM, 0, 0), |
3069 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2" , "AIF1_2 Capture" , |
3070 | 2, SND_SOC_NOPM, 0, 0), |
3071 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3" , "AIF1_2 Capture" , |
3072 | 3, SND_SOC_NOPM, 0, 0), |
3073 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4" , "AIF1_2 Capture" , |
3074 | 4, SND_SOC_NOPM, 0, 0), |
3075 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5" , "AIF1_2 Capture" , |
3076 | 5, SND_SOC_NOPM, 0, 0), |
3077 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6" , "AIF1_2 Capture" , |
3078 | 6, SND_SOC_NOPM, 0, 0), |
3079 | SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7" , "AIF1_2 Capture" , |
3080 | 7, SND_SOC_NOPM, 0, 0), |
3081 | SND_SOC_DAPM_AIF_OUT("AIF2_1TX" , "AIF2_1 Capture" , |
3082 | 0, SND_SOC_NOPM, 0, 0), |
3083 | SND_SOC_DAPM_AIF_OUT("AIF2_2TX" , "AIF2_2 Capture" , |
3084 | 0, SND_SOC_NOPM, 0, 0), |
3085 | SND_SOC_DAPM_AIF_OUT("AIF3TX" , "AIF3 Capture" , |
3086 | 0, SND_SOC_NOPM, 0, 0), |
3087 | SND_SOC_DAPM_AIF_IN("AIF1RX" , "AIF1 Playback" , |
3088 | 0, SND_SOC_NOPM, 0, 0), |
3089 | SND_SOC_DAPM_AIF_IN("AIF2_1RX" , "AIF2_1 Playback" , |
3090 | 0, SND_SOC_NOPM, 0, 0), |
3091 | SND_SOC_DAPM_AIF_IN("AIF2_2RX" , "AIF2_2 Playback" , |
3092 | 0, SND_SOC_NOPM, 0, 0), |
3093 | SND_SOC_DAPM_AIF_IN("AIF3RX" , "AIF3 Playback" , |
3094 | 0, SND_SOC_NOPM, 0, 0), |
3095 | |
3096 | /* Output Side */ |
3097 | /* DAC mixer before sound effect */ |
3098 | SND_SOC_DAPM_MIXER("DAC1 MIXL" , SND_SOC_NOPM, 0, 0, |
3099 | rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)), |
3100 | SND_SOC_DAPM_MIXER("DAC1 MIXR" , SND_SOC_NOPM, 0, 0, |
3101 | rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)), |
3102 | |
3103 | /* DAC channel Mux */ |
3104 | SND_SOC_DAPM_MUX("DAC L1 Mux" , SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux), |
3105 | SND_SOC_DAPM_MUX("DAC R1 Mux" , SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux), |
3106 | SND_SOC_DAPM_MUX("DAC L2 Mux" , SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux), |
3107 | SND_SOC_DAPM_MUX("DAC R2 Mux" , SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux), |
3108 | SND_SOC_DAPM_MUX("DAC L3 Mux" , SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux), |
3109 | SND_SOC_DAPM_MUX("DAC R3 Mux" , SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux), |
3110 | |
3111 | SND_SOC_DAPM_MUX("DAC L1 Source" , SND_SOC_NOPM, 0, 0, |
3112 | &rt5665_alg_dac_l1_mux), |
3113 | SND_SOC_DAPM_MUX("DAC R1 Source" , SND_SOC_NOPM, 0, 0, |
3114 | &rt5665_alg_dac_r1_mux), |
3115 | SND_SOC_DAPM_MUX("DAC L2 Source" , SND_SOC_NOPM, 0, 0, |
3116 | &rt5665_alg_dac_l2_mux), |
3117 | SND_SOC_DAPM_MUX("DAC R2 Source" , SND_SOC_NOPM, 0, 0, |
3118 | &rt5665_alg_dac_r2_mux), |
3119 | |
3120 | /* DAC Mixer */ |
3121 | SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter" , RT5665_PWR_DIG_2, |
3122 | RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0), |
3123 | SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter" , RT5665_PWR_DIG_2, |
3124 | RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0), |
3125 | SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter" , RT5665_PWR_DIG_2, |
3126 | RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0), |
3127 | SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter" , RT5665_PWR_DIG_2, |
3128 | RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0), |
3129 | SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL" , SND_SOC_NOPM, 0, 0, |
3130 | rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)), |
3131 | SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR" , SND_SOC_NOPM, 0, 0, |
3132 | rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)), |
3133 | SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL" , SND_SOC_NOPM, 0, 0, |
3134 | rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)), |
3135 | SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR" , SND_SOC_NOPM, 0, 0, |
3136 | rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)), |
3137 | SND_SOC_DAPM_MIXER("Mono DAC MIXL" , SND_SOC_NOPM, 0, 0, |
3138 | rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)), |
3139 | SND_SOC_DAPM_MIXER("Mono DAC MIXR" , SND_SOC_NOPM, 0, 0, |
3140 | rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)), |
3141 | SND_SOC_DAPM_MUX("DAC MIXL" , SND_SOC_NOPM, 0, 0, |
3142 | &rt5665_dig_dac_mixl_mux), |
3143 | SND_SOC_DAPM_MUX("DAC MIXR" , SND_SOC_NOPM, 0, 0, |
3144 | &rt5665_dig_dac_mixr_mux), |
3145 | |
3146 | /* DACs */ |
3147 | SND_SOC_DAPM_DAC("DAC L1" , NULL, SND_SOC_NOPM, 0, 0), |
3148 | SND_SOC_DAPM_DAC("DAC R1" , NULL, SND_SOC_NOPM, 0, 0), |
3149 | |
3150 | SND_SOC_DAPM_SUPPLY("DAC L2 Power" , RT5665_PWR_DIG_1, |
3151 | RT5665_PWR_DAC_L2_BIT, 0, NULL, 0), |
3152 | SND_SOC_DAPM_SUPPLY("DAC R2 Power" , RT5665_PWR_DIG_1, |
3153 | RT5665_PWR_DAC_R2_BIT, 0, NULL, 0), |
3154 | SND_SOC_DAPM_DAC("DAC L2" , NULL, SND_SOC_NOPM, 0, 0), |
3155 | SND_SOC_DAPM_DAC("DAC R2" , NULL, SND_SOC_NOPM, 0, 0), |
3156 | SND_SOC_DAPM_PGA("DAC1 MIX" , SND_SOC_NOPM, 0, 0, NULL, 0), |
3157 | |
3158 | SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock" , 1, RT5665_CHOP_DAC, |
3159 | RT5665_CKGEN_DAC1_SFT, 0, NULL, 0), |
3160 | SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock" , 1, RT5665_CHOP_DAC, |
3161 | RT5665_CKGEN_DAC2_SFT, 0, NULL, 0), |
3162 | |
3163 | /* OUT Mixer */ |
3164 | SND_SOC_DAPM_MIXER("MONOVOL MIX" , RT5665_PWR_MIXER, RT5665_PWR_MM_BIT, |
3165 | 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)), |
3166 | SND_SOC_DAPM_MIXER("OUT MIXL" , RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT, |
3167 | 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)), |
3168 | SND_SOC_DAPM_MIXER("OUT MIXR" , RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT, |
3169 | 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)), |
3170 | |
3171 | /* Output Volume */ |
3172 | SND_SOC_DAPM_SWITCH("MONOVOL" , RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0, |
3173 | &monovol_switch), |
3174 | SND_SOC_DAPM_SWITCH("OUTVOL L" , RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0, |
3175 | &outvol_l_switch), |
3176 | SND_SOC_DAPM_SWITCH("OUTVOL R" , RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0, |
3177 | &outvol_r_switch), |
3178 | |
3179 | /* MONO/HPO/LOUT */ |
3180 | SND_SOC_DAPM_MIXER("Mono MIX" , SND_SOC_NOPM, 0, 0, rt5665_mono_mix, |
3181 | ARRAY_SIZE(rt5665_mono_mix)), |
3182 | SND_SOC_DAPM_MIXER("LOUT L MIX" , SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix, |
3183 | ARRAY_SIZE(rt5665_lout_l_mix)), |
3184 | SND_SOC_DAPM_MIXER("LOUT R MIX" , SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix, |
3185 | ARRAY_SIZE(rt5665_lout_r_mix)), |
3186 | SND_SOC_DAPM_PGA_S("Mono Amp" , 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT, |
3187 | 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD | |
3188 | SND_SOC_DAPM_PRE_PMU), |
3189 | SND_SOC_DAPM_PGA_S("HP Amp" , 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event, |
3190 | SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), |
3191 | SND_SOC_DAPM_PGA_S("LOUT Amp" , 1, RT5665_PWR_ANLG_1, |
3192 | RT5665_PWR_LM_BIT, 0, rt5665_lout_event, |
3193 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | |
3194 | SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), |
3195 | |
3196 | SND_SOC_DAPM_SUPPLY("Charge Pump" , SND_SOC_NOPM, 0, 0, |
3197 | rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU | |
3198 | SND_SOC_DAPM_POST_PMD), |
3199 | |
3200 | SND_SOC_DAPM_SWITCH("Mono Playback" , SND_SOC_NOPM, 0, 0, |
3201 | &mono_switch), |
3202 | SND_SOC_DAPM_SWITCH("HPO Playback" , SND_SOC_NOPM, 0, 0, |
3203 | &hpo_switch), |
3204 | SND_SOC_DAPM_SWITCH("LOUT L Playback" , SND_SOC_NOPM, 0, 0, |
3205 | &lout_l_switch), |
3206 | SND_SOC_DAPM_SWITCH("LOUT R Playback" , SND_SOC_NOPM, 0, 0, |
3207 | &lout_r_switch), |
3208 | SND_SOC_DAPM_SWITCH("PDM L Playback" , SND_SOC_NOPM, 0, 0, |
3209 | &pdm_l_switch), |
3210 | SND_SOC_DAPM_SWITCH("PDM R Playback" , SND_SOC_NOPM, 0, 0, |
3211 | &pdm_r_switch), |
3212 | |
3213 | /* PDM */ |
3214 | SND_SOC_DAPM_SUPPLY("PDM Power" , RT5665_PWR_DIG_2, |
3215 | RT5665_PWR_PDM1_BIT, 0, NULL, 0), |
3216 | SND_SOC_DAPM_MUX("PDM L Mux" , SND_SOC_NOPM, |
3217 | 0, 1, &rt5665_pdm_l_mux), |
3218 | SND_SOC_DAPM_MUX("PDM R Mux" , SND_SOC_NOPM, |
3219 | 0, 1, &rt5665_pdm_r_mux), |
3220 | |
3221 | /* CLK DET */ |
3222 | SND_SOC_DAPM_SUPPLY("CLKDET SYS" , RT5665_CLK_DET, RT5665_SYS_CLK_DET, |
3223 | 0, NULL, 0), |
3224 | SND_SOC_DAPM_SUPPLY("CLKDET HP" , RT5665_CLK_DET, RT5665_HP_CLK_DET, |
3225 | 0, NULL, 0), |
3226 | SND_SOC_DAPM_SUPPLY("CLKDET MONO" , RT5665_CLK_DET, RT5665_MONO_CLK_DET, |
3227 | 0, NULL, 0), |
3228 | SND_SOC_DAPM_SUPPLY("CLKDET LOUT" , RT5665_CLK_DET, RT5665_LOUT_CLK_DET, |
3229 | 0, NULL, 0), |
3230 | SND_SOC_DAPM_SUPPLY("CLKDET" , RT5665_CLK_DET, RT5665_POW_CLK_DET, |
3231 | 0, NULL, 0), |
3232 | |
3233 | /* Output Lines */ |
3234 | SND_SOC_DAPM_OUTPUT("HPOL" ), |
3235 | SND_SOC_DAPM_OUTPUT("HPOR" ), |
3236 | SND_SOC_DAPM_OUTPUT("LOUTL" ), |
3237 | SND_SOC_DAPM_OUTPUT("LOUTR" ), |
3238 | SND_SOC_DAPM_OUTPUT("MONOOUT" ), |
3239 | SND_SOC_DAPM_OUTPUT("PDML" ), |
3240 | SND_SOC_DAPM_OUTPUT("PDMR" ), |
3241 | }; |
3242 | |
3243 | static const struct snd_soc_dapm_route rt5665_dapm_routes[] = { |
3244 | /*PLL*/ |
3245 | {"ADC Stereo1 Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3246 | {"ADC Stereo2 Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3247 | {"ADC Mono Left Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3248 | {"ADC Mono Right Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3249 | {"DAC Stereo1 Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3250 | {"DAC Stereo2 Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3251 | {"DAC Mono Left Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3252 | {"DAC Mono Right Filter" , NULL, "PLL" , is_sys_clk_from_pll}, |
3253 | |
3254 | /*ASRC*/ |
3255 | {"ADC Stereo1 Filter" , NULL, "ADC STO1 ASRC" , is_using_asrc}, |
3256 | {"ADC Stereo2 Filter" , NULL, "ADC STO2 ASRC" , is_using_asrc}, |
3257 | {"ADC Mono Left Filter" , NULL, "ADC Mono L ASRC" , is_using_asrc}, |
3258 | {"ADC Mono Right Filter" , NULL, "ADC Mono R ASRC" , is_using_asrc}, |
3259 | {"DAC Mono Left Filter" , NULL, "DAC Mono L ASRC" , is_using_asrc}, |
3260 | {"DAC Mono Right Filter" , NULL, "DAC Mono R ASRC" , is_using_asrc}, |
3261 | {"DAC Stereo1 Filter" , NULL, "DAC STO1 ASRC" , is_using_asrc}, |
3262 | {"DAC Stereo2 Filter" , NULL, "DAC STO2 ASRC" , is_using_asrc}, |
3263 | {"I2S1 ASRC" , NULL, "CLKDET" }, |
3264 | {"I2S2 ASRC" , NULL, "CLKDET" }, |
3265 | {"I2S3 ASRC" , NULL, "CLKDET" }, |
3266 | |
3267 | /*Vref*/ |
3268 | {"Mic Det Power" , NULL, "Vref2" }, |
3269 | {"MICBIAS1" , NULL, "Vref1" }, |
3270 | {"MICBIAS1" , NULL, "Vref2" }, |
3271 | {"MICBIAS2" , NULL, "Vref1" }, |
3272 | {"MICBIAS2" , NULL, "Vref2" }, |
3273 | {"MICBIAS3" , NULL, "Vref1" }, |
3274 | {"MICBIAS3" , NULL, "Vref2" }, |
3275 | |
3276 | {"Stereo1 DMIC L Mux" , NULL, "DMIC STO1 ASRC" }, |
3277 | {"Stereo1 DMIC R Mux" , NULL, "DMIC STO1 ASRC" }, |
3278 | {"Stereo2 DMIC L Mux" , NULL, "DMIC STO2 ASRC" }, |
3279 | {"Stereo2 DMIC R Mux" , NULL, "DMIC STO2 ASRC" }, |
3280 | {"Mono DMIC L Mux" , NULL, "DMIC MONO L ASRC" }, |
3281 | {"Mono DMIC R Mux" , NULL, "DMIC MONO R ASRC" }, |
3282 | |
3283 | {"I2S1_1" , NULL, "I2S1 ASRC" }, |
3284 | {"I2S1_2" , NULL, "I2S1 ASRC" }, |
3285 | {"I2S2_1" , NULL, "I2S2 ASRC" }, |
3286 | {"I2S2_2" , NULL, "I2S2 ASRC" }, |
3287 | {"I2S3" , NULL, "I2S3 ASRC" }, |
3288 | |
3289 | {"CLKDET SYS" , NULL, "CLKDET" }, |
3290 | {"CLKDET HP" , NULL, "CLKDET" }, |
3291 | {"CLKDET MONO" , NULL, "CLKDET" }, |
3292 | {"CLKDET LOUT" , NULL, "CLKDET" }, |
3293 | |
3294 | {"IN1P" , NULL, "LDO2" }, |
3295 | {"IN2P" , NULL, "LDO2" }, |
3296 | {"IN3P" , NULL, "LDO2" }, |
3297 | {"IN4P" , NULL, "LDO2" }, |
3298 | |
3299 | {"DMIC1" , NULL, "DMIC L1" }, |
3300 | {"DMIC1" , NULL, "DMIC R1" }, |
3301 | {"DMIC2" , NULL, "DMIC L2" }, |
3302 | {"DMIC2" , NULL, "DMIC R2" }, |
3303 | |
3304 | {"BST1" , NULL, "IN1P" }, |
3305 | {"BST1" , NULL, "IN1N" }, |
3306 | {"BST1" , NULL, "BST1 Power" }, |
3307 | {"BST1" , NULL, "BST1P Power" }, |
3308 | {"BST2" , NULL, "IN2P" }, |
3309 | {"BST2" , NULL, "IN2N" }, |
3310 | {"BST2" , NULL, "BST2 Power" }, |
3311 | {"BST2" , NULL, "BST2P Power" }, |
3312 | {"BST3" , NULL, "IN3P" }, |
3313 | {"BST3" , NULL, "IN3N" }, |
3314 | {"BST3" , NULL, "BST3 Power" }, |
3315 | {"BST3" , NULL, "BST3P Power" }, |
3316 | {"BST4" , NULL, "IN4P" }, |
3317 | {"BST4" , NULL, "IN4N" }, |
3318 | {"BST4" , NULL, "BST4 Power" }, |
3319 | {"BST4" , NULL, "BST4P Power" }, |
3320 | {"BST1 CBJ" , NULL, "IN1P" }, |
3321 | {"BST1 CBJ" , NULL, "IN1N" }, |
3322 | {"BST1 CBJ" , NULL, "CBJ Power" }, |
3323 | {"CBJ Power" , NULL, "Vref2" }, |
3324 | |
3325 | {"INL VOL" , NULL, "IN3P" }, |
3326 | {"INR VOL" , NULL, "IN3N" }, |
3327 | |
3328 | {"RECMIX1L" , "CBJ Switch" , "BST1 CBJ" }, |
3329 | {"RECMIX1L" , "INL Switch" , "INL VOL" }, |
3330 | {"RECMIX1L" , "INR Switch" , "INR VOL" }, |
3331 | {"RECMIX1L" , "BST4 Switch" , "BST4" }, |
3332 | {"RECMIX1L" , "BST3 Switch" , "BST3" }, |
3333 | {"RECMIX1L" , "BST2 Switch" , "BST2" }, |
3334 | {"RECMIX1L" , "BST1 Switch" , "BST1" }, |
3335 | {"RECMIX1L" , NULL, "RECMIX1L Power" }, |
3336 | |
3337 | {"RECMIX1R" , "MONOVOL Switch" , "MONOVOL" }, |
3338 | {"RECMIX1R" , "INR Switch" , "INR VOL" }, |
3339 | {"RECMIX1R" , "BST4 Switch" , "BST4" }, |
3340 | {"RECMIX1R" , "BST3 Switch" , "BST3" }, |
3341 | {"RECMIX1R" , "BST2 Switch" , "BST2" }, |
3342 | {"RECMIX1R" , "BST1 Switch" , "BST1" }, |
3343 | {"RECMIX1R" , NULL, "RECMIX1R Power" }, |
3344 | |
3345 | {"RECMIX2L" , "CBJ Switch" , "BST1 CBJ" }, |
3346 | {"RECMIX2L" , "INL Switch" , "INL VOL" }, |
3347 | {"RECMIX2L" , "INR Switch" , "INR VOL" }, |
3348 | {"RECMIX2L" , "BST4 Switch" , "BST4" }, |
3349 | {"RECMIX2L" , "BST3 Switch" , "BST3" }, |
3350 | {"RECMIX2L" , "BST2 Switch" , "BST2" }, |
3351 | {"RECMIX2L" , "BST1 Switch" , "BST1" }, |
3352 | {"RECMIX2L" , NULL, "RECMIX2L Power" }, |
3353 | |
3354 | {"RECMIX2R" , "MONOVOL Switch" , "MONOVOL" }, |
3355 | {"RECMIX2R" , "INL Switch" , "INL VOL" }, |
3356 | {"RECMIX2R" , "INR Switch" , "INR VOL" }, |
3357 | {"RECMIX2R" , "BST4 Switch" , "BST4" }, |
3358 | {"RECMIX2R" , "BST3 Switch" , "BST3" }, |
3359 | {"RECMIX2R" , "BST2 Switch" , "BST2" }, |
3360 | {"RECMIX2R" , "BST1 Switch" , "BST1" }, |
3361 | {"RECMIX2R" , NULL, "RECMIX2R Power" }, |
3362 | |
3363 | {"ADC1 L" , NULL, "RECMIX1L" }, |
3364 | {"ADC1 L" , NULL, "ADC1 L Power" }, |
3365 | {"ADC1 L" , NULL, "ADC1 clock" }, |
3366 | {"ADC1 R" , NULL, "RECMIX1R" }, |
3367 | {"ADC1 R" , NULL, "ADC1 R Power" }, |
3368 | {"ADC1 R" , NULL, "ADC1 clock" }, |
3369 | |
3370 | {"ADC2 L" , NULL, "RECMIX2L" }, |
3371 | {"ADC2 L" , NULL, "ADC2 L Power" }, |
3372 | {"ADC2 L" , NULL, "ADC2 clock" }, |
3373 | {"ADC2 R" , NULL, "RECMIX2R" }, |
3374 | {"ADC2 R" , NULL, "ADC2 R Power" }, |
3375 | {"ADC2 R" , NULL, "ADC2 clock" }, |
3376 | |
3377 | {"DMIC L1" , NULL, "DMIC CLK" }, |
3378 | {"DMIC L1" , NULL, "DMIC1 Power" }, |
3379 | {"DMIC R1" , NULL, "DMIC CLK" }, |
3380 | {"DMIC R1" , NULL, "DMIC1 Power" }, |
3381 | {"DMIC L2" , NULL, "DMIC CLK" }, |
3382 | {"DMIC L2" , NULL, "DMIC2 Power" }, |
3383 | {"DMIC R2" , NULL, "DMIC CLK" }, |
3384 | {"DMIC R2" , NULL, "DMIC2 Power" }, |
3385 | |
3386 | {"Stereo1 DMIC L Mux" , "DMIC1" , "DMIC L1" }, |
3387 | {"Stereo1 DMIC L Mux" , "DMIC2" , "DMIC L2" }, |
3388 | |
3389 | {"Stereo1 DMIC R Mux" , "DMIC1" , "DMIC R1" }, |
3390 | {"Stereo1 DMIC R Mux" , "DMIC2" , "DMIC R2" }, |
3391 | |
3392 | {"Mono DMIC L Mux" , "DMIC1 L" , "DMIC L1" }, |
3393 | {"Mono DMIC L Mux" , "DMIC2 L" , "DMIC L2" }, |
3394 | |
3395 | {"Mono DMIC R Mux" , "DMIC1 R" , "DMIC R1" }, |
3396 | {"Mono DMIC R Mux" , "DMIC2 R" , "DMIC R2" }, |
3397 | |
3398 | {"Stereo2 DMIC L Mux" , "DMIC1" , "DMIC L1" }, |
3399 | {"Stereo2 DMIC L Mux" , "DMIC2" , "DMIC L2" }, |
3400 | |
3401 | {"Stereo2 DMIC R Mux" , "DMIC1" , "DMIC R1" }, |
3402 | {"Stereo2 DMIC R Mux" , "DMIC2" , "DMIC R2" }, |
3403 | |
3404 | {"Stereo1 ADC L Mux" , "ADC1 L" , "ADC1 L" }, |
3405 | {"Stereo1 ADC L Mux" , "ADC1 R" , "ADC1 R" }, |
3406 | {"Stereo1 ADC L Mux" , "ADC2 L" , "ADC2 L" }, |
3407 | {"Stereo1 ADC L Mux" , "ADC2 R" , "ADC2 R" }, |
3408 | {"Stereo1 ADC R Mux" , "ADC1 L" , "ADC1 L" }, |
3409 | {"Stereo1 ADC R Mux" , "ADC1 R" , "ADC1 R" }, |
3410 | {"Stereo1 ADC R Mux" , "ADC2 L" , "ADC2 L" }, |
3411 | {"Stereo1 ADC R Mux" , "ADC2 R" , "ADC2 R" }, |
3412 | |
3413 | {"Stereo1 DD L Mux" , "STO2 DAC" , "Stereo2 DAC MIXL" }, |
3414 | {"Stereo1 DD L Mux" , "MONO DAC" , "Mono DAC MIXL" }, |
3415 | |
3416 | {"Stereo1 DD R Mux" , "STO2 DAC" , "Stereo2 DAC MIXR" }, |
3417 | {"Stereo1 DD R Mux" , "MONO DAC" , "Mono DAC MIXR" }, |
3418 | |
3419 | {"Stereo1 ADC L1 Mux" , "ADC" , "Stereo1 ADC L Mux" }, |
3420 | {"Stereo1 ADC L1 Mux" , "DD Mux" , "Stereo1 DD L Mux" }, |
3421 | {"Stereo1 ADC L2 Mux" , "DMIC" , "Stereo1 DMIC L Mux" }, |
3422 | {"Stereo1 ADC L2 Mux" , "DAC MIX" , "DAC MIXL" }, |
3423 | |
3424 | {"Stereo1 ADC R1 Mux" , "ADC" , "Stereo1 ADC R Mux" }, |
3425 | {"Stereo1 ADC R1 Mux" , "DD Mux" , "Stereo1 DD R Mux" }, |
3426 | {"Stereo1 ADC R2 Mux" , "DMIC" , "Stereo1 DMIC R Mux" }, |
3427 | {"Stereo1 ADC R2 Mux" , "DAC MIX" , "DAC MIXR" }, |
3428 | |
3429 | {"Mono ADC L Mux" , "ADC1 L" , "ADC1 L" }, |
3430 | {"Mono ADC L Mux" , "ADC1 R" , "ADC1 R" }, |
3431 | {"Mono ADC L Mux" , "ADC2 L" , "ADC2 L" }, |
3432 | {"Mono ADC L Mux" , "ADC2 R" , "ADC2 R" }, |
3433 | |
3434 | {"Mono ADC R Mux" , "ADC1 L" , "ADC1 L" }, |
3435 | {"Mono ADC R Mux" , "ADC1 R" , "ADC1 R" }, |
3436 | {"Mono ADC R Mux" , "ADC2 L" , "ADC2 L" }, |
3437 | {"Mono ADC R Mux" , "ADC2 R" , "ADC2 R" }, |
3438 | |
3439 | {"Mono DD L Mux" , "STO2 DAC" , "Stereo2 DAC MIXL" }, |
3440 | {"Mono DD L Mux" , "MONO DAC" , "Mono DAC MIXL" }, |
3441 | |
3442 | {"Mono DD R Mux" , "STO2 DAC" , "Stereo2 DAC MIXR" }, |
3443 | {"Mono DD R Mux" , "MONO DAC" , "Mono DAC MIXR" }, |
3444 | |
3445 | {"Mono ADC L2 Mux" , "DMIC" , "Mono DMIC L Mux" }, |
3446 | {"Mono ADC L2 Mux" , "DAC MIXL" , "DAC MIXL" }, |
3447 | {"Mono ADC L1 Mux" , "DD Mux" , "Mono DD L Mux" }, |
3448 | {"Mono ADC L1 Mux" , "ADC" , "Mono ADC L Mux" }, |
3449 | |
3450 | {"Mono ADC R1 Mux" , "DD Mux" , "Mono DD R Mux" }, |
3451 | {"Mono ADC R1 Mux" , "ADC" , "Mono ADC R Mux" }, |
3452 | {"Mono ADC R2 Mux" , "DMIC" , "Mono DMIC R Mux" }, |
3453 | {"Mono ADC R2 Mux" , "DAC MIXR" , "DAC MIXR" }, |
3454 | |
3455 | {"Stereo2 ADC L Mux" , "ADC1 L" , "ADC1 L" }, |
3456 | {"Stereo2 ADC L Mux" , "ADC2 L" , "ADC2 L" }, |
3457 | {"Stereo2 ADC L Mux" , "ADC1 R" , "ADC1 R" }, |
3458 | {"Stereo2 ADC R Mux" , "ADC1 L" , "ADC1 L" }, |
3459 | {"Stereo2 ADC R Mux" , "ADC2 L" , "ADC2 L" }, |
3460 | {"Stereo2 ADC R Mux" , "ADC1 R" , "ADC1 R" }, |
3461 | |
3462 | {"Stereo2 DD L Mux" , "STO2 DAC" , "Stereo2 DAC MIXL" }, |
3463 | {"Stereo2 DD L Mux" , "MONO DAC" , "Mono DAC MIXL" }, |
3464 | |
3465 | {"Stereo2 DD R Mux" , "STO2 DAC" , "Stereo2 DAC MIXR" }, |
3466 | {"Stereo2 DD R Mux" , "MONO DAC" , "Mono DAC MIXR" }, |
3467 | |
3468 | {"Stereo2 ADC L1 Mux" , "ADC" , "Stereo2 ADC L Mux" }, |
3469 | {"Stereo2 ADC L1 Mux" , "DD Mux" , "Stereo2 DD L Mux" }, |
3470 | {"Stereo2 ADC L2 Mux" , "DMIC" , "Stereo2 DMIC L Mux" }, |
3471 | {"Stereo2 ADC L2 Mux" , "DAC MIX" , "DAC MIXL" }, |
3472 | |
3473 | {"Stereo2 ADC R1 Mux" , "ADC" , "Stereo2 ADC R Mux" }, |
3474 | {"Stereo2 ADC R1 Mux" , "DD Mux" , "Stereo2 DD R Mux" }, |
3475 | {"Stereo2 ADC R2 Mux" , "DMIC" , "Stereo2 DMIC R Mux" }, |
3476 | {"Stereo2 ADC R2 Mux" , "DAC MIX" , "DAC MIXR" }, |
3477 | |
3478 | {"Stereo1 ADC MIXL" , "ADC1 Switch" , "Stereo1 ADC L1 Mux" }, |
3479 | {"Stereo1 ADC MIXL" , "ADC2 Switch" , "Stereo1 ADC L2 Mux" }, |
3480 | {"Stereo1 ADC MIXL" , NULL, "ADC Stereo1 Filter" }, |
3481 | |
3482 | {"Stereo1 ADC MIXR" , "ADC1 Switch" , "Stereo1 ADC R1 Mux" }, |
3483 | {"Stereo1 ADC MIXR" , "ADC2 Switch" , "Stereo1 ADC R2 Mux" }, |
3484 | {"Stereo1 ADC MIXR" , NULL, "ADC Stereo1 Filter" }, |
3485 | |
3486 | {"Mono ADC MIXL" , "ADC1 Switch" , "Mono ADC L1 Mux" }, |
3487 | {"Mono ADC MIXL" , "ADC2 Switch" , "Mono ADC L2 Mux" }, |
3488 | {"Mono ADC MIXL" , NULL, "ADC Mono Left Filter" }, |
3489 | |
3490 | {"Mono ADC MIXR" , "ADC1 Switch" , "Mono ADC R1 Mux" }, |
3491 | {"Mono ADC MIXR" , "ADC2 Switch" , "Mono ADC R2 Mux" }, |
3492 | {"Mono ADC MIXR" , NULL, "ADC Mono Right Filter" }, |
3493 | |
3494 | {"Stereo2 ADC MIXL" , "ADC1 Switch" , "Stereo2 ADC L1 Mux" }, |
3495 | {"Stereo2 ADC MIXL" , "ADC2 Switch" , "Stereo2 ADC L2 Mux" }, |
3496 | {"Stereo2 ADC MIXL" , NULL, "ADC Stereo2 Filter" }, |
3497 | |
3498 | {"Stereo2 ADC MIXR" , "ADC1 Switch" , "Stereo2 ADC R1 Mux" }, |
3499 | {"Stereo2 ADC MIXR" , "ADC2 Switch" , "Stereo2 ADC R2 Mux" }, |
3500 | {"Stereo2 ADC MIXR" , NULL, "ADC Stereo2 Filter" }, |
3501 | |
3502 | {"Stereo1 ADC MIX" , NULL, "Stereo1 ADC MIXL" }, |
3503 | {"Stereo1 ADC MIX" , NULL, "Stereo1 ADC MIXR" }, |
3504 | {"Stereo2 ADC MIX" , NULL, "Stereo2 ADC MIXL" }, |
3505 | {"Stereo2 ADC MIX" , NULL, "Stereo2 ADC MIXR" }, |
3506 | {"Mono ADC MIX" , NULL, "Mono ADC MIXL" }, |
3507 | {"Mono ADC MIX" , NULL, "Mono ADC MIXR" }, |
3508 | |
3509 | {"IF1_1_ADC1 Mux" , "STO1 ADC" , "Stereo1 ADC MIX" }, |
3510 | {"IF1_1_ADC1 Mux" , "IF2_1 DAC" , "IF2_1 DAC" }, |
3511 | {"IF1_1_ADC2 Mux" , "STO2 ADC" , "Stereo2 ADC MIX" }, |
3512 | {"IF1_1_ADC2 Mux" , "IF2_2 DAC" , "IF2_2 DAC" }, |
3513 | {"IF1_1_ADC3 Mux" , "MONO ADC" , "Mono ADC MIX" }, |
3514 | {"IF1_1_ADC3 Mux" , "IF3 DAC" , "IF3 DAC" }, |
3515 | {"IF1_1_ADC4" , NULL, "DAC1 MIX" }, |
3516 | |
3517 | {"IF1_2_ADC1 Mux" , "STO1 ADC" , "Stereo1 ADC MIX" }, |
3518 | {"IF1_2_ADC1 Mux" , "IF1 DAC" , "IF1 DAC1" }, |
3519 | {"IF1_2_ADC2 Mux" , "STO2 ADC" , "Stereo2 ADC MIX" }, |
3520 | {"IF1_2_ADC2 Mux" , "IF2_1 DAC" , "IF2_1 DAC" }, |
3521 | {"IF1_2_ADC3 Mux" , "MONO ADC" , "Mono ADC MIX" }, |
3522 | {"IF1_2_ADC3 Mux" , "IF2_2 DAC" , "IF2_2 DAC" }, |
3523 | {"IF1_2_ADC4 Mux" , "DAC1" , "DAC1 MIX" }, |
3524 | {"IF1_2_ADC4 Mux" , "IF3 DAC" , "IF3 DAC" }, |
3525 | |
3526 | {"TDM1 slot 01 Data Mux" , "1234" , "IF1_1_ADC1 Mux" }, |
3527 | {"TDM1 slot 01 Data Mux" , "1243" , "IF1_1_ADC1 Mux" }, |
3528 | {"TDM1 slot 01 Data Mux" , "1324" , "IF1_1_ADC1 Mux" }, |
3529 | {"TDM1 slot 01 Data Mux" , "1342" , "IF1_1_ADC1 Mux" }, |
3530 | {"TDM1 slot 01 Data Mux" , "1432" , "IF1_1_ADC1 Mux" }, |
3531 | {"TDM1 slot 01 Data Mux" , "1423" , "IF1_1_ADC1 Mux" }, |
3532 | {"TDM1 slot 01 Data Mux" , "2134" , "IF1_1_ADC2 Mux" }, |
3533 | {"TDM1 slot 01 Data Mux" , "2143" , "IF1_1_ADC2 Mux" }, |
3534 | {"TDM1 slot 01 Data Mux" , "2314" , "IF1_1_ADC2 Mux" }, |
3535 | {"TDM1 slot 01 Data Mux" , "2341" , "IF1_1_ADC2 Mux" }, |
3536 | {"TDM1 slot 01 Data Mux" , "2431" , "IF1_1_ADC2 Mux" }, |
3537 | {"TDM1 slot 01 Data Mux" , "2413" , "IF1_1_ADC2 Mux" }, |
3538 | {"TDM1 slot 01 Data Mux" , "3124" , "IF1_1_ADC3 Mux" }, |
3539 | {"TDM1 slot 01 Data Mux" , "3142" , "IF1_1_ADC3 Mux" }, |
3540 | {"TDM1 slot 01 Data Mux" , "3214" , "IF1_1_ADC3 Mux" }, |
3541 | {"TDM1 slot 01 Data Mux" , "3241" , "IF1_1_ADC3 Mux" }, |
3542 | {"TDM1 slot 01 Data Mux" , "3412" , "IF1_1_ADC3 Mux" }, |
3543 | {"TDM1 slot 01 Data Mux" , "3421" , "IF1_1_ADC3 Mux" }, |
3544 | {"TDM1 slot 01 Data Mux" , "4123" , "IF1_1_ADC4" }, |
3545 | {"TDM1 slot 01 Data Mux" , "4132" , "IF1_1_ADC4" }, |
3546 | {"TDM1 slot 01 Data Mux" , "4213" , "IF1_1_ADC4" }, |
3547 | {"TDM1 slot 01 Data Mux" , "4231" , "IF1_1_ADC4" }, |
3548 | {"TDM1 slot 01 Data Mux" , "4312" , "IF1_1_ADC4" }, |
3549 | {"TDM1 slot 01 Data Mux" , "4321" , "IF1_1_ADC4" }, |
3550 | {"TDM1 slot 01 Data Mux" , NULL, "I2S1_1" }, |
3551 | |
3552 | {"TDM1 slot 23 Data Mux" , "1234" , "IF1_1_ADC2 Mux" }, |
3553 | {"TDM1 slot 23 Data Mux" , "1243" , "IF1_1_ADC2 Mux" }, |
3554 | {"TDM1 slot 23 Data Mux" , "1324" , "IF1_1_ADC3 Mux" }, |
3555 | {"TDM1 slot 23 Data Mux" , "1342" , "IF1_1_ADC3 Mux" }, |
3556 | {"TDM1 slot 23 Data Mux" , "1432" , "IF1_1_ADC4" }, |
3557 | {"TDM1 slot 23 Data Mux" , "1423" , "IF1_1_ADC4" }, |
3558 | {"TDM1 slot 23 Data Mux" , "2134" , "IF1_1_ADC1 Mux" }, |
3559 | {"TDM1 slot 23 Data Mux" , "2143" , "IF1_1_ADC1 Mux" }, |
3560 | {"TDM1 slot 23 Data Mux" , "2314" , "IF1_1_ADC3 Mux" }, |
3561 | {"TDM1 slot 23 Data Mux" , "2341" , "IF1_1_ADC3 Mux" }, |
3562 | {"TDM1 slot 23 Data Mux" , "2431" , "IF1_1_ADC4" }, |
3563 | {"TDM1 slot 23 Data Mux" , "2413" , "IF1_1_ADC4" }, |
3564 | {"TDM1 slot 23 Data Mux" , "3124" , "IF1_1_ADC1 Mux" }, |
3565 | {"TDM1 slot 23 Data Mux" , "3142" , "IF1_1_ADC1 Mux" }, |
3566 | {"TDM1 slot 23 Data Mux" , "3214" , "IF1_1_ADC2 Mux" }, |
3567 | {"TDM1 slot 23 Data Mux" , "3241" , "IF1_1_ADC2 Mux" }, |
3568 | {"TDM1 slot 23 Data Mux" , "3412" , "IF1_1_ADC4" }, |
3569 | {"TDM1 slot 23 Data Mux" , "3421" , "IF1_1_ADC4" }, |
3570 | {"TDM1 slot 23 Data Mux" , "4123" , "IF1_1_ADC1 Mux" }, |
3571 | {"TDM1 slot 23 Data Mux" , "4132" , "IF1_1_ADC1 Mux" }, |
3572 | {"TDM1 slot 23 Data Mux" , "4213" , "IF1_1_ADC2 Mux" }, |
3573 | {"TDM1 slot 23 Data Mux" , "4231" , "IF1_1_ADC2 Mux" }, |
3574 | {"TDM1 slot 23 Data Mux" , "4312" , "IF1_1_ADC3 Mux" }, |
3575 | {"TDM1 slot 23 Data Mux" , "4321" , "IF1_1_ADC3 Mux" }, |
3576 | {"TDM1 slot 23 Data Mux" , NULL, "I2S1_1" }, |
3577 | |
3578 | {"TDM1 slot 45 Data Mux" , "1234" , "IF1_1_ADC3 Mux" }, |
3579 | {"TDM1 slot 45 Data Mux" , "1243" , "IF1_1_ADC4" }, |
3580 | {"TDM1 slot 45 Data Mux" , "1324" , "IF1_1_ADC2 Mux" }, |
3581 | {"TDM1 slot 45 Data Mux" , "1342" , "IF1_1_ADC4" }, |
3582 | {"TDM1 slot 45 Data Mux" , "1432" , "IF1_1_ADC3 Mux" }, |
3583 | {"TDM1 slot 45 Data Mux" , "1423" , "IF1_1_ADC2 Mux" }, |
3584 | {"TDM1 slot 45 Data Mux" , "2134" , "IF1_1_ADC3 Mux" }, |
3585 | {"TDM1 slot 45 Data Mux" , "2143" , "IF1_1_ADC4" }, |
3586 | {"TDM1 slot 45 Data Mux" , "2314" , "IF1_1_ADC1 Mux" }, |
3587 | {"TDM1 slot 45 Data Mux" , "2341" , "IF1_1_ADC4" }, |
3588 | {"TDM1 slot 45 Data Mux" , "2431" , "IF1_1_ADC3 Mux" }, |
3589 | {"TDM1 slot 45 Data Mux" , "2413" , "IF1_1_ADC1 Mux" }, |
3590 | {"TDM1 slot 45 Data Mux" , "3124" , "IF1_1_ADC2 Mux" }, |
3591 | {"TDM1 slot 45 Data Mux" , "3142" , "IF1_1_ADC4" }, |
3592 | {"TDM1 slot 45 Data Mux" , "3214" , "IF1_1_ADC1 Mux" }, |
3593 | {"TDM1 slot 45 Data Mux" , "3241" , "IF1_1_ADC4" }, |
3594 | {"TDM1 slot 45 Data Mux" , "3412" , "IF1_1_ADC1 Mux" }, |
3595 | {"TDM1 slot 45 Data Mux" , "3421" , "IF1_1_ADC2 Mux" }, |
3596 | {"TDM1 slot 45 Data Mux" , "4123" , "IF1_1_ADC2 Mux" }, |
3597 | {"TDM1 slot 45 Data Mux" , "4132" , "IF1_1_ADC3 Mux" }, |
3598 | {"TDM1 slot 45 Data Mux" , "4213" , "IF1_1_ADC1 Mux" }, |
3599 | {"TDM1 slot 45 Data Mux" , "4231" , "IF1_1_ADC3 Mux" }, |
3600 | {"TDM1 slot 45 Data Mux" , "4312" , "IF1_1_ADC1 Mux" }, |
3601 | {"TDM1 slot 45 Data Mux" , "4321" , "IF1_1_ADC2 Mux" }, |
3602 | {"TDM1 slot 45 Data Mux" , NULL, "I2S1_1" }, |
3603 | |
3604 | {"TDM1 slot 67 Data Mux" , "1234" , "IF1_1_ADC4" }, |
3605 | {"TDM1 slot 67 Data Mux" , "1243" , "IF1_1_ADC3 Mux" }, |
3606 | {"TDM1 slot 67 Data Mux" , "1324" , "IF1_1_ADC4" }, |
3607 | {"TDM1 slot 67 Data Mux" , "1342" , "IF1_1_ADC2 Mux" }, |
3608 | {"TDM1 slot 67 Data Mux" , "1432" , "IF1_1_ADC2 Mux" }, |
3609 | {"TDM1 slot 67 Data Mux" , "1423" , "IF1_1_ADC3 Mux" }, |
3610 | {"TDM1 slot 67 Data Mux" , "2134" , "IF1_1_ADC4" }, |
3611 | {"TDM1 slot 67 Data Mux" , "2143" , "IF1_1_ADC3 Mux" }, |
3612 | {"TDM1 slot 67 Data Mux" , "2314" , "IF1_1_ADC4" }, |
3613 | {"TDM1 slot 67 Data Mux" , "2341" , "IF1_1_ADC1 Mux" }, |
3614 | {"TDM1 slot 67 Data Mux" , "2431" , "IF1_1_ADC1 Mux" }, |
3615 | {"TDM1 slot 67 Data Mux" , "2413" , "IF1_1_ADC3 Mux" }, |
3616 | {"TDM1 slot 67 Data Mux" , "3124" , "IF1_1_ADC4" }, |
3617 | {"TDM1 slot 67 Data Mux" , "3142" , "IF1_1_ADC2 Mux" }, |
3618 | {"TDM1 slot 67 Data Mux" , "3214" , "IF1_1_ADC4" }, |
3619 | {"TDM1 slot 67 Data Mux" , "3241" , "IF1_1_ADC1 Mux" }, |
3620 | {"TDM1 slot 67 Data Mux" , "3412" , "IF1_1_ADC2 Mux" }, |
3621 | {"TDM1 slot 67 Data Mux" , "3421" , "IF1_1_ADC1 Mux" }, |
3622 | {"TDM1 slot 67 Data Mux" , "4123" , "IF1_1_ADC3 Mux" }, |
3623 | {"TDM1 slot 67 Data Mux" , "4132" , "IF1_1_ADC2 Mux" }, |
3624 | {"TDM1 slot 67 Data Mux" , "4213" , "IF1_1_ADC3 Mux" }, |
3625 | {"TDM1 slot 67 Data Mux" , "4231" , "IF1_1_ADC1 Mux" }, |
3626 | {"TDM1 slot 67 Data Mux" , "4312" , "IF1_1_ADC2 Mux" }, |
3627 | {"TDM1 slot 67 Data Mux" , "4321" , "IF1_1_ADC1 Mux" }, |
3628 | {"TDM1 slot 67 Data Mux" , NULL, "I2S1_1" }, |
3629 | |
3630 | |
3631 | {"TDM2 slot 01 Data Mux" , "1234" , "IF1_2_ADC1 Mux" }, |
3632 | {"TDM2 slot 01 Data Mux" , "1243" , "IF1_2_ADC1 Mux" }, |
3633 | {"TDM2 slot 01 Data Mux" , "1324" , "IF1_2_ADC1 Mux" }, |
3634 | {"TDM2 slot 01 Data Mux" , "1342" , "IF1_2_ADC1 Mux" }, |
3635 | {"TDM2 slot 01 Data Mux" , "1432" , "IF1_2_ADC1 Mux" }, |
3636 | {"TDM2 slot 01 Data Mux" , "1423" , "IF1_2_ADC1 Mux" }, |
3637 | {"TDM2 slot 01 Data Mux" , "2134" , "IF1_2_ADC2 Mux" }, |
3638 | {"TDM2 slot 01 Data Mux" , "2143" , "IF1_2_ADC2 Mux" }, |
3639 | {"TDM2 slot 01 Data Mux" , "2314" , "IF1_2_ADC2 Mux" }, |
3640 | {"TDM2 slot 01 Data Mux" , "2341" , "IF1_2_ADC2 Mux" }, |
3641 | {"TDM2 slot 01 Data Mux" , "2431" , "IF1_2_ADC2 Mux" }, |
3642 | {"TDM2 slot 01 Data Mux" , "2413" , "IF1_2_ADC2 Mux" }, |
3643 | {"TDM2 slot 01 Data Mux" , "3124" , "IF1_2_ADC3 Mux" }, |
3644 | {"TDM2 slot 01 Data Mux" , "3142" , "IF1_2_ADC3 Mux" }, |
3645 | {"TDM2 slot 01 Data Mux" , "3214" , "IF1_2_ADC3 Mux" }, |
3646 | {"TDM2 slot 01 Data Mux" , "3241" , "IF1_2_ADC3 Mux" }, |
3647 | {"TDM2 slot 01 Data Mux" , "3412" , "IF1_2_ADC3 Mux" }, |
3648 | {"TDM2 slot 01 Data Mux" , "3421" , "IF1_2_ADC3 Mux" }, |
3649 | {"TDM2 slot 01 Data Mux" , "4123" , "IF1_2_ADC4 Mux" }, |
3650 | {"TDM2 slot 01 Data Mux" , "4132" , "IF1_2_ADC4 Mux" }, |
3651 | {"TDM2 slot 01 Data Mux" , "4213" , "IF1_2_ADC4 Mux" }, |
3652 | {"TDM2 slot 01 Data Mux" , "4231" , "IF1_2_ADC4 Mux" }, |
3653 | {"TDM2 slot 01 Data Mux" , "4312" , "IF1_2_ADC4 Mux" }, |
3654 | {"TDM2 slot 01 Data Mux" , "4321" , "IF1_2_ADC4 Mux" }, |
3655 | {"TDM2 slot 01 Data Mux" , NULL, "I2S1_2" }, |
3656 | |
3657 | {"TDM2 slot 23 Data Mux" , "1234" , "IF1_2_ADC2 Mux" }, |
3658 | {"TDM2 slot 23 Data Mux" , "1243" , "IF1_2_ADC2 Mux" }, |
3659 | {"TDM2 slot 23 Data Mux" , "1324" , "IF1_2_ADC3 Mux" }, |
3660 | {"TDM2 slot 23 Data Mux" , "1342" , "IF1_2_ADC3 Mux" }, |
3661 | {"TDM2 slot 23 Data Mux" , "1432" , "IF1_2_ADC4 Mux" }, |
3662 | {"TDM2 slot 23 Data Mux" , "1423" , "IF1_2_ADC4 Mux" }, |
3663 | {"TDM2 slot 23 Data Mux" , "2134" , "IF1_2_ADC1 Mux" }, |
3664 | {"TDM2 slot 23 Data Mux" , "2143" , "IF1_2_ADC1 Mux" }, |
3665 | {"TDM2 slot 23 Data Mux" , "2314" , "IF1_2_ADC3 Mux" }, |
3666 | {"TDM2 slot 23 Data Mux" , "2341" , "IF1_2_ADC3 Mux" }, |
3667 | {"TDM2 slot 23 Data Mux" , "2431" , "IF1_2_ADC4 Mux" }, |
3668 | {"TDM2 slot 23 Data Mux" , "2413" , "IF1_2_ADC4 Mux" }, |
3669 | {"TDM2 slot 23 Data Mux" , "3124" , "IF1_2_ADC1 Mux" }, |
3670 | {"TDM2 slot 23 Data Mux" , "3142" , "IF1_2_ADC1 Mux" }, |
3671 | {"TDM2 slot 23 Data Mux" , "3214" , "IF1_2_ADC2 Mux" }, |
3672 | {"TDM2 slot 23 Data Mux" , "3241" , "IF1_2_ADC2 Mux" }, |
3673 | {"TDM2 slot 23 Data Mux" , "3412" , "IF1_2_ADC4 Mux" }, |
3674 | {"TDM2 slot 23 Data Mux" , "3421" , "IF1_2_ADC4 Mux" }, |
3675 | {"TDM2 slot 23 Data Mux" , "4123" , "IF1_2_ADC1 Mux" }, |
3676 | {"TDM2 slot 23 Data Mux" , "4132" , "IF1_2_ADC1 Mux" }, |
3677 | {"TDM2 slot 23 Data Mux" , "4213" , "IF1_2_ADC2 Mux" }, |
3678 | {"TDM2 slot 23 Data Mux" , "4231" , "IF1_2_ADC2 Mux" }, |
3679 | {"TDM2 slot 23 Data Mux" , "4312" , "IF1_2_ADC3 Mux" }, |
3680 | {"TDM2 slot 23 Data Mux" , "4321" , "IF1_2_ADC3 Mux" }, |
3681 | {"TDM2 slot 23 Data Mux" , NULL, "I2S1_2" }, |
3682 | |
3683 | {"TDM2 slot 45 Data Mux" , "1234" , "IF1_2_ADC3 Mux" }, |
3684 | {"TDM2 slot 45 Data Mux" , "1243" , "IF1_2_ADC4 Mux" }, |
3685 | {"TDM2 slot 45 Data Mux" , "1324" , "IF1_2_ADC2 Mux" }, |
3686 | {"TDM2 slot 45 Data Mux" , "1342" , "IF1_2_ADC4 Mux" }, |
3687 | {"TDM2 slot 45 Data Mux" , "1432" , "IF1_2_ADC3 Mux" }, |
3688 | {"TDM2 slot 45 Data Mux" , "1423" , "IF1_2_ADC2 Mux" }, |
3689 | {"TDM2 slot 45 Data Mux" , "2134" , "IF1_2_ADC3 Mux" }, |
3690 | {"TDM2 slot 45 Data Mux" , "2143" , "IF1_2_ADC4 Mux" }, |
3691 | {"TDM2 slot 45 Data Mux" , "2314" , "IF1_2_ADC1 Mux" }, |
3692 | {"TDM2 slot 45 Data Mux" , "2341" , "IF1_2_ADC4 Mux" }, |
3693 | {"TDM2 slot 45 Data Mux" , "2431" , "IF1_2_ADC3 Mux" }, |
3694 | {"TDM2 slot 45 Data Mux" , "2413" , "IF1_2_ADC1 Mux" }, |
3695 | {"TDM2 slot 45 Data Mux" , "3124" , "IF1_2_ADC2 Mux" }, |
3696 | {"TDM2 slot 45 Data Mux" , "3142" , "IF1_2_ADC4 Mux" }, |
3697 | {"TDM2 slot 45 Data Mux" , "3214" , "IF1_2_ADC1 Mux" }, |
3698 | {"TDM2 slot 45 Data Mux" , "3241" , "IF1_2_ADC4 Mux" }, |
3699 | {"TDM2 slot 45 Data Mux" , "3412" , "IF1_2_ADC1 Mux" }, |
3700 | {"TDM2 slot 45 Data Mux" , "3421" , "IF1_2_ADC2 Mux" }, |
3701 | {"TDM2 slot 45 Data Mux" , "4123" , "IF1_2_ADC2 Mux" }, |
3702 | {"TDM2 slot 45 Data Mux" , "4132" , "IF1_2_ADC3 Mux" }, |
3703 | {"TDM2 slot 45 Data Mux" , "4213" , "IF1_2_ADC1 Mux" }, |
3704 | {"TDM2 slot 45 Data Mux" , "4231" , "IF1_2_ADC3 Mux" }, |
3705 | {"TDM2 slot 45 Data Mux" , "4312" , "IF1_2_ADC1 Mux" }, |
3706 | {"TDM2 slot 45 Data Mux" , "4321" , "IF1_2_ADC2 Mux" }, |
3707 | {"TDM2 slot 45 Data Mux" , NULL, "I2S1_2" }, |
3708 | |
3709 | {"TDM2 slot 67 Data Mux" , "1234" , "IF1_2_ADC4 Mux" }, |
3710 | {"TDM2 slot 67 Data Mux" , "1243" , "IF1_2_ADC3 Mux" }, |
3711 | {"TDM2 slot 67 Data Mux" , "1324" , "IF1_2_ADC4 Mux" }, |
3712 | {"TDM2 slot 67 Data Mux" , "1342" , "IF1_2_ADC2 Mux" }, |
3713 | {"TDM2 slot 67 Data Mux" , "1432" , "IF1_2_ADC2 Mux" }, |
3714 | {"TDM2 slot 67 Data Mux" , "1423" , "IF1_2_ADC3 Mux" }, |
3715 | {"TDM2 slot 67 Data Mux" , "2134" , "IF1_2_ADC4 Mux" }, |
3716 | {"TDM2 slot 67 Data Mux" , "2143" , "IF1_2_ADC3 Mux" }, |
3717 | {"TDM2 slot 67 Data Mux" , "2314" , "IF1_2_ADC4 Mux" }, |
3718 | {"TDM2 slot 67 Data Mux" , "2341" , "IF1_2_ADC1 Mux" }, |
3719 | {"TDM2 slot 67 Data Mux" , "2431" , "IF1_2_ADC1 Mux" }, |
3720 | {"TDM2 slot 67 Data Mux" , "2413" , "IF1_2_ADC3 Mux" }, |
3721 | {"TDM2 slot 67 Data Mux" , "3124" , "IF1_2_ADC4 Mux" }, |
3722 | {"TDM2 slot 67 Data Mux" , "3142" , "IF1_2_ADC2 Mux" }, |
3723 | {"TDM2 slot 67 Data Mux" , "3214" , "IF1_2_ADC4 Mux" }, |
3724 | {"TDM2 slot 67 Data Mux" , "3241" , "IF1_2_ADC1 Mux" }, |
3725 | {"TDM2 slot 67 Data Mux" , "3412" , "IF1_2_ADC2 Mux" }, |
3726 | {"TDM2 slot 67 Data Mux" , "3421" , "IF1_2_ADC1 Mux" }, |
3727 | {"TDM2 slot 67 Data Mux" , "4123" , "IF1_2_ADC3 Mux" }, |
3728 | {"TDM2 slot 67 Data Mux" , "4132" , "IF1_2_ADC2 Mux" }, |
3729 | {"TDM2 slot 67 Data Mux" , "4213" , "IF1_2_ADC3 Mux" }, |
3730 | {"TDM2 slot 67 Data Mux" , "4231" , "IF1_2_ADC1 Mux" }, |
3731 | {"TDM2 slot 67 Data Mux" , "4312" , "IF1_2_ADC2 Mux" }, |
3732 | {"TDM2 slot 67 Data Mux" , "4321" , "IF1_2_ADC1 Mux" }, |
3733 | {"TDM2 slot 67 Data Mux" , NULL, "I2S1_2" }, |
3734 | |
3735 | {"IF1_1 0 ADC Swap Mux" , "L/R" , "TDM1 slot 01 Data Mux" }, |
3736 | {"IF1_1 0 ADC Swap Mux" , "L/L" , "TDM1 slot 01 Data Mux" }, |
3737 | {"IF1_1 1 ADC Swap Mux" , "R/L" , "TDM1 slot 01 Data Mux" }, |
3738 | {"IF1_1 1 ADC Swap Mux" , "R/R" , "TDM1 slot 01 Data Mux" }, |
3739 | {"IF1_1 2 ADC Swap Mux" , "L/R" , "TDM1 slot 23 Data Mux" }, |
3740 | {"IF1_1 2 ADC Swap Mux" , "R/L" , "TDM1 slot 23 Data Mux" }, |
3741 | {"IF1_1 3 ADC Swap Mux" , "L/L" , "TDM1 slot 23 Data Mux" }, |
3742 | {"IF1_1 3 ADC Swap Mux" , "R/R" , "TDM1 slot 23 Data Mux" }, |
3743 | {"IF1_1 4 ADC Swap Mux" , "L/R" , "TDM1 slot 45 Data Mux" }, |
3744 | {"IF1_1 4 ADC Swap Mux" , "R/L" , "TDM1 slot 45 Data Mux" }, |
3745 | {"IF1_1 5 ADC Swap Mux" , "L/L" , "TDM1 slot 45 Data Mux" }, |
3746 | {"IF1_1 5 ADC Swap Mux" , "R/R" , "TDM1 slot 45 Data Mux" }, |
3747 | {"IF1_1 6 ADC Swap Mux" , "L/R" , "TDM1 slot 67 Data Mux" }, |
3748 | {"IF1_1 6 ADC Swap Mux" , "R/L" , "TDM1 slot 67 Data Mux" }, |
3749 | {"IF1_1 7 ADC Swap Mux" , "L/L" , "TDM1 slot 67 Data Mux" }, |
3750 | {"IF1_1 7 ADC Swap Mux" , "R/R" , "TDM1 slot 67 Data Mux" }, |
3751 | {"IF1_2 0 ADC Swap Mux" , "L/R" , "TDM2 slot 01 Data Mux" }, |
3752 | {"IF1_2 0 ADC Swap Mux" , "R/L" , "TDM2 slot 01 Data Mux" }, |
3753 | {"IF1_2 1 ADC Swap Mux" , "L/L" , "TDM2 slot 01 Data Mux" }, |
3754 | {"IF1_2 1 ADC Swap Mux" , "R/R" , "TDM2 slot 01 Data Mux" }, |
3755 | {"IF1_2 2 ADC Swap Mux" , "L/R" , "TDM2 slot 23 Data Mux" }, |
3756 | {"IF1_2 2 ADC Swap Mux" , "R/L" , "TDM2 slot 23 Data Mux" }, |
3757 | {"IF1_2 3 ADC Swap Mux" , "L/L" , "TDM2 slot 23 Data Mux" }, |
3758 | {"IF1_2 3 ADC Swap Mux" , "R/R" , "TDM2 slot 23 Data Mux" }, |
3759 | {"IF1_2 4 ADC Swap Mux" , "L/R" , "TDM2 slot 45 Data Mux" }, |
3760 | {"IF1_2 4 ADC Swap Mux" , "R/L" , "TDM2 slot 45 Data Mux" }, |
3761 | {"IF1_2 5 ADC Swap Mux" , "L/L" , "TDM2 slot 45 Data Mux" }, |
3762 | {"IF1_2 5 ADC Swap Mux" , "R/R" , "TDM2 slot 45 Data Mux" }, |
3763 | {"IF1_2 6 ADC Swap Mux" , "L/R" , "TDM2 slot 67 Data Mux" }, |
3764 | {"IF1_2 6 ADC Swap Mux" , "R/L" , "TDM2 slot 67 Data Mux" }, |
3765 | {"IF1_2 7 ADC Swap Mux" , "L/L" , "TDM2 slot 67 Data Mux" }, |
3766 | {"IF1_2 7 ADC Swap Mux" , "R/R" , "TDM2 slot 67 Data Mux" }, |
3767 | |
3768 | {"IF2_1 ADC Mux" , "STO1 ADC" , "Stereo1 ADC MIX" }, |
3769 | {"IF2_1 ADC Mux" , "STO2 ADC" , "Stereo2 ADC MIX" }, |
3770 | {"IF2_1 ADC Mux" , "MONO ADC" , "Mono ADC MIX" }, |
3771 | {"IF2_1 ADC Mux" , "IF1 DAC1" , "IF1 DAC1" }, |
3772 | {"IF2_1 ADC Mux" , "IF1 DAC2" , "IF1 DAC2" }, |
3773 | {"IF2_1 ADC Mux" , "IF2_2 DAC" , "IF2_2 DAC" }, |
3774 | {"IF2_1 ADC Mux" , "IF3 DAC" , "IF3 DAC" }, |
3775 | {"IF2_1 ADC Mux" , "DAC1 MIX" , "DAC1 MIX" }, |
3776 | {"IF2_1 ADC" , NULL, "IF2_1 ADC Mux" }, |
3777 | {"IF2_1 ADC" , NULL, "I2S2_1" }, |
3778 | |
3779 | {"IF2_2 ADC Mux" , "STO1 ADC" , "Stereo1 ADC MIX" }, |
3780 | {"IF2_2 ADC Mux" , "STO2 ADC" , "Stereo2 ADC MIX" }, |
3781 | {"IF2_2 ADC Mux" , "MONO ADC" , "Mono ADC MIX" }, |
3782 | {"IF2_2 ADC Mux" , "IF1 DAC1" , "IF1 DAC1" }, |
3783 | {"IF2_2 ADC Mux" , "IF1 DAC2" , "IF1 DAC2" }, |
3784 | {"IF2_2 ADC Mux" , "IF2_1 DAC" , "IF2_1 DAC" }, |
3785 | {"IF2_2 ADC Mux" , "IF3 DAC" , "IF3 DAC" }, |
3786 | {"IF2_2 ADC Mux" , "DAC1 MIX" , "DAC1 MIX" }, |
3787 | {"IF2_2 ADC" , NULL, "IF2_2 ADC Mux" }, |
3788 | {"IF2_2 ADC" , NULL, "I2S2_2" }, |
3789 | |
3790 | {"IF3 ADC Mux" , "STO1 ADC" , "Stereo1 ADC MIX" }, |
3791 | {"IF3 ADC Mux" , "STO2 ADC" , "Stereo2 ADC MIX" }, |
3792 | {"IF3 ADC Mux" , "MONO ADC" , "Mono ADC MIX" }, |
3793 | {"IF3 ADC Mux" , "IF1 DAC1" , "IF1 DAC1" }, |
3794 | {"IF3 ADC Mux" , "IF1 DAC2" , "IF1 DAC2" }, |
3795 | {"IF3 ADC Mux" , "IF2_1 DAC" , "IF2_1 DAC" }, |
3796 | {"IF3 ADC Mux" , "IF2_2 DAC" , "IF2_2 DAC" }, |
3797 | {"IF3 ADC Mux" , "DAC1 MIX" , "DAC1 MIX" }, |
3798 | {"IF3 ADC" , NULL, "IF3 ADC Mux" }, |
3799 | {"IF3 ADC" , NULL, "I2S3" }, |
3800 | |
3801 | {"AIF1_1TX slot 0" , NULL, "IF1_1 0 ADC Swap Mux" }, |
3802 | {"AIF1_1TX slot 1" , NULL, "IF1_1 1 ADC Swap Mux" }, |
3803 | {"AIF1_1TX slot 2" , NULL, "IF1_1 2 ADC Swap Mux" }, |
3804 | {"AIF1_1TX slot 3" , NULL, "IF1_1 3 ADC Swap Mux" }, |
3805 | {"AIF1_1TX slot 4" , NULL, "IF1_1 4 ADC Swap Mux" }, |
3806 | {"AIF1_1TX slot 5" , NULL, "IF1_1 5 ADC Swap Mux" }, |
3807 | {"AIF1_1TX slot 6" , NULL, "IF1_1 6 ADC Swap Mux" }, |
3808 | {"AIF1_1TX slot 7" , NULL, "IF1_1 7 ADC Swap Mux" }, |
3809 | {"AIF1_2TX slot 0" , NULL, "IF1_2 0 ADC Swap Mux" }, |
3810 | {"AIF1_2TX slot 1" , NULL, "IF1_2 1 ADC Swap Mux" }, |
3811 | {"AIF1_2TX slot 2" , NULL, "IF1_2 2 ADC Swap Mux" }, |
3812 | {"AIF1_2TX slot 3" , NULL, "IF1_2 3 ADC Swap Mux" }, |
3813 | {"AIF1_2TX slot 4" , NULL, "IF1_2 4 ADC Swap Mux" }, |
3814 | {"AIF1_2TX slot 5" , NULL, "IF1_2 5 ADC Swap Mux" }, |
3815 | {"AIF1_2TX slot 6" , NULL, "IF1_2 6 ADC Swap Mux" }, |
3816 | {"AIF1_2TX slot 7" , NULL, "IF1_2 7 ADC Swap Mux" }, |
3817 | {"IF2_1 ADC Swap Mux" , "L/R" , "IF2_1 ADC" }, |
3818 | {"IF2_1 ADC Swap Mux" , "R/L" , "IF2_1 ADC" }, |
3819 | {"IF2_1 ADC Swap Mux" , "L/L" , "IF2_1 ADC" }, |
3820 | {"IF2_1 ADC Swap Mux" , "R/R" , "IF2_1 ADC" }, |
3821 | {"AIF2_1TX" , NULL, "IF2_1 ADC Swap Mux" }, |
3822 | {"IF2_2 ADC Swap Mux" , "L/R" , "IF2_2 ADC" }, |
3823 | {"IF2_2 ADC Swap Mux" , "R/L" , "IF2_2 ADC" }, |
3824 | {"IF2_2 ADC Swap Mux" , "L/L" , "IF2_2 ADC" }, |
3825 | {"IF2_2 ADC Swap Mux" , "R/R" , "IF2_2 ADC" }, |
3826 | {"AIF2_2TX" , NULL, "IF2_2 ADC Swap Mux" }, |
3827 | {"IF3 ADC Swap Mux" , "L/R" , "IF3 ADC" }, |
3828 | {"IF3 ADC Swap Mux" , "R/L" , "IF3 ADC" }, |
3829 | {"IF3 ADC Swap Mux" , "L/L" , "IF3 ADC" }, |
3830 | {"IF3 ADC Swap Mux" , "R/R" , "IF3 ADC" }, |
3831 | {"AIF3TX" , NULL, "IF3 ADC Swap Mux" }, |
3832 | |
3833 | {"IF1 DAC1" , NULL, "AIF1RX" }, |
3834 | {"IF1 DAC2" , NULL, "AIF1RX" }, |
3835 | {"IF1 DAC3" , NULL, "AIF1RX" }, |
3836 | {"IF2_1 DAC Swap Mux" , "L/R" , "AIF2_1RX" }, |
3837 | {"IF2_1 DAC Swap Mux" , "R/L" , "AIF2_1RX" }, |
3838 | {"IF2_1 DAC Swap Mux" , "L/L" , "AIF2_1RX" }, |
3839 | {"IF2_1 DAC Swap Mux" , "R/R" , "AIF2_1RX" }, |
3840 | {"IF2_2 DAC Swap Mux" , "L/R" , "AIF2_2RX" }, |
3841 | {"IF2_2 DAC Swap Mux" , "R/L" , "AIF2_2RX" }, |
3842 | {"IF2_2 DAC Swap Mux" , "L/L" , "AIF2_2RX" }, |
3843 | {"IF2_2 DAC Swap Mux" , "R/R" , "AIF2_2RX" }, |
3844 | {"IF2_1 DAC" , NULL, "IF2_1 DAC Swap Mux" }, |
3845 | {"IF2_2 DAC" , NULL, "IF2_2 DAC Swap Mux" }, |
3846 | {"IF3 DAC Swap Mux" , "L/R" , "AIF3RX" }, |
3847 | {"IF3 DAC Swap Mux" , "R/L" , "AIF3RX" }, |
3848 | {"IF3 DAC Swap Mux" , "L/L" , "AIF3RX" }, |
3849 | {"IF3 DAC Swap Mux" , "R/R" , "AIF3RX" }, |
3850 | {"IF3 DAC" , NULL, "IF3 DAC Swap Mux" }, |
3851 | |
3852 | {"IF1 DAC1" , NULL, "I2S1_1" }, |
3853 | {"IF1 DAC2" , NULL, "I2S1_1" }, |
3854 | {"IF1 DAC3" , NULL, "I2S1_1" }, |
3855 | {"IF2_1 DAC" , NULL, "I2S2_1" }, |
3856 | {"IF2_2 DAC" , NULL, "I2S2_2" }, |
3857 | {"IF3 DAC" , NULL, "I2S3" }, |
3858 | |
3859 | {"IF1 DAC1 L" , NULL, "IF1 DAC1" }, |
3860 | {"IF1 DAC1 R" , NULL, "IF1 DAC1" }, |
3861 | {"IF1 DAC2 L" , NULL, "IF1 DAC2" }, |
3862 | {"IF1 DAC2 R" , NULL, "IF1 DAC2" }, |
3863 | {"IF1 DAC3 L" , NULL, "IF1 DAC3" }, |
3864 | {"IF1 DAC3 R" , NULL, "IF1 DAC3" }, |
3865 | {"IF2_1 DAC L" , NULL, "IF2_1 DAC" }, |
3866 | {"IF2_1 DAC R" , NULL, "IF2_1 DAC" }, |
3867 | {"IF2_2 DAC L" , NULL, "IF2_2 DAC" }, |
3868 | {"IF2_2 DAC R" , NULL, "IF2_2 DAC" }, |
3869 | {"IF3 DAC L" , NULL, "IF3 DAC" }, |
3870 | {"IF3 DAC R" , NULL, "IF3 DAC" }, |
3871 | |
3872 | {"DAC L1 Mux" , "IF1 DAC1" , "IF1 DAC1 L" }, |
3873 | {"DAC L1 Mux" , "IF2_1 DAC" , "IF2_1 DAC L" }, |
3874 | {"DAC L1 Mux" , "IF2_2 DAC" , "IF2_2 DAC L" }, |
3875 | {"DAC L1 Mux" , "IF3 DAC" , "IF3 DAC L" }, |
3876 | {"DAC L1 Mux" , NULL, "DAC Stereo1 Filter" }, |
3877 | |
3878 | {"DAC R1 Mux" , "IF1 DAC1" , "IF1 DAC1 R" }, |
3879 | {"DAC R1 Mux" , "IF2_1 DAC" , "IF2_1 DAC R" }, |
3880 | {"DAC R1 Mux" , "IF2_2 DAC" , "IF2_2 DAC R" }, |
3881 | {"DAC R1 Mux" , "IF3 DAC" , "IF3 DAC R" }, |
3882 | {"DAC R1 Mux" , NULL, "DAC Stereo1 Filter" }, |
3883 | |
3884 | {"DAC1 MIXL" , "Stereo ADC Switch" , "Stereo1 ADC MIXL" }, |
3885 | {"DAC1 MIXL" , "DAC1 Switch" , "DAC L1 Mux" }, |
3886 | {"DAC1 MIXR" , "Stereo ADC Switch" , "Stereo1 ADC MIXR" }, |
3887 | {"DAC1 MIXR" , "DAC1 Switch" , "DAC R1 Mux" }, |
3888 | |
3889 | {"DAC1 MIX" , NULL, "DAC1 MIXL" }, |
3890 | {"DAC1 MIX" , NULL, "DAC1 MIXR" }, |
3891 | |
3892 | {"DAC L2 Mux" , "IF1 DAC2" , "IF1 DAC2 L" }, |
3893 | {"DAC L2 Mux" , "IF2_1 DAC" , "IF2_1 DAC L" }, |
3894 | {"DAC L2 Mux" , "IF2_2 DAC" , "IF2_2 DAC L" }, |
3895 | {"DAC L2 Mux" , "IF3 DAC" , "IF3 DAC L" }, |
3896 | {"DAC L2 Mux" , "Mono ADC MIX" , "Mono ADC MIXL" }, |
3897 | {"DAC L2 Mux" , NULL, "DAC Mono Left Filter" }, |
3898 | |
3899 | {"DAC R2 Mux" , "IF1 DAC2" , "IF1 DAC2 R" }, |
3900 | {"DAC R2 Mux" , "IF2_1 DAC" , "IF2_1 DAC R" }, |
3901 | {"DAC R2 Mux" , "IF2_2 DAC" , "IF2_2 DAC R" }, |
3902 | {"DAC R2 Mux" , "IF3 DAC" , "IF3 DAC R" }, |
3903 | {"DAC R2 Mux" , "Mono ADC MIX" , "Mono ADC MIXR" }, |
3904 | {"DAC R2 Mux" , NULL, "DAC Mono Right Filter" }, |
3905 | |
3906 | {"DAC L3 Mux" , "IF1 DAC2" , "IF1 DAC2 L" }, |
3907 | {"DAC L3 Mux" , "IF2_1 DAC" , "IF2_1 DAC L" }, |
3908 | {"DAC L3 Mux" , "IF2_2 DAC" , "IF2_2 DAC L" }, |
3909 | {"DAC L3 Mux" , "IF3 DAC" , "IF3 DAC L" }, |
3910 | {"DAC L3 Mux" , "STO2 ADC MIX" , "Stereo2 ADC MIXL" }, |
3911 | {"DAC L3 Mux" , NULL, "DAC Stereo2 Filter" }, |
3912 | |
3913 | {"DAC R3 Mux" , "IF1 DAC2" , "IF1 DAC2 R" }, |
3914 | {"DAC R3 Mux" , "IF2_1 DAC" , "IF2_1 DAC R" }, |
3915 | {"DAC R3 Mux" , "IF2_2 DAC" , "IF2_2 DAC R" }, |
3916 | {"DAC R3 Mux" , "IF3 DAC" , "IF3 DAC R" }, |
3917 | {"DAC R3 Mux" , "STO2 ADC MIX" , "Stereo2 ADC MIXR" }, |
3918 | {"DAC R3 Mux" , NULL, "DAC Stereo2 Filter" }, |
3919 | |
3920 | {"Stereo1 DAC MIXL" , "DAC L1 Switch" , "DAC1 MIXL" }, |
3921 | {"Stereo1 DAC MIXL" , "DAC R1 Switch" , "DAC1 MIXR" }, |
3922 | {"Stereo1 DAC MIXL" , "DAC L2 Switch" , "DAC L2 Mux" }, |
3923 | {"Stereo1 DAC MIXL" , "DAC R2 Switch" , "DAC R2 Mux" }, |
3924 | |
3925 | {"Stereo1 DAC MIXR" , "DAC R1 Switch" , "DAC1 MIXR" }, |
3926 | {"Stereo1 DAC MIXR" , "DAC L1 Switch" , "DAC1 MIXL" }, |
3927 | {"Stereo1 DAC MIXR" , "DAC L2 Switch" , "DAC L2 Mux" }, |
3928 | {"Stereo1 DAC MIXR" , "DAC R2 Switch" , "DAC R2 Mux" }, |
3929 | |
3930 | {"Stereo2 DAC MIXL" , "DAC L1 Switch" , "DAC1 MIXL" }, |
3931 | {"Stereo2 DAC MIXL" , "DAC L2 Switch" , "DAC L2 Mux" }, |
3932 | {"Stereo2 DAC MIXL" , "DAC L3 Switch" , "DAC L3 Mux" }, |
3933 | |
3934 | {"Stereo2 DAC MIXR" , "DAC R1 Switch" , "DAC1 MIXR" }, |
3935 | {"Stereo2 DAC MIXR" , "DAC R2 Switch" , "DAC R2 Mux" }, |
3936 | {"Stereo2 DAC MIXR" , "DAC R3 Switch" , "DAC R3 Mux" }, |
3937 | |
3938 | {"Mono DAC MIXL" , "DAC L1 Switch" , "DAC1 MIXL" }, |
3939 | {"Mono DAC MIXL" , "DAC R1 Switch" , "DAC1 MIXR" }, |
3940 | {"Mono DAC MIXL" , "DAC L2 Switch" , "DAC L2 Mux" }, |
3941 | {"Mono DAC MIXL" , "DAC R2 Switch" , "DAC R2 Mux" }, |
3942 | {"Mono DAC MIXR" , "DAC L1 Switch" , "DAC1 MIXL" }, |
3943 | {"Mono DAC MIXR" , "DAC R1 Switch" , "DAC1 MIXR" }, |
3944 | {"Mono DAC MIXR" , "DAC L2 Switch" , "DAC L2 Mux" }, |
3945 | {"Mono DAC MIXR" , "DAC R2 Switch" , "DAC R2 Mux" }, |
3946 | |
3947 | {"DAC MIXL" , "Stereo1 DAC Mixer" , "Stereo1 DAC MIXL" }, |
3948 | {"DAC MIXL" , "Stereo2 DAC Mixer" , "Stereo2 DAC MIXL" }, |
3949 | {"DAC MIXL" , "Mono DAC Mixer" , "Mono DAC MIXL" }, |
3950 | {"DAC MIXR" , "Stereo1 DAC Mixer" , "Stereo1 DAC MIXR" }, |
3951 | {"DAC MIXR" , "Stereo2 DAC Mixer" , "Stereo2 DAC MIXR" }, |
3952 | {"DAC MIXR" , "Mono DAC Mixer" , "Mono DAC MIXR" }, |
3953 | |
3954 | {"DAC L1 Source" , "DAC1" , "DAC1 MIXL" }, |
3955 | {"DAC L1 Source" , "Stereo1 DAC Mixer" , "Stereo1 DAC MIXL" }, |
3956 | {"DAC L1 Source" , "DMIC1" , "DMIC L1" }, |
3957 | {"DAC R1 Source" , "DAC1" , "DAC1 MIXR" }, |
3958 | {"DAC R1 Source" , "Stereo1 DAC Mixer" , "Stereo1 DAC MIXR" }, |
3959 | {"DAC R1 Source" , "DMIC1" , "DMIC R1" }, |
3960 | |
3961 | {"DAC L2 Source" , "DAC2" , "DAC L2 Mux" }, |
3962 | {"DAC L2 Source" , "Mono DAC Mixer" , "Mono DAC MIXL" }, |
3963 | {"DAC L2 Source" , NULL, "DAC L2 Power" }, |
3964 | {"DAC R2 Source" , "DAC2" , "DAC R2 Mux" }, |
3965 | {"DAC R2 Source" , "Mono DAC Mixer" , "Mono DAC MIXR" }, |
3966 | {"DAC R2 Source" , NULL, "DAC R2 Power" }, |
3967 | |
3968 | {"DAC L1" , NULL, "DAC L1 Source" }, |
3969 | {"DAC R1" , NULL, "DAC R1 Source" }, |
3970 | {"DAC L2" , NULL, "DAC L2 Source" }, |
3971 | {"DAC R2" , NULL, "DAC R2 Source" }, |
3972 | |
3973 | {"DAC L1" , NULL, "DAC 1 Clock" }, |
3974 | {"DAC R1" , NULL, "DAC 1 Clock" }, |
3975 | {"DAC L2" , NULL, "DAC 2 Clock" }, |
3976 | {"DAC R2" , NULL, "DAC 2 Clock" }, |
3977 | |
3978 | {"MONOVOL MIX" , "DAC L2 Switch" , "DAC L2" }, |
3979 | {"MONOVOL MIX" , "RECMIX2L Switch" , "RECMIX2L" }, |
3980 | {"MONOVOL MIX" , "BST1 Switch" , "BST1" }, |
3981 | {"MONOVOL MIX" , "BST2 Switch" , "BST2" }, |
3982 | {"MONOVOL MIX" , "BST3 Switch" , "BST3" }, |
3983 | |
3984 | {"OUT MIXL" , "DAC L2 Switch" , "DAC L2" }, |
3985 | {"OUT MIXL" , "INL Switch" , "INL VOL" }, |
3986 | {"OUT MIXL" , "BST1 Switch" , "BST1" }, |
3987 | {"OUT MIXL" , "BST2 Switch" , "BST2" }, |
3988 | {"OUT MIXL" , "BST3 Switch" , "BST3" }, |
3989 | {"OUT MIXR" , "DAC R2 Switch" , "DAC R2" }, |
3990 | {"OUT MIXR" , "INR Switch" , "INR VOL" }, |
3991 | {"OUT MIXR" , "BST2 Switch" , "BST2" }, |
3992 | {"OUT MIXR" , "BST3 Switch" , "BST3" }, |
3993 | {"OUT MIXR" , "BST4 Switch" , "BST4" }, |
3994 | |
3995 | {"MONOVOL" , "Switch" , "MONOVOL MIX" }, |
3996 | {"Mono MIX" , "DAC L2 Switch" , "DAC L2" }, |
3997 | {"Mono MIX" , "MONOVOL Switch" , "MONOVOL" }, |
3998 | {"Mono Amp" , NULL, "Mono MIX" }, |
3999 | {"Mono Amp" , NULL, "Vref2" }, |
4000 | {"Mono Amp" , NULL, "Vref3" }, |
4001 | {"Mono Amp" , NULL, "CLKDET SYS" }, |
4002 | {"Mono Amp" , NULL, "CLKDET MONO" }, |
4003 | {"Mono Playback" , "Switch" , "Mono Amp" }, |
4004 | {"MONOOUT" , NULL, "Mono Playback" }, |
4005 | |
4006 | {"HP Amp" , NULL, "DAC L1" }, |
4007 | {"HP Amp" , NULL, "DAC R1" }, |
4008 | {"HP Amp" , NULL, "Charge Pump" }, |
4009 | {"HP Amp" , NULL, "CLKDET SYS" }, |
4010 | {"HP Amp" , NULL, "CLKDET HP" }, |
4011 | {"HP Amp" , NULL, "CBJ Power" }, |
4012 | {"HP Amp" , NULL, "Vref2" }, |
4013 | {"HPO Playback" , "Switch" , "HP Amp" }, |
4014 | {"HPOL" , NULL, "HPO Playback" }, |
4015 | {"HPOR" , NULL, "HPO Playback" }, |
4016 | |
4017 | {"OUTVOL L" , "Switch" , "OUT MIXL" }, |
4018 | {"OUTVOL R" , "Switch" , "OUT MIXR" }, |
4019 | {"LOUT L MIX" , "DAC L2 Switch" , "DAC L2" }, |
4020 | {"LOUT L MIX" , "OUTVOL L Switch" , "OUTVOL L" }, |
4021 | {"LOUT R MIX" , "DAC R2 Switch" , "DAC R2" }, |
4022 | {"LOUT R MIX" , "OUTVOL R Switch" , "OUTVOL R" }, |
4023 | {"LOUT Amp" , NULL, "LOUT L MIX" }, |
4024 | {"LOUT Amp" , NULL, "LOUT R MIX" }, |
4025 | {"LOUT Amp" , NULL, "Vref1" }, |
4026 | {"LOUT Amp" , NULL, "Vref2" }, |
4027 | {"LOUT Amp" , NULL, "CLKDET SYS" }, |
4028 | {"LOUT Amp" , NULL, "CLKDET LOUT" }, |
4029 | {"LOUT L Playback" , "Switch" , "LOUT Amp" }, |
4030 | {"LOUT R Playback" , "Switch" , "LOUT Amp" }, |
4031 | {"LOUTL" , NULL, "LOUT L Playback" }, |
4032 | {"LOUTR" , NULL, "LOUT R Playback" }, |
4033 | |
4034 | {"PDM L Mux" , "Mono DAC" , "Mono DAC MIXL" }, |
4035 | {"PDM L Mux" , "Stereo1 DAC" , "Stereo1 DAC MIXL" }, |
4036 | {"PDM L Mux" , "Stereo2 DAC" , "Stereo2 DAC MIXL" }, |
4037 | {"PDM L Mux" , NULL, "PDM Power" }, |
4038 | {"PDM R Mux" , "Mono DAC" , "Mono DAC MIXR" }, |
4039 | {"PDM R Mux" , "Stereo1 DAC" , "Stereo1 DAC MIXR" }, |
4040 | {"PDM R Mux" , "Stereo2 DAC" , "Stereo2 DAC MIXR" }, |
4041 | {"PDM R Mux" , NULL, "PDM Power" }, |
4042 | {"PDM L Playback" , "Switch" , "PDM L Mux" }, |
4043 | {"PDM R Playback" , "Switch" , "PDM R Mux" }, |
4044 | {"PDML" , NULL, "PDM L Playback" }, |
4045 | {"PDMR" , NULL, "PDM R Playback" }, |
4046 | }; |
4047 | |
4048 | static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, |
4049 | unsigned int rx_mask, int slots, int slot_width) |
4050 | { |
4051 | struct snd_soc_component *component = dai->component; |
4052 | unsigned int val = 0; |
4053 | |
4054 | if (rx_mask || tx_mask) |
4055 | val |= RT5665_I2S1_MODE_TDM; |
4056 | |
4057 | switch (slots) { |
4058 | case 4: |
4059 | val |= RT5665_TDM_IN_CH_4; |
4060 | val |= RT5665_TDM_OUT_CH_4; |
4061 | break; |
4062 | case 6: |
4063 | val |= RT5665_TDM_IN_CH_6; |
4064 | val |= RT5665_TDM_OUT_CH_6; |
4065 | break; |
4066 | case 8: |
4067 | val |= RT5665_TDM_IN_CH_8; |
4068 | val |= RT5665_TDM_OUT_CH_8; |
4069 | break; |
4070 | case 2: |
4071 | break; |
4072 | default: |
4073 | return -EINVAL; |
4074 | } |
4075 | |
4076 | switch (slot_width) { |
4077 | case 20: |
4078 | val |= RT5665_TDM_IN_LEN_20; |
4079 | val |= RT5665_TDM_OUT_LEN_20; |
4080 | break; |
4081 | case 24: |
4082 | val |= RT5665_TDM_IN_LEN_24; |
4083 | val |= RT5665_TDM_OUT_LEN_24; |
4084 | break; |
4085 | case 32: |
4086 | val |= RT5665_TDM_IN_LEN_32; |
4087 | val |= RT5665_TDM_OUT_LEN_32; |
4088 | break; |
4089 | case 16: |
4090 | break; |
4091 | default: |
4092 | return -EINVAL; |
4093 | } |
4094 | |
4095 | snd_soc_component_update_bits(component, RT5665_TDM_CTRL_1, |
4096 | RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK | |
4097 | RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK | |
4098 | RT5665_TDM_OUT_LEN_MASK, val); |
4099 | |
4100 | return 0; |
4101 | } |
4102 | |
4103 | |
4104 | static int rt5665_hw_params(struct snd_pcm_substream *substream, |
4105 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
4106 | { |
4107 | struct snd_soc_component *component = dai->component; |
4108 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4109 | unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100; |
4110 | int pre_div, frame_size; |
4111 | |
4112 | rt5665->lrck[dai->id] = params_rate(p: params); |
4113 | pre_div = rl6231_get_clk_info(sclk: rt5665->sysclk, rate: rt5665->lrck[dai->id]); |
4114 | if (pre_div < 0) { |
4115 | dev_warn(component->dev, "Force using PLL" ); |
4116 | snd_soc_component_set_pll(component, pll_id: 0, source: RT5665_PLL1_S_MCLK, |
4117 | freq_in: rt5665->sysclk, freq_out: rt5665->lrck[dai->id] * 512); |
4118 | snd_soc_component_set_sysclk(component, clk_id: RT5665_SCLK_S_PLL1, source: 0, |
4119 | freq: rt5665->lrck[dai->id] * 512, dir: 0); |
4120 | pre_div = 1; |
4121 | } |
4122 | frame_size = snd_soc_params_to_frame_size(params); |
4123 | if (frame_size < 0) { |
4124 | dev_err(component->dev, "Unsupported frame size: %d\n" , frame_size); |
4125 | return -EINVAL; |
4126 | } |
4127 | |
4128 | dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n" , |
4129 | rt5665->lrck[dai->id], pre_div, dai->id); |
4130 | |
4131 | switch (params_width(p: params)) { |
4132 | case 16: |
4133 | val_bits = 0x0100; |
4134 | break; |
4135 | case 20: |
4136 | val_len |= RT5665_I2S_DL_20; |
4137 | val_bits = 0x1300; |
4138 | break; |
4139 | case 24: |
4140 | val_len |= RT5665_I2S_DL_24; |
4141 | val_bits = 0x2500; |
4142 | break; |
4143 | case 8: |
4144 | val_len |= RT5665_I2S_DL_8; |
4145 | break; |
4146 | default: |
4147 | return -EINVAL; |
4148 | } |
4149 | |
4150 | switch (dai->id) { |
4151 | case RT5665_AIF1_1: |
4152 | case RT5665_AIF1_2: |
4153 | if (params_channels(p: params) > 2) |
4154 | rt5665_set_tdm_slot(dai, tx_mask: 0xf, rx_mask: 0xf, |
4155 | slots: params_channels(p: params), slot_width: params_width(p: params)); |
4156 | reg_clk = RT5665_ADDA_CLK_1; |
4157 | mask_clk = RT5665_I2S_PD1_MASK; |
4158 | val_clk = pre_div << RT5665_I2S_PD1_SFT; |
4159 | snd_soc_component_update_bits(component, RT5665_I2S1_SDP, |
4160 | RT5665_I2S_DL_MASK, val: val_len); |
4161 | break; |
4162 | case RT5665_AIF2_1: |
4163 | case RT5665_AIF2_2: |
4164 | reg_clk = RT5665_ADDA_CLK_2; |
4165 | mask_clk = RT5665_I2S_PD2_MASK; |
4166 | val_clk = pre_div << RT5665_I2S_PD2_SFT; |
4167 | snd_soc_component_update_bits(component, RT5665_I2S2_SDP, |
4168 | RT5665_I2S_DL_MASK, val: val_len); |
4169 | break; |
4170 | case RT5665_AIF3: |
4171 | reg_clk = RT5665_ADDA_CLK_2; |
4172 | mask_clk = RT5665_I2S_PD3_MASK; |
4173 | val_clk = pre_div << RT5665_I2S_PD3_SFT; |
4174 | snd_soc_component_update_bits(component, RT5665_I2S3_SDP, |
4175 | RT5665_I2S_DL_MASK, val: val_len); |
4176 | break; |
4177 | default: |
4178 | dev_err(component->dev, "Invalid dai->id: %d\n" , dai->id); |
4179 | return -EINVAL; |
4180 | } |
4181 | |
4182 | snd_soc_component_update_bits(component, reg: reg_clk, mask: mask_clk, val: val_clk); |
4183 | snd_soc_component_update_bits(component, RT5665_STO1_DAC_SIL_DET, mask: 0x3700, val: val_bits); |
4184 | |
4185 | switch (rt5665->lrck[dai->id]) { |
4186 | case 192000: |
4187 | snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, |
4188 | RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK, |
4189 | RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32); |
4190 | break; |
4191 | case 96000: |
4192 | snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, |
4193 | RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK, |
4194 | RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64); |
4195 | break; |
4196 | default: |
4197 | snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1, |
4198 | RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK, |
4199 | RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128); |
4200 | break; |
4201 | } |
4202 | |
4203 | if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { |
4204 | snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, |
4205 | RT5665_I2S2_M_PD_MASK, val: pre_div << RT5665_I2S2_M_PD_SFT); |
4206 | } |
4207 | if (rt5665->master[RT5665_AIF3]) { |
4208 | snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, |
4209 | RT5665_I2S3_M_PD_MASK, val: pre_div << RT5665_I2S3_M_PD_SFT); |
4210 | } |
4211 | |
4212 | return 0; |
4213 | } |
4214 | |
4215 | static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
4216 | { |
4217 | struct snd_soc_component *component = dai->component; |
4218 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4219 | unsigned int reg_val = 0; |
4220 | |
4221 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
4222 | case SND_SOC_DAIFMT_CBM_CFM: |
4223 | rt5665->master[dai->id] = 1; |
4224 | break; |
4225 | case SND_SOC_DAIFMT_CBS_CFS: |
4226 | reg_val |= RT5665_I2S_MS_S; |
4227 | rt5665->master[dai->id] = 0; |
4228 | break; |
4229 | default: |
4230 | return -EINVAL; |
4231 | } |
4232 | |
4233 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
4234 | case SND_SOC_DAIFMT_NB_NF: |
4235 | break; |
4236 | case SND_SOC_DAIFMT_IB_NF: |
4237 | reg_val |= RT5665_I2S_BP_INV; |
4238 | break; |
4239 | default: |
4240 | return -EINVAL; |
4241 | } |
4242 | |
4243 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
4244 | case SND_SOC_DAIFMT_I2S: |
4245 | break; |
4246 | case SND_SOC_DAIFMT_LEFT_J: |
4247 | reg_val |= RT5665_I2S_DF_LEFT; |
4248 | break; |
4249 | case SND_SOC_DAIFMT_DSP_A: |
4250 | reg_val |= RT5665_I2S_DF_PCM_A; |
4251 | break; |
4252 | case SND_SOC_DAIFMT_DSP_B: |
4253 | reg_val |= RT5665_I2S_DF_PCM_B; |
4254 | break; |
4255 | default: |
4256 | return -EINVAL; |
4257 | } |
4258 | |
4259 | switch (dai->id) { |
4260 | case RT5665_AIF1_1: |
4261 | case RT5665_AIF1_2: |
4262 | snd_soc_component_update_bits(component, RT5665_I2S1_SDP, |
4263 | RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK | |
4264 | RT5665_I2S_DF_MASK, val: reg_val); |
4265 | break; |
4266 | case RT5665_AIF2_1: |
4267 | case RT5665_AIF2_2: |
4268 | snd_soc_component_update_bits(component, RT5665_I2S2_SDP, |
4269 | RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK | |
4270 | RT5665_I2S_DF_MASK, val: reg_val); |
4271 | break; |
4272 | case RT5665_AIF3: |
4273 | snd_soc_component_update_bits(component, RT5665_I2S3_SDP, |
4274 | RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK | |
4275 | RT5665_I2S_DF_MASK, val: reg_val); |
4276 | break; |
4277 | default: |
4278 | dev_err(component->dev, "Invalid dai->id: %d\n" , dai->id); |
4279 | return -EINVAL; |
4280 | } |
4281 | return 0; |
4282 | } |
4283 | |
4284 | static int rt5665_set_component_sysclk(struct snd_soc_component *component, int clk_id, |
4285 | int source, unsigned int freq, int dir) |
4286 | { |
4287 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4288 | unsigned int reg_val = 0, src = 0; |
4289 | |
4290 | if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src) |
4291 | return 0; |
4292 | |
4293 | switch (clk_id) { |
4294 | case RT5665_SCLK_S_MCLK: |
4295 | reg_val |= RT5665_SCLK_SRC_MCLK; |
4296 | src = RT5665_CLK_SRC_MCLK; |
4297 | break; |
4298 | case RT5665_SCLK_S_PLL1: |
4299 | reg_val |= RT5665_SCLK_SRC_PLL1; |
4300 | src = RT5665_CLK_SRC_PLL1; |
4301 | break; |
4302 | case RT5665_SCLK_S_RCCLK: |
4303 | reg_val |= RT5665_SCLK_SRC_RCCLK; |
4304 | src = RT5665_CLK_SRC_RCCLK; |
4305 | break; |
4306 | default: |
4307 | dev_err(component->dev, "Invalid clock id (%d)\n" , clk_id); |
4308 | return -EINVAL; |
4309 | } |
4310 | snd_soc_component_update_bits(component, RT5665_GLB_CLK, |
4311 | RT5665_SCLK_SRC_MASK, val: reg_val); |
4312 | |
4313 | if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { |
4314 | snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, |
4315 | RT5665_I2S2_SRC_MASK, val: src << RT5665_I2S2_SRC_SFT); |
4316 | } |
4317 | if (rt5665->master[RT5665_AIF3]) { |
4318 | snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1, |
4319 | RT5665_I2S3_SRC_MASK, val: src << RT5665_I2S3_SRC_SFT); |
4320 | } |
4321 | |
4322 | rt5665->sysclk = freq; |
4323 | rt5665->sysclk_src = clk_id; |
4324 | |
4325 | dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n" , freq, clk_id); |
4326 | |
4327 | return 0; |
4328 | } |
4329 | |
4330 | static int rt5665_set_component_pll(struct snd_soc_component *component, int pll_id, |
4331 | int source, unsigned int freq_in, |
4332 | unsigned int freq_out) |
4333 | { |
4334 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4335 | struct rl6231_pll_code pll_code; |
4336 | int ret; |
4337 | |
4338 | if (source == rt5665->pll_src && freq_in == rt5665->pll_in && |
4339 | freq_out == rt5665->pll_out) |
4340 | return 0; |
4341 | |
4342 | if (!freq_in || !freq_out) { |
4343 | dev_dbg(component->dev, "PLL disabled\n" ); |
4344 | |
4345 | rt5665->pll_in = 0; |
4346 | rt5665->pll_out = 0; |
4347 | snd_soc_component_update_bits(component, RT5665_GLB_CLK, |
4348 | RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK); |
4349 | return 0; |
4350 | } |
4351 | |
4352 | switch (source) { |
4353 | case RT5665_PLL1_S_MCLK: |
4354 | snd_soc_component_update_bits(component, RT5665_GLB_CLK, |
4355 | RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK); |
4356 | break; |
4357 | case RT5665_PLL1_S_BCLK1: |
4358 | snd_soc_component_update_bits(component, RT5665_GLB_CLK, |
4359 | RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1); |
4360 | break; |
4361 | case RT5665_PLL1_S_BCLK2: |
4362 | snd_soc_component_update_bits(component, RT5665_GLB_CLK, |
4363 | RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2); |
4364 | break; |
4365 | case RT5665_PLL1_S_BCLK3: |
4366 | snd_soc_component_update_bits(component, RT5665_GLB_CLK, |
4367 | RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3); |
4368 | break; |
4369 | default: |
4370 | dev_err(component->dev, "Unknown PLL Source %d\n" , source); |
4371 | return -EINVAL; |
4372 | } |
4373 | |
4374 | ret = rl6231_pll_calc(freq_in, freq_out, pll_code: &pll_code); |
4375 | if (ret < 0) { |
4376 | dev_err(component->dev, "Unsupported input clock %d\n" , freq_in); |
4377 | return ret; |
4378 | } |
4379 | |
4380 | dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n" , |
4381 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), |
4382 | pll_code.n_code, pll_code.k_code); |
4383 | |
4384 | snd_soc_component_write(component, RT5665_PLL_CTRL_1, |
4385 | val: pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code); |
4386 | snd_soc_component_write(component, RT5665_PLL_CTRL_2, |
4387 | val: ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT) | |
4388 | (pll_code.m_bp << RT5665_PLL_M_BP_SFT)); |
4389 | |
4390 | rt5665->pll_in = freq_in; |
4391 | rt5665->pll_out = freq_out; |
4392 | rt5665->pll_src = source; |
4393 | |
4394 | return 0; |
4395 | } |
4396 | |
4397 | static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) |
4398 | { |
4399 | struct snd_soc_component *component = dai->component; |
4400 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4401 | |
4402 | dev_dbg(component->dev, "%s ratio=%d\n" , __func__, ratio); |
4403 | |
4404 | rt5665->bclk[dai->id] = ratio; |
4405 | |
4406 | if (ratio == 64) { |
4407 | switch (dai->id) { |
4408 | case RT5665_AIF2_1: |
4409 | case RT5665_AIF2_2: |
4410 | snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2, |
4411 | RT5665_I2S_BCLK_MS2_MASK, |
4412 | RT5665_I2S_BCLK_MS2_64); |
4413 | break; |
4414 | case RT5665_AIF3: |
4415 | snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2, |
4416 | RT5665_I2S_BCLK_MS3_MASK, |
4417 | RT5665_I2S_BCLK_MS3_64); |
4418 | break; |
4419 | } |
4420 | } |
4421 | |
4422 | return 0; |
4423 | } |
4424 | |
4425 | static int rt5665_set_bias_level(struct snd_soc_component *component, |
4426 | enum snd_soc_bias_level level) |
4427 | { |
4428 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4429 | |
4430 | switch (level) { |
4431 | case SND_SOC_BIAS_PREPARE: |
4432 | regmap_update_bits(map: rt5665->regmap, RT5665_DIG_MISC, |
4433 | RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL); |
4434 | break; |
4435 | |
4436 | case SND_SOC_BIAS_STANDBY: |
4437 | regmap_update_bits(map: rt5665->regmap, RT5665_PWR_DIG_1, |
4438 | RT5665_PWR_LDO, RT5665_PWR_LDO); |
4439 | regmap_update_bits(map: rt5665->regmap, RT5665_PWR_ANLG_1, |
4440 | RT5665_PWR_MB, RT5665_PWR_MB); |
4441 | regmap_update_bits(map: rt5665->regmap, RT5665_DIG_MISC, |
4442 | RT5665_DIG_GATE_CTRL, val: 0); |
4443 | break; |
4444 | case SND_SOC_BIAS_OFF: |
4445 | regmap_update_bits(map: rt5665->regmap, RT5665_PWR_DIG_1, |
4446 | RT5665_PWR_LDO, val: 0); |
4447 | regmap_update_bits(map: rt5665->regmap, RT5665_PWR_ANLG_1, |
4448 | RT5665_PWR_MB, val: 0); |
4449 | break; |
4450 | |
4451 | default: |
4452 | break; |
4453 | } |
4454 | |
4455 | return 0; |
4456 | } |
4457 | |
4458 | static int rt5665_probe(struct snd_soc_component *component) |
4459 | { |
4460 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4461 | |
4462 | rt5665->component = component; |
4463 | |
4464 | schedule_delayed_work(dwork: &rt5665->calibrate_work, delay: msecs_to_jiffies(m: 100)); |
4465 | |
4466 | return 0; |
4467 | } |
4468 | |
4469 | static void rt5665_remove(struct snd_soc_component *component) |
4470 | { |
4471 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4472 | |
4473 | regmap_write(map: rt5665->regmap, RT5665_RESET, val: 0); |
4474 | |
4475 | regulator_bulk_disable(ARRAY_SIZE(rt5665->supplies), consumers: rt5665->supplies); |
4476 | } |
4477 | |
4478 | #ifdef CONFIG_PM |
4479 | static int rt5665_suspend(struct snd_soc_component *component) |
4480 | { |
4481 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4482 | |
4483 | regcache_cache_only(map: rt5665->regmap, enable: true); |
4484 | regcache_mark_dirty(map: rt5665->regmap); |
4485 | return 0; |
4486 | } |
4487 | |
4488 | static int rt5665_resume(struct snd_soc_component *component) |
4489 | { |
4490 | struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(c: component); |
4491 | |
4492 | regcache_cache_only(map: rt5665->regmap, enable: false); |
4493 | regcache_sync(map: rt5665->regmap); |
4494 | |
4495 | return 0; |
4496 | } |
4497 | #else |
4498 | #define rt5665_suspend NULL |
4499 | #define rt5665_resume NULL |
4500 | #endif |
4501 | |
4502 | #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000 |
4503 | #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
4504 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) |
4505 | |
4506 | static const struct snd_soc_dai_ops rt5665_aif_dai_ops = { |
4507 | .hw_params = rt5665_hw_params, |
4508 | .set_fmt = rt5665_set_dai_fmt, |
4509 | .set_tdm_slot = rt5665_set_tdm_slot, |
4510 | .set_bclk_ratio = rt5665_set_bclk_ratio, |
4511 | }; |
4512 | |
4513 | static struct snd_soc_dai_driver rt5665_dai[] = { |
4514 | { |
4515 | .name = "rt5665-aif1_1" , |
4516 | .id = RT5665_AIF1_1, |
4517 | .playback = { |
4518 | .stream_name = "AIF1 Playback" , |
4519 | .channels_min = 1, |
4520 | .channels_max = 8, |
4521 | .rates = RT5665_STEREO_RATES, |
4522 | .formats = RT5665_FORMATS, |
4523 | }, |
4524 | .capture = { |
4525 | .stream_name = "AIF1_1 Capture" , |
4526 | .channels_min = 1, |
4527 | .channels_max = 8, |
4528 | .rates = RT5665_STEREO_RATES, |
4529 | .formats = RT5665_FORMATS, |
4530 | }, |
4531 | .ops = &rt5665_aif_dai_ops, |
4532 | }, |
4533 | { |
4534 | .name = "rt5665-aif1_2" , |
4535 | .id = RT5665_AIF1_2, |
4536 | .capture = { |
4537 | .stream_name = "AIF1_2 Capture" , |
4538 | .channels_min = 1, |
4539 | .channels_max = 8, |
4540 | .rates = RT5665_STEREO_RATES, |
4541 | .formats = RT5665_FORMATS, |
4542 | }, |
4543 | .ops = &rt5665_aif_dai_ops, |
4544 | }, |
4545 | { |
4546 | .name = "rt5665-aif2_1" , |
4547 | .id = RT5665_AIF2_1, |
4548 | .playback = { |
4549 | .stream_name = "AIF2_1 Playback" , |
4550 | .channels_min = 1, |
4551 | .channels_max = 2, |
4552 | .rates = RT5665_STEREO_RATES, |
4553 | .formats = RT5665_FORMATS, |
4554 | }, |
4555 | .capture = { |
4556 | .stream_name = "AIF2_1 Capture" , |
4557 | .channels_min = 1, |
4558 | .channels_max = 2, |
4559 | .rates = RT5665_STEREO_RATES, |
4560 | .formats = RT5665_FORMATS, |
4561 | }, |
4562 | .ops = &rt5665_aif_dai_ops, |
4563 | }, |
4564 | { |
4565 | .name = "rt5665-aif2_2" , |
4566 | .id = RT5665_AIF2_2, |
4567 | .playback = { |
4568 | .stream_name = "AIF2_2 Playback" , |
4569 | .channels_min = 1, |
4570 | .channels_max = 2, |
4571 | .rates = RT5665_STEREO_RATES, |
4572 | .formats = RT5665_FORMATS, |
4573 | }, |
4574 | .capture = { |
4575 | .stream_name = "AIF2_2 Capture" , |
4576 | .channels_min = 1, |
4577 | .channels_max = 2, |
4578 | .rates = RT5665_STEREO_RATES, |
4579 | .formats = RT5665_FORMATS, |
4580 | }, |
4581 | .ops = &rt5665_aif_dai_ops, |
4582 | }, |
4583 | { |
4584 | .name = "rt5665-aif3" , |
4585 | .id = RT5665_AIF3, |
4586 | .playback = { |
4587 | .stream_name = "AIF3 Playback" , |
4588 | .channels_min = 1, |
4589 | .channels_max = 2, |
4590 | .rates = RT5665_STEREO_RATES, |
4591 | .formats = RT5665_FORMATS, |
4592 | }, |
4593 | .capture = { |
4594 | .stream_name = "AIF3 Capture" , |
4595 | .channels_min = 1, |
4596 | .channels_max = 2, |
4597 | .rates = RT5665_STEREO_RATES, |
4598 | .formats = RT5665_FORMATS, |
4599 | }, |
4600 | .ops = &rt5665_aif_dai_ops, |
4601 | }, |
4602 | }; |
4603 | |
4604 | static const struct snd_soc_component_driver soc_component_dev_rt5665 = { |
4605 | .probe = rt5665_probe, |
4606 | .remove = rt5665_remove, |
4607 | .suspend = rt5665_suspend, |
4608 | .resume = rt5665_resume, |
4609 | .set_bias_level = rt5665_set_bias_level, |
4610 | .controls = rt5665_snd_controls, |
4611 | .num_controls = ARRAY_SIZE(rt5665_snd_controls), |
4612 | .dapm_widgets = rt5665_dapm_widgets, |
4613 | .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets), |
4614 | .dapm_routes = rt5665_dapm_routes, |
4615 | .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes), |
4616 | .set_sysclk = rt5665_set_component_sysclk, |
4617 | .set_pll = rt5665_set_component_pll, |
4618 | .set_jack = rt5665_set_jack_detect, |
4619 | .use_pmdown_time = 1, |
4620 | .endianness = 1, |
4621 | }; |
4622 | |
4623 | |
4624 | static const struct regmap_config rt5665_regmap = { |
4625 | .reg_bits = 16, |
4626 | .val_bits = 16, |
4627 | .max_register = 0x0400, |
4628 | .volatile_reg = rt5665_volatile_register, |
4629 | .readable_reg = rt5665_readable_register, |
4630 | .cache_type = REGCACHE_MAPLE, |
4631 | .reg_defaults = rt5665_reg, |
4632 | .num_reg_defaults = ARRAY_SIZE(rt5665_reg), |
4633 | .use_single_read = true, |
4634 | .use_single_write = true, |
4635 | }; |
4636 | |
4637 | static const struct i2c_device_id rt5665_i2c_id[] = { |
4638 | {"rt5665" , 0}, |
4639 | {} |
4640 | }; |
4641 | MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id); |
4642 | |
4643 | static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev) |
4644 | { |
4645 | rt5665->pdata.in1_diff = of_property_read_bool(np: dev->of_node, |
4646 | propname: "realtek,in1-differential" ); |
4647 | rt5665->pdata.in2_diff = of_property_read_bool(np: dev->of_node, |
4648 | propname: "realtek,in2-differential" ); |
4649 | rt5665->pdata.in3_diff = of_property_read_bool(np: dev->of_node, |
4650 | propname: "realtek,in3-differential" ); |
4651 | rt5665->pdata.in4_diff = of_property_read_bool(np: dev->of_node, |
4652 | propname: "realtek,in4-differential" ); |
4653 | |
4654 | of_property_read_u32(np: dev->of_node, propname: "realtek,dmic1-data-pin" , |
4655 | out_value: &rt5665->pdata.dmic1_data_pin); |
4656 | of_property_read_u32(np: dev->of_node, propname: "realtek,dmic2-data-pin" , |
4657 | out_value: &rt5665->pdata.dmic2_data_pin); |
4658 | of_property_read_u32(np: dev->of_node, propname: "realtek,jd-src" , |
4659 | out_value: &rt5665->pdata.jd_src); |
4660 | |
4661 | return 0; |
4662 | } |
4663 | |
4664 | static void rt5665_calibrate(struct rt5665_priv *rt5665) |
4665 | { |
4666 | int value, count; |
4667 | |
4668 | mutex_lock(&rt5665->calibrate_mutex); |
4669 | |
4670 | regcache_cache_bypass(map: rt5665->regmap, enable: true); |
4671 | |
4672 | regmap_write(map: rt5665->regmap, RT5665_RESET, val: 0); |
4673 | regmap_write(map: rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, val: 0xa602); |
4674 | regmap_write(map: rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, val: 0x0c26); |
4675 | regmap_write(map: rt5665->regmap, RT5665_MONOMIX_IN_GAIN, val: 0x021f); |
4676 | regmap_write(map: rt5665->regmap, RT5665_MONO_OUT, val: 0x480a); |
4677 | regmap_write(map: rt5665->regmap, RT5665_PWR_MIXER, val: 0x083f); |
4678 | regmap_write(map: rt5665->regmap, RT5665_PWR_DIG_1, val: 0x0180); |
4679 | regmap_write(map: rt5665->regmap, RT5665_EJD_CTRL_1, val: 0x4040); |
4680 | regmap_write(map: rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, val: 0x0000); |
4681 | regmap_write(map: rt5665->regmap, RT5665_DIG_MISC, val: 0x0001); |
4682 | regmap_write(map: rt5665->regmap, RT5665_MICBIAS_2, val: 0x0380); |
4683 | regmap_write(map: rt5665->regmap, RT5665_GLB_CLK, val: 0x8000); |
4684 | regmap_write(map: rt5665->regmap, RT5665_ADDA_CLK_1, val: 0x1000); |
4685 | regmap_write(map: rt5665->regmap, RT5665_CHOP_DAC, val: 0x3030); |
4686 | regmap_write(map: rt5665->regmap, RT5665_CALIB_ADC_CTRL, val: 0x3c05); |
4687 | regmap_write(map: rt5665->regmap, RT5665_PWR_ANLG_1, val: 0xaa3e); |
4688 | usleep_range(min: 15000, max: 20000); |
4689 | regmap_write(map: rt5665->regmap, RT5665_PWR_ANLG_1, val: 0xfe7e); |
4690 | regmap_write(map: rt5665->regmap, RT5665_HP_CALIB_CTRL_2, val: 0x0321); |
4691 | |
4692 | regmap_write(map: rt5665->regmap, RT5665_HP_CALIB_CTRL_1, val: 0xfc00); |
4693 | count = 0; |
4694 | while (true) { |
4695 | regmap_read(map: rt5665->regmap, RT5665_HP_CALIB_STA_1, val: &value); |
4696 | if (value & 0x8000) |
4697 | usleep_range(min: 10000, max: 10005); |
4698 | else |
4699 | break; |
4700 | |
4701 | if (count > 60) { |
4702 | pr_err("HP Calibration Failure\n" ); |
4703 | regmap_write(map: rt5665->regmap, RT5665_RESET, val: 0); |
4704 | regcache_cache_bypass(map: rt5665->regmap, enable: false); |
4705 | goto out_unlock; |
4706 | } |
4707 | |
4708 | count++; |
4709 | } |
4710 | |
4711 | regmap_write(map: rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, val: 0x9e24); |
4712 | count = 0; |
4713 | while (true) { |
4714 | regmap_read(map: rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, val: &value); |
4715 | if (value & 0x8000) |
4716 | usleep_range(min: 10000, max: 10005); |
4717 | else |
4718 | break; |
4719 | |
4720 | if (count > 60) { |
4721 | pr_err("MONO Calibration Failure\n" ); |
4722 | regmap_write(map: rt5665->regmap, RT5665_RESET, val: 0); |
4723 | regcache_cache_bypass(map: rt5665->regmap, enable: false); |
4724 | goto out_unlock; |
4725 | } |
4726 | |
4727 | count++; |
4728 | } |
4729 | |
4730 | regmap_write(map: rt5665->regmap, RT5665_RESET, val: 0); |
4731 | regcache_cache_bypass(map: rt5665->regmap, enable: false); |
4732 | |
4733 | regcache_mark_dirty(map: rt5665->regmap); |
4734 | regcache_sync(map: rt5665->regmap); |
4735 | |
4736 | regmap_write(map: rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, val: 0xa602); |
4737 | regmap_write(map: rt5665->regmap, RT5665_ASRC_8, val: 0x0120); |
4738 | |
4739 | out_unlock: |
4740 | rt5665->calibration_done = true; |
4741 | mutex_unlock(lock: &rt5665->calibrate_mutex); |
4742 | } |
4743 | |
4744 | static void rt5665_calibrate_handler(struct work_struct *work) |
4745 | { |
4746 | struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv, |
4747 | calibrate_work.work); |
4748 | |
4749 | while (!snd_soc_card_is_instantiated(card: rt5665->component->card)) { |
4750 | pr_debug("%s\n" , __func__); |
4751 | usleep_range(min: 10000, max: 15000); |
4752 | } |
4753 | |
4754 | rt5665_calibrate(rt5665); |
4755 | } |
4756 | |
4757 | static int rt5665_i2c_probe(struct i2c_client *i2c) |
4758 | { |
4759 | struct rt5665_platform_data *pdata = dev_get_platdata(dev: &i2c->dev); |
4760 | struct rt5665_priv *rt5665; |
4761 | int i, ret; |
4762 | unsigned int val; |
4763 | |
4764 | rt5665 = devm_kzalloc(dev: &i2c->dev, size: sizeof(struct rt5665_priv), |
4765 | GFP_KERNEL); |
4766 | |
4767 | if (rt5665 == NULL) |
4768 | return -ENOMEM; |
4769 | |
4770 | i2c_set_clientdata(client: i2c, data: rt5665); |
4771 | |
4772 | if (pdata) |
4773 | rt5665->pdata = *pdata; |
4774 | else |
4775 | rt5665_parse_dt(rt5665, dev: &i2c->dev); |
4776 | |
4777 | for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++) |
4778 | rt5665->supplies[i].supply = rt5665_supply_names[i]; |
4779 | |
4780 | ret = devm_regulator_bulk_get(dev: &i2c->dev, ARRAY_SIZE(rt5665->supplies), |
4781 | consumers: rt5665->supplies); |
4782 | if (ret != 0) { |
4783 | dev_err(&i2c->dev, "Failed to request supplies: %d\n" , ret); |
4784 | return ret; |
4785 | } |
4786 | |
4787 | ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies), |
4788 | consumers: rt5665->supplies); |
4789 | if (ret != 0) { |
4790 | dev_err(&i2c->dev, "Failed to enable supplies: %d\n" , ret); |
4791 | return ret; |
4792 | } |
4793 | |
4794 | |
4795 | rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(dev: &i2c->dev, |
4796 | con_id: "realtek,ldo1-en" , |
4797 | flags: GPIOD_OUT_HIGH); |
4798 | if (IS_ERR(ptr: rt5665->gpiod_ldo1_en)) { |
4799 | dev_err(&i2c->dev, "Failed gpio request ldo1_en\n" ); |
4800 | return PTR_ERR(ptr: rt5665->gpiod_ldo1_en); |
4801 | } |
4802 | |
4803 | /* Sleep for 300 ms miniumum */ |
4804 | usleep_range(min: 300000, max: 350000); |
4805 | |
4806 | rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap); |
4807 | if (IS_ERR(ptr: rt5665->regmap)) { |
4808 | ret = PTR_ERR(ptr: rt5665->regmap); |
4809 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n" , |
4810 | ret); |
4811 | return ret; |
4812 | } |
4813 | |
4814 | regmap_read(map: rt5665->regmap, RT5665_DEVICE_ID, val: &val); |
4815 | if (val != DEVICE_ID) { |
4816 | dev_err(&i2c->dev, |
4817 | "Device with ID register %x is not rt5665\n" , val); |
4818 | return -ENODEV; |
4819 | } |
4820 | |
4821 | regmap_read(map: rt5665->regmap, RT5665_RESET, val: &val); |
4822 | switch (val) { |
4823 | case 0x0: |
4824 | rt5665->id = CODEC_5666; |
4825 | break; |
4826 | case 0x3: |
4827 | default: |
4828 | rt5665->id = CODEC_5665; |
4829 | break; |
4830 | } |
4831 | |
4832 | regmap_write(map: rt5665->regmap, RT5665_RESET, val: 0); |
4833 | |
4834 | /* line in diff mode*/ |
4835 | if (rt5665->pdata.in1_diff) |
4836 | regmap_update_bits(map: rt5665->regmap, RT5665_IN1_IN2, |
4837 | RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK); |
4838 | if (rt5665->pdata.in2_diff) |
4839 | regmap_update_bits(map: rt5665->regmap, RT5665_IN1_IN2, |
4840 | RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK); |
4841 | if (rt5665->pdata.in3_diff) |
4842 | regmap_update_bits(map: rt5665->regmap, RT5665_IN3_IN4, |
4843 | RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK); |
4844 | if (rt5665->pdata.in4_diff) |
4845 | regmap_update_bits(map: rt5665->regmap, RT5665_IN3_IN4, |
4846 | RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK); |
4847 | |
4848 | /* DMIC pin*/ |
4849 | if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL || |
4850 | rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) { |
4851 | regmap_update_bits(map: rt5665->regmap, RT5665_GPIO_CTRL_2, |
4852 | RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL); |
4853 | regmap_update_bits(map: rt5665->regmap, RT5665_GPIO_CTRL_1, |
4854 | RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL); |
4855 | switch (rt5665->pdata.dmic1_data_pin) { |
4856 | case RT5665_DMIC1_DATA_IN2N: |
4857 | regmap_update_bits(map: rt5665->regmap, RT5665_DMIC_CTRL_1, |
4858 | RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N); |
4859 | break; |
4860 | |
4861 | case RT5665_DMIC1_DATA_GPIO4: |
4862 | regmap_update_bits(map: rt5665->regmap, RT5665_DMIC_CTRL_1, |
4863 | RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4); |
4864 | regmap_update_bits(map: rt5665->regmap, RT5665_GPIO_CTRL_1, |
4865 | RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA); |
4866 | break; |
4867 | |
4868 | default: |
4869 | dev_dbg(&i2c->dev, "no DMIC1\n" ); |
4870 | break; |
4871 | } |
4872 | |
4873 | switch (rt5665->pdata.dmic2_data_pin) { |
4874 | case RT5665_DMIC2_DATA_IN2P: |
4875 | regmap_update_bits(map: rt5665->regmap, RT5665_DMIC_CTRL_1, |
4876 | RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P); |
4877 | break; |
4878 | |
4879 | case RT5665_DMIC2_DATA_GPIO5: |
4880 | regmap_update_bits(map: rt5665->regmap, |
4881 | RT5665_DMIC_CTRL_1, |
4882 | RT5665_DMIC_2_DP_MASK, |
4883 | RT5665_DMIC_2_DP_GPIO5); |
4884 | regmap_update_bits(map: rt5665->regmap, RT5665_GPIO_CTRL_1, |
4885 | RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA); |
4886 | break; |
4887 | |
4888 | default: |
4889 | dev_dbg(&i2c->dev, "no DMIC2\n" ); |
4890 | break; |
4891 | |
4892 | } |
4893 | } |
4894 | |
4895 | regmap_write(map: rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, val: 0x0002); |
4896 | regmap_update_bits(map: rt5665->regmap, RT5665_EJD_CTRL_1, |
4897 | mask: 0xf000 | RT5665_VREF_POW_MASK, val: 0xe000 | RT5665_VREF_POW_REG); |
4898 | /* Work around for pow_pump */ |
4899 | regmap_update_bits(map: rt5665->regmap, RT5665_STO1_DAC_SIL_DET, |
4900 | RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS); |
4901 | |
4902 | regmap_update_bits(map: rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, |
4903 | RT5665_PM_HP_MASK, RT5665_PM_HP_HV); |
4904 | |
4905 | /* Set GPIO4,8 as input for combo jack */ |
4906 | if (rt5665->id == CODEC_5666) { |
4907 | regmap_update_bits(map: rt5665->regmap, RT5665_GPIO_CTRL_2, |
4908 | RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN); |
4909 | regmap_update_bits(map: rt5665->regmap, RT5665_GPIO_CTRL_3, |
4910 | RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN); |
4911 | } |
4912 | |
4913 | /* Enhance performance*/ |
4914 | regmap_update_bits(map: rt5665->regmap, RT5665_PWR_ANLG_1, |
4915 | RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK, |
4916 | RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12); |
4917 | |
4918 | INIT_DELAYED_WORK(&rt5665->jack_detect_work, |
4919 | rt5665_jack_detect_handler); |
4920 | INIT_DELAYED_WORK(&rt5665->calibrate_work, |
4921 | rt5665_calibrate_handler); |
4922 | INIT_DELAYED_WORK(&rt5665->jd_check_work, |
4923 | rt5665_jd_check_handler); |
4924 | |
4925 | mutex_init(&rt5665->calibrate_mutex); |
4926 | |
4927 | if (i2c->irq) { |
4928 | ret = devm_request_threaded_irq(dev: &i2c->dev, irq: i2c->irq, NULL, |
4929 | thread_fn: rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
4930 | | IRQF_ONESHOT, devname: "rt5665" , dev_id: rt5665); |
4931 | if (ret) |
4932 | dev_err(&i2c->dev, "Failed to request IRQ: %d\n" , ret); |
4933 | |
4934 | } |
4935 | |
4936 | return devm_snd_soc_register_component(dev: &i2c->dev, |
4937 | component_driver: &soc_component_dev_rt5665, |
4938 | dai_drv: rt5665_dai, ARRAY_SIZE(rt5665_dai)); |
4939 | } |
4940 | |
4941 | static void rt5665_i2c_shutdown(struct i2c_client *client) |
4942 | { |
4943 | struct rt5665_priv *rt5665 = i2c_get_clientdata(client); |
4944 | |
4945 | regmap_write(map: rt5665->regmap, RT5665_RESET, val: 0); |
4946 | } |
4947 | |
4948 | #ifdef CONFIG_OF |
4949 | static const struct of_device_id rt5665_of_match[] = { |
4950 | {.compatible = "realtek,rt5665" }, |
4951 | {.compatible = "realtek,rt5666" }, |
4952 | {}, |
4953 | }; |
4954 | MODULE_DEVICE_TABLE(of, rt5665_of_match); |
4955 | #endif |
4956 | |
4957 | #ifdef CONFIG_ACPI |
4958 | static const struct acpi_device_id rt5665_acpi_match[] = { |
4959 | {"10EC5665" , 0,}, |
4960 | {"10EC5666" , 0,}, |
4961 | {}, |
4962 | }; |
4963 | MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match); |
4964 | #endif |
4965 | |
4966 | static struct i2c_driver rt5665_i2c_driver = { |
4967 | .driver = { |
4968 | .name = "rt5665" , |
4969 | .of_match_table = of_match_ptr(rt5665_of_match), |
4970 | .acpi_match_table = ACPI_PTR(rt5665_acpi_match), |
4971 | }, |
4972 | .probe = rt5665_i2c_probe, |
4973 | .shutdown = rt5665_i2c_shutdown, |
4974 | .id_table = rt5665_i2c_id, |
4975 | }; |
4976 | module_i2c_driver(rt5665_i2c_driver); |
4977 | |
4978 | MODULE_DESCRIPTION("ASoC RT5665 driver" ); |
4979 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>" ); |
4980 | MODULE_LICENSE("GPL v2" ); |
4981 | |