1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * STM32 ALSA SoC Digital Audio Interface (SAI) driver. |
4 | * |
5 | * Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
6 | * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. |
7 | */ |
8 | |
9 | #include <linux/clk.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/module.h> |
13 | #include <linux/of_irq.h> |
14 | #include <linux/of_platform.h> |
15 | #include <linux/pm_runtime.h> |
16 | #include <linux/regmap.h> |
17 | |
18 | #include <sound/asoundef.h> |
19 | #include <sound/core.h> |
20 | #include <sound/dmaengine_pcm.h> |
21 | #include <sound/pcm_params.h> |
22 | |
23 | #include "stm32_sai.h" |
24 | |
25 | #define SAI_FREE_PROTOCOL 0x0 |
26 | #define SAI_SPDIF_PROTOCOL 0x1 |
27 | |
28 | #define SAI_SLOT_SIZE_AUTO 0x0 |
29 | #define SAI_SLOT_SIZE_16 0x1 |
30 | #define SAI_SLOT_SIZE_32 0x2 |
31 | |
32 | #define SAI_DATASIZE_8 0x2 |
33 | #define SAI_DATASIZE_10 0x3 |
34 | #define SAI_DATASIZE_16 0x4 |
35 | #define SAI_DATASIZE_20 0x5 |
36 | #define SAI_DATASIZE_24 0x6 |
37 | #define SAI_DATASIZE_32 0x7 |
38 | |
39 | #define STM_SAI_DAI_NAME_SIZE 15 |
40 | |
41 | #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) |
42 | #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) |
43 | |
44 | #define STM_SAI_A_ID 0x0 |
45 | #define STM_SAI_B_ID 0x1 |
46 | |
47 | #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) |
48 | |
49 | #define SAI_SYNC_NONE 0x0 |
50 | #define SAI_SYNC_INTERNAL 0x1 |
51 | #define SAI_SYNC_EXTERNAL 0x2 |
52 | |
53 | #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) |
54 | #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) |
55 | #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) |
56 | #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) |
57 | |
58 | #define SAI_IEC60958_BLOCK_FRAMES 192 |
59 | #define SAI_IEC60958_STATUS_BYTES 24 |
60 | |
61 | #define SAI_MCLK_NAME_LEN 32 |
62 | #define SAI_RATE_11K 11025 |
63 | |
64 | /** |
65 | * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) |
66 | * @pdev: device data pointer |
67 | * @regmap: SAI register map pointer |
68 | * @regmap_config: SAI sub block register map configuration pointer |
69 | * @dma_params: dma configuration data for rx or tx channel |
70 | * @cpu_dai_drv: DAI driver data pointer |
71 | * @cpu_dai: DAI runtime data pointer |
72 | * @substream: PCM substream data pointer |
73 | * @pdata: SAI block parent data pointer |
74 | * @np_sync_provider: synchronization provider node |
75 | * @sai_ck: kernel clock feeding the SAI clock generator |
76 | * @sai_mclk: master clock from SAI mclk provider |
77 | * @phys_addr: SAI registers physical base address |
78 | * @mclk_rate: SAI block master clock frequency (Hz). set at init |
79 | * @id: SAI sub block id corresponding to sub-block A or B |
80 | * @dir: SAI block direction (playback or capture). set at init |
81 | * @master: SAI block mode flag. (true=master, false=slave) set at init |
82 | * @spdif: SAI S/PDIF iec60958 mode flag. set at init |
83 | * @fmt: SAI block format. relevant only for custom protocols. set at init |
84 | * @sync: SAI block synchronization mode. (none, internal or external) |
85 | * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) |
86 | * @synci: SAI block ext sync source (client setting). (SAI sync provider index) |
87 | * @fs_length: frame synchronization length. depends on protocol settings |
88 | * @slots: rx or tx slot number |
89 | * @slot_width: rx or tx slot width in bits |
90 | * @slot_mask: rx or tx active slots mask. set at init or at runtime |
91 | * @data_size: PCM data width. corresponds to PCM substream width. |
92 | * @spdif_frm_cnt: S/PDIF playback frame counter |
93 | * @iec958: iec958 data |
94 | * @ctrl_lock: control lock |
95 | * @irq_lock: prevent race condition with IRQ |
96 | */ |
97 | struct stm32_sai_sub_data { |
98 | struct platform_device *pdev; |
99 | struct regmap *regmap; |
100 | const struct regmap_config *regmap_config; |
101 | struct snd_dmaengine_dai_dma_data dma_params; |
102 | struct snd_soc_dai_driver cpu_dai_drv; |
103 | struct snd_soc_dai *cpu_dai; |
104 | struct snd_pcm_substream *substream; |
105 | struct stm32_sai_data *pdata; |
106 | struct device_node *np_sync_provider; |
107 | struct clk *sai_ck; |
108 | struct clk *sai_mclk; |
109 | dma_addr_t phys_addr; |
110 | unsigned int mclk_rate; |
111 | unsigned int id; |
112 | int dir; |
113 | bool master; |
114 | bool spdif; |
115 | int fmt; |
116 | int sync; |
117 | int synco; |
118 | int synci; |
119 | int fs_length; |
120 | int slots; |
121 | int slot_width; |
122 | int slot_mask; |
123 | int data_size; |
124 | unsigned int spdif_frm_cnt; |
125 | struct snd_aes_iec958 iec958; |
126 | struct mutex ctrl_lock; /* protect resources accessed by controls */ |
127 | spinlock_t irq_lock; /* used to prevent race condition with IRQ */ |
128 | }; |
129 | |
130 | enum stm32_sai_fifo_th { |
131 | STM_SAI_FIFO_TH_EMPTY, |
132 | STM_SAI_FIFO_TH_QUARTER, |
133 | STM_SAI_FIFO_TH_HALF, |
134 | STM_SAI_FIFO_TH_3_QUARTER, |
135 | STM_SAI_FIFO_TH_FULL, |
136 | }; |
137 | |
138 | static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) |
139 | { |
140 | switch (reg) { |
141 | case STM_SAI_CR1_REGX: |
142 | case STM_SAI_CR2_REGX: |
143 | case STM_SAI_FRCR_REGX: |
144 | case STM_SAI_SLOTR_REGX: |
145 | case STM_SAI_IMR_REGX: |
146 | case STM_SAI_SR_REGX: |
147 | case STM_SAI_CLRFR_REGX: |
148 | case STM_SAI_DR_REGX: |
149 | case STM_SAI_PDMCR_REGX: |
150 | case STM_SAI_PDMLY_REGX: |
151 | return true; |
152 | default: |
153 | return false; |
154 | } |
155 | } |
156 | |
157 | static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) |
158 | { |
159 | switch (reg) { |
160 | case STM_SAI_DR_REGX: |
161 | case STM_SAI_SR_REGX: |
162 | return true; |
163 | default: |
164 | return false; |
165 | } |
166 | } |
167 | |
168 | static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) |
169 | { |
170 | switch (reg) { |
171 | case STM_SAI_CR1_REGX: |
172 | case STM_SAI_CR2_REGX: |
173 | case STM_SAI_FRCR_REGX: |
174 | case STM_SAI_SLOTR_REGX: |
175 | case STM_SAI_IMR_REGX: |
176 | case STM_SAI_CLRFR_REGX: |
177 | case STM_SAI_DR_REGX: |
178 | case STM_SAI_PDMCR_REGX: |
179 | case STM_SAI_PDMLY_REGX: |
180 | return true; |
181 | default: |
182 | return false; |
183 | } |
184 | } |
185 | |
186 | static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai, |
187 | unsigned int reg, unsigned int mask, |
188 | unsigned int val) |
189 | { |
190 | int ret; |
191 | |
192 | ret = clk_enable(clk: sai->pdata->pclk); |
193 | if (ret < 0) |
194 | return ret; |
195 | |
196 | ret = regmap_update_bits(map: sai->regmap, reg, mask, val); |
197 | |
198 | clk_disable(clk: sai->pdata->pclk); |
199 | |
200 | return ret; |
201 | } |
202 | |
203 | static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai, |
204 | unsigned int reg, unsigned int mask, |
205 | unsigned int val) |
206 | { |
207 | int ret; |
208 | |
209 | ret = clk_enable(clk: sai->pdata->pclk); |
210 | if (ret < 0) |
211 | return ret; |
212 | |
213 | ret = regmap_write_bits(map: sai->regmap, reg, mask, val); |
214 | |
215 | clk_disable(clk: sai->pdata->pclk); |
216 | |
217 | return ret; |
218 | } |
219 | |
220 | static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai, |
221 | unsigned int reg, unsigned int *val) |
222 | { |
223 | int ret; |
224 | |
225 | ret = clk_enable(clk: sai->pdata->pclk); |
226 | if (ret < 0) |
227 | return ret; |
228 | |
229 | ret = regmap_read(map: sai->regmap, reg, val); |
230 | |
231 | clk_disable(clk: sai->pdata->pclk); |
232 | |
233 | return ret; |
234 | } |
235 | |
236 | static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { |
237 | .reg_bits = 32, |
238 | .reg_stride = 4, |
239 | .val_bits = 32, |
240 | .max_register = STM_SAI_DR_REGX, |
241 | .readable_reg = stm32_sai_sub_readable_reg, |
242 | .volatile_reg = stm32_sai_sub_volatile_reg, |
243 | .writeable_reg = stm32_sai_sub_writeable_reg, |
244 | .fast_io = true, |
245 | .cache_type = REGCACHE_FLAT, |
246 | }; |
247 | |
248 | static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { |
249 | .reg_bits = 32, |
250 | .reg_stride = 4, |
251 | .val_bits = 32, |
252 | .max_register = STM_SAI_PDMLY_REGX, |
253 | .readable_reg = stm32_sai_sub_readable_reg, |
254 | .volatile_reg = stm32_sai_sub_volatile_reg, |
255 | .writeable_reg = stm32_sai_sub_writeable_reg, |
256 | .fast_io = true, |
257 | .cache_type = REGCACHE_FLAT, |
258 | }; |
259 | |
260 | static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, |
261 | struct snd_ctl_elem_info *uinfo) |
262 | { |
263 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
264 | uinfo->count = 1; |
265 | |
266 | return 0; |
267 | } |
268 | |
269 | static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, |
270 | struct snd_ctl_elem_value *uctl) |
271 | { |
272 | struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); |
273 | |
274 | mutex_lock(&sai->ctrl_lock); |
275 | memcpy(uctl->value.iec958.status, sai->iec958.status, 4); |
276 | mutex_unlock(lock: &sai->ctrl_lock); |
277 | |
278 | return 0; |
279 | } |
280 | |
281 | static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, |
282 | struct snd_ctl_elem_value *uctl) |
283 | { |
284 | struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); |
285 | |
286 | mutex_lock(&sai->ctrl_lock); |
287 | memcpy(sai->iec958.status, uctl->value.iec958.status, 4); |
288 | mutex_unlock(lock: &sai->ctrl_lock); |
289 | |
290 | return 0; |
291 | } |
292 | |
293 | static const struct snd_kcontrol_new iec958_ctls = { |
294 | .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | |
295 | SNDRV_CTL_ELEM_ACCESS_VOLATILE), |
296 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
297 | .name = SNDRV_CTL_NAME_IEC958("" , PLAYBACK, DEFAULT), |
298 | .info = snd_pcm_iec958_info, |
299 | .get = snd_pcm_iec958_get, |
300 | .put = snd_pcm_iec958_put, |
301 | }; |
302 | |
303 | struct stm32_sai_mclk_data { |
304 | struct clk_hw hw; |
305 | unsigned long freq; |
306 | struct stm32_sai_sub_data *sai_data; |
307 | }; |
308 | |
309 | #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) |
310 | #define STM32_SAI_MAX_CLKS 1 |
311 | |
312 | static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, |
313 | unsigned long input_rate, |
314 | unsigned long output_rate) |
315 | { |
316 | int version = sai->pdata->conf.version; |
317 | int div; |
318 | |
319 | div = DIV_ROUND_CLOSEST(input_rate, output_rate); |
320 | if (div > SAI_XCR1_MCKDIV_MAX(version)) { |
321 | dev_err(&sai->pdev->dev, "Divider %d out of range\n" , div); |
322 | return -EINVAL; |
323 | } |
324 | dev_dbg(&sai->pdev->dev, "SAI divider %d\n" , div); |
325 | |
326 | if (input_rate % div) |
327 | dev_dbg(&sai->pdev->dev, |
328 | "Rate not accurate. requested (%ld), actual (%ld)\n" , |
329 | output_rate, input_rate / div); |
330 | |
331 | return div; |
332 | } |
333 | |
334 | static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, |
335 | unsigned int div) |
336 | { |
337 | int version = sai->pdata->conf.version; |
338 | int ret, cr1, mask; |
339 | |
340 | if (div > SAI_XCR1_MCKDIV_MAX(version)) { |
341 | dev_err(&sai->pdev->dev, "Divider %d out of range\n" , div); |
342 | return -EINVAL; |
343 | } |
344 | |
345 | mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); |
346 | cr1 = SAI_XCR1_MCKDIV_SET(div); |
347 | ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, val: cr1); |
348 | if (ret < 0) |
349 | dev_err(&sai->pdev->dev, "Failed to update CR1 register\n" ); |
350 | |
351 | return ret; |
352 | } |
353 | |
354 | static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai, |
355 | unsigned int rate) |
356 | { |
357 | struct platform_device *pdev = sai->pdev; |
358 | struct clk *parent_clk = sai->pdata->clk_x8k; |
359 | int ret; |
360 | |
361 | if (!(rate % SAI_RATE_11K)) |
362 | parent_clk = sai->pdata->clk_x11k; |
363 | |
364 | ret = clk_set_parent(clk: sai->sai_ck, parent: parent_clk); |
365 | if (ret) |
366 | dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s" , |
367 | ret, ret == -EBUSY ? |
368 | "Active stream rates conflict\n" : "\n" ); |
369 | |
370 | return ret; |
371 | } |
372 | |
373 | static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, |
374 | unsigned long *prate) |
375 | { |
376 | struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); |
377 | struct stm32_sai_sub_data *sai = mclk->sai_data; |
378 | int div; |
379 | |
380 | div = stm32_sai_get_clk_div(sai, input_rate: *prate, output_rate: rate); |
381 | if (div < 0) |
382 | return div; |
383 | |
384 | mclk->freq = *prate / div; |
385 | |
386 | return mclk->freq; |
387 | } |
388 | |
389 | static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, |
390 | unsigned long parent_rate) |
391 | { |
392 | struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); |
393 | |
394 | return mclk->freq; |
395 | } |
396 | |
397 | static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, |
398 | unsigned long parent_rate) |
399 | { |
400 | struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); |
401 | struct stm32_sai_sub_data *sai = mclk->sai_data; |
402 | int div, ret; |
403 | |
404 | div = stm32_sai_get_clk_div(sai, input_rate: parent_rate, output_rate: rate); |
405 | if (div < 0) |
406 | return div; |
407 | |
408 | ret = stm32_sai_set_clk_div(sai, div); |
409 | if (ret) |
410 | return ret; |
411 | |
412 | mclk->freq = rate; |
413 | |
414 | return 0; |
415 | } |
416 | |
417 | static int stm32_sai_mclk_enable(struct clk_hw *hw) |
418 | { |
419 | struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); |
420 | struct stm32_sai_sub_data *sai = mclk->sai_data; |
421 | |
422 | dev_dbg(&sai->pdev->dev, "Enable master clock\n" ); |
423 | |
424 | return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, |
425 | SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); |
426 | } |
427 | |
428 | static void stm32_sai_mclk_disable(struct clk_hw *hw) |
429 | { |
430 | struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); |
431 | struct stm32_sai_sub_data *sai = mclk->sai_data; |
432 | |
433 | dev_dbg(&sai->pdev->dev, "Disable master clock\n" ); |
434 | |
435 | stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, val: 0); |
436 | } |
437 | |
438 | static const struct clk_ops mclk_ops = { |
439 | .enable = stm32_sai_mclk_enable, |
440 | .disable = stm32_sai_mclk_disable, |
441 | .recalc_rate = stm32_sai_mclk_recalc_rate, |
442 | .round_rate = stm32_sai_mclk_round_rate, |
443 | .set_rate = stm32_sai_mclk_set_rate, |
444 | }; |
445 | |
446 | static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) |
447 | { |
448 | struct clk_hw *hw; |
449 | struct stm32_sai_mclk_data *mclk; |
450 | struct device *dev = &sai->pdev->dev; |
451 | const char *pname = __clk_get_name(clk: sai->sai_ck); |
452 | char *mclk_name, *p, *s = (char *)pname; |
453 | int ret, i = 0; |
454 | |
455 | mclk = devm_kzalloc(dev, size: sizeof(*mclk), GFP_KERNEL); |
456 | if (!mclk) |
457 | return -ENOMEM; |
458 | |
459 | mclk_name = devm_kcalloc(dev, n: sizeof(char), |
460 | SAI_MCLK_NAME_LEN, GFP_KERNEL); |
461 | if (!mclk_name) |
462 | return -ENOMEM; |
463 | |
464 | /* |
465 | * Forge mclk clock name from parent clock name and suffix. |
466 | * String after "_" char is stripped in parent name. |
467 | */ |
468 | p = mclk_name; |
469 | while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { |
470 | *p++ = *s++; |
471 | i++; |
472 | } |
473 | STM_SAI_IS_SUB_A(sai) ? strcat(p, q: "a_mclk" ) : strcat(p, q: "b_mclk" ); |
474 | |
475 | mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); |
476 | mclk->sai_data = sai; |
477 | hw = &mclk->hw; |
478 | |
479 | dev_dbg(dev, "Register master clock %s\n" , mclk_name); |
480 | ret = devm_clk_hw_register(dev: &sai->pdev->dev, hw); |
481 | if (ret) { |
482 | dev_err(dev, "mclk register returned %d\n" , ret); |
483 | return ret; |
484 | } |
485 | sai->sai_mclk = hw->clk; |
486 | |
487 | /* register mclk provider */ |
488 | return devm_of_clk_add_hw_provider(dev, get: of_clk_hw_simple_get, data: hw); |
489 | } |
490 | |
491 | static irqreturn_t stm32_sai_isr(int irq, void *devid) |
492 | { |
493 | struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; |
494 | struct platform_device *pdev = sai->pdev; |
495 | unsigned int sr, imr, flags; |
496 | snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; |
497 | |
498 | stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, val: &imr); |
499 | stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, val: &sr); |
500 | |
501 | flags = sr & imr; |
502 | if (!flags) |
503 | return IRQ_NONE; |
504 | |
505 | stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, |
506 | SAI_XCLRFR_MASK); |
507 | |
508 | if (!sai->substream) { |
509 | dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n" , sr); |
510 | return IRQ_NONE; |
511 | } |
512 | |
513 | if (flags & SAI_XIMR_OVRUDRIE) { |
514 | dev_err(&pdev->dev, "IRQ %s\n" , |
515 | STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun" ); |
516 | status = SNDRV_PCM_STATE_XRUN; |
517 | } |
518 | |
519 | if (flags & SAI_XIMR_MUTEDETIE) |
520 | dev_dbg(&pdev->dev, "IRQ mute detected\n" ); |
521 | |
522 | if (flags & SAI_XIMR_WCKCFGIE) { |
523 | dev_err(&pdev->dev, "IRQ wrong clock configuration\n" ); |
524 | status = SNDRV_PCM_STATE_DISCONNECTED; |
525 | } |
526 | |
527 | if (flags & SAI_XIMR_CNRDYIE) |
528 | dev_err(&pdev->dev, "IRQ Codec not ready\n" ); |
529 | |
530 | if (flags & SAI_XIMR_AFSDETIE) { |
531 | dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n" ); |
532 | status = SNDRV_PCM_STATE_XRUN; |
533 | } |
534 | |
535 | if (flags & SAI_XIMR_LFSDETIE) { |
536 | dev_err(&pdev->dev, "IRQ Late frame synchro\n" ); |
537 | status = SNDRV_PCM_STATE_XRUN; |
538 | } |
539 | |
540 | spin_lock(lock: &sai->irq_lock); |
541 | if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) |
542 | snd_pcm_stop_xrun(substream: sai->substream); |
543 | spin_unlock(lock: &sai->irq_lock); |
544 | |
545 | return IRQ_HANDLED; |
546 | } |
547 | |
548 | static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, |
549 | int clk_id, unsigned int freq, int dir) |
550 | { |
551 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
552 | int ret; |
553 | |
554 | if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { |
555 | ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, |
556 | SAI_XCR1_NODIV, |
557 | val: freq ? 0 : SAI_XCR1_NODIV); |
558 | if (ret < 0) |
559 | return ret; |
560 | |
561 | /* Assume shutdown if requested frequency is 0Hz */ |
562 | if (!freq) { |
563 | /* Release mclk rate only if rate was actually set */ |
564 | if (sai->mclk_rate) { |
565 | clk_rate_exclusive_put(clk: sai->sai_mclk); |
566 | sai->mclk_rate = 0; |
567 | } |
568 | return 0; |
569 | } |
570 | |
571 | /* If master clock is used, set parent clock now */ |
572 | ret = stm32_sai_set_parent_clock(sai, rate: freq); |
573 | if (ret) |
574 | return ret; |
575 | |
576 | ret = clk_set_rate_exclusive(clk: sai->sai_mclk, rate: freq); |
577 | if (ret) { |
578 | dev_err(cpu_dai->dev, |
579 | ret == -EBUSY ? |
580 | "Active streams have incompatible rates" : |
581 | "Could not set mclk rate\n" ); |
582 | return ret; |
583 | } |
584 | |
585 | dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n" , freq); |
586 | sai->mclk_rate = freq; |
587 | } |
588 | |
589 | return 0; |
590 | } |
591 | |
592 | static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, |
593 | u32 rx_mask, int slots, int slot_width) |
594 | { |
595 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
596 | int slotr, slotr_mask, slot_size; |
597 | |
598 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { |
599 | dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n" ); |
600 | return 0; |
601 | } |
602 | |
603 | dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n" , |
604 | tx_mask, rx_mask, slots, slot_width); |
605 | |
606 | switch (slot_width) { |
607 | case 16: |
608 | slot_size = SAI_SLOT_SIZE_16; |
609 | break; |
610 | case 32: |
611 | slot_size = SAI_SLOT_SIZE_32; |
612 | break; |
613 | default: |
614 | slot_size = SAI_SLOT_SIZE_AUTO; |
615 | break; |
616 | } |
617 | |
618 | slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | |
619 | SAI_XSLOTR_NBSLOT_SET(slots - 1); |
620 | slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; |
621 | |
622 | /* tx/rx mask set in machine init, if slot number defined in DT */ |
623 | if (STM_SAI_IS_PLAYBACK(sai)) { |
624 | sai->slot_mask = tx_mask; |
625 | slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); |
626 | } |
627 | |
628 | if (STM_SAI_IS_CAPTURE(sai)) { |
629 | sai->slot_mask = rx_mask; |
630 | slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); |
631 | } |
632 | |
633 | slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; |
634 | |
635 | stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, mask: slotr_mask, val: slotr); |
636 | |
637 | sai->slot_width = slot_width; |
638 | sai->slots = slots; |
639 | |
640 | return 0; |
641 | } |
642 | |
643 | static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) |
644 | { |
645 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
646 | int cr1, frcr = 0; |
647 | int cr1_mask, frcr_mask = 0; |
648 | int ret; |
649 | |
650 | dev_dbg(cpu_dai->dev, "fmt %x\n" , fmt); |
651 | |
652 | /* Do not generate master by default */ |
653 | cr1 = SAI_XCR1_NODIV; |
654 | cr1_mask = SAI_XCR1_NODIV; |
655 | |
656 | cr1_mask |= SAI_XCR1_PRTCFG_MASK; |
657 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { |
658 | cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); |
659 | goto conf_update; |
660 | } |
661 | |
662 | cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); |
663 | |
664 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
665 | /* SCK active high for all protocols */ |
666 | case SND_SOC_DAIFMT_I2S: |
667 | cr1 |= SAI_XCR1_CKSTR; |
668 | frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; |
669 | break; |
670 | /* Left justified */ |
671 | case SND_SOC_DAIFMT_MSB: |
672 | frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; |
673 | break; |
674 | /* Right justified */ |
675 | case SND_SOC_DAIFMT_LSB: |
676 | frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; |
677 | break; |
678 | case SND_SOC_DAIFMT_DSP_A: |
679 | frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; |
680 | break; |
681 | case SND_SOC_DAIFMT_DSP_B: |
682 | frcr |= SAI_XFRCR_FSPOL; |
683 | break; |
684 | default: |
685 | dev_err(cpu_dai->dev, "Unsupported protocol %#x\n" , |
686 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); |
687 | return -EINVAL; |
688 | } |
689 | |
690 | cr1_mask |= SAI_XCR1_CKSTR; |
691 | frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | |
692 | SAI_XFRCR_FSDEF; |
693 | |
694 | /* DAI clock strobing. Invert setting previously set */ |
695 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
696 | case SND_SOC_DAIFMT_NB_NF: |
697 | break; |
698 | case SND_SOC_DAIFMT_IB_NF: |
699 | cr1 ^= SAI_XCR1_CKSTR; |
700 | break; |
701 | case SND_SOC_DAIFMT_NB_IF: |
702 | frcr ^= SAI_XFRCR_FSPOL; |
703 | break; |
704 | case SND_SOC_DAIFMT_IB_IF: |
705 | /* Invert fs & sck */ |
706 | cr1 ^= SAI_XCR1_CKSTR; |
707 | frcr ^= SAI_XFRCR_FSPOL; |
708 | break; |
709 | default: |
710 | dev_err(cpu_dai->dev, "Unsupported strobing %#x\n" , |
711 | fmt & SND_SOC_DAIFMT_INV_MASK); |
712 | return -EINVAL; |
713 | } |
714 | cr1_mask |= SAI_XCR1_CKSTR; |
715 | frcr_mask |= SAI_XFRCR_FSPOL; |
716 | |
717 | stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, mask: frcr_mask, val: frcr); |
718 | |
719 | /* DAI clock master masks */ |
720 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
721 | case SND_SOC_DAIFMT_BC_FC: |
722 | /* codec is master */ |
723 | cr1 |= SAI_XCR1_SLAVE; |
724 | sai->master = false; |
725 | break; |
726 | case SND_SOC_DAIFMT_BP_FP: |
727 | sai->master = true; |
728 | break; |
729 | default: |
730 | dev_err(cpu_dai->dev, "Unsupported mode %#x\n" , |
731 | fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); |
732 | return -EINVAL; |
733 | } |
734 | |
735 | /* Set slave mode if sub-block is synchronized with another SAI */ |
736 | if (sai->sync) { |
737 | dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n" ); |
738 | cr1 |= SAI_XCR1_SLAVE; |
739 | sai->master = false; |
740 | } |
741 | |
742 | cr1_mask |= SAI_XCR1_SLAVE; |
743 | |
744 | conf_update: |
745 | ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask: cr1_mask, val: cr1); |
746 | if (ret < 0) { |
747 | dev_err(cpu_dai->dev, "Failed to update CR1 register\n" ); |
748 | return ret; |
749 | } |
750 | |
751 | sai->fmt = fmt; |
752 | |
753 | return 0; |
754 | } |
755 | |
756 | static int stm32_sai_startup(struct snd_pcm_substream *substream, |
757 | struct snd_soc_dai *cpu_dai) |
758 | { |
759 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
760 | int imr, cr2, ret; |
761 | unsigned long flags; |
762 | |
763 | spin_lock_irqsave(&sai->irq_lock, flags); |
764 | sai->substream = substream; |
765 | spin_unlock_irqrestore(lock: &sai->irq_lock, flags); |
766 | |
767 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { |
768 | snd_pcm_hw_constraint_mask64(runtime: substream->runtime, |
769 | SNDRV_PCM_HW_PARAM_FORMAT, |
770 | SNDRV_PCM_FMTBIT_S32_LE); |
771 | snd_pcm_hw_constraint_single(runtime: substream->runtime, |
772 | SNDRV_PCM_HW_PARAM_CHANNELS, val: 2); |
773 | } |
774 | |
775 | ret = clk_prepare_enable(clk: sai->sai_ck); |
776 | if (ret < 0) { |
777 | dev_err(cpu_dai->dev, "Failed to enable clock: %d\n" , ret); |
778 | return ret; |
779 | } |
780 | |
781 | /* Enable ITs */ |
782 | stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, |
783 | SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); |
784 | |
785 | imr = SAI_XIMR_OVRUDRIE; |
786 | if (STM_SAI_IS_CAPTURE(sai)) { |
787 | stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, val: &cr2); |
788 | if (cr2 & SAI_XCR2_MUTECNT_MASK) |
789 | imr |= SAI_XIMR_MUTEDETIE; |
790 | } |
791 | |
792 | if (sai->master) |
793 | imr |= SAI_XIMR_WCKCFGIE; |
794 | else |
795 | imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; |
796 | |
797 | stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, |
798 | SAI_XIMR_MASK, val: imr); |
799 | |
800 | return 0; |
801 | } |
802 | |
803 | static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, |
804 | struct snd_pcm_substream *substream, |
805 | struct snd_pcm_hw_params *params) |
806 | { |
807 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
808 | int cr1, cr1_mask, ret; |
809 | |
810 | /* |
811 | * DMA bursts increment is set to 4 words. |
812 | * SAI fifo threshold is set to half fifo, to keep enough space |
813 | * for DMA incoming bursts. |
814 | */ |
815 | stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX, |
816 | SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, |
817 | SAI_XCR2_FFLUSH | |
818 | SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); |
819 | |
820 | /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ |
821 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { |
822 | sai->spdif_frm_cnt = 0; |
823 | return 0; |
824 | } |
825 | |
826 | /* Mode, data format and channel config */ |
827 | cr1_mask = SAI_XCR1_DS_MASK; |
828 | switch (params_format(p: params)) { |
829 | case SNDRV_PCM_FORMAT_S8: |
830 | cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); |
831 | break; |
832 | case SNDRV_PCM_FORMAT_S16_LE: |
833 | cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); |
834 | break; |
835 | case SNDRV_PCM_FORMAT_S32_LE: |
836 | cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); |
837 | break; |
838 | default: |
839 | dev_err(cpu_dai->dev, "Data format not supported\n" ); |
840 | return -EINVAL; |
841 | } |
842 | |
843 | cr1_mask |= SAI_XCR1_MONO; |
844 | if ((sai->slots == 2) && (params_channels(p: params) == 1)) |
845 | cr1 |= SAI_XCR1_MONO; |
846 | |
847 | ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask: cr1_mask, val: cr1); |
848 | if (ret < 0) { |
849 | dev_err(cpu_dai->dev, "Failed to update CR1 register\n" ); |
850 | return ret; |
851 | } |
852 | |
853 | return 0; |
854 | } |
855 | |
856 | static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) |
857 | { |
858 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
859 | int slotr, slot_sz; |
860 | |
861 | stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, val: &slotr); |
862 | |
863 | /* |
864 | * If SLOTSZ is set to auto in SLOTR, align slot width on data size |
865 | * By default slot width = data size, if not forced from DT |
866 | */ |
867 | slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; |
868 | if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) |
869 | sai->slot_width = sai->data_size; |
870 | |
871 | if (sai->slot_width < sai->data_size) { |
872 | dev_err(cpu_dai->dev, |
873 | "Data size %d larger than slot width\n" , |
874 | sai->data_size); |
875 | return -EINVAL; |
876 | } |
877 | |
878 | /* Slot number is set to 2, if not specified in DT */ |
879 | if (!sai->slots) |
880 | sai->slots = 2; |
881 | |
882 | /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ |
883 | stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, |
884 | SAI_XSLOTR_NBSLOT_MASK, |
885 | SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); |
886 | |
887 | /* Set default slots mask if not already set from DT */ |
888 | if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { |
889 | sai->slot_mask = (1 << sai->slots) - 1; |
890 | stm32_sai_sub_reg_up(sai, |
891 | STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, |
892 | SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); |
893 | } |
894 | |
895 | dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n" , |
896 | sai->slots, sai->slot_width); |
897 | |
898 | return 0; |
899 | } |
900 | |
901 | static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) |
902 | { |
903 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
904 | int fs_active, offset, format; |
905 | int frcr, frcr_mask; |
906 | |
907 | format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
908 | sai->fs_length = sai->slot_width * sai->slots; |
909 | |
910 | fs_active = sai->fs_length / 2; |
911 | if ((format == SND_SOC_DAIFMT_DSP_A) || |
912 | (format == SND_SOC_DAIFMT_DSP_B)) |
913 | fs_active = 1; |
914 | |
915 | frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); |
916 | frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); |
917 | frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; |
918 | |
919 | dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n" , |
920 | sai->fs_length, fs_active); |
921 | |
922 | stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, mask: frcr_mask, val: frcr); |
923 | |
924 | if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { |
925 | offset = sai->slot_width - sai->data_size; |
926 | |
927 | stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, |
928 | SAI_XSLOTR_FBOFF_MASK, |
929 | SAI_XSLOTR_FBOFF_SET(offset)); |
930 | } |
931 | } |
932 | |
933 | static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) |
934 | { |
935 | unsigned char *cs = sai->iec958.status; |
936 | |
937 | cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; |
938 | cs[1] = IEC958_AES1_CON_GENERAL; |
939 | cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; |
940 | cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; |
941 | } |
942 | |
943 | static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, |
944 | struct snd_pcm_runtime *runtime) |
945 | { |
946 | if (!runtime) |
947 | return; |
948 | |
949 | /* Force the sample rate according to runtime rate */ |
950 | mutex_lock(&sai->ctrl_lock); |
951 | switch (runtime->rate) { |
952 | case 22050: |
953 | sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; |
954 | break; |
955 | case 44100: |
956 | sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; |
957 | break; |
958 | case 88200: |
959 | sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; |
960 | break; |
961 | case 176400: |
962 | sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; |
963 | break; |
964 | case 24000: |
965 | sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; |
966 | break; |
967 | case 48000: |
968 | sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; |
969 | break; |
970 | case 96000: |
971 | sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; |
972 | break; |
973 | case 192000: |
974 | sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; |
975 | break; |
976 | case 32000: |
977 | sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; |
978 | break; |
979 | default: |
980 | sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; |
981 | break; |
982 | } |
983 | mutex_unlock(lock: &sai->ctrl_lock); |
984 | } |
985 | |
986 | static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, |
987 | struct snd_pcm_hw_params *params) |
988 | { |
989 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
990 | int div = 0, cr1 = 0; |
991 | int sai_clk_rate, mclk_ratio, den; |
992 | unsigned int rate = params_rate(p: params); |
993 | int ret; |
994 | |
995 | if (!sai->sai_mclk) { |
996 | ret = stm32_sai_set_parent_clock(sai, rate); |
997 | if (ret) |
998 | return ret; |
999 | } |
1000 | sai_clk_rate = clk_get_rate(clk: sai->sai_ck); |
1001 | |
1002 | if (STM_SAI_IS_F4(sai->pdata)) { |
1003 | /* mclk on (NODIV=0) |
1004 | * mclk_rate = 256 * fs |
1005 | * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate |
1006 | * MCKDIV = sai_ck / (2 * mclk_rate) otherwise |
1007 | * mclk off (NODIV=1) |
1008 | * MCKDIV ignored. sck = sai_ck |
1009 | */ |
1010 | if (!sai->mclk_rate) |
1011 | return 0; |
1012 | |
1013 | if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { |
1014 | div = stm32_sai_get_clk_div(sai, input_rate: sai_clk_rate, |
1015 | output_rate: 2 * sai->mclk_rate); |
1016 | if (div < 0) |
1017 | return div; |
1018 | } |
1019 | } else { |
1020 | /* |
1021 | * TDM mode : |
1022 | * mclk on |
1023 | * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) |
1024 | * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) |
1025 | * mclk off |
1026 | * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) |
1027 | * Note: NOMCK/NODIV correspond to same bit. |
1028 | */ |
1029 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { |
1030 | div = stm32_sai_get_clk_div(sai, input_rate: sai_clk_rate, |
1031 | output_rate: rate * 128); |
1032 | if (div < 0) |
1033 | return div; |
1034 | } else { |
1035 | if (sai->mclk_rate) { |
1036 | mclk_ratio = sai->mclk_rate / rate; |
1037 | if (mclk_ratio == 512) { |
1038 | cr1 = SAI_XCR1_OSR; |
1039 | } else if (mclk_ratio != 256) { |
1040 | dev_err(cpu_dai->dev, |
1041 | "Wrong mclk ratio %d\n" , |
1042 | mclk_ratio); |
1043 | return -EINVAL; |
1044 | } |
1045 | |
1046 | stm32_sai_sub_reg_up(sai, |
1047 | STM_SAI_CR1_REGX, |
1048 | SAI_XCR1_OSR, val: cr1); |
1049 | |
1050 | div = stm32_sai_get_clk_div(sai, input_rate: sai_clk_rate, |
1051 | output_rate: sai->mclk_rate); |
1052 | if (div < 0) |
1053 | return div; |
1054 | } else { |
1055 | /* mclk-fs not set, master clock not active */ |
1056 | den = sai->fs_length * params_rate(p: params); |
1057 | div = stm32_sai_get_clk_div(sai, input_rate: sai_clk_rate, |
1058 | output_rate: den); |
1059 | if (div < 0) |
1060 | return div; |
1061 | } |
1062 | } |
1063 | } |
1064 | |
1065 | return stm32_sai_set_clk_div(sai, div); |
1066 | } |
1067 | |
1068 | static int stm32_sai_hw_params(struct snd_pcm_substream *substream, |
1069 | struct snd_pcm_hw_params *params, |
1070 | struct snd_soc_dai *cpu_dai) |
1071 | { |
1072 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
1073 | int ret; |
1074 | |
1075 | sai->data_size = params_width(p: params); |
1076 | |
1077 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { |
1078 | /* Rate not already set in runtime structure */ |
1079 | substream->runtime->rate = params_rate(p: params); |
1080 | stm32_sai_set_iec958_status(sai, runtime: substream->runtime); |
1081 | } else { |
1082 | ret = stm32_sai_set_slots(cpu_dai); |
1083 | if (ret < 0) |
1084 | return ret; |
1085 | stm32_sai_set_frame(cpu_dai); |
1086 | } |
1087 | |
1088 | ret = stm32_sai_set_config(cpu_dai, substream, params); |
1089 | if (ret) |
1090 | return ret; |
1091 | |
1092 | if (sai->master) |
1093 | ret = stm32_sai_configure_clock(cpu_dai, params); |
1094 | |
1095 | return ret; |
1096 | } |
1097 | |
1098 | static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, |
1099 | struct snd_soc_dai *cpu_dai) |
1100 | { |
1101 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
1102 | int ret; |
1103 | |
1104 | switch (cmd) { |
1105 | case SNDRV_PCM_TRIGGER_START: |
1106 | case SNDRV_PCM_TRIGGER_RESUME: |
1107 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1108 | dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n" ); |
1109 | |
1110 | stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, |
1111 | SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); |
1112 | |
1113 | /* Enable SAI */ |
1114 | ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, |
1115 | SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); |
1116 | if (ret < 0) |
1117 | dev_err(cpu_dai->dev, "Failed to update CR1 register\n" ); |
1118 | break; |
1119 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1120 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
1121 | case SNDRV_PCM_TRIGGER_STOP: |
1122 | dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n" ); |
1123 | |
1124 | stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, |
1125 | SAI_XIMR_MASK, val: 0); |
1126 | |
1127 | stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, |
1128 | SAI_XCR1_SAIEN, |
1129 | val: (unsigned int)~SAI_XCR1_SAIEN); |
1130 | |
1131 | ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, |
1132 | SAI_XCR1_DMAEN, |
1133 | val: (unsigned int)~SAI_XCR1_DMAEN); |
1134 | if (ret < 0) |
1135 | dev_err(cpu_dai->dev, "Failed to update CR1 register\n" ); |
1136 | |
1137 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) |
1138 | sai->spdif_frm_cnt = 0; |
1139 | break; |
1140 | default: |
1141 | return -EINVAL; |
1142 | } |
1143 | |
1144 | return ret; |
1145 | } |
1146 | |
1147 | static void stm32_sai_shutdown(struct snd_pcm_substream *substream, |
1148 | struct snd_soc_dai *cpu_dai) |
1149 | { |
1150 | struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(dai: cpu_dai); |
1151 | unsigned long flags; |
1152 | |
1153 | stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, val: 0); |
1154 | |
1155 | clk_disable_unprepare(clk: sai->sai_ck); |
1156 | |
1157 | spin_lock_irqsave(&sai->irq_lock, flags); |
1158 | sai->substream = NULL; |
1159 | spin_unlock_irqrestore(lock: &sai->irq_lock, flags); |
1160 | } |
1161 | |
1162 | static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, |
1163 | struct snd_soc_dai *cpu_dai) |
1164 | { |
1165 | struct stm32_sai_sub_data *sai = dev_get_drvdata(dev: cpu_dai->dev); |
1166 | struct snd_kcontrol_new knew = iec958_ctls; |
1167 | |
1168 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { |
1169 | dev_dbg(&sai->pdev->dev, "%s: register iec controls" , __func__); |
1170 | knew.device = rtd->pcm->device; |
1171 | return snd_ctl_add(card: rtd->pcm->card, kcontrol: snd_ctl_new1(kcontrolnew: &knew, private_data: sai)); |
1172 | } |
1173 | |
1174 | return 0; |
1175 | } |
1176 | |
1177 | static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) |
1178 | { |
1179 | struct stm32_sai_sub_data *sai = dev_get_drvdata(dev: cpu_dai->dev); |
1180 | int cr1 = 0, cr1_mask, ret; |
1181 | |
1182 | sai->cpu_dai = cpu_dai; |
1183 | |
1184 | sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); |
1185 | /* |
1186 | * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, |
1187 | * as it allows bytes, half-word and words transfers. (See DMA fifos |
1188 | * constraints). |
1189 | */ |
1190 | sai->dma_params.maxburst = 4; |
1191 | if (sai->pdata->conf.fifo_size < 8) |
1192 | sai->dma_params.maxburst = 1; |
1193 | /* Buswidth will be set by framework at runtime */ |
1194 | sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
1195 | |
1196 | if (STM_SAI_IS_PLAYBACK(sai)) |
1197 | snd_soc_dai_init_dma_data(dai: cpu_dai, playback: &sai->dma_params, NULL); |
1198 | else |
1199 | snd_soc_dai_init_dma_data(dai: cpu_dai, NULL, capture: &sai->dma_params); |
1200 | |
1201 | /* Next settings are not relevant for spdif mode */ |
1202 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) |
1203 | return 0; |
1204 | |
1205 | cr1_mask = SAI_XCR1_RX_TX; |
1206 | if (STM_SAI_IS_CAPTURE(sai)) |
1207 | cr1 |= SAI_XCR1_RX_TX; |
1208 | |
1209 | /* Configure synchronization */ |
1210 | if (sai->sync == SAI_SYNC_EXTERNAL) { |
1211 | /* Configure synchro client and provider */ |
1212 | ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, |
1213 | sai->synco, sai->synci); |
1214 | if (ret) |
1215 | return ret; |
1216 | } |
1217 | |
1218 | cr1_mask |= SAI_XCR1_SYNCEN_MASK; |
1219 | cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); |
1220 | |
1221 | return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask: cr1_mask, val: cr1); |
1222 | } |
1223 | |
1224 | static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { |
1225 | .probe = stm32_sai_dai_probe, |
1226 | .set_sysclk = stm32_sai_set_sysclk, |
1227 | .set_fmt = stm32_sai_set_dai_fmt, |
1228 | .set_tdm_slot = stm32_sai_set_dai_tdm_slot, |
1229 | .startup = stm32_sai_startup, |
1230 | .hw_params = stm32_sai_hw_params, |
1231 | .trigger = stm32_sai_trigger, |
1232 | .shutdown = stm32_sai_shutdown, |
1233 | .pcm_new = stm32_sai_pcm_new, |
1234 | }; |
1235 | |
1236 | static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = { |
1237 | .probe = stm32_sai_dai_probe, |
1238 | .set_sysclk = stm32_sai_set_sysclk, |
1239 | .set_fmt = stm32_sai_set_dai_fmt, |
1240 | .set_tdm_slot = stm32_sai_set_dai_tdm_slot, |
1241 | .startup = stm32_sai_startup, |
1242 | .hw_params = stm32_sai_hw_params, |
1243 | .trigger = stm32_sai_trigger, |
1244 | .shutdown = stm32_sai_shutdown, |
1245 | }; |
1246 | |
1247 | static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, |
1248 | int channel, unsigned long hwoff, |
1249 | unsigned long bytes) |
1250 | { |
1251 | struct snd_pcm_runtime *runtime = substream->runtime; |
1252 | struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); |
1253 | struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); |
1254 | struct stm32_sai_sub_data *sai = dev_get_drvdata(dev: cpu_dai->dev); |
1255 | int *ptr = (int *)(runtime->dma_area + hwoff + |
1256 | channel * (runtime->dma_bytes / runtime->channels)); |
1257 | ssize_t cnt = bytes_to_samples(runtime, size: bytes); |
1258 | unsigned int frm_cnt = sai->spdif_frm_cnt; |
1259 | unsigned int byte; |
1260 | unsigned int mask; |
1261 | |
1262 | do { |
1263 | *ptr = ((*ptr >> 8) & 0x00ffffff); |
1264 | |
1265 | /* Set channel status bit */ |
1266 | byte = frm_cnt >> 3; |
1267 | mask = 1 << (frm_cnt - (byte << 3)); |
1268 | if (sai->iec958.status[byte] & mask) |
1269 | *ptr |= 0x04000000; |
1270 | ptr++; |
1271 | |
1272 | if (!(cnt % 2)) |
1273 | frm_cnt++; |
1274 | |
1275 | if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) |
1276 | frm_cnt = 0; |
1277 | } while (--cnt); |
1278 | sai->spdif_frm_cnt = frm_cnt; |
1279 | |
1280 | return 0; |
1281 | } |
1282 | |
1283 | /* No support of mmap in S/PDIF mode */ |
1284 | static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = { |
1285 | .info = SNDRV_PCM_INFO_INTERLEAVED, |
1286 | .buffer_bytes_max = 8 * PAGE_SIZE, |
1287 | .period_bytes_min = 1024, |
1288 | .period_bytes_max = PAGE_SIZE, |
1289 | .periods_min = 2, |
1290 | .periods_max = 8, |
1291 | }; |
1292 | |
1293 | static const struct snd_pcm_hardware stm32_sai_pcm_hw = { |
1294 | .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, |
1295 | .buffer_bytes_max = 8 * PAGE_SIZE, |
1296 | .period_bytes_min = 1024, /* 5ms at 48kHz */ |
1297 | .period_bytes_max = PAGE_SIZE, |
1298 | .periods_min = 2, |
1299 | .periods_max = 8, |
1300 | }; |
1301 | |
1302 | static struct snd_soc_dai_driver stm32_sai_playback_dai = { |
1303 | .id = 1, /* avoid call to fmt_single_name() */ |
1304 | .playback = { |
1305 | .channels_min = 1, |
1306 | .channels_max = 16, |
1307 | .rate_min = 8000, |
1308 | .rate_max = 192000, |
1309 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
1310 | /* DMA does not support 24 bits transfers */ |
1311 | .formats = |
1312 | SNDRV_PCM_FMTBIT_S8 | |
1313 | SNDRV_PCM_FMTBIT_S16_LE | |
1314 | SNDRV_PCM_FMTBIT_S32_LE, |
1315 | }, |
1316 | .ops = &stm32_sai_pcm_dai_ops, |
1317 | }; |
1318 | |
1319 | static struct snd_soc_dai_driver stm32_sai_capture_dai = { |
1320 | .id = 1, /* avoid call to fmt_single_name() */ |
1321 | .capture = { |
1322 | .channels_min = 1, |
1323 | .channels_max = 16, |
1324 | .rate_min = 8000, |
1325 | .rate_max = 192000, |
1326 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
1327 | /* DMA does not support 24 bits transfers */ |
1328 | .formats = |
1329 | SNDRV_PCM_FMTBIT_S8 | |
1330 | SNDRV_PCM_FMTBIT_S16_LE | |
1331 | SNDRV_PCM_FMTBIT_S32_LE, |
1332 | }, |
1333 | .ops = &stm32_sai_pcm_dai_ops2, |
1334 | }; |
1335 | |
1336 | static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { |
1337 | .pcm_hardware = &stm32_sai_pcm_hw, |
1338 | .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, |
1339 | }; |
1340 | |
1341 | static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { |
1342 | .pcm_hardware = &stm32_sai_pcm_hw_spdif, |
1343 | .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, |
1344 | .process = stm32_sai_pcm_process_spdif, |
1345 | }; |
1346 | |
1347 | static const struct snd_soc_component_driver stm32_component = { |
1348 | .name = "stm32-sai" , |
1349 | .legacy_dai_naming = 1, |
1350 | }; |
1351 | |
1352 | static const struct of_device_id stm32_sai_sub_ids[] = { |
1353 | { .compatible = "st,stm32-sai-sub-a" , |
1354 | .data = (void *)STM_SAI_A_ID}, |
1355 | { .compatible = "st,stm32-sai-sub-b" , |
1356 | .data = (void *)STM_SAI_B_ID}, |
1357 | {} |
1358 | }; |
1359 | MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); |
1360 | |
1361 | static int stm32_sai_sub_parse_of(struct platform_device *pdev, |
1362 | struct stm32_sai_sub_data *sai) |
1363 | { |
1364 | struct device_node *np = pdev->dev.of_node; |
1365 | struct resource *res; |
1366 | void __iomem *base; |
1367 | struct of_phandle_args args; |
1368 | int ret; |
1369 | |
1370 | if (!np) |
1371 | return -ENODEV; |
1372 | |
1373 | base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res); |
1374 | if (IS_ERR(ptr: base)) |
1375 | return PTR_ERR(ptr: base); |
1376 | |
1377 | sai->phys_addr = res->start; |
1378 | |
1379 | sai->regmap_config = &stm32_sai_sub_regmap_config_f4; |
1380 | /* Note: PDM registers not available for sub-block B */ |
1381 | if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) |
1382 | sai->regmap_config = &stm32_sai_sub_regmap_config_h7; |
1383 | |
1384 | /* |
1385 | * Do not manage peripheral clock through regmap framework as this |
1386 | * can lead to circular locking issue with sai master clock provider. |
1387 | * Manage peripheral clock directly in driver instead. |
1388 | */ |
1389 | sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, |
1390 | sai->regmap_config); |
1391 | if (IS_ERR(ptr: sai->regmap)) |
1392 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: sai->regmap), |
1393 | fmt: "Regmap init error\n" ); |
1394 | |
1395 | /* Get direction property */ |
1396 | if (of_property_match_string(np, propname: "dma-names" , string: "tx" ) >= 0) { |
1397 | sai->dir = SNDRV_PCM_STREAM_PLAYBACK; |
1398 | } else if (of_property_match_string(np, propname: "dma-names" , string: "rx" ) >= 0) { |
1399 | sai->dir = SNDRV_PCM_STREAM_CAPTURE; |
1400 | } else { |
1401 | dev_err(&pdev->dev, "Unsupported direction\n" ); |
1402 | return -EINVAL; |
1403 | } |
1404 | |
1405 | /* Get spdif iec60958 property */ |
1406 | sai->spdif = false; |
1407 | if (of_property_present(np, propname: "st,iec60958" )) { |
1408 | if (!STM_SAI_HAS_SPDIF(sai) || |
1409 | sai->dir == SNDRV_PCM_STREAM_CAPTURE) { |
1410 | dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n" ); |
1411 | return -EINVAL; |
1412 | } |
1413 | stm32_sai_init_iec958_status(sai); |
1414 | sai->spdif = true; |
1415 | sai->master = true; |
1416 | } |
1417 | |
1418 | /* Get synchronization property */ |
1419 | args.np = NULL; |
1420 | ret = of_parse_phandle_with_fixed_args(np, list_name: "st,sync" , cell_count: 1, index: 0, out_args: &args); |
1421 | if (ret < 0 && ret != -ENOENT) { |
1422 | dev_err(&pdev->dev, "Failed to get st,sync property\n" ); |
1423 | return ret; |
1424 | } |
1425 | |
1426 | sai->sync = SAI_SYNC_NONE; |
1427 | if (args.np) { |
1428 | if (args.np == np) { |
1429 | dev_err(&pdev->dev, "%pOFn sync own reference\n" , np); |
1430 | of_node_put(node: args.np); |
1431 | return -EINVAL; |
1432 | } |
1433 | |
1434 | sai->np_sync_provider = of_get_parent(node: args.np); |
1435 | if (!sai->np_sync_provider) { |
1436 | dev_err(&pdev->dev, "%pOFn parent node not found\n" , |
1437 | np); |
1438 | of_node_put(node: args.np); |
1439 | return -ENODEV; |
1440 | } |
1441 | |
1442 | sai->sync = SAI_SYNC_INTERNAL; |
1443 | if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { |
1444 | if (!STM_SAI_HAS_EXT_SYNC(sai)) { |
1445 | dev_err(&pdev->dev, |
1446 | "External synchro not supported\n" ); |
1447 | of_node_put(node: args.np); |
1448 | return -EINVAL; |
1449 | } |
1450 | sai->sync = SAI_SYNC_EXTERNAL; |
1451 | |
1452 | sai->synci = args.args[0]; |
1453 | if (sai->synci < 1 || |
1454 | (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { |
1455 | dev_err(&pdev->dev, "Wrong SAI index\n" ); |
1456 | of_node_put(node: args.np); |
1457 | return -EINVAL; |
1458 | } |
1459 | |
1460 | if (of_property_match_string(np: args.np, propname: "compatible" , |
1461 | string: "st,stm32-sai-sub-a" ) >= 0) |
1462 | sai->synco = STM_SAI_SYNC_OUT_A; |
1463 | |
1464 | if (of_property_match_string(np: args.np, propname: "compatible" , |
1465 | string: "st,stm32-sai-sub-b" ) >= 0) |
1466 | sai->synco = STM_SAI_SYNC_OUT_B; |
1467 | |
1468 | if (!sai->synco) { |
1469 | dev_err(&pdev->dev, "Unknown SAI sub-block\n" ); |
1470 | of_node_put(node: args.np); |
1471 | return -EINVAL; |
1472 | } |
1473 | } |
1474 | |
1475 | dev_dbg(&pdev->dev, "%s synchronized with %s\n" , |
1476 | pdev->name, args.np->full_name); |
1477 | } |
1478 | |
1479 | of_node_put(node: args.np); |
1480 | sai->sai_ck = devm_clk_get(dev: &pdev->dev, id: "sai_ck" ); |
1481 | if (IS_ERR(ptr: sai->sai_ck)) |
1482 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: sai->sai_ck), |
1483 | fmt: "Missing kernel clock sai_ck\n" ); |
1484 | |
1485 | ret = clk_prepare(clk: sai->pdata->pclk); |
1486 | if (ret < 0) |
1487 | return ret; |
1488 | |
1489 | if (STM_SAI_IS_F4(sai->pdata)) |
1490 | return 0; |
1491 | |
1492 | /* Register mclk provider if requested */ |
1493 | if (of_property_present(np, propname: "#clock-cells" )) { |
1494 | ret = stm32_sai_add_mclk_provider(sai); |
1495 | if (ret < 0) |
1496 | return ret; |
1497 | } else { |
1498 | sai->sai_mclk = devm_clk_get_optional(dev: &pdev->dev, id: "MCLK" ); |
1499 | if (IS_ERR(ptr: sai->sai_mclk)) |
1500 | return PTR_ERR(ptr: sai->sai_mclk); |
1501 | } |
1502 | |
1503 | return 0; |
1504 | } |
1505 | |
1506 | static int stm32_sai_sub_probe(struct platform_device *pdev) |
1507 | { |
1508 | struct stm32_sai_sub_data *sai; |
1509 | const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; |
1510 | int ret; |
1511 | |
1512 | sai = devm_kzalloc(dev: &pdev->dev, size: sizeof(*sai), GFP_KERNEL); |
1513 | if (!sai) |
1514 | return -ENOMEM; |
1515 | |
1516 | sai->id = (uintptr_t)device_get_match_data(dev: &pdev->dev); |
1517 | |
1518 | sai->pdev = pdev; |
1519 | mutex_init(&sai->ctrl_lock); |
1520 | spin_lock_init(&sai->irq_lock); |
1521 | platform_set_drvdata(pdev, data: sai); |
1522 | |
1523 | sai->pdata = dev_get_drvdata(dev: pdev->dev.parent); |
1524 | if (!sai->pdata) { |
1525 | dev_err(&pdev->dev, "Parent device data not available\n" ); |
1526 | return -EINVAL; |
1527 | } |
1528 | |
1529 | ret = stm32_sai_sub_parse_of(pdev, sai); |
1530 | if (ret) |
1531 | return ret; |
1532 | |
1533 | if (STM_SAI_IS_PLAYBACK(sai)) |
1534 | sai->cpu_dai_drv = stm32_sai_playback_dai; |
1535 | else |
1536 | sai->cpu_dai_drv = stm32_sai_capture_dai; |
1537 | sai->cpu_dai_drv.name = dev_name(dev: &pdev->dev); |
1538 | |
1539 | ret = devm_request_irq(dev: &pdev->dev, irq: sai->pdata->irq, handler: stm32_sai_isr, |
1540 | IRQF_SHARED, devname: dev_name(dev: &pdev->dev), dev_id: sai); |
1541 | if (ret) { |
1542 | dev_err(&pdev->dev, "IRQ request returned %d\n" , ret); |
1543 | return ret; |
1544 | } |
1545 | |
1546 | if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) |
1547 | conf = &stm32_sai_pcm_config_spdif; |
1548 | |
1549 | ret = snd_dmaengine_pcm_register(dev: &pdev->dev, config: conf, flags: 0); |
1550 | if (ret) |
1551 | return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Could not register pcm dma\n" ); |
1552 | |
1553 | ret = snd_soc_register_component(dev: &pdev->dev, component_driver: &stm32_component, |
1554 | dai_drv: &sai->cpu_dai_drv, num_dai: 1); |
1555 | if (ret) { |
1556 | snd_dmaengine_pcm_unregister(dev: &pdev->dev); |
1557 | return ret; |
1558 | } |
1559 | |
1560 | pm_runtime_enable(dev: &pdev->dev); |
1561 | |
1562 | return 0; |
1563 | } |
1564 | |
1565 | static void stm32_sai_sub_remove(struct platform_device *pdev) |
1566 | { |
1567 | struct stm32_sai_sub_data *sai = dev_get_drvdata(dev: &pdev->dev); |
1568 | |
1569 | clk_unprepare(clk: sai->pdata->pclk); |
1570 | snd_dmaengine_pcm_unregister(dev: &pdev->dev); |
1571 | snd_soc_unregister_component(dev: &pdev->dev); |
1572 | pm_runtime_disable(dev: &pdev->dev); |
1573 | } |
1574 | |
1575 | #ifdef CONFIG_PM_SLEEP |
1576 | static int stm32_sai_sub_suspend(struct device *dev) |
1577 | { |
1578 | struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); |
1579 | int ret; |
1580 | |
1581 | ret = clk_enable(clk: sai->pdata->pclk); |
1582 | if (ret < 0) |
1583 | return ret; |
1584 | |
1585 | regcache_cache_only(map: sai->regmap, enable: true); |
1586 | regcache_mark_dirty(map: sai->regmap); |
1587 | |
1588 | clk_disable(clk: sai->pdata->pclk); |
1589 | |
1590 | return 0; |
1591 | } |
1592 | |
1593 | static int stm32_sai_sub_resume(struct device *dev) |
1594 | { |
1595 | struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); |
1596 | int ret; |
1597 | |
1598 | ret = clk_enable(clk: sai->pdata->pclk); |
1599 | if (ret < 0) |
1600 | return ret; |
1601 | |
1602 | regcache_cache_only(map: sai->regmap, enable: false); |
1603 | ret = regcache_sync(map: sai->regmap); |
1604 | |
1605 | clk_disable(clk: sai->pdata->pclk); |
1606 | |
1607 | return ret; |
1608 | } |
1609 | #endif /* CONFIG_PM_SLEEP */ |
1610 | |
1611 | static const struct dev_pm_ops stm32_sai_sub_pm_ops = { |
1612 | SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) |
1613 | }; |
1614 | |
1615 | static struct platform_driver stm32_sai_sub_driver = { |
1616 | .driver = { |
1617 | .name = "st,stm32-sai-sub" , |
1618 | .of_match_table = stm32_sai_sub_ids, |
1619 | .pm = &stm32_sai_sub_pm_ops, |
1620 | }, |
1621 | .probe = stm32_sai_sub_probe, |
1622 | .remove_new = stm32_sai_sub_remove, |
1623 | }; |
1624 | |
1625 | module_platform_driver(stm32_sai_sub_driver); |
1626 | |
1627 | MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface" ); |
1628 | MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>" ); |
1629 | MODULE_ALIAS("platform:st,stm32-sai-sub" ); |
1630 | MODULE_LICENSE("GPL v2" ); |
1631 | |