1 | //===-- MipsSEISelDAGToDAG.h - A Dag to Dag Inst Selector for MipsSE -----===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // Subclass of MipsDAGToDAGISel specialized for mips32/64. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H |
14 | #define LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H |
15 | |
16 | #include "MipsISelDAGToDAG.h" |
17 | |
18 | namespace llvm { |
19 | |
20 | class MipsSEDAGToDAGISel : public MipsDAGToDAGISel { |
21 | |
22 | public: |
23 | explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) |
24 | : MipsDAGToDAGISel(TM, OL) {} |
25 | |
26 | private: |
27 | |
28 | bool runOnMachineFunction(MachineFunction &MF) override; |
29 | |
30 | void getAnalysisUsage(AnalysisUsage &AU) const override; |
31 | |
32 | void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, |
33 | MachineFunction &MF); |
34 | |
35 | unsigned getMSACtrlReg(const SDValue RegIdx) const; |
36 | |
37 | bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&); |
38 | |
39 | std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc, |
40 | const SDLoc &dl, EVT Ty, bool HasLo, |
41 | bool HasHi); |
42 | |
43 | void selectAddE(SDNode *Node, const SDLoc &DL) const; |
44 | |
45 | bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const; |
46 | bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset, |
47 | unsigned OffsetBits, |
48 | unsigned ShiftAmount) const; |
49 | |
50 | bool selectAddrRegImm(SDValue Addr, SDValue &Base, |
51 | SDValue &Offset) const override; |
52 | |
53 | bool selectAddrDefault(SDValue Addr, SDValue &Base, |
54 | SDValue &Offset) const override; |
55 | |
56 | bool selectIntAddr(SDValue Addr, SDValue &Base, |
57 | SDValue &Offset) const override; |
58 | |
59 | bool selectAddrRegImm9(SDValue Addr, SDValue &Base, |
60 | SDValue &Offset) const; |
61 | |
62 | bool selectAddrRegImm11(SDValue Addr, SDValue &Base, |
63 | SDValue &Offset) const; |
64 | |
65 | bool selectAddrRegImm12(SDValue Addr, SDValue &Base, |
66 | SDValue &Offset) const; |
67 | |
68 | bool selectAddrRegImm16(SDValue Addr, SDValue &Base, |
69 | SDValue &Offset) const; |
70 | |
71 | bool selectIntAddr11MM(SDValue Addr, SDValue &Base, |
72 | SDValue &Offset) const override; |
73 | |
74 | bool selectIntAddr12MM(SDValue Addr, SDValue &Base, |
75 | SDValue &Offset) const override; |
76 | |
77 | bool selectIntAddr16MM(SDValue Addr, SDValue &Base, |
78 | SDValue &Offset) const override; |
79 | |
80 | bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, |
81 | SDValue &Offset) const override; |
82 | |
83 | bool selectIntAddrSImm10(SDValue Addr, SDValue &Base, |
84 | SDValue &Offset) const override; |
85 | |
86 | bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, |
87 | SDValue &Offset) const override; |
88 | |
89 | bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, |
90 | SDValue &Offset) const override; |
91 | |
92 | bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, |
93 | SDValue &Offset) const override; |
94 | |
95 | /// Select constant vector splats. |
96 | bool selectVSplat(SDNode *N, APInt &Imm, |
97 | unsigned MinSizeInBits) const override; |
98 | /// Select constant vector splats whose value fits in a given integer. |
99 | bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, |
100 | unsigned ImmBitSize) const; |
101 | /// Select constant vector splats whose value fits in a uimm1. |
102 | bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override; |
103 | /// Select constant vector splats whose value fits in a uimm2. |
104 | bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override; |
105 | /// Select constant vector splats whose value fits in a uimm3. |
106 | bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override; |
107 | /// Select constant vector splats whose value fits in a uimm4. |
108 | bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override; |
109 | /// Select constant vector splats whose value fits in a uimm5. |
110 | bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override; |
111 | /// Select constant vector splats whose value fits in a uimm6. |
112 | bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override; |
113 | /// Select constant vector splats whose value fits in a uimm8. |
114 | bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override; |
115 | /// Select constant vector splats whose value fits in a simm5. |
116 | bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override; |
117 | /// Select constant vector splats whose value is a power of 2. |
118 | bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const override; |
119 | /// Select constant vector splats whose value is the inverse of a |
120 | /// power of 2. |
121 | bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const override; |
122 | /// Select constant vector splats whose value is a run of set bits |
123 | /// ending at the most significant bit. |
124 | bool selectVSplatMaskL(SDValue N, SDValue &Imm) const override; |
125 | /// Select constant vector splats whose value is a run of set bits |
126 | /// starting at bit zero. |
127 | bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override; |
128 | |
129 | bool trySelect(SDNode *Node) override; |
130 | |
131 | // Emits proper ABI for _mcount profiling calls. |
132 | void emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB, |
133 | MachineFunction &MF); |
134 | |
135 | void processFunctionAfterISel(MachineFunction &MF) override; |
136 | |
137 | bool SelectInlineAsmMemoryOperand(const SDValue &Op, |
138 | InlineAsm::ConstraintCode ConstraintID, |
139 | std::vector<SDValue> &OutOps) override; |
140 | }; |
141 | |
142 | FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM, |
143 | CodeGenOptLevel OptLevel); |
144 | } |
145 | |
146 | #endif |
147 | |