1//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15
16#include "MCTargetDesc/RISCVBaseInfo.h"
17#include "RISCVFrameLowering.h"
18#include "RISCVISelLowering.h"
19#include "RISCVInstrInfo.h"
20#include "llvm/CodeGen/GlobalISel/CallLowering.h"
21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23#include "llvm/CodeGen/RegisterBankInfo.h"
24#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/Target/TargetMachine.h"
28#include <bitset>
29
30#define GET_RISCV_MACRO_FUSION_PRED_DECL
31#include "RISCVGenMacroFusion.inc"
32
33#define GET_SUBTARGETINFO_HEADER
34#include "RISCVGenSubtargetInfo.inc"
35
36namespace llvm {
37class StringRef;
38
39namespace RISCVTuneInfoTable {
40
41struct RISCVTuneInfo {
42 const char *Name;
43 uint8_t PrefFunctionAlignment;
44 uint8_t PrefLoopAlignment;
45
46 // Information needed by LoopDataPrefetch.
47 uint16_t CacheLineSize;
48 uint16_t PrefetchDistance;
49 uint16_t MinPrefetchStride;
50 unsigned MaxPrefetchIterationsAhead;
51
52 unsigned MinimumJumpTableEntries;
53};
54
55#define GET_RISCVTuneInfoTable_DECL
56#include "RISCVGenSearchableTables.inc"
57} // namespace RISCVTuneInfoTable
58
59class RISCVSubtarget : public RISCVGenSubtargetInfo {
60public:
61 // clang-format off
62 enum RISCVProcFamilyEnum : uint8_t {
63 Others,
64 SiFive7,
65 VentanaVeyron,
66 };
67 // clang-format on
68private:
69 virtual void anchor();
70
71 RISCVProcFamilyEnum RISCVProcFamily = Others;
72
73#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
74 bool ATTRIBUTE = DEFAULT;
75#include "RISCVGenSubtargetInfo.inc"
76
77 unsigned ZvlLen = 0;
78 unsigned RVVVectorBitsMin;
79 unsigned RVVVectorBitsMax;
80 uint8_t MaxInterleaveFactor = 2;
81 RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
82 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
83 const RISCVTuneInfoTable::RISCVTuneInfo *TuneInfo;
84
85 RISCVFrameLowering FrameLowering;
86 RISCVInstrInfo InstrInfo;
87 RISCVRegisterInfo RegInfo;
88 RISCVTargetLowering TLInfo;
89 SelectionDAGTargetInfo TSInfo;
90
91 /// Initializes using the passed in CPU and feature strings so that we can
92 /// use initializer lists for subtarget initialization.
93 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
94 StringRef CPU,
95 StringRef TuneCPU,
96 StringRef FS,
97 StringRef ABIName);
98
99public:
100 // Initializes the data members to match that of the specified triple.
101 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
102 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
103 unsigned RVVVectorLMULMax, const TargetMachine &TM);
104
105 // Parses features string setting specified subtarget options. The
106 // definition of this function is auto-generated by tblgen.
107 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
108
109 const RISCVFrameLowering *getFrameLowering() const override {
110 return &FrameLowering;
111 }
112 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
113 const RISCVRegisterInfo *getRegisterInfo() const override {
114 return &RegInfo;
115 }
116 const RISCVTargetLowering *getTargetLowering() const override {
117 return &TLInfo;
118 }
119 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
120 return &TSInfo;
121 }
122 bool enableMachineScheduler() const override { return true; }
123
124 bool enablePostRAScheduler() const override {
125 return getSchedModel().PostRAScheduler || UsePostRAScheduler;
126 }
127
128 Align getPrefFunctionAlignment() const {
129 return Align(TuneInfo->PrefFunctionAlignment);
130 }
131 Align getPrefLoopAlignment() const {
132 return Align(TuneInfo->PrefLoopAlignment);
133 }
134
135 /// Returns RISC-V processor family.
136 /// Avoid this function! CPU specifics should be kept local to this class
137 /// and preferably modeled with SubtargetFeatures or properties in
138 /// initializeProperties().
139 RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
140
141#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
142 bool GETTER() const { return ATTRIBUTE; }
143#include "RISCVGenSubtargetInfo.inc"
144
145 bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
146 bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
147 bool hasStdExtCOrZcfOrZce() const {
148 return HasStdExtC || HasStdExtZcf || HasStdExtZce;
149 }
150 bool hasStdExtZvl() const { return ZvlLen != 0; }
151 bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
152 bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
153 bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
154 bool hasStdExtZfhminOrZhinxmin() const {
155 return HasStdExtZfhmin || HasStdExtZhinxmin;
156 }
157 bool hasHalfFPLoadStoreMove() const {
158 return HasStdExtZfhmin || HasStdExtZfbfmin;
159 }
160
161 bool hasConditionalMoveFusion() const {
162 // Do we support fusing a branch+mv or branch+c.mv as a conditional move.
163 return (hasConditionalCompressedMoveFusion() && hasStdExtCOrZca()) ||
164 hasShortForwardBranchOpt();
165 }
166
167 bool is64Bit() const { return IsRV64; }
168 MVT getXLenVT() const {
169 return is64Bit() ? MVT::i64 : MVT::i32;
170 }
171 unsigned getXLen() const {
172 return is64Bit() ? 64 : 32;
173 }
174 unsigned getFLen() const {
175 if (HasStdExtD)
176 return 64;
177
178 if (HasStdExtF)
179 return 32;
180
181 return 0;
182 }
183 unsigned getELen() const {
184 assert(hasVInstructions() && "Expected V extension");
185 return hasVInstructionsI64() ? 64 : 32;
186 }
187 unsigned getRealMinVLen() const {
188 unsigned VLen = getMinRVVVectorSizeInBits();
189 return VLen == 0 ? ZvlLen : VLen;
190 }
191 unsigned getRealMaxVLen() const {
192 unsigned VLen = getMaxRVVVectorSizeInBits();
193 return VLen == 0 ? 65536 : VLen;
194 }
195 // If we know the exact VLEN, return it. Otherwise, return std::nullopt.
196 std::optional<unsigned> getRealVLen() const {
197 unsigned Min = getRealMinVLen();
198 if (Min != getRealMaxVLen())
199 return std::nullopt;
200 return Min;
201 }
202
203 RISCVABI::ABI getTargetABI() const { return TargetABI; }
204 bool isSoftFPABI() const {
205 return TargetABI == RISCVABI::ABI_LP64 ||
206 TargetABI == RISCVABI::ABI_ILP32 ||
207 TargetABI == RISCVABI::ABI_ILP32E;
208 }
209 bool isRegisterReservedByUser(Register i) const {
210 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
211 return UserReservedRegister[i];
212 }
213
214 // Vector codegen related methods.
215 bool hasVInstructions() const { return HasStdExtZve32x; }
216 bool hasVInstructionsI64() const { return HasStdExtZve64x; }
217 bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
218 bool hasVInstructionsF16() const { return HasStdExtZvfh; }
219 bool hasVInstructionsBF16() const { return HasStdExtZvfbfmin; }
220 bool hasVInstructionsF32() const { return HasStdExtZve32f; }
221 bool hasVInstructionsF64() const { return HasStdExtZve64d; }
222 // F16 and F64 both require F32.
223 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
224 bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
225 unsigned getMaxInterleaveFactor() const {
226 return hasVInstructions() ? MaxInterleaveFactor : 1;
227 }
228
229 // Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
230 // vector hardware implementation which may be less than VLEN.
231 unsigned getDLenFactor() const {
232 if (DLenFactor2)
233 return 2;
234 return 1;
235 }
236
237protected:
238 // GlobalISel related APIs.
239 std::unique_ptr<CallLowering> CallLoweringInfo;
240 std::unique_ptr<InstructionSelector> InstSelector;
241 std::unique_ptr<LegalizerInfo> Legalizer;
242 std::unique_ptr<RegisterBankInfo> RegBankInfo;
243
244 // Return the known range for the bit length of RVV data registers as set
245 // at the command line. A value of 0 means nothing is known about that particular
246 // limit beyond what's implied by the architecture.
247 // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
248 unsigned getMaxRVVVectorSizeInBits() const;
249 unsigned getMinRVVVectorSizeInBits() const;
250
251public:
252 const CallLowering *getCallLowering() const override;
253 InstructionSelector *getInstructionSelector() const override;
254 const LegalizerInfo *getLegalizerInfo() const override;
255 const RegisterBankInfo *getRegBankInfo() const override;
256
257 bool isTargetAndroid() const { return getTargetTriple().isAndroid(); }
258 bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
259
260 bool useConstantPoolForLargeInts() const;
261
262 // Maximum cost used for building integers, integers will be put into constant
263 // pool if exceeded.
264 unsigned getMaxBuildIntsCost() const;
265
266 unsigned getMaxLMULForFixedLengthVectors() const;
267 bool useRVVForFixedLengthVectors() const;
268
269 bool enableSubRegLiveness() const override;
270
271 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
272 &Mutations) const override;
273
274 bool useAA() const override;
275
276 unsigned getCacheLineSize() const override {
277 return TuneInfo->CacheLineSize;
278 };
279 unsigned getPrefetchDistance() const override {
280 return TuneInfo->PrefetchDistance;
281 };
282 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
283 unsigned NumStridedMemAccesses,
284 unsigned NumPrefetches,
285 bool HasCall) const override {
286 return TuneInfo->MinPrefetchStride;
287 };
288 unsigned getMaxPrefetchIterationsAhead() const override {
289 return TuneInfo->MaxPrefetchIterationsAhead;
290 };
291
292 unsigned getMinimumJumpTableEntries() const;
293
294 bool supportsInitUndef() const override { return hasVInstructions(); }
295};
296} // End llvm namespace
297
298#endif
299

source code of llvm/lib/Target/RISCV/RISCVSubtarget.h