1 | //===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the RISC-V implementation of the TargetInstrInfo class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H |
14 | #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H |
15 | |
16 | #include "RISCV.h" |
17 | #include "RISCVRegisterInfo.h" |
18 | #include "llvm/CodeGen/TargetInstrInfo.h" |
19 | #include "llvm/IR/DiagnosticInfo.h" |
20 | |
21 | #define |
22 | #define GET_INSTRINFO_OPERAND_ENUM |
23 | #include "RISCVGenInstrInfo.inc" |
24 | #include "RISCVGenRegisterInfo.inc" |
25 | |
26 | namespace llvm { |
27 | |
28 | class RISCVSubtarget; |
29 | |
30 | static const MachineMemOperand::Flags MONontemporalBit0 = |
31 | MachineMemOperand::MOTargetFlag1; |
32 | static const MachineMemOperand::Flags MONontemporalBit1 = |
33 | MachineMemOperand::MOTargetFlag2; |
34 | |
35 | namespace RISCVCC { |
36 | |
37 | enum CondCode { |
38 | COND_EQ, |
39 | COND_NE, |
40 | COND_LT, |
41 | COND_GE, |
42 | COND_LTU, |
43 | COND_GEU, |
44 | COND_INVALID |
45 | }; |
46 | |
47 | CondCode getOppositeBranchCondition(CondCode); |
48 | unsigned getBrCond(CondCode CC); |
49 | |
50 | } // end of namespace RISCVCC |
51 | |
52 | // RISCV MachineCombiner patterns |
53 | enum RISCVMachineCombinerPattern : unsigned { |
54 | FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START, |
55 | FMADD_XA, |
56 | FMSUB, |
57 | FNMSUB, |
58 | SHXADD_ADD_SLLI_OP1, |
59 | SHXADD_ADD_SLLI_OP2, |
60 | }; |
61 | |
62 | class RISCVInstrInfo : public RISCVGenInstrInfo { |
63 | |
64 | public: |
65 | explicit RISCVInstrInfo(RISCVSubtarget &STI); |
66 | |
67 | MCInst getNop() const override; |
68 | const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const; |
69 | |
70 | Register isLoadFromStackSlot(const MachineInstr &MI, |
71 | int &FrameIndex) const override; |
72 | Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, |
73 | unsigned &MemBytes) const override; |
74 | Register isStoreToStackSlot(const MachineInstr &MI, |
75 | int &FrameIndex) const override; |
76 | Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, |
77 | unsigned &MemBytes) const override; |
78 | |
79 | void copyPhysRegVector(MachineBasicBlock &MBB, |
80 | MachineBasicBlock::iterator MBBI, const DebugLoc &DL, |
81 | MCRegister DstReg, MCRegister SrcReg, bool KillSrc, |
82 | const TargetRegisterClass *RegClass) const; |
83 | void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, |
84 | const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, |
85 | bool KillSrc) const override; |
86 | |
87 | void storeRegToStackSlot(MachineBasicBlock &MBB, |
88 | MachineBasicBlock::iterator MBBI, Register SrcReg, |
89 | bool IsKill, int FrameIndex, |
90 | const TargetRegisterClass *RC, |
91 | const TargetRegisterInfo *TRI, |
92 | Register VReg) const override; |
93 | |
94 | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
95 | MachineBasicBlock::iterator MBBI, Register DstReg, |
96 | int FrameIndex, const TargetRegisterClass *RC, |
97 | const TargetRegisterInfo *TRI, |
98 | Register VReg) const override; |
99 | |
100 | using TargetInstrInfo::foldMemoryOperandImpl; |
101 | MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, |
102 | ArrayRef<unsigned> Ops, |
103 | MachineBasicBlock::iterator InsertPt, |
104 | int FrameIndex, |
105 | LiveIntervals *LIS = nullptr, |
106 | VirtRegMap *VRM = nullptr) const override; |
107 | |
108 | // Materializes the given integer Val into DstReg. |
109 | void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, |
110 | const DebugLoc &DL, Register DstReg, uint64_t Val, |
111 | MachineInstr::MIFlag Flag = MachineInstr::NoFlags, |
112 | bool DstRenamable = false, bool DstIsDead = false) const; |
113 | |
114 | unsigned getInstSizeInBytes(const MachineInstr &MI) const override; |
115 | |
116 | bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
117 | MachineBasicBlock *&FBB, |
118 | SmallVectorImpl<MachineOperand> &Cond, |
119 | bool AllowModify) const override; |
120 | |
121 | unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
122 | MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, |
123 | const DebugLoc &dl, |
124 | int *BytesAdded = nullptr) const override; |
125 | |
126 | void insertIndirectBranch(MachineBasicBlock &MBB, |
127 | MachineBasicBlock &NewDestBB, |
128 | MachineBasicBlock &RestoreBB, const DebugLoc &DL, |
129 | int64_t BrOffset, RegScavenger *RS) const override; |
130 | |
131 | unsigned removeBranch(MachineBasicBlock &MBB, |
132 | int *BytesRemoved = nullptr) const override; |
133 | |
134 | bool |
135 | reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; |
136 | |
137 | bool optimizeCondBranch(MachineInstr &MI) const override; |
138 | |
139 | MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; |
140 | |
141 | bool isBranchOffsetInRange(unsigned BranchOpc, |
142 | int64_t BrOffset) const override; |
143 | |
144 | bool analyzeSelect(const MachineInstr &MI, |
145 | SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, |
146 | unsigned &FalseOp, bool &Optimizable) const override; |
147 | |
148 | MachineInstr *optimizeSelect(MachineInstr &MI, |
149 | SmallPtrSetImpl<MachineInstr *> &SeenMIs, |
150 | bool) const override; |
151 | |
152 | bool isAsCheapAsAMove(const MachineInstr &MI) const override; |
153 | |
154 | std::optional<DestSourcePair> |
155 | isCopyInstrImpl(const MachineInstr &MI) const override; |
156 | |
157 | bool verifyInstruction(const MachineInstr &MI, |
158 | StringRef &ErrInfo) const override; |
159 | |
160 | bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, |
161 | const MachineInstr &AddrI, |
162 | ExtAddrMode &AM) const override; |
163 | |
164 | MachineInstr *emitLdStWithAddr(MachineInstr &MemI, |
165 | const ExtAddrMode &AM) const override; |
166 | |
167 | bool getMemOperandsWithOffsetWidth( |
168 | const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, |
169 | int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, |
170 | const TargetRegisterInfo *TRI) const override; |
171 | |
172 | bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, |
173 | int64_t Offset1, bool OffsetIsScalable1, |
174 | ArrayRef<const MachineOperand *> BaseOps2, |
175 | int64_t Offset2, bool OffsetIsScalable2, |
176 | unsigned ClusterSize, |
177 | unsigned NumBytes) const override; |
178 | |
179 | bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, |
180 | const MachineOperand *&BaseOp, |
181 | int64_t &Offset, LocationSize &Width, |
182 | const TargetRegisterInfo *TRI) const; |
183 | |
184 | bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, |
185 | const MachineInstr &MIb) const override; |
186 | |
187 | |
188 | std::pair<unsigned, unsigned> |
189 | decomposeMachineOperandsTargetFlags(unsigned TF) const override; |
190 | |
191 | ArrayRef<std::pair<unsigned, const char *>> |
192 | getSerializableDirectMachineOperandTargetFlags() const override; |
193 | |
194 | // Return true if the function can safely be outlined from. |
195 | bool isFunctionSafeToOutlineFrom(MachineFunction &MF, |
196 | bool OutlineFromLinkOnceODRs) const override; |
197 | |
198 | // Return true if MBB is safe to outline from, and return any target-specific |
199 | // information in Flags. |
200 | bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, |
201 | unsigned &Flags) const override; |
202 | |
203 | bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; |
204 | |
205 | // Calculate target-specific information for a set of outlining candidates. |
206 | std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo( |
207 | std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; |
208 | |
209 | // Return if/how a given MachineInstr should be outlined. |
210 | virtual outliner::InstrType |
211 | getOutliningTypeImpl(MachineBasicBlock::iterator &MBBI, |
212 | unsigned Flags) const override; |
213 | |
214 | // Insert a custom frame for outlined functions. |
215 | void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, |
216 | const outliner::OutlinedFunction &OF) const override; |
217 | |
218 | // Insert a call to an outlined function into a given basic block. |
219 | MachineBasicBlock::iterator |
220 | insertOutlinedCall(Module &M, MachineBasicBlock &MBB, |
221 | MachineBasicBlock::iterator &It, MachineFunction &MF, |
222 | outliner::Candidate &C) const override; |
223 | |
224 | std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI, |
225 | Register Reg) const override; |
226 | |
227 | bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, |
228 | unsigned &SrcOpIdx2) const override; |
229 | MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, |
230 | unsigned OpIdx1, |
231 | unsigned OpIdx2) const override; |
232 | |
233 | MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, |
234 | LiveIntervals *LIS) const override; |
235 | |
236 | // MIR printer helper function to annotate Operands with a comment. |
237 | std::string |
238 | createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, |
239 | unsigned OpIdx, |
240 | const TargetRegisterInfo *TRI) const override; |
241 | |
242 | /// Generate code to multiply the value in DestReg by Amt - handles all |
243 | /// the common optimizations for this idiom, and supports fallback for |
244 | /// subtargets which don't support multiply instructions. |
245 | void mulImm(MachineFunction &MF, MachineBasicBlock &MBB, |
246 | MachineBasicBlock::iterator II, const DebugLoc &DL, |
247 | Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const; |
248 | |
249 | bool useMachineCombiner() const override { return true; } |
250 | |
251 | MachineTraceStrategy getMachineCombinerTraceStrategy() const override; |
252 | |
253 | CombinerObjective getCombinerObjective(unsigned Pattern) const override; |
254 | |
255 | bool getMachineCombinerPatterns(MachineInstr &Root, |
256 | SmallVectorImpl<unsigned> &Patterns, |
257 | bool DoRegPressureReduce) const override; |
258 | |
259 | void |
260 | finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, |
261 | SmallVectorImpl<MachineInstr *> &InsInstrs) const override; |
262 | |
263 | void genAlternativeCodeSequence( |
264 | MachineInstr &Root, unsigned Pattern, |
265 | SmallVectorImpl<MachineInstr *> &InsInstrs, |
266 | SmallVectorImpl<MachineInstr *> &DelInstrs, |
267 | DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; |
268 | |
269 | bool hasReassociableSibling(const MachineInstr &Inst, |
270 | bool &Commuted) const override; |
271 | |
272 | bool isAssociativeAndCommutative(const MachineInstr &Inst, |
273 | bool Invert) const override; |
274 | |
275 | std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override; |
276 | |
277 | ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> |
278 | getSerializableMachineMemOperandTargetFlags() const override; |
279 | |
280 | unsigned getUndefInitOpcode(unsigned RegClassID) const override { |
281 | switch (RegClassID) { |
282 | case RISCV::VRRegClassID: |
283 | return RISCV::PseudoRVVInitUndefM1; |
284 | case RISCV::VRM2RegClassID: |
285 | return RISCV::PseudoRVVInitUndefM2; |
286 | case RISCV::VRM4RegClassID: |
287 | return RISCV::PseudoRVVInitUndefM4; |
288 | case RISCV::VRM8RegClassID: |
289 | return RISCV::PseudoRVVInitUndefM8; |
290 | default: |
291 | llvm_unreachable("Unexpected register class." ); |
292 | } |
293 | } |
294 | |
295 | protected: |
296 | const RISCVSubtarget &STI; |
297 | |
298 | private: |
299 | unsigned getInstBundleLength(const MachineInstr &MI) const; |
300 | }; |
301 | |
302 | namespace RISCV { |
303 | |
304 | // Returns true if this is the sext.w pattern, addiw rd, rs1, 0. |
305 | bool isSEXT_W(const MachineInstr &MI); |
306 | bool isZEXT_W(const MachineInstr &MI); |
307 | bool isZEXT_B(const MachineInstr &MI); |
308 | |
309 | // Returns true if the given MI is an RVV instruction opcode for which we may |
310 | // expect to see a FrameIndex operand. |
311 | bool isRVVSpill(const MachineInstr &MI); |
312 | |
313 | std::optional<std::pair<unsigned, unsigned>> |
314 | isRVVSpillForZvlsseg(unsigned Opcode); |
315 | |
316 | bool isFaultFirstLoad(const MachineInstr &MI); |
317 | |
318 | // Implemented in RISCVGenInstrInfo.inc |
319 | int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); |
320 | |
321 | // Return true if both input instructions have equal rounding mode. If at least |
322 | // one of the instructions does not have rounding mode, false will be returned. |
323 | bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2); |
324 | |
325 | // If \p Opcode is a .vx vector instruction, returns the lower number of bits |
326 | // that are used from the scalar .x operand for a given \p Log2SEW. Otherwise |
327 | // returns null. |
328 | std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode, |
329 | unsigned Log2SEW); |
330 | |
331 | // Returns the MC opcode of RVV pseudo instruction. |
332 | unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode); |
333 | |
334 | // Special immediate for AVL operand of V pseudo instructions to indicate VLMax. |
335 | static constexpr int64_t VLMaxSentinel = -1LL; |
336 | |
337 | // Mask assignments for floating-point |
338 | static constexpr unsigned FPMASK_Negative_Infinity = 0x001; |
339 | static constexpr unsigned FPMASK_Negative_Normal = 0x002; |
340 | static constexpr unsigned FPMASK_Negative_Subnormal = 0x004; |
341 | static constexpr unsigned FPMASK_Negative_Zero = 0x008; |
342 | static constexpr unsigned FPMASK_Positive_Zero = 0x010; |
343 | static constexpr unsigned FPMASK_Positive_Subnormal = 0x020; |
344 | static constexpr unsigned FPMASK_Positive_Normal = 0x040; |
345 | static constexpr unsigned FPMASK_Positive_Infinity = 0x080; |
346 | static constexpr unsigned FPMASK_Signaling_NaN = 0x100; |
347 | static constexpr unsigned FPMASK_Quiet_NaN = 0x200; |
348 | } // namespace RISCV |
349 | |
350 | namespace RISCVVPseudosTable { |
351 | |
352 | struct PseudoInfo { |
353 | uint16_t Pseudo; |
354 | uint16_t BaseInstr; |
355 | }; |
356 | |
357 | #define GET_RISCVVPseudosTable_DECL |
358 | #include "RISCVGenSearchableTables.inc" |
359 | |
360 | } // end namespace RISCVVPseudosTable |
361 | |
362 | namespace RISCV { |
363 | |
364 | struct RISCVMaskedPseudoInfo { |
365 | uint16_t MaskedPseudo; |
366 | uint16_t UnmaskedPseudo; |
367 | uint8_t MaskOpIdx; |
368 | uint8_t MaskAffectsResult : 1; |
369 | }; |
370 | #define GET_RISCVMaskedPseudosTable_DECL |
371 | #include "RISCVGenSearchableTables.inc" |
372 | } // end namespace RISCV |
373 | |
374 | } // end namespace llvm |
375 | #endif |
376 | |