1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include "pp_debug.h" |
24 | #include <linux/types.h> |
25 | #include <linux/kernel.h> |
26 | #include <linux/slab.h> |
27 | #include "atom-types.h" |
28 | #include "atombios.h" |
29 | #include "processpptables.h" |
30 | #include "cgs_common.h" |
31 | #include "smu/smu_8_0_d.h" |
32 | #include "smu8_fusion.h" |
33 | #include "smu/smu_8_0_sh_mask.h" |
34 | #include "smumgr.h" |
35 | #include "hwmgr.h" |
36 | #include "hardwaremanager.h" |
37 | #include "cz_ppsmc.h" |
38 | #include "smu8_hwmgr.h" |
39 | #include "power_state.h" |
40 | #include "pp_thermal.h" |
41 | |
42 | #define ixSMUSVI_NB_CURRENTVID 0xD8230044 |
43 | #define CURRENT_NB_VID_MASK 0xff000000 |
44 | #define CURRENT_NB_VID__SHIFT 24 |
45 | #define ixSMUSVI_GFX_CURRENTVID 0xD8230048 |
46 | #define CURRENT_GFX_VID_MASK 0xff000000 |
47 | #define CURRENT_GFX_VID__SHIFT 24 |
48 | |
49 | static const unsigned long smu8_magic = (unsigned long) PHM_Cz_Magic; |
50 | |
51 | static struct smu8_power_state *cast_smu8_power_state(struct pp_hw_power_state *hw_ps) |
52 | { |
53 | if (smu8_magic != hw_ps->magic) |
54 | return NULL; |
55 | |
56 | return (struct smu8_power_state *)hw_ps; |
57 | } |
58 | |
59 | static const struct smu8_power_state *cast_const_smu8_power_state( |
60 | const struct pp_hw_power_state *hw_ps) |
61 | { |
62 | if (smu8_magic != hw_ps->magic) |
63 | return NULL; |
64 | |
65 | return (struct smu8_power_state *)hw_ps; |
66 | } |
67 | |
68 | static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr, |
69 | uint32_t clock, uint32_t msg) |
70 | { |
71 | int i = 0; |
72 | struct phm_vce_clock_voltage_dependency_table *ptable = |
73 | hwmgr->dyn_state.vce_clock_voltage_dependency_table; |
74 | |
75 | switch (msg) { |
76 | case PPSMC_MSG_SetEclkSoftMin: |
77 | case PPSMC_MSG_SetEclkHardMin: |
78 | for (i = 0; i < (int)ptable->count; i++) { |
79 | if (clock <= ptable->entries[i].ecclk) |
80 | break; |
81 | } |
82 | break; |
83 | |
84 | case PPSMC_MSG_SetEclkSoftMax: |
85 | case PPSMC_MSG_SetEclkHardMax: |
86 | for (i = ptable->count - 1; i >= 0; i--) { |
87 | if (clock >= ptable->entries[i].ecclk) |
88 | break; |
89 | } |
90 | break; |
91 | |
92 | default: |
93 | break; |
94 | } |
95 | |
96 | return i; |
97 | } |
98 | |
99 | static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr, |
100 | uint32_t clock, uint32_t msg) |
101 | { |
102 | int i = 0; |
103 | struct phm_clock_voltage_dependency_table *table = |
104 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
105 | |
106 | switch (msg) { |
107 | case PPSMC_MSG_SetSclkSoftMin: |
108 | case PPSMC_MSG_SetSclkHardMin: |
109 | for (i = 0; i < (int)table->count; i++) { |
110 | if (clock <= table->entries[i].clk) |
111 | break; |
112 | } |
113 | break; |
114 | |
115 | case PPSMC_MSG_SetSclkSoftMax: |
116 | case PPSMC_MSG_SetSclkHardMax: |
117 | for (i = table->count - 1; i >= 0; i--) { |
118 | if (clock >= table->entries[i].clk) |
119 | break; |
120 | } |
121 | break; |
122 | |
123 | default: |
124 | break; |
125 | } |
126 | return i; |
127 | } |
128 | |
129 | static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr, |
130 | uint32_t clock, uint32_t msg) |
131 | { |
132 | int i = 0; |
133 | struct phm_uvd_clock_voltage_dependency_table *ptable = |
134 | hwmgr->dyn_state.uvd_clock_voltage_dependency_table; |
135 | |
136 | switch (msg) { |
137 | case PPSMC_MSG_SetUvdSoftMin: |
138 | case PPSMC_MSG_SetUvdHardMin: |
139 | for (i = 0; i < (int)ptable->count; i++) { |
140 | if (clock <= ptable->entries[i].vclk) |
141 | break; |
142 | } |
143 | break; |
144 | |
145 | case PPSMC_MSG_SetUvdSoftMax: |
146 | case PPSMC_MSG_SetUvdHardMax: |
147 | for (i = ptable->count - 1; i >= 0; i--) { |
148 | if (clock >= ptable->entries[i].vclk) |
149 | break; |
150 | } |
151 | break; |
152 | |
153 | default: |
154 | break; |
155 | } |
156 | |
157 | return i; |
158 | } |
159 | |
160 | static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr) |
161 | { |
162 | struct smu8_hwmgr *data = hwmgr->backend; |
163 | |
164 | if (data->max_sclk_level == 0) { |
165 | smum_send_msg_to_smc(hwmgr, |
166 | PPSMC_MSG_GetMaxSclkLevel, |
167 | resp: &data->max_sclk_level); |
168 | data->max_sclk_level += 1; |
169 | } |
170 | |
171 | return data->max_sclk_level; |
172 | } |
173 | |
174 | static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) |
175 | { |
176 | struct smu8_hwmgr *data = hwmgr->backend; |
177 | struct amdgpu_device *adev = hwmgr->adev; |
178 | |
179 | data->gfx_ramp_step = 256*25/100; |
180 | data->gfx_ramp_delay = 1; /* by default, we delay 1us */ |
181 | |
182 | data->mgcg_cgtt_local0 = 0x00000000; |
183 | data->mgcg_cgtt_local1 = 0x00000000; |
184 | data->clock_slow_down_freq = 25000; |
185 | data->skip_clock_slow_down = 1; |
186 | data->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */ |
187 | data->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */ |
188 | data->voting_rights_clients = 0x00C00033; |
189 | data->static_screen_threshold = 8; |
190 | data->ddi_power_gating_disabled = 0; |
191 | data->bapm_enabled = 1; |
192 | data->voltage_drop_threshold = 0; |
193 | data->gfx_power_gating_threshold = 500; |
194 | data->vce_slow_sclk_threshold = 20000; |
195 | data->dce_slow_sclk_threshold = 30000; |
196 | data->disable_driver_thermal_policy = 1; |
197 | data->disable_nb_ps3_in_battery = 0; |
198 | |
199 | phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps, |
200 | c: PHM_PlatformCaps_ABM); |
201 | |
202 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
203 | c: PHM_PlatformCaps_NonABMSupportInPPLib); |
204 | |
205 | phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps, |
206 | c: PHM_PlatformCaps_DynamicM3Arbiter); |
207 | |
208 | data->override_dynamic_mgpg = 1; |
209 | |
210 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
211 | c: PHM_PlatformCaps_DynamicPatchPowerState); |
212 | |
213 | data->thermal_auto_throttling_treshold = 0; |
214 | data->tdr_clock = 0; |
215 | data->disable_gfx_power_gating_in_uvd = 0; |
216 | |
217 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
218 | c: PHM_PlatformCaps_DynamicUVDState); |
219 | |
220 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
221 | c: PHM_PlatformCaps_UVDDPM); |
222 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
223 | c: PHM_PlatformCaps_VCEDPM); |
224 | |
225 | data->cc6_settings.cpu_cc6_disable = false; |
226 | data->cc6_settings.cpu_pstate_disable = false; |
227 | data->cc6_settings.nb_pstate_switch_disable = false; |
228 | data->cc6_settings.cpu_pstate_separation_time = 0; |
229 | |
230 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
231 | c: PHM_PlatformCaps_DisableVoltageIsland); |
232 | |
233 | phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps, |
234 | c: PHM_PlatformCaps_UVDPowerGating); |
235 | phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps, |
236 | c: PHM_PlatformCaps_VCEPowerGating); |
237 | |
238 | if (adev->pg_flags & AMD_PG_SUPPORT_UVD) |
239 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
240 | c: PHM_PlatformCaps_UVDPowerGating); |
241 | if (adev->pg_flags & AMD_PG_SUPPORT_VCE) |
242 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
243 | c: PHM_PlatformCaps_VCEPowerGating); |
244 | |
245 | |
246 | return 0; |
247 | } |
248 | |
249 | /* convert form 8bit vid to real voltage in mV*4 */ |
250 | static uint32_t smu8_convert_8Bit_index_to_voltage( |
251 | struct pp_hwmgr *hwmgr, uint16_t voltage) |
252 | { |
253 | return 6200 - (voltage * 25); |
254 | } |
255 | |
256 | static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, |
257 | struct phm_clock_and_voltage_limits *table) |
258 | { |
259 | struct smu8_hwmgr *data = hwmgr->backend; |
260 | struct smu8_sys_info *sys_info = &data->sys_info; |
261 | struct phm_clock_voltage_dependency_table *dep_table = |
262 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
263 | |
264 | if (dep_table->count > 0) { |
265 | table->sclk = dep_table->entries[dep_table->count-1].clk; |
266 | table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr, |
267 | voltage: (uint16_t)dep_table->entries[dep_table->count-1].v); |
268 | } |
269 | table->mclk = sys_info->nbp_memory_clock[0]; |
270 | return 0; |
271 | } |
272 | |
273 | static int smu8_init_dynamic_state_adjustment_rule_settings( |
274 | struct pp_hwmgr *hwmgr, |
275 | ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table) |
276 | { |
277 | struct phm_clock_voltage_dependency_table *table_clk_vlt; |
278 | |
279 | table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 8), |
280 | GFP_KERNEL); |
281 | |
282 | if (NULL == table_clk_vlt) { |
283 | pr_err("Can not allocate memory!\n" ); |
284 | return -ENOMEM; |
285 | } |
286 | |
287 | table_clk_vlt->count = 8; |
288 | table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; |
289 | table_clk_vlt->entries[0].v = 0; |
290 | table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; |
291 | table_clk_vlt->entries[1].v = 1; |
292 | table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; |
293 | table_clk_vlt->entries[2].v = 2; |
294 | table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; |
295 | table_clk_vlt->entries[3].v = 3; |
296 | table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; |
297 | table_clk_vlt->entries[4].v = 4; |
298 | table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; |
299 | table_clk_vlt->entries[5].v = 5; |
300 | table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; |
301 | table_clk_vlt->entries[6].v = 6; |
302 | table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; |
303 | table_clk_vlt->entries[7].v = 7; |
304 | hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; |
305 | |
306 | return 0; |
307 | } |
308 | |
309 | static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr) |
310 | { |
311 | struct smu8_hwmgr *data = hwmgr->backend; |
312 | ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL; |
313 | uint32_t i; |
314 | int result = 0; |
315 | uint8_t frev, crev; |
316 | uint16_t size; |
317 | |
318 | info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(dev: hwmgr->adev, |
319 | GetIndexIntoMasterTable(DATA, IntegratedSystemInfo), |
320 | size: &size, frev: &frev, crev: &crev); |
321 | |
322 | if (info == NULL) { |
323 | pr_err("Could not retrieve the Integrated System Info Table!\n" ); |
324 | return -EINVAL; |
325 | } |
326 | |
327 | if (crev != 9) { |
328 | pr_err("Unsupported IGP table: %d %d\n" , frev, crev); |
329 | return -EINVAL; |
330 | } |
331 | |
332 | data->sys_info.bootup_uma_clock = |
333 | le32_to_cpu(info->ulBootUpUMAClock); |
334 | |
335 | data->sys_info.bootup_engine_clock = |
336 | le32_to_cpu(info->ulBootUpEngineClock); |
337 | |
338 | data->sys_info.dentist_vco_freq = |
339 | le32_to_cpu(info->ulDentistVCOFreq); |
340 | |
341 | data->sys_info.system_config = |
342 | le32_to_cpu(info->ulSystemConfig); |
343 | |
344 | data->sys_info.bootup_nb_voltage_index = |
345 | le16_to_cpu(info->usBootUpNBVoltage); |
346 | |
347 | data->sys_info.htc_hyst_lmt = |
348 | (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt; |
349 | |
350 | data->sys_info.htc_tmp_lmt = |
351 | (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt; |
352 | |
353 | if (data->sys_info.htc_tmp_lmt <= |
354 | data->sys_info.htc_hyst_lmt) { |
355 | pr_err("The htcTmpLmt should be larger than htcHystLmt.\n" ); |
356 | return -EINVAL; |
357 | } |
358 | |
359 | data->sys_info.nb_dpm_enable = |
360 | data->enable_nb_ps_policy && |
361 | (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1); |
362 | |
363 | for (i = 0; i < SMU8_NUM_NBPSTATES; i++) { |
364 | if (i < SMU8_NUM_NBPMEMORYCLOCK) { |
365 | data->sys_info.nbp_memory_clock[i] = |
366 | le32_to_cpu(info->ulNbpStateMemclkFreq[i]); |
367 | } |
368 | data->sys_info.nbp_n_clock[i] = |
369 | le32_to_cpu(info->ulNbpStateNClkFreq[i]); |
370 | } |
371 | |
372 | for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) { |
373 | data->sys_info.display_clock[i] = |
374 | le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK); |
375 | } |
376 | |
377 | /* Here use 4 levels, make sure not exceed */ |
378 | for (i = 0; i < SMU8_NUM_NBPSTATES; i++) { |
379 | data->sys_info.nbp_voltage_index[i] = |
380 | le16_to_cpu(info->usNBPStateVoltage[i]); |
381 | } |
382 | |
383 | if (!data->sys_info.nb_dpm_enable) { |
384 | for (i = 1; i < SMU8_NUM_NBPSTATES; i++) { |
385 | if (i < SMU8_NUM_NBPMEMORYCLOCK) { |
386 | data->sys_info.nbp_memory_clock[i] = |
387 | data->sys_info.nbp_memory_clock[0]; |
388 | } |
389 | data->sys_info.nbp_n_clock[i] = |
390 | data->sys_info.nbp_n_clock[0]; |
391 | data->sys_info.nbp_voltage_index[i] = |
392 | data->sys_info.nbp_voltage_index[0]; |
393 | } |
394 | } |
395 | |
396 | if (le32_to_cpu(info->ulGPUCapInfo) & |
397 | SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) { |
398 | phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps, |
399 | c: PHM_PlatformCaps_EnableDFSBypass); |
400 | } |
401 | |
402 | data->sys_info.uma_channel_number = info->ucUMAChannelNumber; |
403 | |
404 | smu8_construct_max_power_limits_table (hwmgr, |
405 | table: &hwmgr->dyn_state.max_clock_voltage_on_ac); |
406 | |
407 | smu8_init_dynamic_state_adjustment_rule_settings(hwmgr, |
408 | disp_voltage_table: &info->sDISPCLK_Voltage[0]); |
409 | |
410 | return result; |
411 | } |
412 | |
413 | static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr) |
414 | { |
415 | struct smu8_hwmgr *data = hwmgr->backend; |
416 | |
417 | data->boot_power_level.engineClock = |
418 | data->sys_info.bootup_engine_clock; |
419 | |
420 | data->boot_power_level.vddcIndex = |
421 | (uint8_t)data->sys_info.bootup_nb_voltage_index; |
422 | |
423 | data->boot_power_level.dsDividerIndex = 0; |
424 | data->boot_power_level.ssDividerIndex = 0; |
425 | data->boot_power_level.allowGnbSlow = 1; |
426 | data->boot_power_level.forceNBPstate = 0; |
427 | data->boot_power_level.hysteresis_up = 0; |
428 | data->boot_power_level.numSIMDToPowerDown = 0; |
429 | data->boot_power_level.display_wm = 0; |
430 | data->boot_power_level.vce_wm = 0; |
431 | |
432 | return 0; |
433 | } |
434 | |
435 | static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) |
436 | { |
437 | struct SMU8_Fusion_ClkTable *clock_table; |
438 | int ret; |
439 | uint32_t i; |
440 | void *table = NULL; |
441 | pp_atomctrl_clock_dividers_kong dividers; |
442 | |
443 | struct phm_clock_voltage_dependency_table *vddc_table = |
444 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
445 | struct phm_clock_voltage_dependency_table *vdd_gfx_table = |
446 | hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; |
447 | struct phm_acp_clock_voltage_dependency_table *acp_table = |
448 | hwmgr->dyn_state.acp_clock_voltage_dependency_table; |
449 | struct phm_uvd_clock_voltage_dependency_table *uvd_table = |
450 | hwmgr->dyn_state.uvd_clock_voltage_dependency_table; |
451 | struct phm_vce_clock_voltage_dependency_table *vce_table = |
452 | hwmgr->dyn_state.vce_clock_voltage_dependency_table; |
453 | |
454 | if (!hwmgr->need_pp_table_upload) |
455 | return 0; |
456 | |
457 | ret = smum_download_powerplay_table(hwmgr, table: &table); |
458 | |
459 | PP_ASSERT_WITH_CODE((0 == ret && NULL != table), |
460 | "Fail to get clock table from SMU!" , return -EINVAL;); |
461 | |
462 | clock_table = (struct SMU8_Fusion_ClkTable *)table; |
463 | |
464 | /* patch clock table */ |
465 | PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), |
466 | "Dependency table entry exceeds max limit!" , return -EINVAL;); |
467 | PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), |
468 | "Dependency table entry exceeds max limit!" , return -EINVAL;); |
469 | PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), |
470 | "Dependency table entry exceeds max limit!" , return -EINVAL;); |
471 | PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), |
472 | "Dependency table entry exceeds max limit!" , return -EINVAL;); |
473 | PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), |
474 | "Dependency table entry exceeds max limit!" , return -EINVAL;); |
475 | |
476 | for (i = 0; i < SMU8_MAX_HARDWARE_POWERLEVELS; i++) { |
477 | |
478 | /* vddc_sclk */ |
479 | clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid = |
480 | (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0; |
481 | clock_table->SclkBreakdownTable.ClkLevel[i].Frequency = |
482 | (i < vddc_table->count) ? vddc_table->entries[i].clk : 0; |
483 | |
484 | atomctrl_get_engine_pll_dividers_kong(hwmgr, |
485 | clock_value: clock_table->SclkBreakdownTable.ClkLevel[i].Frequency, |
486 | dividers: ÷rs); |
487 | |
488 | clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid = |
489 | (uint8_t)dividers.pll_post_divider; |
490 | |
491 | /* vddgfx_sclk */ |
492 | clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid = |
493 | (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0; |
494 | |
495 | /* acp breakdown */ |
496 | clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid = |
497 | (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0; |
498 | clock_table->AclkBreakdownTable.ClkLevel[i].Frequency = |
499 | (i < acp_table->count) ? acp_table->entries[i].acpclk : 0; |
500 | |
501 | atomctrl_get_engine_pll_dividers_kong(hwmgr, |
502 | clock_value: clock_table->AclkBreakdownTable.ClkLevel[i].Frequency, |
503 | dividers: ÷rs); |
504 | |
505 | clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid = |
506 | (uint8_t)dividers.pll_post_divider; |
507 | |
508 | |
509 | /* uvd breakdown */ |
510 | clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid = |
511 | (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; |
512 | clock_table->VclkBreakdownTable.ClkLevel[i].Frequency = |
513 | (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; |
514 | |
515 | atomctrl_get_engine_pll_dividers_kong(hwmgr, |
516 | clock_value: clock_table->VclkBreakdownTable.ClkLevel[i].Frequency, |
517 | dividers: ÷rs); |
518 | |
519 | clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid = |
520 | (uint8_t)dividers.pll_post_divider; |
521 | |
522 | clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid = |
523 | (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; |
524 | clock_table->DclkBreakdownTable.ClkLevel[i].Frequency = |
525 | (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0; |
526 | |
527 | atomctrl_get_engine_pll_dividers_kong(hwmgr, |
528 | clock_value: clock_table->DclkBreakdownTable.ClkLevel[i].Frequency, |
529 | dividers: ÷rs); |
530 | |
531 | clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid = |
532 | (uint8_t)dividers.pll_post_divider; |
533 | |
534 | /* vce breakdown */ |
535 | clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid = |
536 | (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0; |
537 | clock_table->EclkBreakdownTable.ClkLevel[i].Frequency = |
538 | (i < vce_table->count) ? vce_table->entries[i].ecclk : 0; |
539 | |
540 | |
541 | atomctrl_get_engine_pll_dividers_kong(hwmgr, |
542 | clock_value: clock_table->EclkBreakdownTable.ClkLevel[i].Frequency, |
543 | dividers: ÷rs); |
544 | |
545 | clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid = |
546 | (uint8_t)dividers.pll_post_divider; |
547 | |
548 | } |
549 | ret = smum_upload_powerplay_table(hwmgr); |
550 | |
551 | return ret; |
552 | } |
553 | |
554 | static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr) |
555 | { |
556 | struct smu8_hwmgr *data = hwmgr->backend; |
557 | struct phm_clock_voltage_dependency_table *table = |
558 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
559 | unsigned long clock = 0, level; |
560 | |
561 | if (NULL == table || table->count <= 0) |
562 | return -EINVAL; |
563 | |
564 | data->sclk_dpm.soft_min_clk = table->entries[0].clk; |
565 | data->sclk_dpm.hard_min_clk = table->entries[0].clk; |
566 | |
567 | level = smu8_get_max_sclk_level(hwmgr) - 1; |
568 | |
569 | if (level < table->count) |
570 | clock = table->entries[level].clk; |
571 | else |
572 | clock = table->entries[table->count - 1].clk; |
573 | |
574 | data->sclk_dpm.soft_max_clk = clock; |
575 | data->sclk_dpm.hard_max_clk = clock; |
576 | |
577 | return 0; |
578 | } |
579 | |
580 | static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr) |
581 | { |
582 | struct smu8_hwmgr *data = hwmgr->backend; |
583 | struct phm_uvd_clock_voltage_dependency_table *table = |
584 | hwmgr->dyn_state.uvd_clock_voltage_dependency_table; |
585 | unsigned long clock = 0; |
586 | uint32_t level; |
587 | |
588 | if (NULL == table || table->count <= 0) |
589 | return -EINVAL; |
590 | |
591 | data->uvd_dpm.soft_min_clk = 0; |
592 | data->uvd_dpm.hard_min_clk = 0; |
593 | |
594 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel, resp: &level); |
595 | |
596 | if (level < table->count) |
597 | clock = table->entries[level].vclk; |
598 | else |
599 | clock = table->entries[table->count - 1].vclk; |
600 | |
601 | data->uvd_dpm.soft_max_clk = clock; |
602 | data->uvd_dpm.hard_max_clk = clock; |
603 | |
604 | return 0; |
605 | } |
606 | |
607 | static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr) |
608 | { |
609 | struct smu8_hwmgr *data = hwmgr->backend; |
610 | struct phm_vce_clock_voltage_dependency_table *table = |
611 | hwmgr->dyn_state.vce_clock_voltage_dependency_table; |
612 | unsigned long clock = 0; |
613 | uint32_t level; |
614 | |
615 | if (NULL == table || table->count <= 0) |
616 | return -EINVAL; |
617 | |
618 | data->vce_dpm.soft_min_clk = 0; |
619 | data->vce_dpm.hard_min_clk = 0; |
620 | |
621 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel, resp: &level); |
622 | |
623 | if (level < table->count) |
624 | clock = table->entries[level].ecclk; |
625 | else |
626 | clock = table->entries[table->count - 1].ecclk; |
627 | |
628 | data->vce_dpm.soft_max_clk = clock; |
629 | data->vce_dpm.hard_max_clk = clock; |
630 | |
631 | return 0; |
632 | } |
633 | |
634 | static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr) |
635 | { |
636 | struct smu8_hwmgr *data = hwmgr->backend; |
637 | struct phm_acp_clock_voltage_dependency_table *table = |
638 | hwmgr->dyn_state.acp_clock_voltage_dependency_table; |
639 | unsigned long clock = 0; |
640 | uint32_t level; |
641 | |
642 | if (NULL == table || table->count <= 0) |
643 | return -EINVAL; |
644 | |
645 | data->acp_dpm.soft_min_clk = 0; |
646 | data->acp_dpm.hard_min_clk = 0; |
647 | |
648 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel, resp: &level); |
649 | |
650 | if (level < table->count) |
651 | clock = table->entries[level].acpclk; |
652 | else |
653 | clock = table->entries[table->count - 1].acpclk; |
654 | |
655 | data->acp_dpm.soft_max_clk = clock; |
656 | data->acp_dpm.hard_max_clk = clock; |
657 | return 0; |
658 | } |
659 | |
660 | static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr) |
661 | { |
662 | struct smu8_hwmgr *data = hwmgr->backend; |
663 | |
664 | data->uvd_power_gated = false; |
665 | data->vce_power_gated = false; |
666 | data->samu_power_gated = false; |
667 | #ifdef CONFIG_DRM_AMD_ACP |
668 | data->acp_power_gated = false; |
669 | #else |
670 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); |
671 | data->acp_power_gated = true; |
672 | #endif |
673 | |
674 | } |
675 | |
676 | static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr) |
677 | { |
678 | struct smu8_hwmgr *data = hwmgr->backend; |
679 | |
680 | data->low_sclk_interrupt_threshold = 0; |
681 | } |
682 | |
683 | static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr) |
684 | { |
685 | struct smu8_hwmgr *data = hwmgr->backend; |
686 | struct phm_clock_voltage_dependency_table *table = |
687 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
688 | |
689 | unsigned long clock = 0; |
690 | unsigned long level; |
691 | unsigned long stable_pstate_sclk; |
692 | unsigned long percentage; |
693 | |
694 | data->sclk_dpm.soft_min_clk = table->entries[0].clk; |
695 | level = smu8_get_max_sclk_level(hwmgr) - 1; |
696 | |
697 | if (level < table->count) |
698 | data->sclk_dpm.soft_max_clk = table->entries[level].clk; |
699 | else |
700 | data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk; |
701 | |
702 | clock = hwmgr->display_config->min_core_set_clock; |
703 | if (clock == 0) |
704 | pr_debug("min_core_set_clock not set\n" ); |
705 | |
706 | if (data->sclk_dpm.hard_min_clk != clock) { |
707 | data->sclk_dpm.hard_min_clk = clock; |
708 | |
709 | smum_send_msg_to_smc_with_parameter(hwmgr, |
710 | PPSMC_MSG_SetSclkHardMin, |
711 | parameter: smu8_get_sclk_level(hwmgr, |
712 | clock: data->sclk_dpm.hard_min_clk, |
713 | PPSMC_MSG_SetSclkHardMin), |
714 | NULL); |
715 | } |
716 | |
717 | clock = data->sclk_dpm.soft_min_clk; |
718 | |
719 | /* update minimum clocks for Stable P-State feature */ |
720 | if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, |
721 | c: PHM_PlatformCaps_StablePState)) { |
722 | percentage = 75; |
723 | /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */ |
724 | stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * |
725 | percentage) / 100; |
726 | |
727 | if (clock < stable_pstate_sclk) |
728 | clock = stable_pstate_sclk; |
729 | } |
730 | |
731 | if (data->sclk_dpm.soft_min_clk != clock) { |
732 | data->sclk_dpm.soft_min_clk = clock; |
733 | smum_send_msg_to_smc_with_parameter(hwmgr, |
734 | PPSMC_MSG_SetSclkSoftMin, |
735 | parameter: smu8_get_sclk_level(hwmgr, |
736 | clock: data->sclk_dpm.soft_min_clk, |
737 | PPSMC_MSG_SetSclkSoftMin), |
738 | NULL); |
739 | } |
740 | |
741 | if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, |
742 | c: PHM_PlatformCaps_StablePState) && |
743 | data->sclk_dpm.soft_max_clk != clock) { |
744 | data->sclk_dpm.soft_max_clk = clock; |
745 | smum_send_msg_to_smc_with_parameter(hwmgr, |
746 | PPSMC_MSG_SetSclkSoftMax, |
747 | parameter: smu8_get_sclk_level(hwmgr, |
748 | clock: data->sclk_dpm.soft_max_clk, |
749 | PPSMC_MSG_SetSclkSoftMax), |
750 | NULL); |
751 | } |
752 | |
753 | return 0; |
754 | } |
755 | |
756 | static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) |
757 | { |
758 | if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, |
759 | c: PHM_PlatformCaps_SclkDeepSleep)) { |
760 | uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; |
761 | if (clks == 0) |
762 | clks = SMU8_MIN_DEEP_SLEEP_SCLK; |
763 | |
764 | PP_DBG_LOG("Setting Deep Sleep Clock: %d\n" , clks); |
765 | |
766 | smum_send_msg_to_smc_with_parameter(hwmgr, |
767 | PPSMC_MSG_SetMinDeepSleepSclk, |
768 | parameter: clks, |
769 | NULL); |
770 | } |
771 | |
772 | return 0; |
773 | } |
774 | |
775 | static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr) |
776 | { |
777 | struct smu8_hwmgr *data = |
778 | hwmgr->backend; |
779 | |
780 | smum_send_msg_to_smc_with_parameter(hwmgr, |
781 | PPSMC_MSG_SetWatermarkFrequency, |
782 | parameter: data->sclk_dpm.soft_max_clk, |
783 | NULL); |
784 | |
785 | return 0; |
786 | } |
787 | |
788 | static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock) |
789 | { |
790 | struct smu8_hwmgr *hw_data = hwmgr->backend; |
791 | |
792 | if (hw_data->is_nb_dpm_enabled) { |
793 | if (enable) { |
794 | PP_DBG_LOG("enable Low Memory PState.\n" ); |
795 | |
796 | return smum_send_msg_to_smc_with_parameter(hwmgr, |
797 | PPSMC_MSG_EnableLowMemoryPstate, |
798 | parameter: (lock ? 1 : 0), |
799 | NULL); |
800 | } else { |
801 | PP_DBG_LOG("disable Low Memory PState.\n" ); |
802 | |
803 | return smum_send_msg_to_smc_with_parameter(hwmgr, |
804 | PPSMC_MSG_DisableLowMemoryPstate, |
805 | parameter: (lock ? 1 : 0), |
806 | NULL); |
807 | } |
808 | } |
809 | |
810 | return 0; |
811 | } |
812 | |
813 | static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr) |
814 | { |
815 | int ret = 0; |
816 | |
817 | struct smu8_hwmgr *data = hwmgr->backend; |
818 | unsigned long dpm_features = 0; |
819 | |
820 | if (data->is_nb_dpm_enabled) { |
821 | smu8_nbdpm_pstate_enable_disable(hwmgr, enable: true, lock: true); |
822 | dpm_features |= NB_DPM_MASK; |
823 | ret = smum_send_msg_to_smc_with_parameter( |
824 | hwmgr, |
825 | PPSMC_MSG_DisableAllSmuFeatures, |
826 | parameter: dpm_features, |
827 | NULL); |
828 | if (ret == 0) |
829 | data->is_nb_dpm_enabled = false; |
830 | } |
831 | |
832 | return ret; |
833 | } |
834 | |
835 | static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr) |
836 | { |
837 | int ret = 0; |
838 | |
839 | struct smu8_hwmgr *data = hwmgr->backend; |
840 | unsigned long dpm_features = 0; |
841 | |
842 | if (!data->is_nb_dpm_enabled) { |
843 | PP_DBG_LOG("enabling ALL SMU features.\n" ); |
844 | dpm_features |= NB_DPM_MASK; |
845 | ret = smum_send_msg_to_smc_with_parameter( |
846 | hwmgr, |
847 | PPSMC_MSG_EnableAllSmuFeatures, |
848 | parameter: dpm_features, |
849 | NULL); |
850 | if (ret == 0) |
851 | data->is_nb_dpm_enabled = true; |
852 | } |
853 | |
854 | return ret; |
855 | } |
856 | |
857 | static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input) |
858 | { |
859 | bool disable_switch; |
860 | bool enable_low_mem_state; |
861 | struct smu8_hwmgr *hw_data = hwmgr->backend; |
862 | const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input; |
863 | const struct smu8_power_state *pnew_state = cast_const_smu8_power_state(hw_ps: states->pnew_state); |
864 | |
865 | if (hw_data->sys_info.nb_dpm_enable) { |
866 | disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false; |
867 | enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true; |
868 | |
869 | if (pnew_state->action == FORCE_HIGH) |
870 | smu8_nbdpm_pstate_enable_disable(hwmgr, enable: false, lock: disable_switch); |
871 | else if (pnew_state->action == CANCEL_FORCE_HIGH) |
872 | smu8_nbdpm_pstate_enable_disable(hwmgr, enable: true, lock: disable_switch); |
873 | else |
874 | smu8_nbdpm_pstate_enable_disable(hwmgr, enable: enable_low_mem_state, lock: disable_switch); |
875 | } |
876 | return 0; |
877 | } |
878 | |
879 | static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) |
880 | { |
881 | int ret = 0; |
882 | |
883 | smu8_update_sclk_limit(hwmgr); |
884 | smu8_set_deep_sleep_sclk_threshold(hwmgr); |
885 | smu8_set_watermark_threshold(hwmgr); |
886 | ret = smu8_enable_nb_dpm(hwmgr); |
887 | if (ret) |
888 | return ret; |
889 | smu8_update_low_mem_pstate(hwmgr, input); |
890 | |
891 | return 0; |
892 | } |
893 | |
894 | |
895 | static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr) |
896 | { |
897 | int ret; |
898 | |
899 | ret = smu8_upload_pptable_to_smu(hwmgr); |
900 | if (ret) |
901 | return ret; |
902 | ret = smu8_init_sclk_limit(hwmgr); |
903 | if (ret) |
904 | return ret; |
905 | ret = smu8_init_uvd_limit(hwmgr); |
906 | if (ret) |
907 | return ret; |
908 | ret = smu8_init_vce_limit(hwmgr); |
909 | if (ret) |
910 | return ret; |
911 | ret = smu8_init_acp_limit(hwmgr); |
912 | if (ret) |
913 | return ret; |
914 | |
915 | smu8_init_power_gate_state(hwmgr); |
916 | smu8_init_sclk_threshold(hwmgr); |
917 | |
918 | return 0; |
919 | } |
920 | |
921 | static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr) |
922 | { |
923 | struct smu8_hwmgr *hw_data = hwmgr->backend; |
924 | |
925 | hw_data->disp_clk_bypass_pending = false; |
926 | hw_data->disp_clk_bypass = false; |
927 | } |
928 | |
929 | static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr) |
930 | { |
931 | struct smu8_hwmgr *hw_data = hwmgr->backend; |
932 | |
933 | hw_data->is_nb_dpm_enabled = false; |
934 | } |
935 | |
936 | static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr) |
937 | { |
938 | struct smu8_hwmgr *hw_data = hwmgr->backend; |
939 | |
940 | hw_data->cc6_settings.cc6_setting_changed = false; |
941 | hw_data->cc6_settings.cpu_pstate_separation_time = 0; |
942 | hw_data->cc6_settings.cpu_cc6_disable = false; |
943 | hw_data->cc6_settings.cpu_pstate_disable = false; |
944 | } |
945 | |
946 | static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr) |
947 | { |
948 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
949 | ixCG_FREQ_TRAN_VOTING_0, |
950 | SMU8_VOTINGRIGHTSCLIENTS_DFLT0); |
951 | } |
952 | |
953 | static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr) |
954 | { |
955 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
956 | ixCG_FREQ_TRAN_VOTING_0, 0); |
957 | } |
958 | |
959 | static int smu8_start_dpm(struct pp_hwmgr *hwmgr) |
960 | { |
961 | struct smu8_hwmgr *data = hwmgr->backend; |
962 | |
963 | data->dpm_flags |= DPMFlags_SCLK_Enabled; |
964 | |
965 | return smum_send_msg_to_smc_with_parameter(hwmgr, |
966 | PPSMC_MSG_EnableAllSmuFeatures, |
967 | SCLK_DPM_MASK, |
968 | NULL); |
969 | } |
970 | |
971 | static int smu8_stop_dpm(struct pp_hwmgr *hwmgr) |
972 | { |
973 | int ret = 0; |
974 | struct smu8_hwmgr *data = hwmgr->backend; |
975 | unsigned long dpm_features = 0; |
976 | |
977 | if (data->dpm_flags & DPMFlags_SCLK_Enabled) { |
978 | dpm_features |= SCLK_DPM_MASK; |
979 | data->dpm_flags &= ~DPMFlags_SCLK_Enabled; |
980 | ret = smum_send_msg_to_smc_with_parameter(hwmgr, |
981 | PPSMC_MSG_DisableAllSmuFeatures, |
982 | parameter: dpm_features, |
983 | NULL); |
984 | } |
985 | return ret; |
986 | } |
987 | |
988 | static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr) |
989 | { |
990 | struct smu8_hwmgr *data = hwmgr->backend; |
991 | |
992 | data->sclk_dpm.soft_min_clk = data->sys_info.bootup_engine_clock; |
993 | data->sclk_dpm.soft_max_clk = data->sys_info.bootup_engine_clock; |
994 | |
995 | smum_send_msg_to_smc_with_parameter(hwmgr, |
996 | PPSMC_MSG_SetSclkSoftMin, |
997 | parameter: smu8_get_sclk_level(hwmgr, |
998 | clock: data->sclk_dpm.soft_min_clk, |
999 | PPSMC_MSG_SetSclkSoftMin), |
1000 | NULL); |
1001 | |
1002 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1003 | PPSMC_MSG_SetSclkSoftMax, |
1004 | parameter: smu8_get_sclk_level(hwmgr, |
1005 | clock: data->sclk_dpm.soft_max_clk, |
1006 | PPSMC_MSG_SetSclkSoftMax), |
1007 | NULL); |
1008 | |
1009 | return 0; |
1010 | } |
1011 | |
1012 | static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr) |
1013 | { |
1014 | struct smu8_hwmgr *data = hwmgr->backend; |
1015 | |
1016 | data->acp_boot_level = 0xff; |
1017 | } |
1018 | |
1019 | static void smu8_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) |
1020 | { |
1021 | struct phm_clock_voltage_dependency_table *table = |
1022 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
1023 | |
1024 | hwmgr->pstate_sclk = table->entries[0].clk / 100; |
1025 | hwmgr->pstate_mclk = 0; |
1026 | |
1027 | hwmgr->pstate_sclk_peak = table->entries[table->count - 1].clk / 100; |
1028 | hwmgr->pstate_mclk_peak = 0; |
1029 | } |
1030 | |
1031 | static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) |
1032 | { |
1033 | smu8_program_voting_clients(hwmgr); |
1034 | if (smu8_start_dpm(hwmgr)) |
1035 | return -EINVAL; |
1036 | smu8_program_bootup_state(hwmgr); |
1037 | smu8_reset_acp_boot_level(hwmgr); |
1038 | |
1039 | smu8_populate_umdpstate_clocks(hwmgr); |
1040 | |
1041 | return 0; |
1042 | } |
1043 | |
1044 | static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr) |
1045 | { |
1046 | smu8_disable_nb_dpm(hwmgr); |
1047 | |
1048 | smu8_clear_voting_clients(hwmgr); |
1049 | if (smu8_stop_dpm(hwmgr)) |
1050 | return -EINVAL; |
1051 | |
1052 | return 0; |
1053 | } |
1054 | |
1055 | static int smu8_power_off_asic(struct pp_hwmgr *hwmgr) |
1056 | { |
1057 | smu8_disable_dpm_tasks(hwmgr); |
1058 | smu8_power_up_display_clock_sys_pll(hwmgr); |
1059 | smu8_clear_nb_dpm_flag(hwmgr); |
1060 | smu8_reset_cc6_data(hwmgr); |
1061 | return 0; |
1062 | } |
1063 | |
1064 | static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, |
1065 | struct pp_power_state *prequest_ps, |
1066 | const struct pp_power_state *pcurrent_ps) |
1067 | { |
1068 | struct smu8_power_state *smu8_ps = |
1069 | cast_smu8_power_state(hw_ps: &prequest_ps->hardware); |
1070 | |
1071 | const struct smu8_power_state *smu8_current_ps = |
1072 | cast_const_smu8_power_state(hw_ps: &pcurrent_ps->hardware); |
1073 | |
1074 | struct smu8_hwmgr *data = hwmgr->backend; |
1075 | struct PP_Clocks clocks = {0, 0, 0, 0}; |
1076 | bool force_high; |
1077 | |
1078 | smu8_ps->need_dfs_bypass = true; |
1079 | |
1080 | data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); |
1081 | |
1082 | clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? |
1083 | hwmgr->display_config->min_mem_set_clock : |
1084 | data->sys_info.nbp_memory_clock[1]; |
1085 | |
1086 | |
1087 | if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, c: PHM_PlatformCaps_StablePState)) |
1088 | clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; |
1089 | |
1090 | force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]) |
1091 | || (hwmgr->display_config->num_display >= 3); |
1092 | |
1093 | smu8_ps->action = smu8_current_ps->action; |
1094 | |
1095 | if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) |
1096 | smu8_nbdpm_pstate_enable_disable(hwmgr, enable: false, lock: false); |
1097 | else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) |
1098 | smu8_nbdpm_pstate_enable_disable(hwmgr, enable: false, lock: true); |
1099 | else if (!force_high && (smu8_ps->action == FORCE_HIGH)) |
1100 | smu8_ps->action = CANCEL_FORCE_HIGH; |
1101 | else if (force_high && (smu8_ps->action != FORCE_HIGH)) |
1102 | smu8_ps->action = FORCE_HIGH; |
1103 | else |
1104 | smu8_ps->action = DO_NOTHING; |
1105 | |
1106 | return 0; |
1107 | } |
1108 | |
1109 | static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr) |
1110 | { |
1111 | int result = 0; |
1112 | struct smu8_hwmgr *data; |
1113 | |
1114 | data = kzalloc(size: sizeof(struct smu8_hwmgr), GFP_KERNEL); |
1115 | if (data == NULL) |
1116 | return -ENOMEM; |
1117 | |
1118 | hwmgr->backend = data; |
1119 | |
1120 | result = smu8_initialize_dpm_defaults(hwmgr); |
1121 | if (result != 0) { |
1122 | pr_err("smu8_initialize_dpm_defaults failed\n" ); |
1123 | return result; |
1124 | } |
1125 | |
1126 | result = smu8_get_system_info_data(hwmgr); |
1127 | if (result != 0) { |
1128 | pr_err("smu8_get_system_info_data failed\n" ); |
1129 | return result; |
1130 | } |
1131 | |
1132 | smu8_construct_boot_state(hwmgr); |
1133 | |
1134 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = SMU8_MAX_HARDWARE_POWERLEVELS; |
1135 | |
1136 | return result; |
1137 | } |
1138 | |
1139 | static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) |
1140 | { |
1141 | if (hwmgr != NULL) { |
1142 | kfree(objp: hwmgr->dyn_state.vddc_dep_on_dal_pwrl); |
1143 | hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; |
1144 | |
1145 | kfree(objp: hwmgr->backend); |
1146 | hwmgr->backend = NULL; |
1147 | } |
1148 | return 0; |
1149 | } |
1150 | |
1151 | static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) |
1152 | { |
1153 | struct smu8_hwmgr *data = hwmgr->backend; |
1154 | |
1155 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1156 | PPSMC_MSG_SetSclkSoftMin, |
1157 | parameter: smu8_get_sclk_level(hwmgr, |
1158 | clock: data->sclk_dpm.soft_max_clk, |
1159 | PPSMC_MSG_SetSclkSoftMin), |
1160 | NULL); |
1161 | |
1162 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1163 | PPSMC_MSG_SetSclkSoftMax, |
1164 | parameter: smu8_get_sclk_level(hwmgr, |
1165 | clock: data->sclk_dpm.soft_max_clk, |
1166 | PPSMC_MSG_SetSclkSoftMax), |
1167 | NULL); |
1168 | |
1169 | return 0; |
1170 | } |
1171 | |
1172 | static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) |
1173 | { |
1174 | struct smu8_hwmgr *data = hwmgr->backend; |
1175 | struct phm_clock_voltage_dependency_table *table = |
1176 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
1177 | unsigned long clock = 0, level; |
1178 | |
1179 | if (NULL == table || table->count <= 0) |
1180 | return -EINVAL; |
1181 | |
1182 | data->sclk_dpm.soft_min_clk = table->entries[0].clk; |
1183 | data->sclk_dpm.hard_min_clk = table->entries[0].clk; |
1184 | |
1185 | level = smu8_get_max_sclk_level(hwmgr) - 1; |
1186 | |
1187 | if (level < table->count) |
1188 | clock = table->entries[level].clk; |
1189 | else |
1190 | clock = table->entries[table->count - 1].clk; |
1191 | |
1192 | data->sclk_dpm.soft_max_clk = clock; |
1193 | data->sclk_dpm.hard_max_clk = clock; |
1194 | |
1195 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1196 | PPSMC_MSG_SetSclkSoftMin, |
1197 | parameter: smu8_get_sclk_level(hwmgr, |
1198 | clock: data->sclk_dpm.soft_min_clk, |
1199 | PPSMC_MSG_SetSclkSoftMin), |
1200 | NULL); |
1201 | |
1202 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1203 | PPSMC_MSG_SetSclkSoftMax, |
1204 | parameter: smu8_get_sclk_level(hwmgr, |
1205 | clock: data->sclk_dpm.soft_max_clk, |
1206 | PPSMC_MSG_SetSclkSoftMax), |
1207 | NULL); |
1208 | |
1209 | return 0; |
1210 | } |
1211 | |
1212 | static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) |
1213 | { |
1214 | struct smu8_hwmgr *data = hwmgr->backend; |
1215 | |
1216 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1217 | PPSMC_MSG_SetSclkSoftMax, |
1218 | parameter: smu8_get_sclk_level(hwmgr, |
1219 | clock: data->sclk_dpm.soft_min_clk, |
1220 | PPSMC_MSG_SetSclkSoftMax), |
1221 | NULL); |
1222 | |
1223 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1224 | PPSMC_MSG_SetSclkSoftMin, |
1225 | parameter: smu8_get_sclk_level(hwmgr, |
1226 | clock: data->sclk_dpm.soft_min_clk, |
1227 | PPSMC_MSG_SetSclkSoftMin), |
1228 | NULL); |
1229 | |
1230 | return 0; |
1231 | } |
1232 | |
1233 | static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, |
1234 | enum amd_dpm_forced_level level) |
1235 | { |
1236 | int ret = 0; |
1237 | |
1238 | switch (level) { |
1239 | case AMD_DPM_FORCED_LEVEL_HIGH: |
1240 | case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: |
1241 | ret = smu8_phm_force_dpm_highest(hwmgr); |
1242 | break; |
1243 | case AMD_DPM_FORCED_LEVEL_LOW: |
1244 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: |
1245 | case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: |
1246 | ret = smu8_phm_force_dpm_lowest(hwmgr); |
1247 | break; |
1248 | case AMD_DPM_FORCED_LEVEL_AUTO: |
1249 | ret = smu8_phm_unforce_dpm_levels(hwmgr); |
1250 | break; |
1251 | case AMD_DPM_FORCED_LEVEL_MANUAL: |
1252 | case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: |
1253 | default: |
1254 | break; |
1255 | } |
1256 | |
1257 | return ret; |
1258 | } |
1259 | |
1260 | static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) |
1261 | { |
1262 | if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) |
1263 | return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF, NULL); |
1264 | return 0; |
1265 | } |
1266 | |
1267 | static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) |
1268 | { |
1269 | if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) { |
1270 | return smum_send_msg_to_smc_with_parameter( |
1271 | hwmgr, |
1272 | PPSMC_MSG_UVDPowerON, |
1273 | PP_CAP(PHM_PlatformCaps_UVDDynamicPowerGating) ? 1 : 0, |
1274 | NULL); |
1275 | } |
1276 | |
1277 | return 0; |
1278 | } |
1279 | |
1280 | static int smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) |
1281 | { |
1282 | struct smu8_hwmgr *data = hwmgr->backend; |
1283 | struct phm_vce_clock_voltage_dependency_table *ptable = |
1284 | hwmgr->dyn_state.vce_clock_voltage_dependency_table; |
1285 | |
1286 | /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */ |
1287 | if (PP_CAP(PHM_PlatformCaps_StablePState) || |
1288 | hwmgr->en_umd_pstate) { |
1289 | data->vce_dpm.hard_min_clk = |
1290 | ptable->entries[ptable->count - 1].ecclk; |
1291 | |
1292 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1293 | PPSMC_MSG_SetEclkHardMin, |
1294 | parameter: smu8_get_eclk_level(hwmgr, |
1295 | clock: data->vce_dpm.hard_min_clk, |
1296 | PPSMC_MSG_SetEclkHardMin), |
1297 | NULL); |
1298 | } else { |
1299 | |
1300 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1301 | PPSMC_MSG_SetEclkHardMin, |
1302 | parameter: 0, |
1303 | NULL); |
1304 | /* disable ECLK DPM 0. Otherwise VCE could hang if |
1305 | * switching SCLK from DPM 0 to 6/7 */ |
1306 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1307 | PPSMC_MSG_SetEclkSoftMin, |
1308 | parameter: 1, |
1309 | NULL); |
1310 | } |
1311 | return 0; |
1312 | } |
1313 | |
1314 | static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) |
1315 | { |
1316 | if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) |
1317 | return smum_send_msg_to_smc(hwmgr, |
1318 | PPSMC_MSG_VCEPowerOFF, |
1319 | NULL); |
1320 | return 0; |
1321 | } |
1322 | |
1323 | static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr) |
1324 | { |
1325 | if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) |
1326 | return smum_send_msg_to_smc(hwmgr, |
1327 | PPSMC_MSG_VCEPowerON, |
1328 | NULL); |
1329 | return 0; |
1330 | } |
1331 | |
1332 | static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) |
1333 | { |
1334 | struct smu8_hwmgr *data = hwmgr->backend; |
1335 | |
1336 | return data->sys_info.bootup_uma_clock; |
1337 | } |
1338 | |
1339 | static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) |
1340 | { |
1341 | struct pp_power_state *ps; |
1342 | struct smu8_power_state *smu8_ps; |
1343 | |
1344 | if (hwmgr == NULL) |
1345 | return -EINVAL; |
1346 | |
1347 | ps = hwmgr->request_ps; |
1348 | |
1349 | if (ps == NULL) |
1350 | return -EINVAL; |
1351 | |
1352 | smu8_ps = cast_smu8_power_state(hw_ps: &ps->hardware); |
1353 | |
1354 | if (low) |
1355 | return smu8_ps->levels[0].engineClock; |
1356 | else |
1357 | return smu8_ps->levels[smu8_ps->level-1].engineClock; |
1358 | } |
1359 | |
1360 | static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, |
1361 | struct pp_hw_power_state *hw_ps) |
1362 | { |
1363 | struct smu8_hwmgr *data = hwmgr->backend; |
1364 | struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); |
1365 | |
1366 | smu8_ps->level = 1; |
1367 | smu8_ps->nbps_flags = 0; |
1368 | smu8_ps->bapm_flags = 0; |
1369 | smu8_ps->levels[0] = data->boot_power_level; |
1370 | |
1371 | return 0; |
1372 | } |
1373 | |
1374 | static int smu8_dpm_get_pp_table_entry_callback( |
1375 | struct pp_hwmgr *hwmgr, |
1376 | struct pp_hw_power_state *hw_ps, |
1377 | unsigned int index, |
1378 | const void *clock_info) |
1379 | { |
1380 | struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); |
1381 | |
1382 | const ATOM_PPLIB_CZ_CLOCK_INFO *smu8_clock_info = clock_info; |
1383 | |
1384 | struct phm_clock_voltage_dependency_table *table = |
1385 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
1386 | uint8_t clock_info_index = smu8_clock_info->index; |
1387 | |
1388 | if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) |
1389 | clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); |
1390 | |
1391 | smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; |
1392 | smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v; |
1393 | |
1394 | smu8_ps->level = index + 1; |
1395 | |
1396 | if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, c: PHM_PlatformCaps_SclkDeepSleep)) { |
1397 | smu8_ps->levels[index].dsDividerIndex = 5; |
1398 | smu8_ps->levels[index].ssDividerIndex = 5; |
1399 | } |
1400 | |
1401 | return 0; |
1402 | } |
1403 | |
1404 | static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) |
1405 | { |
1406 | int result; |
1407 | unsigned long ret = 0; |
1408 | |
1409 | result = pp_tables_get_num_of_entries(hwmgr, num_of_entries: &ret); |
1410 | |
1411 | return result ? 0 : ret; |
1412 | } |
1413 | |
1414 | static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, |
1415 | unsigned long entry, struct pp_power_state *ps) |
1416 | { |
1417 | int result; |
1418 | struct smu8_power_state *smu8_ps; |
1419 | |
1420 | ps->hardware.magic = smu8_magic; |
1421 | |
1422 | smu8_ps = cast_smu8_power_state(hw_ps: &(ps->hardware)); |
1423 | |
1424 | result = pp_tables_get_entry(hwmgr, entry_index: entry, ps, |
1425 | func: smu8_dpm_get_pp_table_entry_callback); |
1426 | |
1427 | smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; |
1428 | smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; |
1429 | |
1430 | return result; |
1431 | } |
1432 | |
1433 | static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr) |
1434 | { |
1435 | return sizeof(struct smu8_power_state); |
1436 | } |
1437 | |
1438 | static void smu8_hw_print_display_cfg( |
1439 | const struct cc6_settings *cc6_settings) |
1440 | { |
1441 | PP_DBG_LOG("New Display Configuration:\n" ); |
1442 | |
1443 | PP_DBG_LOG(" cpu_cc6_disable: %d\n" , |
1444 | cc6_settings->cpu_cc6_disable); |
1445 | PP_DBG_LOG(" cpu_pstate_disable: %d\n" , |
1446 | cc6_settings->cpu_pstate_disable); |
1447 | PP_DBG_LOG(" nb_pstate_switch_disable: %d\n" , |
1448 | cc6_settings->nb_pstate_switch_disable); |
1449 | PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n" , |
1450 | cc6_settings->cpu_pstate_separation_time); |
1451 | } |
1452 | |
1453 | static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr) |
1454 | { |
1455 | struct smu8_hwmgr *hw_data = hwmgr->backend; |
1456 | uint32_t data = 0; |
1457 | |
1458 | if (hw_data->cc6_settings.cc6_setting_changed) { |
1459 | |
1460 | hw_data->cc6_settings.cc6_setting_changed = false; |
1461 | |
1462 | smu8_hw_print_display_cfg(cc6_settings: &hw_data->cc6_settings); |
1463 | |
1464 | data |= (hw_data->cc6_settings.cpu_pstate_separation_time |
1465 | & PWRMGT_SEPARATION_TIME_MASK) |
1466 | << PWRMGT_SEPARATION_TIME_SHIFT; |
1467 | |
1468 | data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0) |
1469 | << PWRMGT_DISABLE_CPU_CSTATES_SHIFT; |
1470 | |
1471 | data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0) |
1472 | << PWRMGT_DISABLE_CPU_PSTATES_SHIFT; |
1473 | |
1474 | PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n" , |
1475 | data); |
1476 | |
1477 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1478 | PPSMC_MSG_SetDisplaySizePowerParams, |
1479 | parameter: data, |
1480 | NULL); |
1481 | } |
1482 | |
1483 | return 0; |
1484 | } |
1485 | |
1486 | |
1487 | static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, |
1488 | bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) |
1489 | { |
1490 | struct smu8_hwmgr *hw_data = hwmgr->backend; |
1491 | |
1492 | if (separation_time != |
1493 | hw_data->cc6_settings.cpu_pstate_separation_time || |
1494 | cc6_disable != hw_data->cc6_settings.cpu_cc6_disable || |
1495 | pstate_disable != hw_data->cc6_settings.cpu_pstate_disable || |
1496 | pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) { |
1497 | |
1498 | hw_data->cc6_settings.cc6_setting_changed = true; |
1499 | |
1500 | hw_data->cc6_settings.cpu_pstate_separation_time = |
1501 | separation_time; |
1502 | hw_data->cc6_settings.cpu_cc6_disable = |
1503 | cc6_disable; |
1504 | hw_data->cc6_settings.cpu_pstate_disable = |
1505 | pstate_disable; |
1506 | hw_data->cc6_settings.nb_pstate_switch_disable = |
1507 | pstate_switch_disable; |
1508 | |
1509 | } |
1510 | |
1511 | return 0; |
1512 | } |
1513 | |
1514 | static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr, |
1515 | struct amd_pp_simple_clock_info *info) |
1516 | { |
1517 | uint32_t i; |
1518 | const struct phm_clock_voltage_dependency_table *table = |
1519 | hwmgr->dyn_state.vddc_dep_on_dal_pwrl; |
1520 | const struct phm_clock_and_voltage_limits *limits = |
1521 | &hwmgr->dyn_state.max_clock_voltage_on_ac; |
1522 | |
1523 | info->engine_max_clock = limits->sclk; |
1524 | info->memory_max_clock = limits->mclk; |
1525 | |
1526 | for (i = table->count - 1; i > 0; i--) { |
1527 | if (limits->vddc >= table->entries[i].v) { |
1528 | info->level = table->entries[i].clk; |
1529 | return 0; |
1530 | } |
1531 | } |
1532 | return -EINVAL; |
1533 | } |
1534 | |
1535 | static int smu8_force_clock_level(struct pp_hwmgr *hwmgr, |
1536 | enum pp_clock_type type, uint32_t mask) |
1537 | { |
1538 | switch (type) { |
1539 | case PP_SCLK: |
1540 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1541 | PPSMC_MSG_SetSclkSoftMin, |
1542 | parameter: mask, |
1543 | NULL); |
1544 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1545 | PPSMC_MSG_SetSclkSoftMax, |
1546 | parameter: mask, |
1547 | NULL); |
1548 | break; |
1549 | default: |
1550 | break; |
1551 | } |
1552 | |
1553 | return 0; |
1554 | } |
1555 | |
1556 | static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, |
1557 | enum pp_clock_type type, char *buf) |
1558 | { |
1559 | struct smu8_hwmgr *data = hwmgr->backend; |
1560 | struct phm_clock_voltage_dependency_table *sclk_table = |
1561 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
1562 | uint32_t i, now; |
1563 | int size = 0; |
1564 | |
1565 | switch (type) { |
1566 | case PP_SCLK: |
1567 | now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, |
1568 | CGS_IND_REG__SMC, |
1569 | ixTARGET_AND_CURRENT_PROFILE_INDEX), |
1570 | TARGET_AND_CURRENT_PROFILE_INDEX, |
1571 | CURR_SCLK_INDEX); |
1572 | |
1573 | for (i = 0; i < sclk_table->count; i++) |
1574 | size += sprintf(buf: buf + size, fmt: "%d: %uMhz %s\n" , |
1575 | i, sclk_table->entries[i].clk / 100, |
1576 | (i == now) ? "*" : "" ); |
1577 | break; |
1578 | case PP_MCLK: |
1579 | now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, |
1580 | CGS_IND_REG__SMC, |
1581 | ixTARGET_AND_CURRENT_PROFILE_INDEX), |
1582 | TARGET_AND_CURRENT_PROFILE_INDEX, |
1583 | CURR_MCLK_INDEX); |
1584 | |
1585 | for (i = SMU8_NUM_NBPMEMORYCLOCK; i > 0; i--) |
1586 | size += sprintf(buf: buf + size, fmt: "%d: %uMhz %s\n" , |
1587 | SMU8_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100, |
1588 | (SMU8_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "" ); |
1589 | break; |
1590 | default: |
1591 | break; |
1592 | } |
1593 | return size; |
1594 | } |
1595 | |
1596 | static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, |
1597 | PHM_PerformanceLevelDesignation designation, uint32_t index, |
1598 | PHM_PerformanceLevel *level) |
1599 | { |
1600 | const struct smu8_power_state *ps; |
1601 | struct smu8_hwmgr *data; |
1602 | uint32_t level_index; |
1603 | uint32_t i; |
1604 | |
1605 | if (level == NULL || hwmgr == NULL || state == NULL) |
1606 | return -EINVAL; |
1607 | |
1608 | data = hwmgr->backend; |
1609 | ps = cast_const_smu8_power_state(hw_ps: state); |
1610 | |
1611 | level_index = index > ps->level - 1 ? ps->level - 1 : index; |
1612 | level->coreClock = ps->levels[level_index].engineClock; |
1613 | |
1614 | if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { |
1615 | for (i = 1; i < ps->level; i++) { |
1616 | if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { |
1617 | level->coreClock = ps->levels[i].engineClock; |
1618 | break; |
1619 | } |
1620 | } |
1621 | } |
1622 | |
1623 | if (level_index == 0) |
1624 | level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; |
1625 | else |
1626 | level->memory_clock = data->sys_info.nbp_memory_clock[0]; |
1627 | |
1628 | level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, voltage: ps->levels[level_index].vddcIndex) + 2) / 4; |
1629 | level->nonLocalMemoryFreq = 0; |
1630 | level->nonLocalMemoryWidth = 0; |
1631 | |
1632 | return 0; |
1633 | } |
1634 | |
1635 | static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, |
1636 | const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) |
1637 | { |
1638 | const struct smu8_power_state *ps = cast_const_smu8_power_state(hw_ps: state); |
1639 | |
1640 | clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); |
1641 | clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex)); |
1642 | |
1643 | return 0; |
1644 | } |
1645 | |
1646 | static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, |
1647 | struct amd_pp_clocks *clocks) |
1648 | { |
1649 | struct smu8_hwmgr *data = hwmgr->backend; |
1650 | int i; |
1651 | struct phm_clock_voltage_dependency_table *table; |
1652 | |
1653 | clocks->count = smu8_get_max_sclk_level(hwmgr); |
1654 | switch (type) { |
1655 | case amd_pp_disp_clock: |
1656 | for (i = 0; i < clocks->count; i++) |
1657 | clocks->clock[i] = data->sys_info.display_clock[i] * 10; |
1658 | break; |
1659 | case amd_pp_sys_clock: |
1660 | table = hwmgr->dyn_state.vddc_dependency_on_sclk; |
1661 | for (i = 0; i < clocks->count; i++) |
1662 | clocks->clock[i] = table->entries[i].clk * 10; |
1663 | break; |
1664 | case amd_pp_mem_clock: |
1665 | clocks->count = SMU8_NUM_NBPMEMORYCLOCK; |
1666 | for (i = 0; i < clocks->count; i++) |
1667 | clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10; |
1668 | break; |
1669 | default: |
1670 | return -1; |
1671 | } |
1672 | |
1673 | return 0; |
1674 | } |
1675 | |
1676 | static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) |
1677 | { |
1678 | struct phm_clock_voltage_dependency_table *table = |
1679 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
1680 | unsigned long level; |
1681 | const struct phm_clock_and_voltage_limits *limits = |
1682 | &hwmgr->dyn_state.max_clock_voltage_on_ac; |
1683 | |
1684 | if ((NULL == table) || (table->count <= 0) || (clocks == NULL)) |
1685 | return -EINVAL; |
1686 | |
1687 | level = smu8_get_max_sclk_level(hwmgr) - 1; |
1688 | |
1689 | if (level < table->count) |
1690 | clocks->engine_max_clock = table->entries[level].clk; |
1691 | else |
1692 | clocks->engine_max_clock = table->entries[table->count - 1].clk; |
1693 | |
1694 | clocks->memory_max_clock = limits->mclk; |
1695 | |
1696 | return 0; |
1697 | } |
1698 | |
1699 | static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr) |
1700 | { |
1701 | int actual_temp = 0; |
1702 | uint32_t val = cgs_read_ind_register(hwmgr->device, |
1703 | CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP); |
1704 | uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP); |
1705 | |
1706 | if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL)) |
1707 | actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; |
1708 | else |
1709 | actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; |
1710 | |
1711 | return actual_temp; |
1712 | } |
1713 | |
1714 | static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx, |
1715 | void *value, int *size) |
1716 | { |
1717 | struct smu8_hwmgr *data = hwmgr->backend; |
1718 | |
1719 | struct phm_clock_voltage_dependency_table *table = |
1720 | hwmgr->dyn_state.vddc_dependency_on_sclk; |
1721 | |
1722 | struct phm_vce_clock_voltage_dependency_table *vce_table = |
1723 | hwmgr->dyn_state.vce_clock_voltage_dependency_table; |
1724 | |
1725 | struct phm_uvd_clock_voltage_dependency_table *uvd_table = |
1726 | hwmgr->dyn_state.uvd_clock_voltage_dependency_table; |
1727 | |
1728 | uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX), |
1729 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX); |
1730 | uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), |
1731 | TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX); |
1732 | uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), |
1733 | TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX); |
1734 | |
1735 | uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; |
1736 | uint16_t vddnb, vddgfx; |
1737 | int result; |
1738 | |
1739 | /* size must be at least 4 bytes for all sensors */ |
1740 | if (*size < 4) |
1741 | return -EINVAL; |
1742 | *size = 4; |
1743 | |
1744 | switch (idx) { |
1745 | case AMDGPU_PP_SENSOR_GFX_SCLK: |
1746 | if (sclk_index < NUM_SCLK_LEVELS) { |
1747 | sclk = table->entries[sclk_index].clk; |
1748 | *((uint32_t *)value) = sclk; |
1749 | return 0; |
1750 | } |
1751 | return -EINVAL; |
1752 | case AMDGPU_PP_SENSOR_VDDNB: |
1753 | tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & |
1754 | CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT; |
1755 | vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, voltage: tmp) / 4; |
1756 | *((uint32_t *)value) = vddnb; |
1757 | return 0; |
1758 | case AMDGPU_PP_SENSOR_VDDGFX: |
1759 | tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & |
1760 | CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT; |
1761 | vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, voltage: (u16)tmp) / 4; |
1762 | *((uint32_t *)value) = vddgfx; |
1763 | return 0; |
1764 | case AMDGPU_PP_SENSOR_UVD_VCLK: |
1765 | if (!data->uvd_power_gated) { |
1766 | if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { |
1767 | return -EINVAL; |
1768 | } else { |
1769 | vclk = uvd_table->entries[uvd_index].vclk; |
1770 | *((uint32_t *)value) = vclk; |
1771 | return 0; |
1772 | } |
1773 | } |
1774 | *((uint32_t *)value) = 0; |
1775 | return 0; |
1776 | case AMDGPU_PP_SENSOR_UVD_DCLK: |
1777 | if (!data->uvd_power_gated) { |
1778 | if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { |
1779 | return -EINVAL; |
1780 | } else { |
1781 | dclk = uvd_table->entries[uvd_index].dclk; |
1782 | *((uint32_t *)value) = dclk; |
1783 | return 0; |
1784 | } |
1785 | } |
1786 | *((uint32_t *)value) = 0; |
1787 | return 0; |
1788 | case AMDGPU_PP_SENSOR_VCE_ECCLK: |
1789 | if (!data->vce_power_gated) { |
1790 | if (vce_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { |
1791 | return -EINVAL; |
1792 | } else { |
1793 | ecclk = vce_table->entries[vce_index].ecclk; |
1794 | *((uint32_t *)value) = ecclk; |
1795 | return 0; |
1796 | } |
1797 | } |
1798 | *((uint32_t *)value) = 0; |
1799 | return 0; |
1800 | case AMDGPU_PP_SENSOR_GPU_LOAD: |
1801 | result = smum_send_msg_to_smc(hwmgr, |
1802 | PPSMC_MSG_GetAverageGraphicsActivity, |
1803 | resp: &activity_percent); |
1804 | if (0 == result) |
1805 | activity_percent = activity_percent > 100 ? 100 : activity_percent; |
1806 | else |
1807 | return -EIO; |
1808 | *((uint32_t *)value) = activity_percent; |
1809 | return 0; |
1810 | case AMDGPU_PP_SENSOR_UVD_POWER: |
1811 | *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; |
1812 | return 0; |
1813 | case AMDGPU_PP_SENSOR_VCE_POWER: |
1814 | *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; |
1815 | return 0; |
1816 | case AMDGPU_PP_SENSOR_GPU_TEMP: |
1817 | *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr); |
1818 | return 0; |
1819 | default: |
1820 | return -EOPNOTSUPP; |
1821 | } |
1822 | } |
1823 | |
1824 | static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, |
1825 | uint32_t virtual_addr_low, |
1826 | uint32_t virtual_addr_hi, |
1827 | uint32_t mc_addr_low, |
1828 | uint32_t mc_addr_hi, |
1829 | uint32_t size) |
1830 | { |
1831 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1832 | PPSMC_MSG_DramAddrHiVirtual, |
1833 | parameter: mc_addr_hi, |
1834 | NULL); |
1835 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1836 | PPSMC_MSG_DramAddrLoVirtual, |
1837 | parameter: mc_addr_low, |
1838 | NULL); |
1839 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1840 | PPSMC_MSG_DramAddrHiPhysical, |
1841 | parameter: virtual_addr_hi, |
1842 | NULL); |
1843 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1844 | PPSMC_MSG_DramAddrLoPhysical, |
1845 | parameter: virtual_addr_low, |
1846 | NULL); |
1847 | |
1848 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1849 | PPSMC_MSG_DramBufferSize, |
1850 | parameter: size, |
1851 | NULL); |
1852 | return 0; |
1853 | } |
1854 | |
1855 | static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, |
1856 | struct PP_TemperatureRange *thermal_data) |
1857 | { |
1858 | struct smu8_hwmgr *data = hwmgr->backend; |
1859 | |
1860 | memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); |
1861 | |
1862 | thermal_data->max = (data->thermal_auto_throttling_treshold + |
1863 | data->sys_info.htc_hyst_lmt) * |
1864 | PP_TEMPERATURE_UNITS_PER_CENTIGRADES; |
1865 | |
1866 | return 0; |
1867 | } |
1868 | |
1869 | static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) |
1870 | { |
1871 | struct smu8_hwmgr *data = hwmgr->backend; |
1872 | uint32_t dpm_features = 0; |
1873 | |
1874 | if (enable && |
1875 | phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, |
1876 | c: PHM_PlatformCaps_UVDDPM)) { |
1877 | data->dpm_flags |= DPMFlags_UVD_Enabled; |
1878 | dpm_features |= UVD_DPM_MASK; |
1879 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1880 | PPSMC_MSG_EnableAllSmuFeatures, |
1881 | parameter: dpm_features, |
1882 | NULL); |
1883 | } else { |
1884 | dpm_features |= UVD_DPM_MASK; |
1885 | data->dpm_flags &= ~DPMFlags_UVD_Enabled; |
1886 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1887 | PPSMC_MSG_DisableAllSmuFeatures, |
1888 | parameter: dpm_features, |
1889 | NULL); |
1890 | } |
1891 | return 0; |
1892 | } |
1893 | |
1894 | static int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) |
1895 | { |
1896 | struct smu8_hwmgr *data = hwmgr->backend; |
1897 | struct phm_uvd_clock_voltage_dependency_table *ptable = |
1898 | hwmgr->dyn_state.uvd_clock_voltage_dependency_table; |
1899 | |
1900 | if (!bgate) { |
1901 | /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */ |
1902 | if (PP_CAP(PHM_PlatformCaps_StablePState) || |
1903 | hwmgr->en_umd_pstate) { |
1904 | data->uvd_dpm.hard_min_clk = |
1905 | ptable->entries[ptable->count - 1].vclk; |
1906 | |
1907 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1908 | PPSMC_MSG_SetUvdHardMin, |
1909 | parameter: smu8_get_uvd_level(hwmgr, |
1910 | clock: data->uvd_dpm.hard_min_clk, |
1911 | PPSMC_MSG_SetUvdHardMin), |
1912 | NULL); |
1913 | |
1914 | smu8_enable_disable_uvd_dpm(hwmgr, enable: true); |
1915 | } else { |
1916 | smu8_enable_disable_uvd_dpm(hwmgr, enable: true); |
1917 | } |
1918 | } else { |
1919 | smu8_enable_disable_uvd_dpm(hwmgr, enable: false); |
1920 | } |
1921 | |
1922 | return 0; |
1923 | } |
1924 | |
1925 | static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) |
1926 | { |
1927 | struct smu8_hwmgr *data = hwmgr->backend; |
1928 | uint32_t dpm_features = 0; |
1929 | |
1930 | if (enable && phm_cap_enabled( |
1931 | caps: hwmgr->platform_descriptor.platformCaps, |
1932 | c: PHM_PlatformCaps_VCEDPM)) { |
1933 | data->dpm_flags |= DPMFlags_VCE_Enabled; |
1934 | dpm_features |= VCE_DPM_MASK; |
1935 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1936 | PPSMC_MSG_EnableAllSmuFeatures, |
1937 | parameter: dpm_features, |
1938 | NULL); |
1939 | } else { |
1940 | dpm_features |= VCE_DPM_MASK; |
1941 | data->dpm_flags &= ~DPMFlags_VCE_Enabled; |
1942 | smum_send_msg_to_smc_with_parameter(hwmgr, |
1943 | PPSMC_MSG_DisableAllSmuFeatures, |
1944 | parameter: dpm_features, |
1945 | NULL); |
1946 | } |
1947 | |
1948 | return 0; |
1949 | } |
1950 | |
1951 | |
1952 | static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate) |
1953 | { |
1954 | struct smu8_hwmgr *data = hwmgr->backend; |
1955 | |
1956 | if (data->acp_power_gated == bgate) |
1957 | return; |
1958 | |
1959 | if (bgate) |
1960 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); |
1961 | else |
1962 | smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON, NULL); |
1963 | } |
1964 | |
1965 | #define WIDTH_4K 3840 |
1966 | |
1967 | static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) |
1968 | { |
1969 | struct smu8_hwmgr *data = hwmgr->backend; |
1970 | struct amdgpu_device *adev = hwmgr->adev; |
1971 | |
1972 | data->uvd_power_gated = bgate; |
1973 | |
1974 | if (bgate) { |
1975 | amdgpu_device_ip_set_powergating_state(dev: hwmgr->adev, |
1976 | block_type: AMD_IP_BLOCK_TYPE_UVD, |
1977 | state: AMD_PG_STATE_GATE); |
1978 | amdgpu_device_ip_set_clockgating_state(dev: hwmgr->adev, |
1979 | block_type: AMD_IP_BLOCK_TYPE_UVD, |
1980 | state: AMD_CG_STATE_GATE); |
1981 | smu8_dpm_update_uvd_dpm(hwmgr, bgate: true); |
1982 | smu8_dpm_powerdown_uvd(hwmgr); |
1983 | } else { |
1984 | smu8_dpm_powerup_uvd(hwmgr); |
1985 | amdgpu_device_ip_set_clockgating_state(dev: hwmgr->adev, |
1986 | block_type: AMD_IP_BLOCK_TYPE_UVD, |
1987 | state: AMD_CG_STATE_UNGATE); |
1988 | amdgpu_device_ip_set_powergating_state(dev: hwmgr->adev, |
1989 | block_type: AMD_IP_BLOCK_TYPE_UVD, |
1990 | state: AMD_PG_STATE_UNGATE); |
1991 | smu8_dpm_update_uvd_dpm(hwmgr, bgate: false); |
1992 | } |
1993 | |
1994 | /* enable/disable Low Memory PState for UVD (4k videos) */ |
1995 | if (adev->asic_type == CHIP_STONEY && |
1996 | adev->uvd.decode_image_width >= WIDTH_4K) |
1997 | smu8_nbdpm_pstate_enable_disable(hwmgr, |
1998 | enable: bgate, |
1999 | lock: true); |
2000 | } |
2001 | |
2002 | static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) |
2003 | { |
2004 | struct smu8_hwmgr *data = hwmgr->backend; |
2005 | |
2006 | if (bgate) { |
2007 | amdgpu_device_ip_set_powergating_state(dev: hwmgr->adev, |
2008 | block_type: AMD_IP_BLOCK_TYPE_VCE, |
2009 | state: AMD_PG_STATE_GATE); |
2010 | amdgpu_device_ip_set_clockgating_state(dev: hwmgr->adev, |
2011 | block_type: AMD_IP_BLOCK_TYPE_VCE, |
2012 | state: AMD_CG_STATE_GATE); |
2013 | smu8_enable_disable_vce_dpm(hwmgr, enable: false); |
2014 | smu8_dpm_powerdown_vce(hwmgr); |
2015 | data->vce_power_gated = true; |
2016 | } else { |
2017 | smu8_dpm_powerup_vce(hwmgr); |
2018 | data->vce_power_gated = false; |
2019 | amdgpu_device_ip_set_clockgating_state(dev: hwmgr->adev, |
2020 | block_type: AMD_IP_BLOCK_TYPE_VCE, |
2021 | state: AMD_CG_STATE_UNGATE); |
2022 | amdgpu_device_ip_set_powergating_state(dev: hwmgr->adev, |
2023 | block_type: AMD_IP_BLOCK_TYPE_VCE, |
2024 | state: AMD_PG_STATE_UNGATE); |
2025 | smu8_dpm_update_vce_dpm(hwmgr); |
2026 | smu8_enable_disable_vce_dpm(hwmgr, enable: true); |
2027 | } |
2028 | } |
2029 | |
2030 | static const struct pp_hwmgr_func smu8_hwmgr_funcs = { |
2031 | .backend_init = smu8_hwmgr_backend_init, |
2032 | .backend_fini = smu8_hwmgr_backend_fini, |
2033 | .apply_state_adjust_rules = smu8_apply_state_adjust_rules, |
2034 | .force_dpm_level = smu8_dpm_force_dpm_level, |
2035 | .get_power_state_size = smu8_get_power_state_size, |
2036 | .powerdown_uvd = smu8_dpm_powerdown_uvd, |
2037 | .powergate_uvd = smu8_dpm_powergate_uvd, |
2038 | .powergate_vce = smu8_dpm_powergate_vce, |
2039 | .powergate_acp = smu8_dpm_powergate_acp, |
2040 | .get_mclk = smu8_dpm_get_mclk, |
2041 | .get_sclk = smu8_dpm_get_sclk, |
2042 | .patch_boot_state = smu8_dpm_patch_boot_state, |
2043 | .get_pp_table_entry = smu8_dpm_get_pp_table_entry, |
2044 | .get_num_of_pp_table_entries = smu8_dpm_get_num_of_pp_table_entries, |
2045 | .set_cpu_power_state = smu8_set_cpu_power_state, |
2046 | .store_cc6_data = smu8_store_cc6_data, |
2047 | .force_clock_level = smu8_force_clock_level, |
2048 | .print_clock_levels = smu8_print_clock_levels, |
2049 | .get_dal_power_level = smu8_get_dal_power_level, |
2050 | .get_performance_level = smu8_get_performance_level, |
2051 | .get_current_shallow_sleep_clocks = smu8_get_current_shallow_sleep_clocks, |
2052 | .get_clock_by_type = smu8_get_clock_by_type, |
2053 | .get_max_high_clocks = smu8_get_max_high_clocks, |
2054 | .read_sensor = smu8_read_sensor, |
2055 | .power_off_asic = smu8_power_off_asic, |
2056 | .asic_setup = smu8_setup_asic_task, |
2057 | .dynamic_state_management_enable = smu8_enable_dpm_tasks, |
2058 | .power_state_set = smu8_set_power_state_tasks, |
2059 | .dynamic_state_management_disable = smu8_disable_dpm_tasks, |
2060 | .notify_cac_buffer_info = smu8_notify_cac_buffer_info, |
2061 | .get_thermal_temperature_range = smu8_get_thermal_temperature_range, |
2062 | }; |
2063 | |
2064 | int smu8_init_function_pointers(struct pp_hwmgr *hwmgr) |
2065 | { |
2066 | hwmgr->hwmgr_func = &smu8_hwmgr_funcs; |
2067 | hwmgr->pptable_func = &pptable_funcs; |
2068 | return 0; |
2069 | } |
2070 | |