1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (C) 2022, Intel Corporation. */
3
4#include "ice.h"
5#include "ice_lib.h"
6#include "ice_trace.h"
7#include <linux/dpll.h>
8
9#define ICE_CGU_STATE_ACQ_ERR_THRESHOLD 50
10#define ICE_DPLL_PIN_IDX_INVALID 0xff
11#define ICE_DPLL_RCLK_NUM_PER_PF 1
12
13/**
14 * enum ice_dpll_pin_type - enumerate ice pin types:
15 * @ICE_DPLL_PIN_INVALID: invalid pin type
16 * @ICE_DPLL_PIN_TYPE_INPUT: input pin
17 * @ICE_DPLL_PIN_TYPE_OUTPUT: output pin
18 * @ICE_DPLL_PIN_TYPE_RCLK_INPUT: recovery clock input pin
19 */
20enum ice_dpll_pin_type {
21 ICE_DPLL_PIN_INVALID,
22 ICE_DPLL_PIN_TYPE_INPUT,
23 ICE_DPLL_PIN_TYPE_OUTPUT,
24 ICE_DPLL_PIN_TYPE_RCLK_INPUT,
25};
26
27static const char * const pin_type_name[] = {
28 [ICE_DPLL_PIN_TYPE_INPUT] = "input",
29 [ICE_DPLL_PIN_TYPE_OUTPUT] = "output",
30 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
31};
32
33/**
34 * ice_dpll_is_reset - check if reset is in progress
35 * @pf: private board structure
36 * @extack: error reporting
37 *
38 * If reset is in progress, fill extack with error.
39 *
40 * Return:
41 * * false - no reset in progress
42 * * true - reset in progress
43 */
44static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack *extack)
45{
46 if (ice_is_reset_in_progress(state: pf->state)) {
47 NL_SET_ERR_MSG(extack, "PF reset in progress");
48 return true;
49 }
50 return false;
51}
52
53/**
54 * ice_dpll_pin_freq_set - set pin's frequency
55 * @pf: private board structure
56 * @pin: pointer to a pin
57 * @pin_type: type of pin being configured
58 * @freq: frequency to be set
59 * @extack: error reporting
60 *
61 * Set requested frequency on a pin.
62 *
63 * Context: Called under pf->dplls.lock
64 * Return:
65 * * 0 - success
66 * * negative - error on AQ or wrong pin type given
67 */
68static int
69ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin,
70 enum ice_dpll_pin_type pin_type, const u32 freq,
71 struct netlink_ext_ack *extack)
72{
73 u8 flags;
74 int ret;
75
76 switch (pin_type) {
77 case ICE_DPLL_PIN_TYPE_INPUT:
78 flags = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ;
79 ret = ice_aq_set_input_pin_cfg(hw: &pf->hw, input_idx: pin->idx, flags1: flags,
80 flags2: pin->flags[0], freq, phase_delay: 0);
81 break;
82 case ICE_DPLL_PIN_TYPE_OUTPUT:
83 flags = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ;
84 ret = ice_aq_set_output_pin_cfg(hw: &pf->hw, output_idx: pin->idx, flags,
85 src_sel: 0, freq, phase_delay: 0);
86 break;
87 default:
88 return -EINVAL;
89 }
90 if (ret) {
91 NL_SET_ERR_MSG_FMT(extack,
92 "err:%d %s failed to set pin freq:%u on pin:%u\n",
93 ret,
94 ice_aq_str(pf->hw.adminq.sq_last_status),
95 freq, pin->idx);
96 return ret;
97 }
98 pin->freq = freq;
99
100 return 0;
101}
102
103/**
104 * ice_dpll_frequency_set - wrapper for pin callback for set frequency
105 * @pin: pointer to a pin
106 * @pin_priv: private data pointer passed on pin registration
107 * @dpll: pointer to dpll
108 * @dpll_priv: private data pointer passed on dpll registration
109 * @frequency: frequency to be set
110 * @extack: error reporting
111 * @pin_type: type of pin being configured
112 *
113 * Wraps internal set frequency command on a pin.
114 *
115 * Context: Acquires pf->dplls.lock
116 * Return:
117 * * 0 - success
118 * * negative - error pin not found or couldn't set in hw
119 */
120static int
121ice_dpll_frequency_set(const struct dpll_pin *pin, void *pin_priv,
122 const struct dpll_device *dpll, void *dpll_priv,
123 const u32 frequency,
124 struct netlink_ext_ack *extack,
125 enum ice_dpll_pin_type pin_type)
126{
127 struct ice_dpll_pin *p = pin_priv;
128 struct ice_dpll *d = dpll_priv;
129 struct ice_pf *pf = d->pf;
130 int ret;
131
132 if (ice_dpll_is_reset(pf, extack))
133 return -EBUSY;
134
135 mutex_lock(&pf->dplls.lock);
136 ret = ice_dpll_pin_freq_set(pf, pin: p, pin_type, freq: frequency, extack);
137 mutex_unlock(lock: &pf->dplls.lock);
138
139 return ret;
140}
141
142/**
143 * ice_dpll_input_frequency_set - input pin callback for set frequency
144 * @pin: pointer to a pin
145 * @pin_priv: private data pointer passed on pin registration
146 * @dpll: pointer to dpll
147 * @dpll_priv: private data pointer passed on dpll registration
148 * @frequency: frequency to be set
149 * @extack: error reporting
150 *
151 * Wraps internal set frequency command on a pin.
152 *
153 * Context: Calls a function which acquires pf->dplls.lock
154 * Return:
155 * * 0 - success
156 * * negative - error pin not found or couldn't set in hw
157 */
158static int
159ice_dpll_input_frequency_set(const struct dpll_pin *pin, void *pin_priv,
160 const struct dpll_device *dpll, void *dpll_priv,
161 u64 frequency, struct netlink_ext_ack *extack)
162{
163 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency,
164 extack, pin_type: ICE_DPLL_PIN_TYPE_INPUT);
165}
166
167/**
168 * ice_dpll_output_frequency_set - output pin callback for set frequency
169 * @pin: pointer to a pin
170 * @pin_priv: private data pointer passed on pin registration
171 * @dpll: pointer to dpll
172 * @dpll_priv: private data pointer passed on dpll registration
173 * @frequency: frequency to be set
174 * @extack: error reporting
175 *
176 * Wraps internal set frequency command on a pin.
177 *
178 * Context: Calls a function which acquires pf->dplls.lock
179 * Return:
180 * * 0 - success
181 * * negative - error pin not found or couldn't set in hw
182 */
183static int
184ice_dpll_output_frequency_set(const struct dpll_pin *pin, void *pin_priv,
185 const struct dpll_device *dpll, void *dpll_priv,
186 u64 frequency, struct netlink_ext_ack *extack)
187{
188 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency,
189 extack, pin_type: ICE_DPLL_PIN_TYPE_OUTPUT);
190}
191
192/**
193 * ice_dpll_frequency_get - wrapper for pin callback for get frequency
194 * @pin: pointer to a pin
195 * @pin_priv: private data pointer passed on pin registration
196 * @dpll: pointer to dpll
197 * @dpll_priv: private data pointer passed on dpll registration
198 * @frequency: on success holds pin's frequency
199 * @extack: error reporting
200 * @pin_type: type of pin being configured
201 *
202 * Wraps internal get frequency command of a pin.
203 *
204 * Context: Acquires pf->dplls.lock
205 * Return:
206 * * 0 - success
207 * * negative - error pin not found or couldn't get from hw
208 */
209static int
210ice_dpll_frequency_get(const struct dpll_pin *pin, void *pin_priv,
211 const struct dpll_device *dpll, void *dpll_priv,
212 u64 *frequency, struct netlink_ext_ack *extack,
213 enum ice_dpll_pin_type pin_type)
214{
215 struct ice_dpll_pin *p = pin_priv;
216 struct ice_dpll *d = dpll_priv;
217 struct ice_pf *pf = d->pf;
218
219 mutex_lock(&pf->dplls.lock);
220 *frequency = p->freq;
221 mutex_unlock(lock: &pf->dplls.lock);
222
223 return 0;
224}
225
226/**
227 * ice_dpll_input_frequency_get - input pin callback for get frequency
228 * @pin: pointer to a pin
229 * @pin_priv: private data pointer passed on pin registration
230 * @dpll: pointer to dpll
231 * @dpll_priv: private data pointer passed on dpll registration
232 * @frequency: on success holds pin's frequency
233 * @extack: error reporting
234 *
235 * Wraps internal get frequency command of a input pin.
236 *
237 * Context: Calls a function which acquires pf->dplls.lock
238 * Return:
239 * * 0 - success
240 * * negative - error pin not found or couldn't get from hw
241 */
242static int
243ice_dpll_input_frequency_get(const struct dpll_pin *pin, void *pin_priv,
244 const struct dpll_device *dpll, void *dpll_priv,
245 u64 *frequency, struct netlink_ext_ack *extack)
246{
247 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency,
248 extack, pin_type: ICE_DPLL_PIN_TYPE_INPUT);
249}
250
251/**
252 * ice_dpll_output_frequency_get - output pin callback for get frequency
253 * @pin: pointer to a pin
254 * @pin_priv: private data pointer passed on pin registration
255 * @dpll: pointer to dpll
256 * @dpll_priv: private data pointer passed on dpll registration
257 * @frequency: on success holds pin's frequency
258 * @extack: error reporting
259 *
260 * Wraps internal get frequency command of a pin.
261 *
262 * Context: Calls a function which acquires pf->dplls.lock
263 * Return:
264 * * 0 - success
265 * * negative - error pin not found or couldn't get from hw
266 */
267static int
268ice_dpll_output_frequency_get(const struct dpll_pin *pin, void *pin_priv,
269 const struct dpll_device *dpll, void *dpll_priv,
270 u64 *frequency, struct netlink_ext_ack *extack)
271{
272 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency,
273 extack, pin_type: ICE_DPLL_PIN_TYPE_OUTPUT);
274}
275
276/**
277 * ice_dpll_pin_enable - enable a pin on dplls
278 * @hw: board private hw structure
279 * @pin: pointer to a pin
280 * @dpll_idx: dpll index to connect to output pin
281 * @pin_type: type of pin being enabled
282 * @extack: error reporting
283 *
284 * Enable a pin on both dplls. Store current state in pin->flags.
285 *
286 * Context: Called under pf->dplls.lock
287 * Return:
288 * * 0 - OK
289 * * negative - error
290 */
291static int
292ice_dpll_pin_enable(struct ice_hw *hw, struct ice_dpll_pin *pin,
293 u8 dpll_idx, enum ice_dpll_pin_type pin_type,
294 struct netlink_ext_ack *extack)
295{
296 u8 flags = 0;
297 int ret;
298
299 switch (pin_type) {
300 case ICE_DPLL_PIN_TYPE_INPUT:
301 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
302 flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
303 flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
304 ret = ice_aq_set_input_pin_cfg(hw, input_idx: pin->idx, flags1: 0, flags2: flags, freq: 0, phase_delay: 0);
305 break;
306 case ICE_DPLL_PIN_TYPE_OUTPUT:
307 flags = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL;
308 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
309 flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
310 flags |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
311 ret = ice_aq_set_output_pin_cfg(hw, output_idx: pin->idx, flags, src_sel: dpll_idx,
312 freq: 0, phase_delay: 0);
313 break;
314 default:
315 return -EINVAL;
316 }
317 if (ret)
318 NL_SET_ERR_MSG_FMT(extack,
319 "err:%d %s failed to enable %s pin:%u\n",
320 ret, ice_aq_str(hw->adminq.sq_last_status),
321 pin_type_name[pin_type], pin->idx);
322
323 return ret;
324}
325
326/**
327 * ice_dpll_pin_disable - disable a pin on dplls
328 * @hw: board private hw structure
329 * @pin: pointer to a pin
330 * @pin_type: type of pin being disabled
331 * @extack: error reporting
332 *
333 * Disable a pin on both dplls. Store current state in pin->flags.
334 *
335 * Context: Called under pf->dplls.lock
336 * Return:
337 * * 0 - OK
338 * * negative - error
339 */
340static int
341ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpll_pin *pin,
342 enum ice_dpll_pin_type pin_type,
343 struct netlink_ext_ack *extack)
344{
345 u8 flags = 0;
346 int ret;
347
348 switch (pin_type) {
349 case ICE_DPLL_PIN_TYPE_INPUT:
350 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
351 flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
352 ret = ice_aq_set_input_pin_cfg(hw, input_idx: pin->idx, flags1: 0, flags2: flags, freq: 0, phase_delay: 0);
353 break;
354 case ICE_DPLL_PIN_TYPE_OUTPUT:
355 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
356 flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
357 ret = ice_aq_set_output_pin_cfg(hw, output_idx: pin->idx, flags, src_sel: 0, freq: 0, phase_delay: 0);
358 break;
359 default:
360 return -EINVAL;
361 }
362 if (ret)
363 NL_SET_ERR_MSG_FMT(extack,
364 "err:%d %s failed to disable %s pin:%u\n",
365 ret, ice_aq_str(hw->adminq.sq_last_status),
366 pin_type_name[pin_type], pin->idx);
367
368 return ret;
369}
370
371/**
372 * ice_dpll_pin_state_update - update pin's state
373 * @pf: private board struct
374 * @pin: structure with pin attributes to be updated
375 * @pin_type: type of pin being updated
376 * @extack: error reporting
377 *
378 * Determine pin current state and frequency, then update struct
379 * holding the pin info. For input pin states are separated for each
380 * dpll, for rclk pins states are separated for each parent.
381 *
382 * Context: Called under pf->dplls.lock
383 * Return:
384 * * 0 - OK
385 * * negative - error
386 */
387static int
388ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
389 enum ice_dpll_pin_type pin_type,
390 struct netlink_ext_ack *extack)
391{
392 u8 parent, port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT;
393 int ret;
394
395 switch (pin_type) {
396 case ICE_DPLL_PIN_TYPE_INPUT:
397 ret = ice_aq_get_input_pin_cfg(hw: &pf->hw, input_idx: pin->idx, NULL, NULL,
398 NULL, flags2: &pin->flags[0],
399 freq: &pin->freq, phase_delay: &pin->phase_adjust);
400 if (ret)
401 goto err;
402 if (ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN & pin->flags[0]) {
403 if (pin->pin) {
404 pin->state[pf->dplls.eec.dpll_idx] =
405 pin->pin == pf->dplls.eec.active_input ?
406 DPLL_PIN_STATE_CONNECTED :
407 DPLL_PIN_STATE_SELECTABLE;
408 pin->state[pf->dplls.pps.dpll_idx] =
409 pin->pin == pf->dplls.pps.active_input ?
410 DPLL_PIN_STATE_CONNECTED :
411 DPLL_PIN_STATE_SELECTABLE;
412 } else {
413 pin->state[pf->dplls.eec.dpll_idx] =
414 DPLL_PIN_STATE_SELECTABLE;
415 pin->state[pf->dplls.pps.dpll_idx] =
416 DPLL_PIN_STATE_SELECTABLE;
417 }
418 } else {
419 pin->state[pf->dplls.eec.dpll_idx] =
420 DPLL_PIN_STATE_DISCONNECTED;
421 pin->state[pf->dplls.pps.dpll_idx] =
422 DPLL_PIN_STATE_DISCONNECTED;
423 }
424 break;
425 case ICE_DPLL_PIN_TYPE_OUTPUT:
426 ret = ice_aq_get_output_pin_cfg(hw: &pf->hw, output_idx: pin->idx,
427 flags: &pin->flags[0], src_sel: &parent,
428 freq: &pin->freq, NULL);
429 if (ret)
430 goto err;
431
432 parent &= ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL;
433 if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) {
434 pin->state[pf->dplls.eec.dpll_idx] =
435 parent == pf->dplls.eec.dpll_idx ?
436 DPLL_PIN_STATE_CONNECTED :
437 DPLL_PIN_STATE_DISCONNECTED;
438 pin->state[pf->dplls.pps.dpll_idx] =
439 parent == pf->dplls.pps.dpll_idx ?
440 DPLL_PIN_STATE_CONNECTED :
441 DPLL_PIN_STATE_DISCONNECTED;
442 } else {
443 pin->state[pf->dplls.eec.dpll_idx] =
444 DPLL_PIN_STATE_DISCONNECTED;
445 pin->state[pf->dplls.pps.dpll_idx] =
446 DPLL_PIN_STATE_DISCONNECTED;
447 }
448 break;
449 case ICE_DPLL_PIN_TYPE_RCLK_INPUT:
450 for (parent = 0; parent < pf->dplls.rclk.num_parents;
451 parent++) {
452 u8 p = parent;
453
454 ret = ice_aq_get_phy_rec_clk_out(hw: &pf->hw, phy_output: &p,
455 port_num: &port_num,
456 flags: &pin->flags[parent],
457 NULL);
458 if (ret)
459 goto err;
460 if (ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN &
461 pin->flags[parent])
462 pin->state[parent] = DPLL_PIN_STATE_CONNECTED;
463 else
464 pin->state[parent] =
465 DPLL_PIN_STATE_DISCONNECTED;
466 }
467 break;
468 default:
469 return -EINVAL;
470 }
471
472 return 0;
473err:
474 if (extack)
475 NL_SET_ERR_MSG_FMT(extack,
476 "err:%d %s failed to update %s pin:%u\n",
477 ret,
478 ice_aq_str(pf->hw.adminq.sq_last_status),
479 pin_type_name[pin_type], pin->idx);
480 else
481 dev_err_ratelimited(ice_pf_to_dev(pf),
482 "err:%d %s failed to update %s pin:%u\n",
483 ret,
484 ice_aq_str(pf->hw.adminq.sq_last_status),
485 pin_type_name[pin_type], pin->idx);
486 return ret;
487}
488
489/**
490 * ice_dpll_hw_input_prio_set - set input priority value in hardware
491 * @pf: board private structure
492 * @dpll: ice dpll pointer
493 * @pin: ice pin pointer
494 * @prio: priority value being set on a dpll
495 * @extack: error reporting
496 *
497 * Internal wrapper for setting the priority in the hardware.
498 *
499 * Context: Called under pf->dplls.lock
500 * Return:
501 * * 0 - success
502 * * negative - failure
503 */
504static int
505ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll,
506 struct ice_dpll_pin *pin, const u32 prio,
507 struct netlink_ext_ack *extack)
508{
509 int ret;
510
511 ret = ice_aq_set_cgu_ref_prio(hw: &pf->hw, dpll_num: dpll->dpll_idx, ref_idx: pin->idx,
512 ref_priority: (u8)prio);
513 if (ret)
514 NL_SET_ERR_MSG_FMT(extack,
515 "err:%d %s failed to set pin prio:%u on pin:%u\n",
516 ret,
517 ice_aq_str(pf->hw.adminq.sq_last_status),
518 prio, pin->idx);
519 else
520 dpll->input_prio[pin->idx] = prio;
521
522 return ret;
523}
524
525/**
526 * ice_dpll_lock_status_get - get dpll lock status callback
527 * @dpll: registered dpll pointer
528 * @dpll_priv: private data pointer passed on dpll registration
529 * @status: on success holds dpll's lock status
530 * @status_error: status error value
531 * @extack: error reporting
532 *
533 * Dpll subsystem callback, provides dpll's lock status.
534 *
535 * Context: Acquires pf->dplls.lock
536 * Return:
537 * * 0 - success
538 * * negative - failure
539 */
540static int
541ice_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv,
542 enum dpll_lock_status *status,
543 enum dpll_lock_status_error *status_error,
544 struct netlink_ext_ack *extack)
545{
546 struct ice_dpll *d = dpll_priv;
547 struct ice_pf *pf = d->pf;
548
549 mutex_lock(&pf->dplls.lock);
550 *status = d->dpll_state;
551 mutex_unlock(lock: &pf->dplls.lock);
552
553 return 0;
554}
555
556/**
557 * ice_dpll_mode_get - get dpll's working mode
558 * @dpll: registered dpll pointer
559 * @dpll_priv: private data pointer passed on dpll registration
560 * @mode: on success holds current working mode of dpll
561 * @extack: error reporting
562 *
563 * Dpll subsystem callback. Provides working mode of dpll.
564 *
565 * Context: Acquires pf->dplls.lock
566 * Return:
567 * * 0 - success
568 * * negative - failure
569 */
570static int ice_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv,
571 enum dpll_mode *mode,
572 struct netlink_ext_ack *extack)
573{
574 struct ice_dpll *d = dpll_priv;
575 struct ice_pf *pf = d->pf;
576
577 mutex_lock(&pf->dplls.lock);
578 *mode = d->mode;
579 mutex_unlock(lock: &pf->dplls.lock);
580
581 return 0;
582}
583
584/**
585 * ice_dpll_pin_state_set - set pin's state on dpll
586 * @pin: pointer to a pin
587 * @pin_priv: private data pointer passed on pin registration
588 * @dpll: registered dpll pointer
589 * @dpll_priv: private data pointer passed on dpll registration
590 * @enable: if pin shalll be enabled
591 * @extack: error reporting
592 * @pin_type: type of a pin
593 *
594 * Set pin state on a pin.
595 *
596 * Context: Acquires pf->dplls.lock
597 * Return:
598 * * 0 - OK or no change required
599 * * negative - error
600 */
601static int
602ice_dpll_pin_state_set(const struct dpll_pin *pin, void *pin_priv,
603 const struct dpll_device *dpll, void *dpll_priv,
604 bool enable, struct netlink_ext_ack *extack,
605 enum ice_dpll_pin_type pin_type)
606{
607 struct ice_dpll_pin *p = pin_priv;
608 struct ice_dpll *d = dpll_priv;
609 struct ice_pf *pf = d->pf;
610 int ret;
611
612 if (ice_dpll_is_reset(pf, extack))
613 return -EBUSY;
614
615 mutex_lock(&pf->dplls.lock);
616 if (enable)
617 ret = ice_dpll_pin_enable(hw: &pf->hw, pin: p, dpll_idx: d->dpll_idx, pin_type,
618 extack);
619 else
620 ret = ice_dpll_pin_disable(hw: &pf->hw, pin: p, pin_type, extack);
621 if (!ret)
622 ret = ice_dpll_pin_state_update(pf, pin: p, pin_type, extack);
623 mutex_unlock(lock: &pf->dplls.lock);
624
625 return ret;
626}
627
628/**
629 * ice_dpll_output_state_set - enable/disable output pin on dpll device
630 * @pin: pointer to a pin
631 * @pin_priv: private data pointer passed on pin registration
632 * @dpll: dpll being configured
633 * @dpll_priv: private data pointer passed on dpll registration
634 * @state: state of pin to be set
635 * @extack: error reporting
636 *
637 * Dpll subsystem callback. Set given state on output type pin.
638 *
639 * Context: Calls a function which acquires pf->dplls.lock
640 * Return:
641 * * 0 - successfully enabled mode
642 * * negative - failed to enable mode
643 */
644static int
645ice_dpll_output_state_set(const struct dpll_pin *pin, void *pin_priv,
646 const struct dpll_device *dpll, void *dpll_priv,
647 enum dpll_pin_state state,
648 struct netlink_ext_ack *extack)
649{
650 bool enable = state == DPLL_PIN_STATE_CONNECTED;
651 struct ice_dpll_pin *p = pin_priv;
652 struct ice_dpll *d = dpll_priv;
653
654 if (!enable && p->state[d->dpll_idx] == DPLL_PIN_STATE_DISCONNECTED)
655 return 0;
656
657 return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable,
658 extack, pin_type: ICE_DPLL_PIN_TYPE_OUTPUT);
659}
660
661/**
662 * ice_dpll_input_state_set - enable/disable input pin on dpll levice
663 * @pin: pointer to a pin
664 * @pin_priv: private data pointer passed on pin registration
665 * @dpll: dpll being configured
666 * @dpll_priv: private data pointer passed on dpll registration
667 * @state: state of pin to be set
668 * @extack: error reporting
669 *
670 * Dpll subsystem callback. Enables given mode on input type pin.
671 *
672 * Context: Calls a function which acquires pf->dplls.lock
673 * Return:
674 * * 0 - successfully enabled mode
675 * * negative - failed to enable mode
676 */
677static int
678ice_dpll_input_state_set(const struct dpll_pin *pin, void *pin_priv,
679 const struct dpll_device *dpll, void *dpll_priv,
680 enum dpll_pin_state state,
681 struct netlink_ext_ack *extack)
682{
683 bool enable = state == DPLL_PIN_STATE_SELECTABLE;
684
685 return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable,
686 extack, pin_type: ICE_DPLL_PIN_TYPE_INPUT);
687}
688
689/**
690 * ice_dpll_pin_state_get - set pin's state on dpll
691 * @pin: pointer to a pin
692 * @pin_priv: private data pointer passed on pin registration
693 * @dpll: registered dpll pointer
694 * @dpll_priv: private data pointer passed on dpll registration
695 * @state: on success holds state of the pin
696 * @extack: error reporting
697 * @pin_type: type of questioned pin
698 *
699 * Determine pin state set it on a pin.
700 *
701 * Context: Acquires pf->dplls.lock
702 * Return:
703 * * 0 - success
704 * * negative - failed to get state
705 */
706static int
707ice_dpll_pin_state_get(const struct dpll_pin *pin, void *pin_priv,
708 const struct dpll_device *dpll, void *dpll_priv,
709 enum dpll_pin_state *state,
710 struct netlink_ext_ack *extack,
711 enum ice_dpll_pin_type pin_type)
712{
713 struct ice_dpll_pin *p = pin_priv;
714 struct ice_dpll *d = dpll_priv;
715 struct ice_pf *pf = d->pf;
716 int ret;
717
718 if (ice_dpll_is_reset(pf, extack))
719 return -EBUSY;
720
721 mutex_lock(&pf->dplls.lock);
722 ret = ice_dpll_pin_state_update(pf, pin: p, pin_type, extack);
723 if (ret)
724 goto unlock;
725 if (pin_type == ICE_DPLL_PIN_TYPE_INPUT ||
726 pin_type == ICE_DPLL_PIN_TYPE_OUTPUT)
727 *state = p->state[d->dpll_idx];
728 ret = 0;
729unlock:
730 mutex_unlock(lock: &pf->dplls.lock);
731
732 return ret;
733}
734
735/**
736 * ice_dpll_output_state_get - get output pin state on dpll device
737 * @pin: pointer to a pin
738 * @pin_priv: private data pointer passed on pin registration
739 * @dpll: registered dpll pointer
740 * @dpll_priv: private data pointer passed on dpll registration
741 * @state: on success holds state of the pin
742 * @extack: error reporting
743 *
744 * Dpll subsystem callback. Check state of a pin.
745 *
746 * Context: Calls a function which acquires pf->dplls.lock
747 * Return:
748 * * 0 - success
749 * * negative - failed to get state
750 */
751static int
752ice_dpll_output_state_get(const struct dpll_pin *pin, void *pin_priv,
753 const struct dpll_device *dpll, void *dpll_priv,
754 enum dpll_pin_state *state,
755 struct netlink_ext_ack *extack)
756{
757 return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state,
758 extack, pin_type: ICE_DPLL_PIN_TYPE_OUTPUT);
759}
760
761/**
762 * ice_dpll_input_state_get - get input pin state on dpll device
763 * @pin: pointer to a pin
764 * @pin_priv: private data pointer passed on pin registration
765 * @dpll: registered dpll pointer
766 * @dpll_priv: private data pointer passed on dpll registration
767 * @state: on success holds state of the pin
768 * @extack: error reporting
769 *
770 * Dpll subsystem callback. Check state of a input pin.
771 *
772 * Context: Calls a function which acquires pf->dplls.lock
773 * Return:
774 * * 0 - success
775 * * negative - failed to get state
776 */
777static int
778ice_dpll_input_state_get(const struct dpll_pin *pin, void *pin_priv,
779 const struct dpll_device *dpll, void *dpll_priv,
780 enum dpll_pin_state *state,
781 struct netlink_ext_ack *extack)
782{
783 return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state,
784 extack, pin_type: ICE_DPLL_PIN_TYPE_INPUT);
785}
786
787/**
788 * ice_dpll_input_prio_get - get dpll's input prio
789 * @pin: pointer to a pin
790 * @pin_priv: private data pointer passed on pin registration
791 * @dpll: registered dpll pointer
792 * @dpll_priv: private data pointer passed on dpll registration
793 * @prio: on success - returns input priority on dpll
794 * @extack: error reporting
795 *
796 * Dpll subsystem callback. Handler for getting priority of a input pin.
797 *
798 * Context: Acquires pf->dplls.lock
799 * Return:
800 * * 0 - success
801 * * negative - failure
802 */
803static int
804ice_dpll_input_prio_get(const struct dpll_pin *pin, void *pin_priv,
805 const struct dpll_device *dpll, void *dpll_priv,
806 u32 *prio, struct netlink_ext_ack *extack)
807{
808 struct ice_dpll_pin *p = pin_priv;
809 struct ice_dpll *d = dpll_priv;
810 struct ice_pf *pf = d->pf;
811
812 mutex_lock(&pf->dplls.lock);
813 *prio = d->input_prio[p->idx];
814 mutex_unlock(lock: &pf->dplls.lock);
815
816 return 0;
817}
818
819/**
820 * ice_dpll_input_prio_set - set dpll input prio
821 * @pin: pointer to a pin
822 * @pin_priv: private data pointer passed on pin registration
823 * @dpll: registered dpll pointer
824 * @dpll_priv: private data pointer passed on dpll registration
825 * @prio: input priority to be set on dpll
826 * @extack: error reporting
827 *
828 * Dpll subsystem callback. Handler for setting priority of a input pin.
829 *
830 * Context: Acquires pf->dplls.lock
831 * Return:
832 * * 0 - success
833 * * negative - failure
834 */
835static int
836ice_dpll_input_prio_set(const struct dpll_pin *pin, void *pin_priv,
837 const struct dpll_device *dpll, void *dpll_priv,
838 u32 prio, struct netlink_ext_ack *extack)
839{
840 struct ice_dpll_pin *p = pin_priv;
841 struct ice_dpll *d = dpll_priv;
842 struct ice_pf *pf = d->pf;
843 int ret;
844
845 if (ice_dpll_is_reset(pf, extack))
846 return -EBUSY;
847
848 mutex_lock(&pf->dplls.lock);
849 ret = ice_dpll_hw_input_prio_set(pf, dpll: d, pin: p, prio, extack);
850 mutex_unlock(lock: &pf->dplls.lock);
851
852 return ret;
853}
854
855/**
856 * ice_dpll_input_direction - callback for get input pin direction
857 * @pin: pointer to a pin
858 * @pin_priv: private data pointer passed on pin registration
859 * @dpll: registered dpll pointer
860 * @dpll_priv: private data pointer passed on dpll registration
861 * @direction: holds input pin direction
862 * @extack: error reporting
863 *
864 * Dpll subsystem callback. Handler for getting direction of a input pin.
865 *
866 * Return:
867 * * 0 - success
868 */
869static int
870ice_dpll_input_direction(const struct dpll_pin *pin, void *pin_priv,
871 const struct dpll_device *dpll, void *dpll_priv,
872 enum dpll_pin_direction *direction,
873 struct netlink_ext_ack *extack)
874{
875 *direction = DPLL_PIN_DIRECTION_INPUT;
876
877 return 0;
878}
879
880/**
881 * ice_dpll_output_direction - callback for get output pin direction
882 * @pin: pointer to a pin
883 * @pin_priv: private data pointer passed on pin registration
884 * @dpll: registered dpll pointer
885 * @dpll_priv: private data pointer passed on dpll registration
886 * @direction: holds output pin direction
887 * @extack: error reporting
888 *
889 * Dpll subsystem callback. Handler for getting direction of an output pin.
890 *
891 * Return:
892 * * 0 - success
893 */
894static int
895ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv,
896 const struct dpll_device *dpll, void *dpll_priv,
897 enum dpll_pin_direction *direction,
898 struct netlink_ext_ack *extack)
899{
900 *direction = DPLL_PIN_DIRECTION_OUTPUT;
901
902 return 0;
903}
904
905/**
906 * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
907 * @pin: pointer to a pin
908 * @pin_priv: private data pointer passed on pin registration
909 * @dpll: registered dpll pointer
910 * @dpll_priv: private data pointer passed on dpll registration
911 * @phase_adjust: on success holds pin phase_adjust value
912 * @extack: error reporting
913 *
914 * Dpll subsystem callback. Handler for getting phase adjust value of a pin.
915 *
916 * Context: Acquires pf->dplls.lock
917 * Return:
918 * * 0 - success
919 * * negative - error
920 */
921static int
922ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv,
923 const struct dpll_device *dpll, void *dpll_priv,
924 s32 *phase_adjust,
925 struct netlink_ext_ack *extack)
926{
927 struct ice_dpll_pin *p = pin_priv;
928 struct ice_pf *pf = p->pf;
929
930 mutex_lock(&pf->dplls.lock);
931 *phase_adjust = p->phase_adjust;
932 mutex_unlock(lock: &pf->dplls.lock);
933
934 return 0;
935}
936
937/**
938 * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
939 * @pin: pointer to a pin
940 * @pin_priv: private data pointer passed on pin registration
941 * @dpll: registered dpll pointer
942 * @dpll_priv: private data pointer passed on dpll registration
943 * @phase_adjust: phase_adjust to be set
944 * @extack: error reporting
945 * @type: type of a pin
946 *
947 * Helper for dpll subsystem callback. Handler for setting phase adjust value
948 * of a pin.
949 *
950 * Context: Acquires pf->dplls.lock
951 * Return:
952 * * 0 - success
953 * * negative - error
954 */
955static int
956ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
957 const struct dpll_device *dpll, void *dpll_priv,
958 s32 phase_adjust,
959 struct netlink_ext_ack *extack,
960 enum ice_dpll_pin_type type)
961{
962 struct ice_dpll_pin *p = pin_priv;
963 struct ice_dpll *d = dpll_priv;
964 struct ice_pf *pf = d->pf;
965 u8 flag, flags_en = 0;
966 int ret;
967
968 if (ice_dpll_is_reset(pf, extack))
969 return -EBUSY;
970
971 mutex_lock(&pf->dplls.lock);
972 switch (type) {
973 case ICE_DPLL_PIN_TYPE_INPUT:
974 flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY;
975 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
976 flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
977 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
978 flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
979 ret = ice_aq_set_input_pin_cfg(hw: &pf->hw, input_idx: p->idx, flags1: flag, flags2: flags_en,
980 freq: 0, phase_delay: phase_adjust);
981 break;
982 case ICE_DPLL_PIN_TYPE_OUTPUT:
983 flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE;
984 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
985 flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
986 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
987 flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
988 ret = ice_aq_set_output_pin_cfg(hw: &pf->hw, output_idx: p->idx, flags: flag, src_sel: 0, freq: 0,
989 phase_delay: phase_adjust);
990 break;
991 default:
992 ret = -EINVAL;
993 }
994 if (!ret)
995 p->phase_adjust = phase_adjust;
996 mutex_unlock(lock: &pf->dplls.lock);
997 if (ret)
998 NL_SET_ERR_MSG_FMT(extack,
999 "err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u\n",
1000 ret,
1001 ice_aq_str(pf->hw.adminq.sq_last_status),
1002 phase_adjust, p->idx, d->dpll_idx);
1003
1004 return ret;
1005}
1006
1007/**
1008 * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
1009 * @pin: pointer to a pin
1010 * @pin_priv: private data pointer passed on pin registration
1011 * @dpll: registered dpll pointer
1012 * @dpll_priv: private data pointer passed on dpll registration
1013 * @phase_adjust: phase_adjust to be set
1014 * @extack: error reporting
1015 *
1016 * Dpll subsystem callback. Wraps a handler for setting phase adjust on input
1017 * pin.
1018 *
1019 * Context: Calls a function which acquires pf->dplls.lock
1020 * Return:
1021 * * 0 - success
1022 * * negative - error
1023 */
1024static int
1025ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
1026 const struct dpll_device *dpll, void *dpll_priv,
1027 s32 phase_adjust,
1028 struct netlink_ext_ack *extack)
1029{
1030 return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
1031 phase_adjust, extack,
1032 type: ICE_DPLL_PIN_TYPE_INPUT);
1033}
1034
1035/**
1036 * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
1037 * @pin: pointer to a pin
1038 * @pin_priv: private data pointer passed on pin registration
1039 * @dpll: registered dpll pointer
1040 * @dpll_priv: private data pointer passed on dpll registration
1041 * @phase_adjust: phase_adjust to be set
1042 * @extack: error reporting
1043 *
1044 * Dpll subsystem callback. Wraps a handler for setting phase adjust on output
1045 * pin.
1046 *
1047 * Context: Calls a function which acquires pf->dplls.lock
1048 * Return:
1049 * * 0 - success
1050 * * negative - error
1051 */
1052static int
1053ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
1054 const struct dpll_device *dpll, void *dpll_priv,
1055 s32 phase_adjust,
1056 struct netlink_ext_ack *extack)
1057{
1058 return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
1059 phase_adjust, extack,
1060 type: ICE_DPLL_PIN_TYPE_OUTPUT);
1061}
1062
1063#define ICE_DPLL_PHASE_OFFSET_DIVIDER 100
1064#define ICE_DPLL_PHASE_OFFSET_FACTOR \
1065 (DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER)
1066/**
1067 * ice_dpll_phase_offset_get - callback for get dpll phase shift value
1068 * @pin: pointer to a pin
1069 * @pin_priv: private data pointer passed on pin registration
1070 * @dpll: registered dpll pointer
1071 * @dpll_priv: private data pointer passed on dpll registration
1072 * @phase_offset: on success holds pin phase_offset value
1073 * @extack: error reporting
1074 *
1075 * Dpll subsystem callback. Handler for getting phase shift value between
1076 * dpll's input and output.
1077 *
1078 * Context: Acquires pf->dplls.lock
1079 * Return:
1080 * * 0 - success
1081 * * negative - error
1082 */
1083static int
1084ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
1085 const struct dpll_device *dpll, void *dpll_priv,
1086 s64 *phase_offset, struct netlink_ext_ack *extack)
1087{
1088 struct ice_dpll *d = dpll_priv;
1089 struct ice_pf *pf = d->pf;
1090
1091 mutex_lock(&pf->dplls.lock);
1092 if (d->active_input == pin)
1093 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
1094 else
1095 *phase_offset = 0;
1096 mutex_unlock(lock: &pf->dplls.lock);
1097
1098 return 0;
1099}
1100
1101/**
1102 * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
1103 * @pin: pointer to a pin
1104 * @pin_priv: private data pointer passed on pin registration
1105 * @parent_pin: pin parent pointer
1106 * @parent_pin_priv: parent private data pointer passed on pin registration
1107 * @state: state to be set on pin
1108 * @extack: error reporting
1109 *
1110 * Dpll subsystem callback, set a state of a rclk pin on a parent pin
1111 *
1112 * Context: Acquires pf->dplls.lock
1113 * Return:
1114 * * 0 - success
1115 * * negative - failure
1116 */
1117static int
1118ice_dpll_rclk_state_on_pin_set(const struct dpll_pin *pin, void *pin_priv,
1119 const struct dpll_pin *parent_pin,
1120 void *parent_pin_priv,
1121 enum dpll_pin_state state,
1122 struct netlink_ext_ack *extack)
1123{
1124 struct ice_dpll_pin *p = pin_priv, *parent = parent_pin_priv;
1125 bool enable = state == DPLL_PIN_STATE_CONNECTED;
1126 struct ice_pf *pf = p->pf;
1127 int ret = -EINVAL;
1128 u32 hw_idx;
1129
1130 if (ice_dpll_is_reset(pf, extack))
1131 return -EBUSY;
1132
1133 mutex_lock(&pf->dplls.lock);
1134 hw_idx = parent->idx - pf->dplls.base_rclk_idx;
1135 if (hw_idx >= pf->dplls.num_inputs)
1136 goto unlock;
1137
1138 if ((enable && p->state[hw_idx] == DPLL_PIN_STATE_CONNECTED) ||
1139 (!enable && p->state[hw_idx] == DPLL_PIN_STATE_DISCONNECTED)) {
1140 NL_SET_ERR_MSG_FMT(extack,
1141 "pin:%u state:%u on parent:%u already set",
1142 p->idx, state, parent->idx);
1143 goto unlock;
1144 }
1145 ret = ice_aq_set_phy_rec_clk_out(hw: &pf->hw, phy_output: hw_idx, enable,
1146 freq: &p->freq);
1147 if (ret)
1148 NL_SET_ERR_MSG_FMT(extack,
1149 "err:%d %s failed to set pin state:%u for pin:%u on parent:%u\n",
1150 ret,
1151 ice_aq_str(pf->hw.adminq.sq_last_status),
1152 state, p->idx, parent->idx);
1153unlock:
1154 mutex_unlock(lock: &pf->dplls.lock);
1155
1156 return ret;
1157}
1158
1159/**
1160 * ice_dpll_rclk_state_on_pin_get - get a state of rclk pin
1161 * @pin: pointer to a pin
1162 * @pin_priv: private data pointer passed on pin registration
1163 * @parent_pin: pin parent pointer
1164 * @parent_pin_priv: pin parent priv data pointer passed on pin registration
1165 * @state: on success holds pin state on parent pin
1166 * @extack: error reporting
1167 *
1168 * dpll subsystem callback, get a state of a recovered clock pin.
1169 *
1170 * Context: Acquires pf->dplls.lock
1171 * Return:
1172 * * 0 - success
1173 * * negative - failure
1174 */
1175static int
1176ice_dpll_rclk_state_on_pin_get(const struct dpll_pin *pin, void *pin_priv,
1177 const struct dpll_pin *parent_pin,
1178 void *parent_pin_priv,
1179 enum dpll_pin_state *state,
1180 struct netlink_ext_ack *extack)
1181{
1182 struct ice_dpll_pin *p = pin_priv, *parent = parent_pin_priv;
1183 struct ice_pf *pf = p->pf;
1184 int ret = -EINVAL;
1185 u32 hw_idx;
1186
1187 if (ice_dpll_is_reset(pf, extack))
1188 return -EBUSY;
1189
1190 mutex_lock(&pf->dplls.lock);
1191 hw_idx = parent->idx - pf->dplls.base_rclk_idx;
1192 if (hw_idx >= pf->dplls.num_inputs)
1193 goto unlock;
1194
1195 ret = ice_dpll_pin_state_update(pf, pin: p, pin_type: ICE_DPLL_PIN_TYPE_RCLK_INPUT,
1196 extack);
1197 if (ret)
1198 goto unlock;
1199
1200 *state = p->state[hw_idx];
1201 ret = 0;
1202unlock:
1203 mutex_unlock(lock: &pf->dplls.lock);
1204
1205 return ret;
1206}
1207
1208static const struct dpll_pin_ops ice_dpll_rclk_ops = {
1209 .state_on_pin_set = ice_dpll_rclk_state_on_pin_set,
1210 .state_on_pin_get = ice_dpll_rclk_state_on_pin_get,
1211 .direction_get = ice_dpll_input_direction,
1212};
1213
1214static const struct dpll_pin_ops ice_dpll_input_ops = {
1215 .frequency_get = ice_dpll_input_frequency_get,
1216 .frequency_set = ice_dpll_input_frequency_set,
1217 .state_on_dpll_get = ice_dpll_input_state_get,
1218 .state_on_dpll_set = ice_dpll_input_state_set,
1219 .prio_get = ice_dpll_input_prio_get,
1220 .prio_set = ice_dpll_input_prio_set,
1221 .direction_get = ice_dpll_input_direction,
1222 .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
1223 .phase_adjust_set = ice_dpll_input_phase_adjust_set,
1224 .phase_offset_get = ice_dpll_phase_offset_get,
1225};
1226
1227static const struct dpll_pin_ops ice_dpll_output_ops = {
1228 .frequency_get = ice_dpll_output_frequency_get,
1229 .frequency_set = ice_dpll_output_frequency_set,
1230 .state_on_dpll_get = ice_dpll_output_state_get,
1231 .state_on_dpll_set = ice_dpll_output_state_set,
1232 .direction_get = ice_dpll_output_direction,
1233 .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
1234 .phase_adjust_set = ice_dpll_output_phase_adjust_set,
1235};
1236
1237static const struct dpll_device_ops ice_dpll_ops = {
1238 .lock_status_get = ice_dpll_lock_status_get,
1239 .mode_get = ice_dpll_mode_get,
1240};
1241
1242/**
1243 * ice_generate_clock_id - generates unique clock_id for registering dpll.
1244 * @pf: board private structure
1245 *
1246 * Generates unique (per board) clock_id for allocation and search of dpll
1247 * devices in Linux dpll subsystem.
1248 *
1249 * Return: generated clock id for the board
1250 */
1251static u64 ice_generate_clock_id(struct ice_pf *pf)
1252{
1253 return pci_get_dsn(dev: pf->pdev);
1254}
1255
1256/**
1257 * ice_dpll_notify_changes - notify dpll subsystem about changes
1258 * @d: pointer do dpll
1259 *
1260 * Once change detected appropriate event is submitted to the dpll subsystem.
1261 */
1262static void ice_dpll_notify_changes(struct ice_dpll *d)
1263{
1264 bool pin_notified = false;
1265
1266 if (d->prev_dpll_state != d->dpll_state) {
1267 d->prev_dpll_state = d->dpll_state;
1268 dpll_device_change_ntf(dpll: d->dpll);
1269 }
1270 if (d->prev_input != d->active_input) {
1271 if (d->prev_input)
1272 dpll_pin_change_ntf(pin: d->prev_input);
1273 d->prev_input = d->active_input;
1274 if (d->active_input) {
1275 dpll_pin_change_ntf(pin: d->active_input);
1276 pin_notified = true;
1277 }
1278 }
1279 if (d->prev_phase_offset != d->phase_offset) {
1280 d->prev_phase_offset = d->phase_offset;
1281 if (!pin_notified && d->active_input)
1282 dpll_pin_change_ntf(pin: d->active_input);
1283 }
1284}
1285
1286/**
1287 * ice_dpll_update_state - update dpll state
1288 * @pf: pf private structure
1289 * @d: pointer to queried dpll device
1290 * @init: if function called on initialization of ice dpll
1291 *
1292 * Poll current state of dpll from hw and update ice_dpll struct.
1293 *
1294 * Context: Called by kworker under pf->dplls.lock
1295 * Return:
1296 * * 0 - success
1297 * * negative - AQ failure
1298 */
1299static int
1300ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
1301{
1302 struct ice_dpll_pin *p = NULL;
1303 int ret;
1304
1305 ret = ice_get_cgu_state(hw: &pf->hw, dpll_idx: d->dpll_idx, last_dpll_state: d->prev_dpll_state,
1306 pin: &d->input_idx, ref_state: &d->ref_state, eec_mode: &d->eec_mode,
1307 phase_offset: &d->phase_offset, dpll_state: &d->dpll_state);
1308
1309 dev_dbg(ice_pf_to_dev(pf),
1310 "update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n",
1311 d->dpll_idx, d->prev_input_idx, d->input_idx,
1312 d->dpll_state, d->prev_dpll_state, d->mode);
1313 if (ret) {
1314 dev_err(ice_pf_to_dev(pf),
1315 "update dpll=%d state failed, ret=%d %s\n",
1316 d->dpll_idx, ret,
1317 ice_aq_str(pf->hw.adminq.sq_last_status));
1318 return ret;
1319 }
1320 if (init) {
1321 if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED ||
1322 d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ)
1323 d->active_input = pf->dplls.inputs[d->input_idx].pin;
1324 p = &pf->dplls.inputs[d->input_idx];
1325 return ice_dpll_pin_state_update(pf, pin: p,
1326 pin_type: ICE_DPLL_PIN_TYPE_INPUT, NULL);
1327 }
1328 if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER ||
1329 d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) {
1330 d->active_input = NULL;
1331 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID)
1332 p = &pf->dplls.inputs[d->input_idx];
1333 d->prev_input_idx = ICE_DPLL_PIN_IDX_INVALID;
1334 d->input_idx = ICE_DPLL_PIN_IDX_INVALID;
1335 if (!p)
1336 return 0;
1337 ret = ice_dpll_pin_state_update(pf, pin: p,
1338 pin_type: ICE_DPLL_PIN_TYPE_INPUT, NULL);
1339 } else if (d->input_idx != d->prev_input_idx) {
1340 if (d->prev_input_idx != ICE_DPLL_PIN_IDX_INVALID) {
1341 p = &pf->dplls.inputs[d->prev_input_idx];
1342 ice_dpll_pin_state_update(pf, pin: p,
1343 pin_type: ICE_DPLL_PIN_TYPE_INPUT,
1344 NULL);
1345 }
1346 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) {
1347 p = &pf->dplls.inputs[d->input_idx];
1348 d->active_input = p->pin;
1349 ice_dpll_pin_state_update(pf, pin: p,
1350 pin_type: ICE_DPLL_PIN_TYPE_INPUT,
1351 NULL);
1352 }
1353 d->prev_input_idx = d->input_idx;
1354 }
1355
1356 return ret;
1357}
1358
1359/**
1360 * ice_dpll_periodic_work - DPLLs periodic worker
1361 * @work: pointer to kthread_work structure
1362 *
1363 * DPLLs periodic worker is responsible for polling state of dpll.
1364 * Context: Holds pf->dplls.lock
1365 */
1366static void ice_dpll_periodic_work(struct kthread_work *work)
1367{
1368 struct ice_dplls *d = container_of(work, struct ice_dplls, work.work);
1369 struct ice_pf *pf = container_of(d, struct ice_pf, dplls);
1370 struct ice_dpll *de = &pf->dplls.eec;
1371 struct ice_dpll *dp = &pf->dplls.pps;
1372 int ret = 0;
1373
1374 if (ice_is_reset_in_progress(state: pf->state))
1375 goto resched;
1376 mutex_lock(&pf->dplls.lock);
1377 ret = ice_dpll_update_state(pf, d: de, init: false);
1378 if (!ret)
1379 ret = ice_dpll_update_state(pf, d: dp, init: false);
1380 if (ret) {
1381 d->cgu_state_acq_err_num++;
1382 /* stop rescheduling this worker */
1383 if (d->cgu_state_acq_err_num >
1384 ICE_CGU_STATE_ACQ_ERR_THRESHOLD) {
1385 dev_err(ice_pf_to_dev(pf),
1386 "EEC/PPS DPLLs periodic work disabled\n");
1387 mutex_unlock(lock: &pf->dplls.lock);
1388 return;
1389 }
1390 }
1391 mutex_unlock(lock: &pf->dplls.lock);
1392 ice_dpll_notify_changes(d: de);
1393 ice_dpll_notify_changes(d: dp);
1394
1395resched:
1396 /* Run twice a second or reschedule if update failed */
1397 kthread_queue_delayed_work(worker: d->kworker, dwork: &d->work,
1398 delay: ret ? msecs_to_jiffies(m: 10) :
1399 msecs_to_jiffies(m: 500));
1400}
1401
1402/**
1403 * ice_dpll_release_pins - release pins resources from dpll subsystem
1404 * @pins: pointer to pins array
1405 * @count: number of pins
1406 *
1407 * Release resources of given pins array in the dpll subsystem.
1408 */
1409static void ice_dpll_release_pins(struct ice_dpll_pin *pins, int count)
1410{
1411 int i;
1412
1413 for (i = 0; i < count; i++)
1414 dpll_pin_put(pin: pins[i].pin);
1415}
1416
1417/**
1418 * ice_dpll_get_pins - get pins from dpll subsystem
1419 * @pf: board private structure
1420 * @pins: pointer to pins array
1421 * @start_idx: get starts from this pin idx value
1422 * @count: number of pins
1423 * @clock_id: clock_id of dpll device
1424 *
1425 * Get pins - allocate - in dpll subsystem, store them in pin field of given
1426 * pins array.
1427 *
1428 * Return:
1429 * * 0 - success
1430 * * negative - allocation failure reason
1431 */
1432static int
1433ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins,
1434 int start_idx, int count, u64 clock_id)
1435{
1436 int i, ret;
1437
1438 for (i = 0; i < count; i++) {
1439 pins[i].pin = dpll_pin_get(clock_id, dev_driver_id: i + start_idx, THIS_MODULE,
1440 prop: &pins[i].prop);
1441 if (IS_ERR(ptr: pins[i].pin)) {
1442 ret = PTR_ERR(ptr: pins[i].pin);
1443 goto release_pins;
1444 }
1445 }
1446
1447 return 0;
1448
1449release_pins:
1450 while (--i >= 0)
1451 dpll_pin_put(pin: pins[i].pin);
1452 return ret;
1453}
1454
1455/**
1456 * ice_dpll_unregister_pins - unregister pins from a dpll
1457 * @dpll: dpll device pointer
1458 * @pins: pointer to pins array
1459 * @ops: callback ops registered with the pins
1460 * @count: number of pins
1461 *
1462 * Unregister pins of a given array of pins from given dpll device registered in
1463 * dpll subsystem.
1464 */
1465static void
1466ice_dpll_unregister_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins,
1467 const struct dpll_pin_ops *ops, int count)
1468{
1469 int i;
1470
1471 for (i = 0; i < count; i++)
1472 dpll_pin_unregister(dpll, pin: pins[i].pin, ops, priv: &pins[i]);
1473}
1474
1475/**
1476 * ice_dpll_register_pins - register pins with a dpll
1477 * @dpll: dpll pointer to register pins with
1478 * @pins: pointer to pins array
1479 * @ops: callback ops registered with the pins
1480 * @count: number of pins
1481 *
1482 * Register pins of a given array with given dpll in dpll subsystem.
1483 *
1484 * Return:
1485 * * 0 - success
1486 * * negative - registration failure reason
1487 */
1488static int
1489ice_dpll_register_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins,
1490 const struct dpll_pin_ops *ops, int count)
1491{
1492 int ret, i;
1493
1494 for (i = 0; i < count; i++) {
1495 ret = dpll_pin_register(dpll, pin: pins[i].pin, ops, priv: &pins[i]);
1496 if (ret)
1497 goto unregister_pins;
1498 }
1499
1500 return 0;
1501
1502unregister_pins:
1503 while (--i >= 0)
1504 dpll_pin_unregister(dpll, pin: pins[i].pin, ops, priv: &pins[i]);
1505 return ret;
1506}
1507
1508/**
1509 * ice_dpll_deinit_direct_pins - deinitialize direct pins
1510 * @cgu: if cgu is present and controlled by this NIC
1511 * @pins: pointer to pins array
1512 * @count: number of pins
1513 * @ops: callback ops registered with the pins
1514 * @first: dpll device pointer
1515 * @second: dpll device pointer
1516 *
1517 * If cgu is owned unregister pins from given dplls.
1518 * Release pins resources to the dpll subsystem.
1519 */
1520static void
1521ice_dpll_deinit_direct_pins(bool cgu, struct ice_dpll_pin *pins, int count,
1522 const struct dpll_pin_ops *ops,
1523 struct dpll_device *first,
1524 struct dpll_device *second)
1525{
1526 if (cgu) {
1527 ice_dpll_unregister_pins(dpll: first, pins, ops, count);
1528 ice_dpll_unregister_pins(dpll: second, pins, ops, count);
1529 }
1530 ice_dpll_release_pins(pins, count);
1531}
1532
1533/**
1534 * ice_dpll_init_direct_pins - initialize direct pins
1535 * @pf: board private structure
1536 * @cgu: if cgu is present and controlled by this NIC
1537 * @pins: pointer to pins array
1538 * @start_idx: on which index shall allocation start in dpll subsystem
1539 * @count: number of pins
1540 * @ops: callback ops registered with the pins
1541 * @first: dpll device pointer
1542 * @second: dpll device pointer
1543 *
1544 * Allocate directly connected pins of a given array in dpll subsystem.
1545 * If cgu is owned register allocated pins with given dplls.
1546 *
1547 * Return:
1548 * * 0 - success
1549 * * negative - registration failure reason
1550 */
1551static int
1552ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu,
1553 struct ice_dpll_pin *pins, int start_idx, int count,
1554 const struct dpll_pin_ops *ops,
1555 struct dpll_device *first, struct dpll_device *second)
1556{
1557 int ret;
1558
1559 ret = ice_dpll_get_pins(pf, pins, start_idx, count, clock_id: pf->dplls.clock_id);
1560 if (ret)
1561 return ret;
1562 if (cgu) {
1563 ret = ice_dpll_register_pins(dpll: first, pins, ops, count);
1564 if (ret)
1565 goto release_pins;
1566 ret = ice_dpll_register_pins(dpll: second, pins, ops, count);
1567 if (ret)
1568 goto unregister_first;
1569 }
1570
1571 return 0;
1572
1573unregister_first:
1574 ice_dpll_unregister_pins(dpll: first, pins, ops, count);
1575release_pins:
1576 ice_dpll_release_pins(pins, count);
1577 return ret;
1578}
1579
1580/**
1581 * ice_dpll_deinit_rclk_pin - release rclk pin resources
1582 * @pf: board private structure
1583 *
1584 * Deregister rclk pin from parent pins and release resources in dpll subsystem.
1585 */
1586static void ice_dpll_deinit_rclk_pin(struct ice_pf *pf)
1587{
1588 struct ice_dpll_pin *rclk = &pf->dplls.rclk;
1589 struct ice_vsi *vsi = ice_get_main_vsi(pf);
1590 struct dpll_pin *parent;
1591 int i;
1592
1593 for (i = 0; i < rclk->num_parents; i++) {
1594 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin;
1595 if (!parent)
1596 continue;
1597 dpll_pin_on_pin_unregister(parent, pin: rclk->pin,
1598 ops: &ice_dpll_rclk_ops, priv: rclk);
1599 }
1600 if (WARN_ON_ONCE(!vsi || !vsi->netdev))
1601 return;
1602 dpll_netdev_pin_clear(dev: vsi->netdev);
1603 dpll_pin_put(pin: rclk->pin);
1604}
1605
1606/**
1607 * ice_dpll_init_rclk_pins - initialize recovered clock pin
1608 * @pf: board private structure
1609 * @pin: pin to register
1610 * @start_idx: on which index shall allocation start in dpll subsystem
1611 * @ops: callback ops registered with the pins
1612 *
1613 * Allocate resource for recovered clock pin in dpll subsystem. Register the
1614 * pin with the parents it has in the info. Register pin with the pf's main vsi
1615 * netdev.
1616 *
1617 * Return:
1618 * * 0 - success
1619 * * negative - registration failure reason
1620 */
1621static int
1622ice_dpll_init_rclk_pins(struct ice_pf *pf, struct ice_dpll_pin *pin,
1623 int start_idx, const struct dpll_pin_ops *ops)
1624{
1625 struct ice_vsi *vsi = ice_get_main_vsi(pf);
1626 struct dpll_pin *parent;
1627 int ret, i;
1628
1629 ret = ice_dpll_get_pins(pf, pins: pin, start_idx, ICE_DPLL_RCLK_NUM_PER_PF,
1630 clock_id: pf->dplls.clock_id);
1631 if (ret)
1632 return ret;
1633 for (i = 0; i < pf->dplls.rclk.num_parents; i++) {
1634 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin;
1635 if (!parent) {
1636 ret = -ENODEV;
1637 goto unregister_pins;
1638 }
1639 ret = dpll_pin_on_pin_register(parent, pin: pf->dplls.rclk.pin,
1640 ops, priv: &pf->dplls.rclk);
1641 if (ret)
1642 goto unregister_pins;
1643 }
1644 if (WARN_ON((!vsi || !vsi->netdev)))
1645 return -EINVAL;
1646 dpll_netdev_pin_set(dev: vsi->netdev, dpll_pin: pf->dplls.rclk.pin);
1647
1648 return 0;
1649
1650unregister_pins:
1651 while (i) {
1652 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin;
1653 dpll_pin_on_pin_unregister(parent, pin: pf->dplls.rclk.pin,
1654 ops: &ice_dpll_rclk_ops, priv: &pf->dplls.rclk);
1655 }
1656 ice_dpll_release_pins(pins: pin, ICE_DPLL_RCLK_NUM_PER_PF);
1657 return ret;
1658}
1659
1660/**
1661 * ice_dpll_deinit_pins - deinitialize direct pins
1662 * @pf: board private structure
1663 * @cgu: if cgu is controlled by this pf
1664 *
1665 * If cgu is owned unregister directly connected pins from the dplls.
1666 * Release resources of directly connected pins from the dpll subsystem.
1667 */
1668static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu)
1669{
1670 struct ice_dpll_pin *outputs = pf->dplls.outputs;
1671 struct ice_dpll_pin *inputs = pf->dplls.inputs;
1672 int num_outputs = pf->dplls.num_outputs;
1673 int num_inputs = pf->dplls.num_inputs;
1674 struct ice_dplls *d = &pf->dplls;
1675 struct ice_dpll *de = &d->eec;
1676 struct ice_dpll *dp = &d->pps;
1677
1678 ice_dpll_deinit_rclk_pin(pf);
1679 if (cgu) {
1680 ice_dpll_unregister_pins(dpll: dp->dpll, pins: inputs, ops: &ice_dpll_input_ops,
1681 count: num_inputs);
1682 ice_dpll_unregister_pins(dpll: de->dpll, pins: inputs, ops: &ice_dpll_input_ops,
1683 count: num_inputs);
1684 }
1685 ice_dpll_release_pins(pins: inputs, count: num_inputs);
1686 if (cgu) {
1687 ice_dpll_unregister_pins(dpll: dp->dpll, pins: outputs,
1688 ops: &ice_dpll_output_ops, count: num_outputs);
1689 ice_dpll_unregister_pins(dpll: de->dpll, pins: outputs,
1690 ops: &ice_dpll_output_ops, count: num_outputs);
1691 ice_dpll_release_pins(pins: outputs, count: num_outputs);
1692 }
1693}
1694
1695/**
1696 * ice_dpll_init_pins - init pins and register pins with a dplls
1697 * @pf: board private structure
1698 * @cgu: if cgu is present and controlled by this NIC
1699 *
1700 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll
1701 * subsystem.
1702 *
1703 * Return:
1704 * * 0 - success
1705 * * negative - initialization failure reason
1706 */
1707static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu)
1708{
1709 u32 rclk_idx;
1710 int ret;
1711
1712 ret = ice_dpll_init_direct_pins(pf, cgu, pins: pf->dplls.inputs, start_idx: 0,
1713 count: pf->dplls.num_inputs,
1714 ops: &ice_dpll_input_ops,
1715 first: pf->dplls.eec.dpll, second: pf->dplls.pps.dpll);
1716 if (ret)
1717 return ret;
1718 if (cgu) {
1719 ret = ice_dpll_init_direct_pins(pf, cgu, pins: pf->dplls.outputs,
1720 start_idx: pf->dplls.num_inputs,
1721 count: pf->dplls.num_outputs,
1722 ops: &ice_dpll_output_ops,
1723 first: pf->dplls.eec.dpll,
1724 second: pf->dplls.pps.dpll);
1725 if (ret)
1726 goto deinit_inputs;
1727 }
1728 rclk_idx = pf->dplls.num_inputs + pf->dplls.num_outputs + pf->hw.pf_id;
1729 ret = ice_dpll_init_rclk_pins(pf, pin: &pf->dplls.rclk, start_idx: rclk_idx,
1730 ops: &ice_dpll_rclk_ops);
1731 if (ret)
1732 goto deinit_outputs;
1733
1734 return 0;
1735deinit_outputs:
1736 ice_dpll_deinit_direct_pins(cgu, pins: pf->dplls.outputs,
1737 count: pf->dplls.num_outputs,
1738 ops: &ice_dpll_output_ops, first: pf->dplls.pps.dpll,
1739 second: pf->dplls.eec.dpll);
1740deinit_inputs:
1741 ice_dpll_deinit_direct_pins(cgu, pins: pf->dplls.inputs, count: pf->dplls.num_inputs,
1742 ops: &ice_dpll_input_ops, first: pf->dplls.pps.dpll,
1743 second: pf->dplls.eec.dpll);
1744 return ret;
1745}
1746
1747/**
1748 * ice_dpll_deinit_dpll - deinitialize dpll device
1749 * @pf: board private structure
1750 * @d: pointer to ice_dpll
1751 * @cgu: if cgu is present and controlled by this NIC
1752 *
1753 * If cgu is owned unregister the dpll from dpll subsystem.
1754 * Release resources of dpll device from dpll subsystem.
1755 */
1756static void
1757ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu)
1758{
1759 if (cgu)
1760 dpll_device_unregister(dpll: d->dpll, ops: &ice_dpll_ops, priv: d);
1761 dpll_device_put(dpll: d->dpll);
1762}
1763
1764/**
1765 * ice_dpll_init_dpll - initialize dpll device in dpll subsystem
1766 * @pf: board private structure
1767 * @d: dpll to be initialized
1768 * @cgu: if cgu is present and controlled by this NIC
1769 * @type: type of dpll being initialized
1770 *
1771 * Allocate dpll instance for this board in dpll subsystem, if cgu is controlled
1772 * by this NIC, register dpll with the callback ops.
1773 *
1774 * Return:
1775 * * 0 - success
1776 * * negative - initialization failure reason
1777 */
1778static int
1779ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu,
1780 enum dpll_type type)
1781{
1782 u64 clock_id = pf->dplls.clock_id;
1783 int ret;
1784
1785 d->dpll = dpll_device_get(clock_id, dev_driver_id: d->dpll_idx, THIS_MODULE);
1786 if (IS_ERR(ptr: d->dpll)) {
1787 ret = PTR_ERR(ptr: d->dpll);
1788 dev_err(ice_pf_to_dev(pf),
1789 "dpll_device_get failed (%p) err=%d\n", d, ret);
1790 return ret;
1791 }
1792 d->pf = pf;
1793 if (cgu) {
1794 ice_dpll_update_state(pf, d, init: true);
1795 ret = dpll_device_register(dpll: d->dpll, type, ops: &ice_dpll_ops, priv: d);
1796 if (ret) {
1797 dpll_device_put(dpll: d->dpll);
1798 return ret;
1799 }
1800 }
1801
1802 return 0;
1803}
1804
1805/**
1806 * ice_dpll_deinit_worker - deinitialize dpll kworker
1807 * @pf: board private structure
1808 *
1809 * Stop dpll's kworker, release it's resources.
1810 */
1811static void ice_dpll_deinit_worker(struct ice_pf *pf)
1812{
1813 struct ice_dplls *d = &pf->dplls;
1814
1815 kthread_cancel_delayed_work_sync(work: &d->work);
1816 kthread_destroy_worker(worker: d->kworker);
1817}
1818
1819/**
1820 * ice_dpll_init_worker - Initialize DPLLs periodic worker
1821 * @pf: board private structure
1822 *
1823 * Create and start DPLLs periodic worker.
1824 *
1825 * Context: Shall be called after pf->dplls.lock is initialized.
1826 * Return:
1827 * * 0 - success
1828 * * negative - create worker failure
1829 */
1830static int ice_dpll_init_worker(struct ice_pf *pf)
1831{
1832 struct ice_dplls *d = &pf->dplls;
1833 struct kthread_worker *kworker;
1834
1835 kthread_init_delayed_work(&d->work, ice_dpll_periodic_work);
1836 kworker = kthread_create_worker(flags: 0, namefmt: "ice-dplls-%s",
1837 dev_name(ice_pf_to_dev(pf)));
1838 if (IS_ERR(ptr: kworker))
1839 return PTR_ERR(ptr: kworker);
1840 d->kworker = kworker;
1841 d->cgu_state_acq_err_num = 0;
1842 kthread_queue_delayed_work(worker: d->kworker, dwork: &d->work, delay: 0);
1843
1844 return 0;
1845}
1846
1847/**
1848 * ice_dpll_init_info_direct_pins - initializes direct pins info
1849 * @pf: board private structure
1850 * @pin_type: type of pins being initialized
1851 *
1852 * Init information for directly connected pins, cache them in pf's pins
1853 * structures.
1854 *
1855 * Return:
1856 * * 0 - success
1857 * * negative - init failure reason
1858 */
1859static int
1860ice_dpll_init_info_direct_pins(struct ice_pf *pf,
1861 enum ice_dpll_pin_type pin_type)
1862{
1863 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps;
1864 int num_pins, i, ret = -EINVAL;
1865 struct ice_hw *hw = &pf->hw;
1866 struct ice_dpll_pin *pins;
1867 unsigned long caps;
1868 u8 freq_supp_num;
1869 bool input;
1870
1871 switch (pin_type) {
1872 case ICE_DPLL_PIN_TYPE_INPUT:
1873 pins = pf->dplls.inputs;
1874 num_pins = pf->dplls.num_inputs;
1875 input = true;
1876 break;
1877 case ICE_DPLL_PIN_TYPE_OUTPUT:
1878 pins = pf->dplls.outputs;
1879 num_pins = pf->dplls.num_outputs;
1880 input = false;
1881 break;
1882 default:
1883 return -EINVAL;
1884 }
1885
1886 for (i = 0; i < num_pins; i++) {
1887 caps = 0;
1888 pins[i].idx = i;
1889 pins[i].prop.board_label = ice_cgu_get_pin_name(hw, pin: i, input);
1890 pins[i].prop.type = ice_cgu_get_pin_type(hw, pin: i, input);
1891 if (input) {
1892 ret = ice_aq_get_cgu_ref_prio(hw, dpll_num: de->dpll_idx, ref_idx: i,
1893 ref_prio: &de->input_prio[i]);
1894 if (ret)
1895 return ret;
1896 ret = ice_aq_get_cgu_ref_prio(hw, dpll_num: dp->dpll_idx, ref_idx: i,
1897 ref_prio: &dp->input_prio[i]);
1898 if (ret)
1899 return ret;
1900 caps |= (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE |
1901 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE);
1902 pins[i].prop.phase_range.min =
1903 pf->dplls.input_phase_adj_max;
1904 pins[i].prop.phase_range.max =
1905 -pf->dplls.input_phase_adj_max;
1906 } else {
1907 pins[i].prop.phase_range.min =
1908 pf->dplls.output_phase_adj_max;
1909 pins[i].prop.phase_range.max =
1910 -pf->dplls.output_phase_adj_max;
1911 ret = ice_cgu_get_output_pin_state_caps(hw, pin_id: i, caps: &caps);
1912 if (ret)
1913 return ret;
1914 }
1915 pins[i].prop.capabilities = caps;
1916 ret = ice_dpll_pin_state_update(pf, pin: &pins[i], pin_type, NULL);
1917 if (ret)
1918 return ret;
1919 pins[i].prop.freq_supported =
1920 ice_cgu_get_pin_freq_supp(hw, pin: i, input, num: &freq_supp_num);
1921 pins[i].prop.freq_supported_num = freq_supp_num;
1922 pins[i].pf = pf;
1923 }
1924
1925 return ret;
1926}
1927
1928/**
1929 * ice_dpll_init_info_rclk_pin - initializes rclk pin information
1930 * @pf: board private structure
1931 *
1932 * Init information for rclk pin, cache them in pf->dplls.rclk.
1933 *
1934 * Return:
1935 * * 0 - success
1936 * * negative - init failure reason
1937 */
1938static int ice_dpll_init_info_rclk_pin(struct ice_pf *pf)
1939{
1940 struct ice_dpll_pin *pin = &pf->dplls.rclk;
1941
1942 pin->prop.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT;
1943 pin->prop.capabilities |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
1944 pin->pf = pf;
1945
1946 return ice_dpll_pin_state_update(pf, pin,
1947 pin_type: ICE_DPLL_PIN_TYPE_RCLK_INPUT, NULL);
1948}
1949
1950/**
1951 * ice_dpll_init_pins_info - init pins info wrapper
1952 * @pf: board private structure
1953 * @pin_type: type of pins being initialized
1954 *
1955 * Wraps functions for pin initialization.
1956 *
1957 * Return:
1958 * * 0 - success
1959 * * negative - init failure reason
1960 */
1961static int
1962ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_dpll_pin_type pin_type)
1963{
1964 switch (pin_type) {
1965 case ICE_DPLL_PIN_TYPE_INPUT:
1966 case ICE_DPLL_PIN_TYPE_OUTPUT:
1967 return ice_dpll_init_info_direct_pins(pf, pin_type);
1968 case ICE_DPLL_PIN_TYPE_RCLK_INPUT:
1969 return ice_dpll_init_info_rclk_pin(pf);
1970 default:
1971 return -EINVAL;
1972 }
1973}
1974
1975/**
1976 * ice_dpll_deinit_info - release memory allocated for pins info
1977 * @pf: board private structure
1978 *
1979 * Release memory allocated for pins by ice_dpll_init_info function.
1980 */
1981static void ice_dpll_deinit_info(struct ice_pf *pf)
1982{
1983 kfree(objp: pf->dplls.inputs);
1984 kfree(objp: pf->dplls.outputs);
1985 kfree(objp: pf->dplls.eec.input_prio);
1986 kfree(objp: pf->dplls.pps.input_prio);
1987}
1988
1989/**
1990 * ice_dpll_init_info - prepare pf's dpll information structure
1991 * @pf: board private structure
1992 * @cgu: if cgu is present and controlled by this NIC
1993 *
1994 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
1995 *
1996 * Return:
1997 * * 0 - success
1998 * * negative - init failure reason
1999 */
2000static int ice_dpll_init_info(struct ice_pf *pf, bool cgu)
2001{
2002 struct ice_aqc_get_cgu_abilities abilities;
2003 struct ice_dpll *de = &pf->dplls.eec;
2004 struct ice_dpll *dp = &pf->dplls.pps;
2005 struct ice_dplls *d = &pf->dplls;
2006 struct ice_hw *hw = &pf->hw;
2007 int ret, alloc_size, i;
2008
2009 d->clock_id = ice_generate_clock_id(pf);
2010 ret = ice_aq_get_cgu_abilities(hw, abilities: &abilities);
2011 if (ret) {
2012 dev_err(ice_pf_to_dev(pf),
2013 "err:%d %s failed to read cgu abilities\n",
2014 ret, ice_aq_str(hw->adminq.sq_last_status));
2015 return ret;
2016 }
2017
2018 de->dpll_idx = abilities.eec_dpll_idx;
2019 dp->dpll_idx = abilities.pps_dpll_idx;
2020 d->num_inputs = abilities.num_inputs;
2021 d->num_outputs = abilities.num_outputs;
2022 d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj);
2023 d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj);
2024
2025 alloc_size = sizeof(*d->inputs) * d->num_inputs;
2026 d->inputs = kzalloc(size: alloc_size, GFP_KERNEL);
2027 if (!d->inputs)
2028 return -ENOMEM;
2029
2030 alloc_size = sizeof(*de->input_prio) * d->num_inputs;
2031 de->input_prio = kzalloc(size: alloc_size, GFP_KERNEL);
2032 if (!de->input_prio)
2033 return -ENOMEM;
2034
2035 dp->input_prio = kzalloc(size: alloc_size, GFP_KERNEL);
2036 if (!dp->input_prio)
2037 return -ENOMEM;
2038
2039 ret = ice_dpll_init_pins_info(pf, pin_type: ICE_DPLL_PIN_TYPE_INPUT);
2040 if (ret)
2041 goto deinit_info;
2042
2043 if (cgu) {
2044 alloc_size = sizeof(*d->outputs) * d->num_outputs;
2045 d->outputs = kzalloc(size: alloc_size, GFP_KERNEL);
2046 if (!d->outputs) {
2047 ret = -ENOMEM;
2048 goto deinit_info;
2049 }
2050
2051 ret = ice_dpll_init_pins_info(pf, pin_type: ICE_DPLL_PIN_TYPE_OUTPUT);
2052 if (ret)
2053 goto deinit_info;
2054 }
2055
2056 ret = ice_get_cgu_rclk_pin_info(hw: &pf->hw, base_idx: &d->base_rclk_idx,
2057 pin_num: &pf->dplls.rclk.num_parents);
2058 if (ret)
2059 return ret;
2060 for (i = 0; i < pf->dplls.rclk.num_parents; i++)
2061 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i;
2062 ret = ice_dpll_init_pins_info(pf, pin_type: ICE_DPLL_PIN_TYPE_RCLK_INPUT);
2063 if (ret)
2064 return ret;
2065 de->mode = DPLL_MODE_AUTOMATIC;
2066 dp->mode = DPLL_MODE_AUTOMATIC;
2067
2068 dev_dbg(ice_pf_to_dev(pf),
2069 "%s - success, inputs:%u, outputs:%u rclk-parents:%u\n",
2070 __func__, d->num_inputs, d->num_outputs, d->rclk.num_parents);
2071
2072 return 0;
2073
2074deinit_info:
2075 dev_err(ice_pf_to_dev(pf),
2076 "%s - fail: d->inputs:%p, de->input_prio:%p, dp->input_prio:%p, d->outputs:%p\n",
2077 __func__, d->inputs, de->input_prio,
2078 dp->input_prio, d->outputs);
2079 ice_dpll_deinit_info(pf);
2080 return ret;
2081}
2082
2083/**
2084 * ice_dpll_deinit - Disable the driver/HW support for dpll subsystem
2085 * the dpll device.
2086 * @pf: board private structure
2087 *
2088 * Handles the cleanup work required after dpll initialization, freeing
2089 * resources and unregistering the dpll, pin and all resources used for
2090 * handling them.
2091 *
2092 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
2093 */
2094void ice_dpll_deinit(struct ice_pf *pf)
2095{
2096 bool cgu = ice_is_feature_supported(pf, f: ICE_F_CGU);
2097
2098 clear_bit(nr: ICE_FLAG_DPLL, addr: pf->flags);
2099 if (cgu)
2100 ice_dpll_deinit_worker(pf);
2101
2102 ice_dpll_deinit_pins(pf, cgu);
2103 ice_dpll_deinit_dpll(pf, d: &pf->dplls.pps, cgu);
2104 ice_dpll_deinit_dpll(pf, d: &pf->dplls.eec, cgu);
2105 ice_dpll_deinit_info(pf);
2106 mutex_destroy(lock: &pf->dplls.lock);
2107}
2108
2109/**
2110 * ice_dpll_init - initialize support for dpll subsystem
2111 * @pf: board private structure
2112 *
2113 * Set up the device dplls, register them and pins connected within Linux dpll
2114 * subsystem. Allow userspace to obtain state of DPLL and handling of DPLL
2115 * configuration requests.
2116 *
2117 * Context: Initializes pf->dplls.lock mutex.
2118 */
2119void ice_dpll_init(struct ice_pf *pf)
2120{
2121 bool cgu = ice_is_feature_supported(pf, f: ICE_F_CGU);
2122 struct ice_dplls *d = &pf->dplls;
2123 int err = 0;
2124
2125 mutex_init(&d->lock);
2126 err = ice_dpll_init_info(pf, cgu);
2127 if (err)
2128 goto err_exit;
2129 err = ice_dpll_init_dpll(pf, d: &pf->dplls.eec, cgu, type: DPLL_TYPE_EEC);
2130 if (err)
2131 goto deinit_info;
2132 err = ice_dpll_init_dpll(pf, d: &pf->dplls.pps, cgu, type: DPLL_TYPE_PPS);
2133 if (err)
2134 goto deinit_eec;
2135 err = ice_dpll_init_pins(pf, cgu);
2136 if (err)
2137 goto deinit_pps;
2138 if (cgu) {
2139 err = ice_dpll_init_worker(pf);
2140 if (err)
2141 goto deinit_pins;
2142 }
2143 set_bit(nr: ICE_FLAG_DPLL, addr: pf->flags);
2144
2145 return;
2146
2147deinit_pins:
2148 ice_dpll_deinit_pins(pf, cgu);
2149deinit_pps:
2150 ice_dpll_deinit_dpll(pf, d: &pf->dplls.pps, cgu);
2151deinit_eec:
2152 ice_dpll_deinit_dpll(pf, d: &pf->dplls.eec, cgu);
2153deinit_info:
2154 ice_dpll_deinit_info(pf);
2155err_exit:
2156 mutex_destroy(lock: &d->lock);
2157 dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err);
2158}
2159

source code of linux/drivers/net/ethernet/intel/ice/ice_dpll.c