1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
2 | /* Copyright(c) 2020-2022 Realtek Corporation |
3 | */ |
4 | |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> |
7 | |
8 | #include "pci.h" |
9 | #include "reg.h" |
10 | #include "rtw8852c.h" |
11 | |
12 | static const struct rtw89_pci_bd_idx_addr rtw8852c_bd_idx_addr_low_power = { |
13 | .tx_bd_addrs = {R_AX_DRV_FW_HSK_0, R_AX_DRV_FW_HSK_1, R_AX_DRV_FW_HSK_2, |
14 | R_AX_DRV_FW_HSK_3, 0, 0, |
15 | 0, 0, R_AX_DRV_FW_HSK_4, |
16 | 0, 0, 0, |
17 | R_AX_DRV_FW_HSK_5}, |
18 | .rx_bd_addrs = {R_AX_DRV_FW_HSK_6, R_AX_DRV_FW_HSK_7}, |
19 | }; |
20 | |
21 | static const struct rtw89_pci_info rtw8852c_pci_info = { |
22 | .gen_def = &rtw89_pci_gen_ax, |
23 | .txbd_trunc_mode = MAC_AX_BD_TRUNC, |
24 | .rxbd_trunc_mode = MAC_AX_BD_TRUNC, |
25 | .rxbd_mode = MAC_AX_RXBD_PKT, |
26 | .tag_mode = MAC_AX_TAG_MULTI, |
27 | .tx_burst = MAC_AX_TX_BURST_V1_256B, |
28 | .rx_burst = MAC_AX_RX_BURST_V1_128B, |
29 | .wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS, |
30 | .wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS, |
31 | .multi_tag_num = MAC_AX_TAG_NUM_8, |
32 | .lbc_en = MAC_AX_PCIE_ENABLE, |
33 | .lbc_tmr = MAC_AX_LBC_TMR_2MS, |
34 | .autok_en = MAC_AX_PCIE_DISABLE, |
35 | .io_rcy_en = MAC_AX_PCIE_ENABLE, |
36 | .io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_6MS, |
37 | .rx_ring_eq_is_full = false, |
38 | .check_rx_tag = false, |
39 | |
40 | .init_cfg_reg = R_AX_HAXI_INIT_CFG1, |
41 | .txhci_en_bit = B_AX_TXHCI_EN_V1, |
42 | .rxhci_en_bit = B_AX_RXHCI_EN_V1, |
43 | .rxbd_mode_bit = B_AX_RXBD_MODE_V1, |
44 | .exp_ctrl_reg = R_AX_HAXI_EXP_CTRL, |
45 | .max_tag_num_mask = B_AX_MAX_TAG_NUM_V1_MASK, |
46 | .rxbd_rwptr_clr_reg = R_AX_RXBD_RWPTR_CLR_V1, |
47 | .txbd_rwptr_clr2_reg = R_AX_TXBD_RWPTR_CLR2_V1, |
48 | .dma_io_stop = {R_AX_HAXI_INIT_CFG1, B_AX_STOP_AXI_MST}, |
49 | .dma_stop1 = {R_AX_HAXI_DMA_STOP1, B_AX_TX_STOP1_MASK}, |
50 | .dma_stop2 = {R_AX_HAXI_DMA_STOP2, B_AX_TX_STOP2_ALL}, |
51 | .dma_busy1 = {R_AX_HAXI_DMA_BUSY1, DMA_BUSY1_CHECK}, |
52 | .dma_busy2_reg = R_AX_HAXI_DMA_BUSY2, |
53 | .dma_busy3_reg = R_AX_HAXI_DMA_BUSY3, |
54 | |
55 | .rpwm_addr = R_AX_PCIE_HRPWM_V1, |
56 | .cpwm_addr = R_AX_PCIE_CRPWM, |
57 | .mit_addr = R_AX_INT_MIT_RX_V1, |
58 | .tx_dma_ch_mask = 0, |
59 | .bd_idx_addr_low_power = &rtw8852c_bd_idx_addr_low_power, |
60 | .dma_addr_set = &rtw89_pci_ch_dma_addr_set_v1, |
61 | .bd_ram_table = &rtw89_bd_ram_table_dual, |
62 | |
63 | .ltr_set = rtw89_pci_ltr_set_v1, |
64 | .fill_txaddr_info = rtw89_pci_fill_txaddr_info_v1, |
65 | .config_intr_mask = rtw89_pci_config_intr_mask_v1, |
66 | .enable_intr = rtw89_pci_enable_intr_v1, |
67 | .disable_intr = rtw89_pci_disable_intr_v1, |
68 | .recognize_intrs = rtw89_pci_recognize_intrs_v1, |
69 | }; |
70 | |
71 | static const struct rtw89_driver_info rtw89_8852ce_info = { |
72 | .chip = &rtw8852c_chip_info, |
73 | .bus = { |
74 | .pci = &rtw8852c_pci_info, |
75 | }, |
76 | }; |
77 | |
78 | static const struct pci_device_id rtw89_8852ce_id_table[] = { |
79 | { |
80 | PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xc852), |
81 | .driver_data = (kernel_ulong_t)&rtw89_8852ce_info, |
82 | }, |
83 | {}, |
84 | }; |
85 | MODULE_DEVICE_TABLE(pci, rtw89_8852ce_id_table); |
86 | |
87 | static struct pci_driver rtw89_8852ce_driver = { |
88 | .name = "rtw89_8852ce" , |
89 | .id_table = rtw89_8852ce_id_table, |
90 | .probe = rtw89_pci_probe, |
91 | .remove = rtw89_pci_remove, |
92 | .driver.pm = &rtw89_pm_ops, |
93 | }; |
94 | module_pci_driver(rtw89_8852ce_driver); |
95 | |
96 | MODULE_AUTHOR("Realtek Corporation" ); |
97 | MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852CE driver" ); |
98 | MODULE_LICENSE("Dual BSD/GPL" ); |
99 | |