1//===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This declares the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
16#define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
17
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/SelectionDAGNodes.h"
21
22namespace llvm {
23
24class MachineInstrBuilder;
25class MCInstrDesc;
26class SDDbgLabel;
27class SDDbgValue;
28class SDDbgOperand;
29class TargetLowering;
30class TargetMachine;
31
32class LLVM_LIBRARY_VISIBILITY InstrEmitter {
33 MachineFunction *MF;
34 MachineRegisterInfo *MRI;
35 const TargetInstrInfo *TII;
36 const TargetRegisterInfo *TRI;
37 const TargetLowering *TLI;
38
39 MachineBasicBlock *MBB;
40 MachineBasicBlock::iterator InsertPos;
41
42 /// Should we try to produce DBG_INSTR_REF instructions?
43 bool EmitDebugInstrRefs;
44
45 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
46 /// implicit physical register output.
47 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
48 Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap);
49
50 void CreateVirtualRegisters(SDNode *Node,
51 MachineInstrBuilder &MIB,
52 const MCInstrDesc &II,
53 bool IsClone, bool IsCloned,
54 DenseMap<SDValue, Register> &VRBaseMap);
55
56 /// getVR - Return the virtual register corresponding to the specified result
57 /// of the specified node.
58 Register getVR(SDValue Op,
59 DenseMap<SDValue, Register> &VRBaseMap);
60
61 /// AddRegisterOperand - Add the specified register as an operand to the
62 /// specified machine instr. Insert register copies if the register is
63 /// not in the required register class.
64 void AddRegisterOperand(MachineInstrBuilder &MIB,
65 SDValue Op,
66 unsigned IIOpNum,
67 const MCInstrDesc *II,
68 DenseMap<SDValue, Register> &VRBaseMap,
69 bool IsDebug, bool IsClone, bool IsCloned);
70
71 /// AddOperand - Add the specified operand to the specified machine instr. II
72 /// specifies the instruction information for the node, and IIOpNum is the
73 /// operand number (in the II) that we are adding. IIOpNum and II are used for
74 /// assertions only.
75 void AddOperand(MachineInstrBuilder &MIB,
76 SDValue Op,
77 unsigned IIOpNum,
78 const MCInstrDesc *II,
79 DenseMap<SDValue, Register> &VRBaseMap,
80 bool IsDebug, bool IsClone, bool IsCloned);
81
82 /// ConstrainForSubReg - Try to constrain VReg to a register class that
83 /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
84 /// Return the virtual register to use.
85 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
86 bool isDivergent, const DebugLoc &DL);
87
88 /// EmitSubregNode - Generate machine code for subreg nodes.
89 ///
90 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
91 bool IsClone, bool IsCloned);
92
93 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
94 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
95 /// register is constrained to be in a particular register class.
96 ///
97 void EmitCopyToRegClassNode(SDNode *Node,
98 DenseMap<SDValue, Register> &VRBaseMap);
99
100 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
101 ///
102 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
103 bool IsClone, bool IsCloned);
104public:
105 /// CountResults - The results of target nodes have register or immediate
106 /// operands first, then an optional chain, and optional flag operands
107 /// (which do not go into the machine instrs.)
108 static unsigned CountResults(SDNode *Node);
109
110 void AddDbgValueLocationOps(MachineInstrBuilder &MIB,
111 const MCInstrDesc &DbgValDesc,
112 ArrayRef<SDDbgOperand> Locations,
113 DenseMap<SDValue, Register> &VRBaseMap);
114
115 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
116 ///
117 MachineInstr *EmitDbgValue(SDDbgValue *SD,
118 DenseMap<SDValue, Register> &VRBaseMap);
119
120 /// Emit a dbg_value as a DBG_INSTR_REF. May produce DBG_VALUE $noreg instead
121 /// if there is no variable location; alternately a half-formed DBG_INSTR_REF
122 /// that refers to a virtual register and is corrected later in isel.
123 MachineInstr *EmitDbgInstrRef(SDDbgValue *SD,
124 DenseMap<SDValue, Register> &VRBaseMap);
125
126 /// Emit a DBG_VALUE $noreg, indicating a variable has no location.
127 MachineInstr *EmitDbgNoLocation(SDDbgValue *SD);
128
129 /// Emit a DBG_VALUE_LIST from the operands to SDDbgValue.
130 MachineInstr *EmitDbgValueList(SDDbgValue *SD,
131 DenseMap<SDValue, Register> &VRBaseMap);
132
133 /// Emit a DBG_VALUE from the operands to SDDbgValue.
134 MachineInstr *EmitDbgValueFromSingleOp(SDDbgValue *SD,
135 DenseMap<SDValue, Register> &VRBaseMap);
136
137 /// Generate machine instruction for a dbg_label node.
138 MachineInstr *EmitDbgLabel(SDDbgLabel *SD);
139
140 /// EmitNode - Generate machine code for a node and needed dependencies.
141 ///
142 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
143 DenseMap<SDValue, Register> &VRBaseMap) {
144 if (Node->isMachineOpcode())
145 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap);
146 else
147 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
148 }
149
150 /// getBlock - Return the current basic block.
151 MachineBasicBlock *getBlock() { return MBB; }
152
153 /// getInsertPos - Return the current insertion position.
154 MachineBasicBlock::iterator getInsertPos() { return InsertPos; }
155
156 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
157 /// at the given position in the given block.
158 InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
159 MachineBasicBlock::iterator insertpos);
160
161private:
162 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
163 DenseMap<SDValue, Register> &VRBaseMap);
164 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
165 DenseMap<SDValue, Register> &VRBaseMap);
166};
167} // namespace llvm
168
169#endif
170

source code of llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h