1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/pci.h>
41#include <linux/mc146818rtc.h>
42#include <linux/compiler.h>
43#include <linux/acpi.h>
44#include <linux/export.h>
45#include <linux/syscore_ops.h>
46#include <linux/freezer.h>
47#include <linux/kthread.h>
48#include <linux/jiffies.h> /* time_after() */
49#include <linux/slab.h>
50#include <linux/memblock.h>
51
52#include <asm/irqdomain.h>
53#include <asm/io.h>
54#include <asm/smp.h>
55#include <asm/cpu.h>
56#include <asm/desc.h>
57#include <asm/proto.h>
58#include <asm/acpi.h>
59#include <asm/dma.h>
60#include <asm/timer.h>
61#include <asm/i8259.h>
62#include <asm/setup.h>
63#include <asm/irq_remapping.h>
64#include <asm/hw_irq.h>
65
66#include <asm/apic.h>
67
68#define for_each_ioapic(idx) \
69 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
70#define for_each_ioapic_reverse(idx) \
71 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
72#define for_each_pin(idx, pin) \
73 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
74#define for_each_ioapic_pin(idx, pin) \
75 for_each_ioapic((idx)) \
76 for_each_pin((idx), (pin))
77#define for_each_irq_pin(entry, head) \
78 list_for_each_entry(entry, &head, list)
79
80static DEFINE_RAW_SPINLOCK(ioapic_lock);
81static DEFINE_MUTEX(ioapic_mutex);
82static unsigned int ioapic_dynirq_base;
83static int ioapic_initialized;
84
85struct irq_pin_list {
86 struct list_head list;
87 int apic, pin;
88};
89
90struct mp_chip_data {
91 struct list_head irq_2_pin;
92 struct IO_APIC_route_entry entry;
93 int trigger;
94 int polarity;
95 u32 count;
96 bool isa_irq;
97};
98
99struct mp_ioapic_gsi {
100 u32 gsi_base;
101 u32 gsi_end;
102};
103
104static struct ioapic {
105 /*
106 * # of IRQ routing registers
107 */
108 int nr_registers;
109 /*
110 * Saved state during suspend/resume, or while enabling intr-remap.
111 */
112 struct IO_APIC_route_entry *saved_registers;
113 /* I/O APIC config */
114 struct mpc_ioapic mp_config;
115 /* IO APIC gsi routing info */
116 struct mp_ioapic_gsi gsi_config;
117 struct ioapic_domain_cfg irqdomain_cfg;
118 struct irq_domain *irqdomain;
119 struct resource *iomem_res;
120} ioapics[MAX_IO_APICS];
121
122#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
123
124int mpc_ioapic_id(int ioapic_idx)
125{
126 return ioapics[ioapic_idx].mp_config.apicid;
127}
128
129unsigned int mpc_ioapic_addr(int ioapic_idx)
130{
131 return ioapics[ioapic_idx].mp_config.apicaddr;
132}
133
134static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
135{
136 return &ioapics[ioapic_idx].gsi_config;
137}
138
139static inline int mp_ioapic_pin_count(int ioapic)
140{
141 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
142
143 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
144}
145
146static inline u32 mp_pin_to_gsi(int ioapic, int pin)
147{
148 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
149}
150
151static inline bool mp_is_legacy_irq(int irq)
152{
153 return irq >= 0 && irq < nr_legacy_irqs();
154}
155
156/*
157 * Initialize all legacy IRQs and all pins on the first IOAPIC
158 * if we have legacy interrupt controller. Kernel boot option "pirq="
159 * may rely on non-legacy pins on the first IOAPIC.
160 */
161static inline int mp_init_irq_at_boot(int ioapic, int irq)
162{
163 if (!nr_legacy_irqs())
164 return 0;
165
166 return ioapic == 0 || mp_is_legacy_irq(irq);
167}
168
169static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
170{
171 return ioapics[ioapic].irqdomain;
172}
173
174int nr_ioapics;
175
176/* The one past the highest gsi number used */
177u32 gsi_top;
178
179/* MP IRQ source entries */
180struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
181
182/* # of MP IRQ source entries */
183int mp_irq_entries;
184
185#ifdef CONFIG_EISA
186int mp_bus_id_to_type[MAX_MP_BUSSES];
187#endif
188
189DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
190
191int skip_ioapic_setup;
192
193/**
194 * disable_ioapic_support() - disables ioapic support at runtime
195 */
196void disable_ioapic_support(void)
197{
198#ifdef CONFIG_PCI
199 noioapicquirk = 1;
200 noioapicreroute = -1;
201#endif
202 skip_ioapic_setup = 1;
203}
204
205static int __init parse_noapic(char *str)
206{
207 /* disable IO-APIC */
208 disable_ioapic_support();
209 return 0;
210}
211early_param("noapic", parse_noapic);
212
213/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
214void mp_save_irq(struct mpc_intsrc *m)
215{
216 int i;
217
218 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
219 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
220 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
221 m->srcbusirq, m->dstapic, m->dstirq);
222
223 for (i = 0; i < mp_irq_entries; i++) {
224 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
225 return;
226 }
227
228 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
229 if (++mp_irq_entries == MAX_IRQ_SOURCES)
230 panic("Max # of irq sources exceeded!!\n");
231}
232
233static void alloc_ioapic_saved_registers(int idx)
234{
235 size_t size;
236
237 if (ioapics[idx].saved_registers)
238 return;
239
240 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
241 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
242 if (!ioapics[idx].saved_registers)
243 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
244}
245
246static void free_ioapic_saved_registers(int idx)
247{
248 kfree(ioapics[idx].saved_registers);
249 ioapics[idx].saved_registers = NULL;
250}
251
252int __init arch_early_ioapic_init(void)
253{
254 int i;
255
256 if (!nr_legacy_irqs())
257 io_apic_irqs = ~0UL;
258
259 for_each_ioapic(i)
260 alloc_ioapic_saved_registers(i);
261
262 return 0;
263}
264
265struct io_apic {
266 unsigned int index;
267 unsigned int unused[3];
268 unsigned int data;
269 unsigned int unused2[11];
270 unsigned int eoi;
271};
272
273static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
274{
275 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
276 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
277}
278
279static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
280{
281 struct io_apic __iomem *io_apic = io_apic_base(apic);
282 writel(vector, &io_apic->eoi);
283}
284
285unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
286{
287 struct io_apic __iomem *io_apic = io_apic_base(apic);
288 writel(reg, &io_apic->index);
289 return readl(&io_apic->data);
290}
291
292static void io_apic_write(unsigned int apic, unsigned int reg,
293 unsigned int value)
294{
295 struct io_apic __iomem *io_apic = io_apic_base(apic);
296
297 writel(reg, &io_apic->index);
298 writel(value, &io_apic->data);
299}
300
301union entry_union {
302 struct { u32 w1, w2; };
303 struct IO_APIC_route_entry entry;
304};
305
306static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
307{
308 union entry_union eu;
309
310 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
311 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
312
313 return eu.entry;
314}
315
316static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
317{
318 union entry_union eu;
319 unsigned long flags;
320
321 raw_spin_lock_irqsave(&ioapic_lock, flags);
322 eu.entry = __ioapic_read_entry(apic, pin);
323 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
324
325 return eu.entry;
326}
327
328/*
329 * When we write a new IO APIC routing entry, we need to write the high
330 * word first! If the mask bit in the low word is clear, we will enable
331 * the interrupt, and we need to make sure the entry is fully populated
332 * before that happens.
333 */
334static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
335{
336 union entry_union eu = {{0, 0}};
337
338 eu.entry = e;
339 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
340 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
341}
342
343static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
344{
345 unsigned long flags;
346
347 raw_spin_lock_irqsave(&ioapic_lock, flags);
348 __ioapic_write_entry(apic, pin, e);
349 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
350}
351
352/*
353 * When we mask an IO APIC routing entry, we need to write the low
354 * word first, in order to set the mask bit before we change the
355 * high bits!
356 */
357static void ioapic_mask_entry(int apic, int pin)
358{
359 unsigned long flags;
360 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
361
362 raw_spin_lock_irqsave(&ioapic_lock, flags);
363 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
364 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
365 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
366}
367
368/*
369 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
370 * shared ISA-space IRQs, so we have to support them. We are super
371 * fast in the common case, and fast for shared ISA-space IRQs.
372 */
373static int __add_pin_to_irq_node(struct mp_chip_data *data,
374 int node, int apic, int pin)
375{
376 struct irq_pin_list *entry;
377
378 /* don't allow duplicates */
379 for_each_irq_pin(entry, data->irq_2_pin)
380 if (entry->apic == apic && entry->pin == pin)
381 return 0;
382
383 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
384 if (!entry) {
385 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
386 node, apic, pin);
387 return -ENOMEM;
388 }
389 entry->apic = apic;
390 entry->pin = pin;
391 list_add_tail(&entry->list, &data->irq_2_pin);
392
393 return 0;
394}
395
396static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
397{
398 struct irq_pin_list *tmp, *entry;
399
400 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
401 if (entry->apic == apic && entry->pin == pin) {
402 list_del(&entry->list);
403 kfree(entry);
404 return;
405 }
406}
407
408static void add_pin_to_irq_node(struct mp_chip_data *data,
409 int node, int apic, int pin)
410{
411 if (__add_pin_to_irq_node(data, node, apic, pin))
412 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
413}
414
415/*
416 * Reroute an IRQ to a different pin.
417 */
418static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
419 int oldapic, int oldpin,
420 int newapic, int newpin)
421{
422 struct irq_pin_list *entry;
423
424 for_each_irq_pin(entry, data->irq_2_pin) {
425 if (entry->apic == oldapic && entry->pin == oldpin) {
426 entry->apic = newapic;
427 entry->pin = newpin;
428 /* every one is different, right? */
429 return;
430 }
431 }
432
433 /* old apic/pin didn't exist, so just add new ones */
434 add_pin_to_irq_node(data, node, newapic, newpin);
435}
436
437static void io_apic_modify_irq(struct mp_chip_data *data,
438 int mask_and, int mask_or,
439 void (*final)(struct irq_pin_list *entry))
440{
441 union entry_union eu;
442 struct irq_pin_list *entry;
443
444 eu.entry = data->entry;
445 eu.w1 &= mask_and;
446 eu.w1 |= mask_or;
447 data->entry = eu.entry;
448
449 for_each_irq_pin(entry, data->irq_2_pin) {
450 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
451 if (final)
452 final(entry);
453 }
454}
455
456static void io_apic_sync(struct irq_pin_list *entry)
457{
458 /*
459 * Synchronize the IO-APIC and the CPU by doing
460 * a dummy read from the IO-APIC
461 */
462 struct io_apic __iomem *io_apic;
463
464 io_apic = io_apic_base(entry->apic);
465 readl(&io_apic->data);
466}
467
468static void mask_ioapic_irq(struct irq_data *irq_data)
469{
470 struct mp_chip_data *data = irq_data->chip_data;
471 unsigned long flags;
472
473 raw_spin_lock_irqsave(&ioapic_lock, flags);
474 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
475 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
476}
477
478static void __unmask_ioapic(struct mp_chip_data *data)
479{
480 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
481}
482
483static void unmask_ioapic_irq(struct irq_data *irq_data)
484{
485 struct mp_chip_data *data = irq_data->chip_data;
486 unsigned long flags;
487
488 raw_spin_lock_irqsave(&ioapic_lock, flags);
489 __unmask_ioapic(data);
490 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
491}
492
493/*
494 * IO-APIC versions below 0x20 don't support EOI register.
495 * For the record, here is the information about various versions:
496 * 0Xh 82489DX
497 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
498 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
499 * 30h-FFh Reserved
500 *
501 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
502 * version as 0x2. This is an error with documentation and these ICH chips
503 * use io-apic's of version 0x20.
504 *
505 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
506 * Otherwise, we simulate the EOI message manually by changing the trigger
507 * mode to edge and then back to level, with RTE being masked during this.
508 */
509static void __eoi_ioapic_pin(int apic, int pin, int vector)
510{
511 if (mpc_ioapic_ver(apic) >= 0x20) {
512 io_apic_eoi(apic, vector);
513 } else {
514 struct IO_APIC_route_entry entry, entry1;
515
516 entry = entry1 = __ioapic_read_entry(apic, pin);
517
518 /*
519 * Mask the entry and change the trigger mode to edge.
520 */
521 entry1.mask = IOAPIC_MASKED;
522 entry1.trigger = IOAPIC_EDGE;
523
524 __ioapic_write_entry(apic, pin, entry1);
525
526 /*
527 * Restore the previous level triggered entry.
528 */
529 __ioapic_write_entry(apic, pin, entry);
530 }
531}
532
533static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
534{
535 unsigned long flags;
536 struct irq_pin_list *entry;
537
538 raw_spin_lock_irqsave(&ioapic_lock, flags);
539 for_each_irq_pin(entry, data->irq_2_pin)
540 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
541 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
542}
543
544static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
545{
546 struct IO_APIC_route_entry entry;
547
548 /* Check delivery_mode to be sure we're not clearing an SMI pin */
549 entry = ioapic_read_entry(apic, pin);
550 if (entry.delivery_mode == dest_SMI)
551 return;
552
553 /*
554 * Make sure the entry is masked and re-read the contents to check
555 * if it is a level triggered pin and if the remote-IRR is set.
556 */
557 if (entry.mask == IOAPIC_UNMASKED) {
558 entry.mask = IOAPIC_MASKED;
559 ioapic_write_entry(apic, pin, entry);
560 entry = ioapic_read_entry(apic, pin);
561 }
562
563 if (entry.irr) {
564 unsigned long flags;
565
566 /*
567 * Make sure the trigger mode is set to level. Explicit EOI
568 * doesn't clear the remote-IRR if the trigger mode is not
569 * set to level.
570 */
571 if (entry.trigger == IOAPIC_EDGE) {
572 entry.trigger = IOAPIC_LEVEL;
573 ioapic_write_entry(apic, pin, entry);
574 }
575 raw_spin_lock_irqsave(&ioapic_lock, flags);
576 __eoi_ioapic_pin(apic, pin, entry.vector);
577 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
578 }
579
580 /*
581 * Clear the rest of the bits in the IO-APIC RTE except for the mask
582 * bit.
583 */
584 ioapic_mask_entry(apic, pin);
585 entry = ioapic_read_entry(apic, pin);
586 if (entry.irr)
587 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
588 mpc_ioapic_id(apic), pin);
589}
590
591void clear_IO_APIC (void)
592{
593 int apic, pin;
594
595 for_each_ioapic_pin(apic, pin)
596 clear_IO_APIC_pin(apic, pin);
597}
598
599#ifdef CONFIG_X86_32
600/*
601 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
602 * specific CPU-side IRQs.
603 */
604
605#define MAX_PIRQS 8
606static int pirq_entries[MAX_PIRQS] = {
607 [0 ... MAX_PIRQS - 1] = -1
608};
609
610static int __init ioapic_pirq_setup(char *str)
611{
612 int i, max;
613 int ints[MAX_PIRQS+1];
614
615 get_options(str, ARRAY_SIZE(ints), ints);
616
617 apic_printk(APIC_VERBOSE, KERN_INFO
618 "PIRQ redirection, working around broken MP-BIOS.\n");
619 max = MAX_PIRQS;
620 if (ints[0] < MAX_PIRQS)
621 max = ints[0];
622
623 for (i = 0; i < max; i++) {
624 apic_printk(APIC_VERBOSE, KERN_DEBUG
625 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
626 /*
627 * PIRQs are mapped upside down, usually.
628 */
629 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
630 }
631 return 1;
632}
633
634__setup("pirq=", ioapic_pirq_setup);
635#endif /* CONFIG_X86_32 */
636
637/*
638 * Saves all the IO-APIC RTE's
639 */
640int save_ioapic_entries(void)
641{
642 int apic, pin;
643 int err = 0;
644
645 for_each_ioapic(apic) {
646 if (!ioapics[apic].saved_registers) {
647 err = -ENOMEM;
648 continue;
649 }
650
651 for_each_pin(apic, pin)
652 ioapics[apic].saved_registers[pin] =
653 ioapic_read_entry(apic, pin);
654 }
655
656 return err;
657}
658
659/*
660 * Mask all IO APIC entries.
661 */
662void mask_ioapic_entries(void)
663{
664 int apic, pin;
665
666 for_each_ioapic(apic) {
667 if (!ioapics[apic].saved_registers)
668 continue;
669
670 for_each_pin(apic, pin) {
671 struct IO_APIC_route_entry entry;
672
673 entry = ioapics[apic].saved_registers[pin];
674 if (entry.mask == IOAPIC_UNMASKED) {
675 entry.mask = IOAPIC_MASKED;
676 ioapic_write_entry(apic, pin, entry);
677 }
678 }
679 }
680}
681
682/*
683 * Restore IO APIC entries which was saved in the ioapic structure.
684 */
685int restore_ioapic_entries(void)
686{
687 int apic, pin;
688
689 for_each_ioapic(apic) {
690 if (!ioapics[apic].saved_registers)
691 continue;
692
693 for_each_pin(apic, pin)
694 ioapic_write_entry(apic, pin,
695 ioapics[apic].saved_registers[pin]);
696 }
697 return 0;
698}
699
700/*
701 * Find the IRQ entry number of a certain pin.
702 */
703static int find_irq_entry(int ioapic_idx, int pin, int type)
704{
705 int i;
706
707 for (i = 0; i < mp_irq_entries; i++)
708 if (mp_irqs[i].irqtype == type &&
709 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
710 mp_irqs[i].dstapic == MP_APIC_ALL) &&
711 mp_irqs[i].dstirq == pin)
712 return i;
713
714 return -1;
715}
716
717/*
718 * Find the pin to which IRQ[irq] (ISA) is connected
719 */
720static int __init find_isa_irq_pin(int irq, int type)
721{
722 int i;
723
724 for (i = 0; i < mp_irq_entries; i++) {
725 int lbus = mp_irqs[i].srcbus;
726
727 if (test_bit(lbus, mp_bus_not_pci) &&
728 (mp_irqs[i].irqtype == type) &&
729 (mp_irqs[i].srcbusirq == irq))
730
731 return mp_irqs[i].dstirq;
732 }
733 return -1;
734}
735
736static int __init find_isa_irq_apic(int irq, int type)
737{
738 int i;
739
740 for (i = 0; i < mp_irq_entries; i++) {
741 int lbus = mp_irqs[i].srcbus;
742
743 if (test_bit(lbus, mp_bus_not_pci) &&
744 (mp_irqs[i].irqtype == type) &&
745 (mp_irqs[i].srcbusirq == irq))
746 break;
747 }
748
749 if (i < mp_irq_entries) {
750 int ioapic_idx;
751
752 for_each_ioapic(ioapic_idx)
753 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
754 return ioapic_idx;
755 }
756
757 return -1;
758}
759
760#ifdef CONFIG_EISA
761/*
762 * EISA Edge/Level control register, ELCR
763 */
764static int EISA_ELCR(unsigned int irq)
765{
766 if (irq < nr_legacy_irqs()) {
767 unsigned int port = 0x4d0 + (irq >> 3);
768 return (inb(port) >> (irq & 7)) & 1;
769 }
770 apic_printk(APIC_VERBOSE, KERN_INFO
771 "Broken MPtable reports ISA irq %d\n", irq);
772 return 0;
773}
774
775#endif
776
777/* ISA interrupts are always active high edge triggered,
778 * when listed as conforming in the MP table. */
779
780#define default_ISA_trigger(idx) (IOAPIC_EDGE)
781#define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
782
783/* EISA interrupts are always polarity zero and can be edge or level
784 * trigger depending on the ELCR value. If an interrupt is listed as
785 * EISA conforming in the MP table, that means its trigger type must
786 * be read in from the ELCR */
787
788#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
789#define default_EISA_polarity(idx) default_ISA_polarity(idx)
790
791/* PCI interrupts are always active low level triggered,
792 * when listed as conforming in the MP table. */
793
794#define default_PCI_trigger(idx) (IOAPIC_LEVEL)
795#define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
796
797static int irq_polarity(int idx)
798{
799 int bus = mp_irqs[idx].srcbus;
800
801 /*
802 * Determine IRQ line polarity (high active or low active):
803 */
804 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
805 case MP_IRQPOL_DEFAULT:
806 /* conforms to spec, ie. bus-type dependent polarity */
807 if (test_bit(bus, mp_bus_not_pci))
808 return default_ISA_polarity(idx);
809 else
810 return default_PCI_polarity(idx);
811 case MP_IRQPOL_ACTIVE_HIGH:
812 return IOAPIC_POL_HIGH;
813 case MP_IRQPOL_RESERVED:
814 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
815 /* fall through */
816 case MP_IRQPOL_ACTIVE_LOW:
817 default: /* Pointless default required due to do gcc stupidity */
818 return IOAPIC_POL_LOW;
819 }
820}
821
822#ifdef CONFIG_EISA
823static int eisa_irq_trigger(int idx, int bus, int trigger)
824{
825 switch (mp_bus_id_to_type[bus]) {
826 case MP_BUS_PCI:
827 case MP_BUS_ISA:
828 return trigger;
829 case MP_BUS_EISA:
830 return default_EISA_trigger(idx);
831 }
832 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
833 return IOAPIC_LEVEL;
834}
835#else
836static inline int eisa_irq_trigger(int idx, int bus, int trigger)
837{
838 return trigger;
839}
840#endif
841
842static int irq_trigger(int idx)
843{
844 int bus = mp_irqs[idx].srcbus;
845 int trigger;
846
847 /*
848 * Determine IRQ trigger mode (edge or level sensitive):
849 */
850 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
851 case MP_IRQTRIG_DEFAULT:
852 /* conforms to spec, ie. bus-type dependent trigger mode */
853 if (test_bit(bus, mp_bus_not_pci))
854 trigger = default_ISA_trigger(idx);
855 else
856 trigger = default_PCI_trigger(idx);
857 /* Take EISA into account */
858 return eisa_irq_trigger(idx, bus, trigger);
859 case MP_IRQTRIG_EDGE:
860 return IOAPIC_EDGE;
861 case MP_IRQTRIG_RESERVED:
862 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
863 /* fall through */
864 case MP_IRQTRIG_LEVEL:
865 default: /* Pointless default required due to do gcc stupidity */
866 return IOAPIC_LEVEL;
867 }
868}
869
870void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
871 int trigger, int polarity)
872{
873 init_irq_alloc_info(info, NULL);
874 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
875 info->ioapic_node = node;
876 info->ioapic_trigger = trigger;
877 info->ioapic_polarity = polarity;
878 info->ioapic_valid = 1;
879}
880
881#ifndef CONFIG_ACPI
882int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
883#endif
884
885static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
886 struct irq_alloc_info *src,
887 u32 gsi, int ioapic_idx, int pin)
888{
889 int trigger, polarity;
890
891 copy_irq_alloc_info(dst, src);
892 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
893 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
894 dst->ioapic_pin = pin;
895 dst->ioapic_valid = 1;
896 if (src && src->ioapic_valid) {
897 dst->ioapic_node = src->ioapic_node;
898 dst->ioapic_trigger = src->ioapic_trigger;
899 dst->ioapic_polarity = src->ioapic_polarity;
900 } else {
901 dst->ioapic_node = NUMA_NO_NODE;
902 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
903 dst->ioapic_trigger = trigger;
904 dst->ioapic_polarity = polarity;
905 } else {
906 /*
907 * PCI interrupts are always active low level
908 * triggered.
909 */
910 dst->ioapic_trigger = IOAPIC_LEVEL;
911 dst->ioapic_polarity = IOAPIC_POL_LOW;
912 }
913 }
914}
915
916static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
917{
918 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
919}
920
921static void mp_register_handler(unsigned int irq, unsigned long trigger)
922{
923 irq_flow_handler_t hdl;
924 bool fasteoi;
925
926 if (trigger) {
927 irq_set_status_flags(irq, IRQ_LEVEL);
928 fasteoi = true;
929 } else {
930 irq_clear_status_flags(irq, IRQ_LEVEL);
931 fasteoi = false;
932 }
933
934 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
935 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
936}
937
938static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
939{
940 struct mp_chip_data *data = irq_get_chip_data(irq);
941
942 /*
943 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
944 * and polarity attirbutes. So allow the first user to reprogram the
945 * pin with real trigger and polarity attributes.
946 */
947 if (irq < nr_legacy_irqs() && data->count == 1) {
948 if (info->ioapic_trigger != data->trigger)
949 mp_register_handler(irq, info->ioapic_trigger);
950 data->entry.trigger = data->trigger = info->ioapic_trigger;
951 data->entry.polarity = data->polarity = info->ioapic_polarity;
952 }
953
954 return data->trigger == info->ioapic_trigger &&
955 data->polarity == info->ioapic_polarity;
956}
957
958static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
959 struct irq_alloc_info *info)
960{
961 bool legacy = false;
962 int irq = -1;
963 int type = ioapics[ioapic].irqdomain_cfg.type;
964
965 switch (type) {
966 case IOAPIC_DOMAIN_LEGACY:
967 /*
968 * Dynamically allocate IRQ number for non-ISA IRQs in the first
969 * 16 GSIs on some weird platforms.
970 */
971 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
972 irq = gsi;
973 legacy = mp_is_legacy_irq(irq);
974 break;
975 case IOAPIC_DOMAIN_STRICT:
976 irq = gsi;
977 break;
978 case IOAPIC_DOMAIN_DYNAMIC:
979 break;
980 default:
981 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
982 return -1;
983 }
984
985 return __irq_domain_alloc_irqs(domain, irq, 1,
986 ioapic_alloc_attr_node(info),
987 info, legacy, NULL);
988}
989
990/*
991 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
992 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
993 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
994 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
995 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
996 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
997 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
998 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
999 */
1000static int alloc_isa_irq_from_domain(struct irq_domain *domain,
1001 int irq, int ioapic, int pin,
1002 struct irq_alloc_info *info)
1003{
1004 struct mp_chip_data *data;
1005 struct irq_data *irq_data = irq_get_irq_data(irq);
1006 int node = ioapic_alloc_attr_node(info);
1007
1008 /*
1009 * Legacy ISA IRQ has already been allocated, just add pin to
1010 * the pin list assoicated with this IRQ and program the IOAPIC
1011 * entry. The IOAPIC entry
1012 */
1013 if (irq_data && irq_data->parent_data) {
1014 if (!mp_check_pin_attr(irq, info))
1015 return -EBUSY;
1016 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1017 info->ioapic_pin))
1018 return -ENOMEM;
1019 } else {
1020 info->flags |= X86_IRQ_ALLOC_LEGACY;
1021 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1022 NULL);
1023 if (irq >= 0) {
1024 irq_data = irq_domain_get_irq_data(domain, irq);
1025 data = irq_data->chip_data;
1026 data->isa_irq = true;
1027 }
1028 }
1029
1030 return irq;
1031}
1032
1033static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1034 unsigned int flags, struct irq_alloc_info *info)
1035{
1036 int irq;
1037 bool legacy = false;
1038 struct irq_alloc_info tmp;
1039 struct mp_chip_data *data;
1040 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1041
1042 if (!domain)
1043 return -ENOSYS;
1044
1045 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1046 irq = mp_irqs[idx].srcbusirq;
1047 legacy = mp_is_legacy_irq(irq);
1048 }
1049
1050 mutex_lock(&ioapic_mutex);
1051 if (!(flags & IOAPIC_MAP_ALLOC)) {
1052 if (!legacy) {
1053 irq = irq_find_mapping(domain, pin);
1054 if (irq == 0)
1055 irq = -ENOENT;
1056 }
1057 } else {
1058 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1059 if (legacy)
1060 irq = alloc_isa_irq_from_domain(domain, irq,
1061 ioapic, pin, &tmp);
1062 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1063 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1064 else if (!mp_check_pin_attr(irq, &tmp))
1065 irq = -EBUSY;
1066 if (irq >= 0) {
1067 data = irq_get_chip_data(irq);
1068 data->count++;
1069 }
1070 }
1071 mutex_unlock(&ioapic_mutex);
1072
1073 return irq;
1074}
1075
1076static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1077{
1078 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1079
1080 /*
1081 * Debugging check, we are in big trouble if this message pops up!
1082 */
1083 if (mp_irqs[idx].dstirq != pin)
1084 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1085
1086#ifdef CONFIG_X86_32
1087 /*
1088 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1089 */
1090 if ((pin >= 16) && (pin <= 23)) {
1091 if (pirq_entries[pin-16] != -1) {
1092 if (!pirq_entries[pin-16]) {
1093 apic_printk(APIC_VERBOSE, KERN_DEBUG
1094 "disabling PIRQ%d\n", pin-16);
1095 } else {
1096 int irq = pirq_entries[pin-16];
1097 apic_printk(APIC_VERBOSE, KERN_DEBUG
1098 "using PIRQ%d -> IRQ %d\n",
1099 pin-16, irq);
1100 return irq;
1101 }
1102 }
1103 }
1104#endif
1105
1106 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1107}
1108
1109int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1110{
1111 int ioapic, pin, idx;
1112
1113 ioapic = mp_find_ioapic(gsi);
1114 if (ioapic < 0)
1115 return -ENODEV;
1116
1117 pin = mp_find_ioapic_pin(ioapic, gsi);
1118 idx = find_irq_entry(ioapic, pin, mp_INT);
1119 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1120 return -ENODEV;
1121
1122 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1123}
1124
1125void mp_unmap_irq(int irq)
1126{
1127 struct irq_data *irq_data = irq_get_irq_data(irq);
1128 struct mp_chip_data *data;
1129
1130 if (!irq_data || !irq_data->domain)
1131 return;
1132
1133 data = irq_data->chip_data;
1134 if (!data || data->isa_irq)
1135 return;
1136
1137 mutex_lock(&ioapic_mutex);
1138 if (--data->count == 0)
1139 irq_domain_free_irqs(irq, 1);
1140 mutex_unlock(&ioapic_mutex);
1141}
1142
1143/*
1144 * Find a specific PCI IRQ entry.
1145 * Not an __init, possibly needed by modules
1146 */
1147int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1148{
1149 int irq, i, best_ioapic = -1, best_idx = -1;
1150
1151 apic_printk(APIC_DEBUG,
1152 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1153 bus, slot, pin);
1154 if (test_bit(bus, mp_bus_not_pci)) {
1155 apic_printk(APIC_VERBOSE,
1156 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1157 return -1;
1158 }
1159
1160 for (i = 0; i < mp_irq_entries; i++) {
1161 int lbus = mp_irqs[i].srcbus;
1162 int ioapic_idx, found = 0;
1163
1164 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1165 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1166 continue;
1167
1168 for_each_ioapic(ioapic_idx)
1169 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1170 mp_irqs[i].dstapic == MP_APIC_ALL) {
1171 found = 1;
1172 break;
1173 }
1174 if (!found)
1175 continue;
1176
1177 /* Skip ISA IRQs */
1178 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1179 if (irq > 0 && !IO_APIC_IRQ(irq))
1180 continue;
1181
1182 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1183 best_idx = i;
1184 best_ioapic = ioapic_idx;
1185 goto out;
1186 }
1187
1188 /*
1189 * Use the first all-but-pin matching entry as a
1190 * best-guess fuzzy result for broken mptables.
1191 */
1192 if (best_idx < 0) {
1193 best_idx = i;
1194 best_ioapic = ioapic_idx;
1195 }
1196 }
1197 if (best_idx < 0)
1198 return -1;
1199
1200out:
1201 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1202 IOAPIC_MAP_ALLOC);
1203}
1204EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1205
1206static struct irq_chip ioapic_chip, ioapic_ir_chip;
1207
1208static void __init setup_IO_APIC_irqs(void)
1209{
1210 unsigned int ioapic, pin;
1211 int idx;
1212
1213 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1214
1215 for_each_ioapic_pin(ioapic, pin) {
1216 idx = find_irq_entry(ioapic, pin, mp_INT);
1217 if (idx < 0)
1218 apic_printk(APIC_VERBOSE,
1219 KERN_DEBUG " apic %d pin %d not connected\n",
1220 mpc_ioapic_id(ioapic), pin);
1221 else
1222 pin_2_irq(idx, ioapic, pin,
1223 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1224 }
1225}
1226
1227void ioapic_zap_locks(void)
1228{
1229 raw_spin_lock_init(&ioapic_lock);
1230}
1231
1232static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1233{
1234 int i;
1235 char buf[256];
1236 struct IO_APIC_route_entry entry;
1237 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1238
1239 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1240 for (i = 0; i <= nr_entries; i++) {
1241 entry = ioapic_read_entry(apic, i);
1242 snprintf(buf, sizeof(buf),
1243 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1244 i,
1245 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1246 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1247 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1248 entry.vector, entry.irr, entry.delivery_status);
1249 if (ir_entry->format)
1250 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1251 buf, (ir_entry->index2 << 15) | ir_entry->index,
1252 ir_entry->zero);
1253 else
1254 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1255 buf,
1256 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1257 "logical " : "physical",
1258 entry.dest, entry.delivery_mode);
1259 }
1260}
1261
1262static void __init print_IO_APIC(int ioapic_idx)
1263{
1264 union IO_APIC_reg_00 reg_00;
1265 union IO_APIC_reg_01 reg_01;
1266 union IO_APIC_reg_02 reg_02;
1267 union IO_APIC_reg_03 reg_03;
1268 unsigned long flags;
1269
1270 raw_spin_lock_irqsave(&ioapic_lock, flags);
1271 reg_00.raw = io_apic_read(ioapic_idx, 0);
1272 reg_01.raw = io_apic_read(ioapic_idx, 1);
1273 if (reg_01.bits.version >= 0x10)
1274 reg_02.raw = io_apic_read(ioapic_idx, 2);
1275 if (reg_01.bits.version >= 0x20)
1276 reg_03.raw = io_apic_read(ioapic_idx, 3);
1277 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1278
1279 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1280 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1281 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1282 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1283 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1284
1285 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1286 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1287 reg_01.bits.entries);
1288
1289 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1290 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1291 reg_01.bits.version);
1292
1293 /*
1294 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1295 * but the value of reg_02 is read as the previous read register
1296 * value, so ignore it if reg_02 == reg_01.
1297 */
1298 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1299 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1300 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1301 }
1302
1303 /*
1304 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1305 * or reg_03, but the value of reg_0[23] is read as the previous read
1306 * register value, so ignore it if reg_03 == reg_0[12].
1307 */
1308 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1309 reg_03.raw != reg_01.raw) {
1310 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1311 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1312 }
1313
1314 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1315 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1316}
1317
1318void __init print_IO_APICs(void)
1319{
1320 int ioapic_idx;
1321 unsigned int irq;
1322
1323 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1324 for_each_ioapic(ioapic_idx)
1325 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1326 mpc_ioapic_id(ioapic_idx),
1327 ioapics[ioapic_idx].nr_registers);
1328
1329 /*
1330 * We are a bit conservative about what we expect. We have to
1331 * know about every hardware change ASAP.
1332 */
1333 printk(KERN_INFO "testing the IO APIC.......................\n");
1334
1335 for_each_ioapic(ioapic_idx)
1336 print_IO_APIC(ioapic_idx);
1337
1338 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1339 for_each_active_irq(irq) {
1340 struct irq_pin_list *entry;
1341 struct irq_chip *chip;
1342 struct mp_chip_data *data;
1343
1344 chip = irq_get_chip(irq);
1345 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1346 continue;
1347 data = irq_get_chip_data(irq);
1348 if (!data)
1349 continue;
1350 if (list_empty(&data->irq_2_pin))
1351 continue;
1352
1353 printk(KERN_DEBUG "IRQ%d ", irq);
1354 for_each_irq_pin(entry, data->irq_2_pin)
1355 pr_cont("-> %d:%d", entry->apic, entry->pin);
1356 pr_cont("\n");
1357 }
1358
1359 printk(KERN_INFO ".................................... done.\n");
1360}
1361
1362/* Where if anywhere is the i8259 connect in external int mode */
1363static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1364
1365void __init enable_IO_APIC(void)
1366{
1367 int i8259_apic, i8259_pin;
1368 int apic, pin;
1369
1370 if (skip_ioapic_setup)
1371 nr_ioapics = 0;
1372
1373 if (!nr_legacy_irqs() || !nr_ioapics)
1374 return;
1375
1376 for_each_ioapic_pin(apic, pin) {
1377 /* See if any of the pins is in ExtINT mode */
1378 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1379
1380 /* If the interrupt line is enabled and in ExtInt mode
1381 * I have found the pin where the i8259 is connected.
1382 */
1383 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1384 ioapic_i8259.apic = apic;
1385 ioapic_i8259.pin = pin;
1386 goto found_i8259;
1387 }
1388 }
1389 found_i8259:
1390 /* Look to see what if the MP table has reported the ExtINT */
1391 /* If we could not find the appropriate pin by looking at the ioapic
1392 * the i8259 probably is not connected the ioapic but give the
1393 * mptable a chance anyway.
1394 */
1395 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1396 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1397 /* Trust the MP table if nothing is setup in the hardware */
1398 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1399 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1400 ioapic_i8259.pin = i8259_pin;
1401 ioapic_i8259.apic = i8259_apic;
1402 }
1403 /* Complain if the MP table and the hardware disagree */
1404 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1405 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1406 {
1407 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1408 }
1409
1410 /*
1411 * Do not trust the IO-APIC being empty at bootup
1412 */
1413 clear_IO_APIC();
1414}
1415
1416void native_restore_boot_irq_mode(void)
1417{
1418 /*
1419 * If the i8259 is routed through an IOAPIC
1420 * Put that IOAPIC in virtual wire mode
1421 * so legacy interrupts can be delivered.
1422 */
1423 if (ioapic_i8259.pin != -1) {
1424 struct IO_APIC_route_entry entry;
1425
1426 memset(&entry, 0, sizeof(entry));
1427 entry.mask = IOAPIC_UNMASKED;
1428 entry.trigger = IOAPIC_EDGE;
1429 entry.polarity = IOAPIC_POL_HIGH;
1430 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1431 entry.delivery_mode = dest_ExtINT;
1432 entry.dest = read_apic_id();
1433
1434 /*
1435 * Add it to the IO-APIC irq-routing table:
1436 */
1437 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1438 }
1439
1440 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1441 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1442}
1443
1444void restore_boot_irq_mode(void)
1445{
1446 if (!nr_legacy_irqs())
1447 return;
1448
1449 x86_apic_ops.restore();
1450}
1451
1452#ifdef CONFIG_X86_32
1453/*
1454 * function to set the IO-APIC physical IDs based on the
1455 * values stored in the MPC table.
1456 *
1457 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1458 */
1459void __init setup_ioapic_ids_from_mpc_nocheck(void)
1460{
1461 union IO_APIC_reg_00 reg_00;
1462 physid_mask_t phys_id_present_map;
1463 int ioapic_idx;
1464 int i;
1465 unsigned char old_id;
1466 unsigned long flags;
1467
1468 /*
1469 * This is broken; anything with a real cpu count has to
1470 * circumvent this idiocy regardless.
1471 */
1472 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1473
1474 /*
1475 * Set the IOAPIC ID to the value stored in the MPC table.
1476 */
1477 for_each_ioapic(ioapic_idx) {
1478 /* Read the register 0 value */
1479 raw_spin_lock_irqsave(&ioapic_lock, flags);
1480 reg_00.raw = io_apic_read(ioapic_idx, 0);
1481 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1482
1483 old_id = mpc_ioapic_id(ioapic_idx);
1484
1485 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1486 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1487 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1488 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1489 reg_00.bits.ID);
1490 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1491 }
1492
1493 /*
1494 * Sanity check, is the ID really free? Every APIC in a
1495 * system must have a unique ID or we get lots of nice
1496 * 'stuck on smp_invalidate_needed IPI wait' messages.
1497 */
1498 if (apic->check_apicid_used(&phys_id_present_map,
1499 mpc_ioapic_id(ioapic_idx))) {
1500 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1501 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1502 for (i = 0; i < get_physical_broadcast(); i++)
1503 if (!physid_isset(i, phys_id_present_map))
1504 break;
1505 if (i >= get_physical_broadcast())
1506 panic("Max APIC ID exceeded!\n");
1507 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1508 i);
1509 physid_set(i, phys_id_present_map);
1510 ioapics[ioapic_idx].mp_config.apicid = i;
1511 } else {
1512 physid_mask_t tmp;
1513 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1514 &tmp);
1515 apic_printk(APIC_VERBOSE, "Setting %d in the "
1516 "phys_id_present_map\n",
1517 mpc_ioapic_id(ioapic_idx));
1518 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1519 }
1520
1521 /*
1522 * We need to adjust the IRQ routing table
1523 * if the ID changed.
1524 */
1525 if (old_id != mpc_ioapic_id(ioapic_idx))
1526 for (i = 0; i < mp_irq_entries; i++)
1527 if (mp_irqs[i].dstapic == old_id)
1528 mp_irqs[i].dstapic
1529 = mpc_ioapic_id(ioapic_idx);
1530
1531 /*
1532 * Update the ID register according to the right value
1533 * from the MPC table if they are different.
1534 */
1535 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1536 continue;
1537
1538 apic_printk(APIC_VERBOSE, KERN_INFO
1539 "...changing IO-APIC physical APIC ID to %d ...",
1540 mpc_ioapic_id(ioapic_idx));
1541
1542 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1543 raw_spin_lock_irqsave(&ioapic_lock, flags);
1544 io_apic_write(ioapic_idx, 0, reg_00.raw);
1545 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1546
1547 /*
1548 * Sanity check
1549 */
1550 raw_spin_lock_irqsave(&ioapic_lock, flags);
1551 reg_00.raw = io_apic_read(ioapic_idx, 0);
1552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1553 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1554 pr_cont("could not set ID!\n");
1555 else
1556 apic_printk(APIC_VERBOSE, " ok.\n");
1557 }
1558}
1559
1560void __init setup_ioapic_ids_from_mpc(void)
1561{
1562
1563 if (acpi_ioapic)
1564 return;
1565 /*
1566 * Don't check I/O APIC IDs for xAPIC systems. They have
1567 * no meaning without the serial APIC bus.
1568 */
1569 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1570 || APIC_XAPIC(boot_cpu_apic_version))
1571 return;
1572 setup_ioapic_ids_from_mpc_nocheck();
1573}
1574#endif
1575
1576int no_timer_check __initdata;
1577
1578static int __init notimercheck(char *s)
1579{
1580 no_timer_check = 1;
1581 return 1;
1582}
1583__setup("no_timer_check", notimercheck);
1584
1585static void __init delay_with_tsc(void)
1586{
1587 unsigned long long start, now;
1588 unsigned long end = jiffies + 4;
1589
1590 start = rdtsc();
1591
1592 /*
1593 * We don't know the TSC frequency yet, but waiting for
1594 * 40000000000/HZ TSC cycles is safe:
1595 * 4 GHz == 10 jiffies
1596 * 1 GHz == 40 jiffies
1597 */
1598 do {
1599 rep_nop();
1600 now = rdtsc();
1601 } while ((now - start) < 40000000000ULL / HZ &&
1602 time_before_eq(jiffies, end));
1603}
1604
1605static void __init delay_without_tsc(void)
1606{
1607 unsigned long end = jiffies + 4;
1608 int band = 1;
1609
1610 /*
1611 * We don't know any frequency yet, but waiting for
1612 * 40940000000/HZ cycles is safe:
1613 * 4 GHz == 10 jiffies
1614 * 1 GHz == 40 jiffies
1615 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1616 */
1617 do {
1618 __delay(((1U << band++) * 10000000UL) / HZ);
1619 } while (band < 12 && time_before_eq(jiffies, end));
1620}
1621
1622/*
1623 * There is a nasty bug in some older SMP boards, their mptable lies
1624 * about the timer IRQ. We do the following to work around the situation:
1625 *
1626 * - timer IRQ defaults to IO-APIC IRQ
1627 * - if this function detects that timer IRQs are defunct, then we fall
1628 * back to ISA timer IRQs
1629 */
1630static int __init timer_irq_works(void)
1631{
1632 unsigned long t1 = jiffies;
1633 unsigned long flags;
1634
1635 if (no_timer_check)
1636 return 1;
1637
1638 local_save_flags(flags);
1639 local_irq_enable();
1640
1641 if (boot_cpu_has(X86_FEATURE_TSC))
1642 delay_with_tsc();
1643 else
1644 delay_without_tsc();
1645
1646 local_irq_restore(flags);
1647
1648 /*
1649 * Expect a few ticks at least, to be sure some possible
1650 * glue logic does not lock up after one or two first
1651 * ticks in a non-ExtINT mode. Also the local APIC
1652 * might have cached one ExtINT interrupt. Finally, at
1653 * least one tick may be lost due to delays.
1654 */
1655
1656 /* jiffies wrap? */
1657 if (time_after(jiffies, t1 + 4))
1658 return 1;
1659 return 0;
1660}
1661
1662/*
1663 * In the SMP+IOAPIC case it might happen that there are an unspecified
1664 * number of pending IRQ events unhandled. These cases are very rare,
1665 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1666 * better to do it this way as thus we do not have to be aware of
1667 * 'pending' interrupts in the IRQ path, except at this point.
1668 */
1669/*
1670 * Edge triggered needs to resend any interrupt
1671 * that was delayed but this is now handled in the device
1672 * independent code.
1673 */
1674
1675/*
1676 * Starting up a edge-triggered IO-APIC interrupt is
1677 * nasty - we need to make sure that we get the edge.
1678 * If it is already asserted for some reason, we need
1679 * return 1 to indicate that is was pending.
1680 *
1681 * This is not complete - we should be able to fake
1682 * an edge even if it isn't on the 8259A...
1683 */
1684static unsigned int startup_ioapic_irq(struct irq_data *data)
1685{
1686 int was_pending = 0, irq = data->irq;
1687 unsigned long flags;
1688
1689 raw_spin_lock_irqsave(&ioapic_lock, flags);
1690 if (irq < nr_legacy_irqs()) {
1691 legacy_pic->mask(irq);
1692 if (legacy_pic->irq_pending(irq))
1693 was_pending = 1;
1694 }
1695 __unmask_ioapic(data->chip_data);
1696 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1697
1698 return was_pending;
1699}
1700
1701atomic_t irq_mis_count;
1702
1703#ifdef CONFIG_GENERIC_PENDING_IRQ
1704static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1705{
1706 struct irq_pin_list *entry;
1707 unsigned long flags;
1708
1709 raw_spin_lock_irqsave(&ioapic_lock, flags);
1710 for_each_irq_pin(entry, data->irq_2_pin) {
1711 unsigned int reg;
1712 int pin;
1713
1714 pin = entry->pin;
1715 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1716 /* Is the remote IRR bit set? */
1717 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1718 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1719 return true;
1720 }
1721 }
1722 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1723
1724 return false;
1725}
1726
1727static inline bool ioapic_irqd_mask(struct irq_data *data)
1728{
1729 /* If we are moving the irq we need to mask it */
1730 if (unlikely(irqd_is_setaffinity_pending(data))) {
1731 mask_ioapic_irq(data);
1732 return true;
1733 }
1734 return false;
1735}
1736
1737static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1738{
1739 if (unlikely(masked)) {
1740 /* Only migrate the irq if the ack has been received.
1741 *
1742 * On rare occasions the broadcast level triggered ack gets
1743 * delayed going to ioapics, and if we reprogram the
1744 * vector while Remote IRR is still set the irq will never
1745 * fire again.
1746 *
1747 * To prevent this scenario we read the Remote IRR bit
1748 * of the ioapic. This has two effects.
1749 * - On any sane system the read of the ioapic will
1750 * flush writes (and acks) going to the ioapic from
1751 * this cpu.
1752 * - We get to see if the ACK has actually been delivered.
1753 *
1754 * Based on failed experiments of reprogramming the
1755 * ioapic entry from outside of irq context starting
1756 * with masking the ioapic entry and then polling until
1757 * Remote IRR was clear before reprogramming the
1758 * ioapic I don't trust the Remote IRR bit to be
1759 * completey accurate.
1760 *
1761 * However there appears to be no other way to plug
1762 * this race, so if the Remote IRR bit is not
1763 * accurate and is causing problems then it is a hardware bug
1764 * and you can go talk to the chipset vendor about it.
1765 */
1766 if (!io_apic_level_ack_pending(data->chip_data))
1767 irq_move_masked_irq(data);
1768 unmask_ioapic_irq(data);
1769 }
1770}
1771#else
1772static inline bool ioapic_irqd_mask(struct irq_data *data)
1773{
1774 return false;
1775}
1776static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1777{
1778}
1779#endif
1780
1781static void ioapic_ack_level(struct irq_data *irq_data)
1782{
1783 struct irq_cfg *cfg = irqd_cfg(irq_data);
1784 unsigned long v;
1785 bool masked;
1786 int i;
1787
1788 irq_complete_move(cfg);
1789 masked = ioapic_irqd_mask(irq_data);
1790
1791 /*
1792 * It appears there is an erratum which affects at least version 0x11
1793 * of I/O APIC (that's the 82093AA and cores integrated into various
1794 * chipsets). Under certain conditions a level-triggered interrupt is
1795 * erroneously delivered as edge-triggered one but the respective IRR
1796 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1797 * message but it will never arrive and further interrupts are blocked
1798 * from the source. The exact reason is so far unknown, but the
1799 * phenomenon was observed when two consecutive interrupt requests
1800 * from a given source get delivered to the same CPU and the source is
1801 * temporarily disabled in between.
1802 *
1803 * A workaround is to simulate an EOI message manually. We achieve it
1804 * by setting the trigger mode to edge and then to level when the edge
1805 * trigger mode gets detected in the TMR of a local APIC for a
1806 * level-triggered interrupt. We mask the source for the time of the
1807 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1808 * The idea is from Manfred Spraul. --macro
1809 *
1810 * Also in the case when cpu goes offline, fixup_irqs() will forward
1811 * any unhandled interrupt on the offlined cpu to the new cpu
1812 * destination that is handling the corresponding interrupt. This
1813 * interrupt forwarding is done via IPI's. Hence, in this case also
1814 * level-triggered io-apic interrupt will be seen as an edge
1815 * interrupt in the IRR. And we can't rely on the cpu's EOI
1816 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1817 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1818 * supporting EOI register, we do an explicit EOI to clear the
1819 * remote IRR and on IO-APIC's which don't have an EOI register,
1820 * we use the above logic (mask+edge followed by unmask+level) from
1821 * Manfred Spraul to clear the remote IRR.
1822 */
1823 i = cfg->vector;
1824 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1825
1826 /*
1827 * We must acknowledge the irq before we move it or the acknowledge will
1828 * not propagate properly.
1829 */
1830 ack_APIC_irq();
1831
1832 /*
1833 * Tail end of clearing remote IRR bit (either by delivering the EOI
1834 * message via io-apic EOI register write or simulating it using
1835 * mask+edge followed by unnask+level logic) manually when the
1836 * level triggered interrupt is seen as the edge triggered interrupt
1837 * at the cpu.
1838 */
1839 if (!(v & (1 << (i & 0x1f)))) {
1840 atomic_inc(&irq_mis_count);
1841 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1842 }
1843
1844 ioapic_irqd_unmask(irq_data, masked);
1845}
1846
1847static void ioapic_ir_ack_level(struct irq_data *irq_data)
1848{
1849 struct mp_chip_data *data = irq_data->chip_data;
1850
1851 /*
1852 * Intr-remapping uses pin number as the virtual vector
1853 * in the RTE. Actual vector is programmed in
1854 * intr-remapping table entry. Hence for the io-apic
1855 * EOI we use the pin number.
1856 */
1857 apic_ack_irq(irq_data);
1858 eoi_ioapic_pin(data->entry.vector, data);
1859}
1860
1861static void ioapic_configure_entry(struct irq_data *irqd)
1862{
1863 struct mp_chip_data *mpd = irqd->chip_data;
1864 struct irq_cfg *cfg = irqd_cfg(irqd);
1865 struct irq_pin_list *entry;
1866
1867 /*
1868 * Only update when the parent is the vector domain, don't touch it
1869 * if the parent is the remapping domain. Check the installed
1870 * ioapic chip to verify that.
1871 */
1872 if (irqd->chip == &ioapic_chip) {
1873 mpd->entry.dest = cfg->dest_apicid;
1874 mpd->entry.vector = cfg->vector;
1875 }
1876 for_each_irq_pin(entry, mpd->irq_2_pin)
1877 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1878}
1879
1880static int ioapic_set_affinity(struct irq_data *irq_data,
1881 const struct cpumask *mask, bool force)
1882{
1883 struct irq_data *parent = irq_data->parent_data;
1884 unsigned long flags;
1885 int ret;
1886
1887 ret = parent->chip->irq_set_affinity(parent, mask, force);
1888 raw_spin_lock_irqsave(&ioapic_lock, flags);
1889 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1890 ioapic_configure_entry(irq_data);
1891 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1892
1893 return ret;
1894}
1895
1896static struct irq_chip ioapic_chip __read_mostly = {
1897 .name = "IO-APIC",
1898 .irq_startup = startup_ioapic_irq,
1899 .irq_mask = mask_ioapic_irq,
1900 .irq_unmask = unmask_ioapic_irq,
1901 .irq_ack = irq_chip_ack_parent,
1902 .irq_eoi = ioapic_ack_level,
1903 .irq_set_affinity = ioapic_set_affinity,
1904 .irq_retrigger = irq_chip_retrigger_hierarchy,
1905 .flags = IRQCHIP_SKIP_SET_WAKE,
1906};
1907
1908static struct irq_chip ioapic_ir_chip __read_mostly = {
1909 .name = "IR-IO-APIC",
1910 .irq_startup = startup_ioapic_irq,
1911 .irq_mask = mask_ioapic_irq,
1912 .irq_unmask = unmask_ioapic_irq,
1913 .irq_ack = irq_chip_ack_parent,
1914 .irq_eoi = ioapic_ir_ack_level,
1915 .irq_set_affinity = ioapic_set_affinity,
1916 .irq_retrigger = irq_chip_retrigger_hierarchy,
1917 .flags = IRQCHIP_SKIP_SET_WAKE,
1918};
1919
1920static inline void init_IO_APIC_traps(void)
1921{
1922 struct irq_cfg *cfg;
1923 unsigned int irq;
1924
1925 for_each_active_irq(irq) {
1926 cfg = irq_cfg(irq);
1927 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1928 /*
1929 * Hmm.. We don't have an entry for this,
1930 * so default to an old-fashioned 8259
1931 * interrupt if we can..
1932 */
1933 if (irq < nr_legacy_irqs())
1934 legacy_pic->make_irq(irq);
1935 else
1936 /* Strange. Oh, well.. */
1937 irq_set_chip(irq, &no_irq_chip);
1938 }
1939 }
1940}
1941
1942/*
1943 * The local APIC irq-chip implementation:
1944 */
1945
1946static void mask_lapic_irq(struct irq_data *data)
1947{
1948 unsigned long v;
1949
1950 v = apic_read(APIC_LVT0);
1951 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1952}
1953
1954static void unmask_lapic_irq(struct irq_data *data)
1955{
1956 unsigned long v;
1957
1958 v = apic_read(APIC_LVT0);
1959 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1960}
1961
1962static void ack_lapic_irq(struct irq_data *data)
1963{
1964 ack_APIC_irq();
1965}
1966
1967static struct irq_chip lapic_chip __read_mostly = {
1968 .name = "local-APIC",
1969 .irq_mask = mask_lapic_irq,
1970 .irq_unmask = unmask_lapic_irq,
1971 .irq_ack = ack_lapic_irq,
1972};
1973
1974static void lapic_register_intr(int irq)
1975{
1976 irq_clear_status_flags(irq, IRQ_LEVEL);
1977 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1978 "edge");
1979}
1980
1981/*
1982 * This looks a bit hackish but it's about the only one way of sending
1983 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1984 * not support the ExtINT mode, unfortunately. We need to send these
1985 * cycles as some i82489DX-based boards have glue logic that keeps the
1986 * 8259A interrupt line asserted until INTA. --macro
1987 */
1988static inline void __init unlock_ExtINT_logic(void)
1989{
1990 int apic, pin, i;
1991 struct IO_APIC_route_entry entry0, entry1;
1992 unsigned char save_control, save_freq_select;
1993
1994 pin = find_isa_irq_pin(8, mp_INT);
1995 if (pin == -1) {
1996 WARN_ON_ONCE(1);
1997 return;
1998 }
1999 apic = find_isa_irq_apic(8, mp_INT);
2000 if (apic == -1) {
2001 WARN_ON_ONCE(1);
2002 return;
2003 }
2004
2005 entry0 = ioapic_read_entry(apic, pin);
2006 clear_IO_APIC_pin(apic, pin);
2007
2008 memset(&entry1, 0, sizeof(entry1));
2009
2010 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2011 entry1.mask = IOAPIC_UNMASKED;
2012 entry1.dest = hard_smp_processor_id();
2013 entry1.delivery_mode = dest_ExtINT;
2014 entry1.polarity = entry0.polarity;
2015 entry1.trigger = IOAPIC_EDGE;
2016 entry1.vector = 0;
2017
2018 ioapic_write_entry(apic, pin, entry1);
2019
2020 save_control = CMOS_READ(RTC_CONTROL);
2021 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2022 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2023 RTC_FREQ_SELECT);
2024 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2025
2026 i = 100;
2027 while (i-- > 0) {
2028 mdelay(10);
2029 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2030 i -= 10;
2031 }
2032
2033 CMOS_WRITE(save_control, RTC_CONTROL);
2034 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2035 clear_IO_APIC_pin(apic, pin);
2036
2037 ioapic_write_entry(apic, pin, entry0);
2038}
2039
2040static int disable_timer_pin_1 __initdata;
2041/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2042static int __init disable_timer_pin_setup(char *arg)
2043{
2044 disable_timer_pin_1 = 1;
2045 return 0;
2046}
2047early_param("disable_timer_pin_1", disable_timer_pin_setup);
2048
2049static int mp_alloc_timer_irq(int ioapic, int pin)
2050{
2051 int irq = -1;
2052 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2053
2054 if (domain) {
2055 struct irq_alloc_info info;
2056
2057 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2058 info.ioapic_id = mpc_ioapic_id(ioapic);
2059 info.ioapic_pin = pin;
2060 mutex_lock(&ioapic_mutex);
2061 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2062 mutex_unlock(&ioapic_mutex);
2063 }
2064
2065 return irq;
2066}
2067
2068/*
2069 * This code may look a bit paranoid, but it's supposed to cooperate with
2070 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2071 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2072 * fanatically on his truly buggy board.
2073 *
2074 * FIXME: really need to revamp this for all platforms.
2075 */
2076static inline void __init check_timer(void)
2077{
2078 struct irq_data *irq_data = irq_get_irq_data(0);
2079 struct mp_chip_data *data = irq_data->chip_data;
2080 struct irq_cfg *cfg = irqd_cfg(irq_data);
2081 int node = cpu_to_node(0);
2082 int apic1, pin1, apic2, pin2;
2083 unsigned long flags;
2084 int no_pin1 = 0;
2085
2086 local_irq_save(flags);
2087
2088 /*
2089 * get/set the timer IRQ vector:
2090 */
2091 legacy_pic->mask(0);
2092
2093 /*
2094 * As IRQ0 is to be enabled in the 8259A, the virtual
2095 * wire has to be disabled in the local APIC. Also
2096 * timer interrupts need to be acknowledged manually in
2097 * the 8259A for the i82489DX when using the NMI
2098 * watchdog as that APIC treats NMIs as level-triggered.
2099 * The AEOI mode will finish them in the 8259A
2100 * automatically.
2101 */
2102 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2103 legacy_pic->init(1);
2104
2105 pin1 = find_isa_irq_pin(0, mp_INT);
2106 apic1 = find_isa_irq_apic(0, mp_INT);
2107 pin2 = ioapic_i8259.pin;
2108 apic2 = ioapic_i8259.apic;
2109
2110 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2111 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2112 cfg->vector, apic1, pin1, apic2, pin2);
2113
2114 /*
2115 * Some BIOS writers are clueless and report the ExtINTA
2116 * I/O APIC input from the cascaded 8259A as the timer
2117 * interrupt input. So just in case, if only one pin
2118 * was found above, try it both directly and through the
2119 * 8259A.
2120 */
2121 if (pin1 == -1) {
2122 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2123 pin1 = pin2;
2124 apic1 = apic2;
2125 no_pin1 = 1;
2126 } else if (pin2 == -1) {
2127 pin2 = pin1;
2128 apic2 = apic1;
2129 }
2130
2131 if (pin1 != -1) {
2132 /* Ok, does IRQ0 through the IOAPIC work? */
2133 if (no_pin1) {
2134 mp_alloc_timer_irq(apic1, pin1);
2135 } else {
2136 /*
2137 * for edge trigger, it's already unmasked,
2138 * so only need to unmask if it is level-trigger
2139 * do we really have level trigger timer?
2140 */
2141 int idx;
2142 idx = find_irq_entry(apic1, pin1, mp_INT);
2143 if (idx != -1 && irq_trigger(idx))
2144 unmask_ioapic_irq(irq_get_irq_data(0));
2145 }
2146 irq_domain_deactivate_irq(irq_data);
2147 irq_domain_activate_irq(irq_data, false);
2148 if (timer_irq_works()) {
2149 if (disable_timer_pin_1 > 0)
2150 clear_IO_APIC_pin(0, pin1);
2151 goto out;
2152 }
2153 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2154 local_irq_disable();
2155 clear_IO_APIC_pin(apic1, pin1);
2156 if (!no_pin1)
2157 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2158 "8254 timer not connected to IO-APIC\n");
2159
2160 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2161 "(IRQ0) through the 8259A ...\n");
2162 apic_printk(APIC_QUIET, KERN_INFO
2163 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2164 /*
2165 * legacy devices should be connected to IO APIC #0
2166 */
2167 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2168 irq_domain_deactivate_irq(irq_data);
2169 irq_domain_activate_irq(irq_data, false);
2170 legacy_pic->unmask(0);
2171 if (timer_irq_works()) {
2172 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2173 goto out;
2174 }
2175 /*
2176 * Cleanup, just in case ...
2177 */
2178 local_irq_disable();
2179 legacy_pic->mask(0);
2180 clear_IO_APIC_pin(apic2, pin2);
2181 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2182 }
2183
2184 apic_printk(APIC_QUIET, KERN_INFO
2185 "...trying to set up timer as Virtual Wire IRQ...\n");
2186
2187 lapic_register_intr(0);
2188 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2189 legacy_pic->unmask(0);
2190
2191 if (timer_irq_works()) {
2192 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2193 goto out;
2194 }
2195 local_irq_disable();
2196 legacy_pic->mask(0);
2197 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2198 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2199
2200 apic_printk(APIC_QUIET, KERN_INFO
2201 "...trying to set up timer as ExtINT IRQ...\n");
2202
2203 legacy_pic->init(0);
2204 legacy_pic->make_irq(0);
2205 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2206
2207 unlock_ExtINT_logic();
2208
2209 if (timer_irq_works()) {
2210 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2211 goto out;
2212 }
2213 local_irq_disable();
2214 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2215 if (apic_is_x2apic_enabled())
2216 apic_printk(APIC_QUIET, KERN_INFO
2217 "Perhaps problem with the pre-enabled x2apic mode\n"
2218 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2219 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2220 "report. Then try booting with the 'noapic' option.\n");
2221out:
2222 local_irq_restore(flags);
2223}
2224
2225/*
2226 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2227 * to devices. However there may be an I/O APIC pin available for
2228 * this interrupt regardless. The pin may be left unconnected, but
2229 * typically it will be reused as an ExtINT cascade interrupt for
2230 * the master 8259A. In the MPS case such a pin will normally be
2231 * reported as an ExtINT interrupt in the MP table. With ACPI
2232 * there is no provision for ExtINT interrupts, and in the absence
2233 * of an override it would be treated as an ordinary ISA I/O APIC
2234 * interrupt, that is edge-triggered and unmasked by default. We
2235 * used to do this, but it caused problems on some systems because
2236 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2237 * the same ExtINT cascade interrupt to drive the local APIC of the
2238 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2239 * the I/O APIC in all cases now. No actual device should request
2240 * it anyway. --macro
2241 */
2242#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2243
2244static int mp_irqdomain_create(int ioapic)
2245{
2246 struct irq_alloc_info info;
2247 struct irq_domain *parent;
2248 int hwirqs = mp_ioapic_pin_count(ioapic);
2249 struct ioapic *ip = &ioapics[ioapic];
2250 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2251 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2252 struct fwnode_handle *fn;
2253 char *name = "IO-APIC";
2254
2255 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2256 return 0;
2257
2258 init_irq_alloc_info(&info, NULL);
2259 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2260 info.ioapic_id = mpc_ioapic_id(ioapic);
2261 parent = irq_remapping_get_ir_irq_domain(&info);
2262 if (!parent)
2263 parent = x86_vector_domain;
2264 else
2265 name = "IO-APIC-IR";
2266
2267 /* Handle device tree enumerated APICs proper */
2268 if (cfg->dev) {
2269 fn = of_node_to_fwnode(cfg->dev);
2270 } else {
2271 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2272 if (!fn)
2273 return -ENOMEM;
2274 }
2275
2276 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2277 (void *)(long)ioapic);
2278
2279 /* Release fw handle if it was allocated above */
2280 if (!cfg->dev)
2281 irq_domain_free_fwnode(fn);
2282
2283 if (!ip->irqdomain)
2284 return -ENOMEM;
2285
2286 ip->irqdomain->parent = parent;
2287
2288 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2289 cfg->type == IOAPIC_DOMAIN_STRICT)
2290 ioapic_dynirq_base = max(ioapic_dynirq_base,
2291 gsi_cfg->gsi_end + 1);
2292
2293 return 0;
2294}
2295
2296static void ioapic_destroy_irqdomain(int idx)
2297{
2298 if (ioapics[idx].irqdomain) {
2299 irq_domain_remove(ioapics[idx].irqdomain);
2300 ioapics[idx].irqdomain = NULL;
2301 }
2302}
2303
2304void __init setup_IO_APIC(void)
2305{
2306 int ioapic;
2307
2308 if (skip_ioapic_setup || !nr_ioapics)
2309 return;
2310
2311 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2312
2313 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2314 for_each_ioapic(ioapic)
2315 BUG_ON(mp_irqdomain_create(ioapic));
2316
2317 /*
2318 * Set up IO-APIC IRQ routing.
2319 */
2320 x86_init.mpparse.setup_ioapic_ids();
2321
2322 sync_Arb_IDs();
2323 setup_IO_APIC_irqs();
2324 init_IO_APIC_traps();
2325 if (nr_legacy_irqs())
2326 check_timer();
2327
2328 ioapic_initialized = 1;
2329}
2330
2331static void resume_ioapic_id(int ioapic_idx)
2332{
2333 unsigned long flags;
2334 union IO_APIC_reg_00 reg_00;
2335
2336 raw_spin_lock_irqsave(&ioapic_lock, flags);
2337 reg_00.raw = io_apic_read(ioapic_idx, 0);
2338 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2339 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2340 io_apic_write(ioapic_idx, 0, reg_00.raw);
2341 }
2342 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2343}
2344
2345static void ioapic_resume(void)
2346{
2347 int ioapic_idx;
2348
2349 for_each_ioapic_reverse(ioapic_idx)
2350 resume_ioapic_id(ioapic_idx);
2351
2352 restore_ioapic_entries();
2353}
2354
2355static struct syscore_ops ioapic_syscore_ops = {
2356 .suspend = save_ioapic_entries,
2357 .resume = ioapic_resume,
2358};
2359
2360static int __init ioapic_init_ops(void)
2361{
2362 register_syscore_ops(&ioapic_syscore_ops);
2363
2364 return 0;
2365}
2366
2367device_initcall(ioapic_init_ops);
2368
2369static int io_apic_get_redir_entries(int ioapic)
2370{
2371 union IO_APIC_reg_01 reg_01;
2372 unsigned long flags;
2373
2374 raw_spin_lock_irqsave(&ioapic_lock, flags);
2375 reg_01.raw = io_apic_read(ioapic, 1);
2376 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2377
2378 /* The register returns the maximum index redir index
2379 * supported, which is one less than the total number of redir
2380 * entries.
2381 */
2382 return reg_01.bits.entries + 1;
2383}
2384
2385unsigned int arch_dynirq_lower_bound(unsigned int from)
2386{
2387 /*
2388 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2389 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2390 */
2391 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2392}
2393
2394#ifdef CONFIG_X86_32
2395static int io_apic_get_unique_id(int ioapic, int apic_id)
2396{
2397 union IO_APIC_reg_00 reg_00;
2398 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2399 physid_mask_t tmp;
2400 unsigned long flags;
2401 int i = 0;
2402
2403 /*
2404 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2405 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2406 * supports up to 16 on one shared APIC bus.
2407 *
2408 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2409 * advantage of new APIC bus architecture.
2410 */
2411
2412 if (physids_empty(apic_id_map))
2413 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2414
2415 raw_spin_lock_irqsave(&ioapic_lock, flags);
2416 reg_00.raw = io_apic_read(ioapic, 0);
2417 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2418
2419 if (apic_id >= get_physical_broadcast()) {
2420 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2421 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2422 apic_id = reg_00.bits.ID;
2423 }
2424
2425 /*
2426 * Every APIC in a system must have a unique ID or we get lots of nice
2427 * 'stuck on smp_invalidate_needed IPI wait' messages.
2428 */
2429 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2430
2431 for (i = 0; i < get_physical_broadcast(); i++) {
2432 if (!apic->check_apicid_used(&apic_id_map, i))
2433 break;
2434 }
2435
2436 if (i == get_physical_broadcast())
2437 panic("Max apic_id exceeded!\n");
2438
2439 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2440 "trying %d\n", ioapic, apic_id, i);
2441
2442 apic_id = i;
2443 }
2444
2445 apic->apicid_to_cpu_present(apic_id, &tmp);
2446 physids_or(apic_id_map, apic_id_map, tmp);
2447
2448 if (reg_00.bits.ID != apic_id) {
2449 reg_00.bits.ID = apic_id;
2450
2451 raw_spin_lock_irqsave(&ioapic_lock, flags);
2452 io_apic_write(ioapic, 0, reg_00.raw);
2453 reg_00.raw = io_apic_read(ioapic, 0);
2454 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2455
2456 /* Sanity check */
2457 if (reg_00.bits.ID != apic_id) {
2458 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2459 ioapic);
2460 return -1;
2461 }
2462 }
2463
2464 apic_printk(APIC_VERBOSE, KERN_INFO
2465 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2466
2467 return apic_id;
2468}
2469
2470static u8 io_apic_unique_id(int idx, u8 id)
2471{
2472 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2473 !APIC_XAPIC(boot_cpu_apic_version))
2474 return io_apic_get_unique_id(idx, id);
2475 else
2476 return id;
2477}
2478#else
2479static u8 io_apic_unique_id(int idx, u8 id)
2480{
2481 union IO_APIC_reg_00 reg_00;
2482 DECLARE_BITMAP(used, 256);
2483 unsigned long flags;
2484 u8 new_id;
2485 int i;
2486
2487 bitmap_zero(used, 256);
2488 for_each_ioapic(i)
2489 __set_bit(mpc_ioapic_id(i), used);
2490
2491 /* Hand out the requested id if available */
2492 if (!test_bit(id, used))
2493 return id;
2494
2495 /*
2496 * Read the current id from the ioapic and keep it if
2497 * available.
2498 */
2499 raw_spin_lock_irqsave(&ioapic_lock, flags);
2500 reg_00.raw = io_apic_read(idx, 0);
2501 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2502 new_id = reg_00.bits.ID;
2503 if (!test_bit(new_id, used)) {
2504 apic_printk(APIC_VERBOSE, KERN_INFO
2505 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2506 idx, new_id, id);
2507 return new_id;
2508 }
2509
2510 /*
2511 * Get the next free id and write it to the ioapic.
2512 */
2513 new_id = find_first_zero_bit(used, 256);
2514 reg_00.bits.ID = new_id;
2515 raw_spin_lock_irqsave(&ioapic_lock, flags);
2516 io_apic_write(idx, 0, reg_00.raw);
2517 reg_00.raw = io_apic_read(idx, 0);
2518 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2519 /* Sanity check */
2520 BUG_ON(reg_00.bits.ID != new_id);
2521
2522 return new_id;
2523}
2524#endif
2525
2526static int io_apic_get_version(int ioapic)
2527{
2528 union IO_APIC_reg_01 reg_01;
2529 unsigned long flags;
2530
2531 raw_spin_lock_irqsave(&ioapic_lock, flags);
2532 reg_01.raw = io_apic_read(ioapic, 1);
2533 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2534
2535 return reg_01.bits.version;
2536}
2537
2538int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2539{
2540 int ioapic, pin, idx;
2541
2542 if (skip_ioapic_setup)
2543 return -1;
2544
2545 ioapic = mp_find_ioapic(gsi);
2546 if (ioapic < 0)
2547 return -1;
2548
2549 pin = mp_find_ioapic_pin(ioapic, gsi);
2550 if (pin < 0)
2551 return -1;
2552
2553 idx = find_irq_entry(ioapic, pin, mp_INT);
2554 if (idx < 0)
2555 return -1;
2556
2557 *trigger = irq_trigger(idx);
2558 *polarity = irq_polarity(idx);
2559 return 0;
2560}
2561
2562/*
2563 * This function updates target affinity of IOAPIC interrupts to include
2564 * the CPUs which came online during SMP bringup.
2565 */
2566#define IOAPIC_RESOURCE_NAME_SIZE 11
2567
2568static struct resource *ioapic_resources;
2569
2570static struct resource * __init ioapic_setup_resources(void)
2571{
2572 unsigned long n;
2573 struct resource *res;
2574 char *mem;
2575 int i;
2576
2577 if (nr_ioapics == 0)
2578 return NULL;
2579
2580 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2581 n *= nr_ioapics;
2582
2583 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2584 if (!mem)
2585 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2586 res = (void *)mem;
2587
2588 mem += sizeof(struct resource) * nr_ioapics;
2589
2590 for_each_ioapic(i) {
2591 res[i].name = mem;
2592 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2593 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2594 mem += IOAPIC_RESOURCE_NAME_SIZE;
2595 ioapics[i].iomem_res = &res[i];
2596 }
2597
2598 ioapic_resources = res;
2599
2600 return res;
2601}
2602
2603void __init io_apic_init_mappings(void)
2604{
2605 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2606 struct resource *ioapic_res;
2607 int i;
2608
2609 ioapic_res = ioapic_setup_resources();
2610 for_each_ioapic(i) {
2611 if (smp_found_config) {
2612 ioapic_phys = mpc_ioapic_addr(i);
2613#ifdef CONFIG_X86_32
2614 if (!ioapic_phys) {
2615 printk(KERN_ERR
2616 "WARNING: bogus zero IO-APIC "
2617 "address found in MPTABLE, "
2618 "disabling IO/APIC support!\n");
2619 smp_found_config = 0;
2620 skip_ioapic_setup = 1;
2621 goto fake_ioapic_page;
2622 }
2623#endif
2624 } else {
2625#ifdef CONFIG_X86_32
2626fake_ioapic_page:
2627#endif
2628 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2629 PAGE_SIZE);
2630 if (!ioapic_phys)
2631 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2632 __func__, PAGE_SIZE, PAGE_SIZE);
2633 ioapic_phys = __pa(ioapic_phys);
2634 }
2635 set_fixmap_nocache(idx, ioapic_phys);
2636 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2637 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2638 ioapic_phys);
2639 idx++;
2640
2641 ioapic_res->start = ioapic_phys;
2642 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2643 ioapic_res++;
2644 }
2645}
2646
2647void __init ioapic_insert_resources(void)
2648{
2649 int i;
2650 struct resource *r = ioapic_resources;
2651
2652 if (!r) {
2653 if (nr_ioapics > 0)
2654 printk(KERN_ERR
2655 "IO APIC resources couldn't be allocated.\n");
2656 return;
2657 }
2658
2659 for_each_ioapic(i) {
2660 insert_resource(&iomem_resource, r);
2661 r++;
2662 }
2663}
2664
2665int mp_find_ioapic(u32 gsi)
2666{
2667 int i;
2668
2669 if (nr_ioapics == 0)
2670 return -1;
2671
2672 /* Find the IOAPIC that manages this GSI. */
2673 for_each_ioapic(i) {
2674 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2675 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2676 return i;
2677 }
2678
2679 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2680 return -1;
2681}
2682
2683int mp_find_ioapic_pin(int ioapic, u32 gsi)
2684{
2685 struct mp_ioapic_gsi *gsi_cfg;
2686
2687 if (WARN_ON(ioapic < 0))
2688 return -1;
2689
2690 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2691 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2692 return -1;
2693
2694 return gsi - gsi_cfg->gsi_base;
2695}
2696
2697static int bad_ioapic_register(int idx)
2698{
2699 union IO_APIC_reg_00 reg_00;
2700 union IO_APIC_reg_01 reg_01;
2701 union IO_APIC_reg_02 reg_02;
2702
2703 reg_00.raw = io_apic_read(idx, 0);
2704 reg_01.raw = io_apic_read(idx, 1);
2705 reg_02.raw = io_apic_read(idx, 2);
2706
2707 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2708 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2709 mpc_ioapic_addr(idx));
2710 return 1;
2711 }
2712
2713 return 0;
2714}
2715
2716static int find_free_ioapic_entry(void)
2717{
2718 int idx;
2719
2720 for (idx = 0; idx < MAX_IO_APICS; idx++)
2721 if (ioapics[idx].nr_registers == 0)
2722 return idx;
2723
2724 return MAX_IO_APICS;
2725}
2726
2727/**
2728 * mp_register_ioapic - Register an IOAPIC device
2729 * @id: hardware IOAPIC ID
2730 * @address: physical address of IOAPIC register area
2731 * @gsi_base: base of GSI associated with the IOAPIC
2732 * @cfg: configuration information for the IOAPIC
2733 */
2734int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2735 struct ioapic_domain_cfg *cfg)
2736{
2737 bool hotplug = !!ioapic_initialized;
2738 struct mp_ioapic_gsi *gsi_cfg;
2739 int idx, ioapic, entries;
2740 u32 gsi_end;
2741
2742 if (!address) {
2743 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2744 return -EINVAL;
2745 }
2746 for_each_ioapic(ioapic)
2747 if (ioapics[ioapic].mp_config.apicaddr == address) {
2748 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2749 address, ioapic);
2750 return -EEXIST;
2751 }
2752
2753 idx = find_free_ioapic_entry();
2754 if (idx >= MAX_IO_APICS) {
2755 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2756 MAX_IO_APICS, idx);
2757 return -ENOSPC;
2758 }
2759
2760 ioapics[idx].mp_config.type = MP_IOAPIC;
2761 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2762 ioapics[idx].mp_config.apicaddr = address;
2763
2764 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2765 if (bad_ioapic_register(idx)) {
2766 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2767 return -ENODEV;
2768 }
2769
2770 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2771 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2772
2773 /*
2774 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2775 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2776 */
2777 entries = io_apic_get_redir_entries(idx);
2778 gsi_end = gsi_base + entries - 1;
2779 for_each_ioapic(ioapic) {
2780 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2781 if ((gsi_base >= gsi_cfg->gsi_base &&
2782 gsi_base <= gsi_cfg->gsi_end) ||
2783 (gsi_end >= gsi_cfg->gsi_base &&
2784 gsi_end <= gsi_cfg->gsi_end)) {
2785 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2786 gsi_base, gsi_end,
2787 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2788 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2789 return -ENOSPC;
2790 }
2791 }
2792 gsi_cfg = mp_ioapic_gsi_routing(idx);
2793 gsi_cfg->gsi_base = gsi_base;
2794 gsi_cfg->gsi_end = gsi_end;
2795
2796 ioapics[idx].irqdomain = NULL;
2797 ioapics[idx].irqdomain_cfg = *cfg;
2798
2799 /*
2800 * If mp_register_ioapic() is called during early boot stage when
2801 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2802 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2803 */
2804 if (hotplug) {
2805 if (mp_irqdomain_create(idx)) {
2806 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2807 return -ENOMEM;
2808 }
2809 alloc_ioapic_saved_registers(idx);
2810 }
2811
2812 if (gsi_cfg->gsi_end >= gsi_top)
2813 gsi_top = gsi_cfg->gsi_end + 1;
2814 if (nr_ioapics <= idx)
2815 nr_ioapics = idx + 1;
2816
2817 /* Set nr_registers to mark entry present */
2818 ioapics[idx].nr_registers = entries;
2819
2820 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2821 idx, mpc_ioapic_id(idx),
2822 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2823 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2824
2825 return 0;
2826}
2827
2828int mp_unregister_ioapic(u32 gsi_base)
2829{
2830 int ioapic, pin;
2831 int found = 0;
2832
2833 for_each_ioapic(ioapic)
2834 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2835 found = 1;
2836 break;
2837 }
2838 if (!found) {
2839 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2840 return -ENODEV;
2841 }
2842
2843 for_each_pin(ioapic, pin) {
2844 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2845 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2846 struct mp_chip_data *data;
2847
2848 if (irq >= 0) {
2849 data = irq_get_chip_data(irq);
2850 if (data && data->count) {
2851 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2852 pin, ioapic);
2853 return -EBUSY;
2854 }
2855 }
2856 }
2857
2858 /* Mark entry not present */
2859 ioapics[ioapic].nr_registers = 0;
2860 ioapic_destroy_irqdomain(ioapic);
2861 free_ioapic_saved_registers(ioapic);
2862 if (ioapics[ioapic].iomem_res)
2863 release_resource(ioapics[ioapic].iomem_res);
2864 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2865 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2866
2867 return 0;
2868}
2869
2870int mp_ioapic_registered(u32 gsi_base)
2871{
2872 int ioapic;
2873
2874 for_each_ioapic(ioapic)
2875 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2876 return 1;
2877
2878 return 0;
2879}
2880
2881static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2882 struct irq_alloc_info *info)
2883{
2884 if (info && info->ioapic_valid) {
2885 data->trigger = info->ioapic_trigger;
2886 data->polarity = info->ioapic_polarity;
2887 } else if (acpi_get_override_irq(gsi, &data->trigger,
2888 &data->polarity) < 0) {
2889 /* PCI interrupts are always active low level triggered. */
2890 data->trigger = IOAPIC_LEVEL;
2891 data->polarity = IOAPIC_POL_LOW;
2892 }
2893}
2894
2895static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2896 struct IO_APIC_route_entry *entry)
2897{
2898 memset(entry, 0, sizeof(*entry));
2899 entry->delivery_mode = apic->irq_delivery_mode;
2900 entry->dest_mode = apic->irq_dest_mode;
2901 entry->dest = cfg->dest_apicid;
2902 entry->vector = cfg->vector;
2903 entry->trigger = data->trigger;
2904 entry->polarity = data->polarity;
2905 /*
2906 * Mask level triggered irqs. Edge triggered irqs are masked
2907 * by the irq core code in case they fire.
2908 */
2909 if (data->trigger == IOAPIC_LEVEL)
2910 entry->mask = IOAPIC_MASKED;
2911 else
2912 entry->mask = IOAPIC_UNMASKED;
2913}
2914
2915int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2916 unsigned int nr_irqs, void *arg)
2917{
2918 int ret, ioapic, pin;
2919 struct irq_cfg *cfg;
2920 struct irq_data *irq_data;
2921 struct mp_chip_data *data;
2922 struct irq_alloc_info *info = arg;
2923 unsigned long flags;
2924
2925 if (!info || nr_irqs > 1)
2926 return -EINVAL;
2927 irq_data = irq_domain_get_irq_data(domain, virq);
2928 if (!irq_data)
2929 return -EINVAL;
2930
2931 ioapic = mp_irqdomain_ioapic_idx(domain);
2932 pin = info->ioapic_pin;
2933 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2934 return -EEXIST;
2935
2936 data = kzalloc(sizeof(*data), GFP_KERNEL);
2937 if (!data)
2938 return -ENOMEM;
2939
2940 info->ioapic_entry = &data->entry;
2941 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2942 if (ret < 0) {
2943 kfree(data);
2944 return ret;
2945 }
2946
2947 INIT_LIST_HEAD(&data->irq_2_pin);
2948 irq_data->hwirq = info->ioapic_pin;
2949 irq_data->chip = (domain->parent == x86_vector_domain) ?
2950 &ioapic_chip : &ioapic_ir_chip;
2951 irq_data->chip_data = data;
2952 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2953
2954 cfg = irqd_cfg(irq_data);
2955 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2956
2957 local_irq_save(flags);
2958 if (info->ioapic_entry)
2959 mp_setup_entry(cfg, data, info->ioapic_entry);
2960 mp_register_handler(virq, data->trigger);
2961 if (virq < nr_legacy_irqs())
2962 legacy_pic->mask(virq);
2963 local_irq_restore(flags);
2964
2965 apic_printk(APIC_VERBOSE, KERN_DEBUG
2966 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2967 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2968 virq, data->trigger, data->polarity, cfg->dest_apicid);
2969
2970 return 0;
2971}
2972
2973void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2974 unsigned int nr_irqs)
2975{
2976 struct irq_data *irq_data;
2977 struct mp_chip_data *data;
2978
2979 BUG_ON(nr_irqs != 1);
2980 irq_data = irq_domain_get_irq_data(domain, virq);
2981 if (irq_data && irq_data->chip_data) {
2982 data = irq_data->chip_data;
2983 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
2984 (int)irq_data->hwirq);
2985 WARN_ON(!list_empty(&data->irq_2_pin));
2986 kfree(irq_data->chip_data);
2987 }
2988 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2989}
2990
2991int mp_irqdomain_activate(struct irq_domain *domain,
2992 struct irq_data *irq_data, bool reserve)
2993{
2994 unsigned long flags;
2995
2996 raw_spin_lock_irqsave(&ioapic_lock, flags);
2997 ioapic_configure_entry(irq_data);
2998 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2999 return 0;
3000}
3001
3002void mp_irqdomain_deactivate(struct irq_domain *domain,
3003 struct irq_data *irq_data)
3004{
3005 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3006 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3007 (int)irq_data->hwirq);
3008}
3009
3010int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3011{
3012 return (int)(long)domain->host_data;
3013}
3014
3015const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3016 .alloc = mp_irqdomain_alloc,
3017 .free = mp_irqdomain_free,
3018 .activate = mp_irqdomain_activate,
3019 .deactivate = mp_irqdomain_deactivate,
3020};
3021