1 | /* |
2 | * Copyright 2012-16 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "core_types.h" |
27 | #include "clk_mgr_internal.h" |
28 | |
29 | #include "dce/dce_11_2_d.h" |
30 | #include "dce/dce_11_2_sh_mask.h" |
31 | #include "dce100/dce_clk_mgr.h" |
32 | #include "dce110/dce110_clk_mgr.h" |
33 | #include "dce112_clk_mgr.h" |
34 | #include "dal_asic_id.h" |
35 | |
36 | /* set register offset */ |
37 | #define SR(reg_name)\ |
38 | .reg_name = mm ## reg_name |
39 | |
40 | /* set register offset with instance */ |
41 | #define SRI(reg_name, block, id)\ |
42 | .reg_name = mm ## block ## id ## _ ## reg_name |
43 | |
44 | static const struct clk_mgr_registers disp_clk_regs = { |
45 | CLK_COMMON_REG_LIST_DCE_BASE() |
46 | }; |
47 | |
48 | static const struct clk_mgr_shift disp_clk_shift = { |
49 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) |
50 | }; |
51 | |
52 | static const struct clk_mgr_mask disp_clk_mask = { |
53 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) |
54 | }; |
55 | |
56 | static const struct state_dependent_clocks dce112_max_clks_by_state[] = { |
57 | /*ClocksStateInvalid - should not be used*/ |
58 | { .display_clk_khz = 0, .pixel_clk_khz = 0 }, |
59 | /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ |
60 | { .display_clk_khz = 389189, .pixel_clk_khz = 346672 }, |
61 | /*ClocksStateLow*/ |
62 | { .display_clk_khz = 459000, .pixel_clk_khz = 400000 }, |
63 | /*ClocksStateNominal*/ |
64 | { .display_clk_khz = 667000, .pixel_clk_khz = 600000 }, |
65 | /*ClocksStatePerformance*/ |
66 | { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; |
67 | |
68 | |
69 | //TODO: remove use the two broken down functions |
70 | int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) |
71 | { |
72 | struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); |
73 | struct bp_set_dce_clock_parameters dce_clk_params; |
74 | struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; |
75 | struct dc *dc = clk_mgr_base->ctx->dc; |
76 | struct dmcu *dmcu = dc->res_pool->dmcu; |
77 | int actual_clock = requested_clk_khz; |
78 | /* Prepare to program display clock*/ |
79 | memset(&dce_clk_params, 0, sizeof(dce_clk_params)); |
80 | |
81 | /* Make sure requested clock isn't lower than minimum threshold*/ |
82 | requested_clk_khz = max(requested_clk_khz, |
83 | clk_mgr_dce->base.dentist_vco_freq_khz / 62); |
84 | |
85 | dce_clk_params.target_clock_frequency = requested_clk_khz; |
86 | dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; |
87 | dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; |
88 | |
89 | bp->funcs->set_dce_clock(bp, &dce_clk_params); |
90 | actual_clock = dce_clk_params.target_clock_frequency; |
91 | |
92 | /* |
93 | * from power down, we need mark the clock state as ClocksStateNominal |
94 | * from HWReset, so when resume we will call pplib voltage regulator. |
95 | */ |
96 | if (requested_clk_khz == 0) |
97 | clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; |
98 | |
99 | /*Program DP ref Clock*/ |
100 | /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ |
101 | dce_clk_params.target_clock_frequency = 0; |
102 | dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; |
103 | |
104 | if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && |
105 | ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) |
106 | dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = |
107 | (dce_clk_params.pll_id == |
108 | CLOCK_SOURCE_COMBO_DISPLAY_PLL0); |
109 | else |
110 | dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; |
111 | |
112 | bp->funcs->set_dce_clock(bp, &dce_clk_params); |
113 | |
114 | if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { |
115 | if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock) |
116 | dmcu->funcs->set_psr_wait_loop(dmcu, |
117 | actual_clock / 1000 / 7); |
118 | } |
119 | |
120 | clk_mgr_dce->dfs_bypass_disp_clk = actual_clock; |
121 | return actual_clock; |
122 | } |
123 | |
124 | int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) |
125 | { |
126 | struct bp_set_dce_clock_parameters dce_clk_params; |
127 | struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; |
128 | struct dc *dc = clk_mgr->base.ctx->dc; |
129 | struct dmcu *dmcu = dc->res_pool->dmcu; |
130 | int actual_clock = requested_clk_khz; |
131 | /* Prepare to program display clock*/ |
132 | memset(&dce_clk_params, 0, sizeof(dce_clk_params)); |
133 | |
134 | /* Make sure requested clock isn't lower than minimum threshold*/ |
135 | if (requested_clk_khz > 0) |
136 | requested_clk_khz = max(requested_clk_khz, |
137 | clk_mgr->base.dentist_vco_freq_khz / 62); |
138 | |
139 | dce_clk_params.target_clock_frequency = requested_clk_khz; |
140 | dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; |
141 | dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; |
142 | |
143 | bp->funcs->set_dce_clock(bp, &dce_clk_params); |
144 | actual_clock = dce_clk_params.target_clock_frequency; |
145 | |
146 | /* |
147 | * from power down, we need mark the clock state as ClocksStateNominal |
148 | * from HWReset, so when resume we will call pplib voltage regulator. |
149 | */ |
150 | if (requested_clk_khz == 0) |
151 | clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; |
152 | |
153 | |
154 | if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { |
155 | if (clk_mgr->dfs_bypass_disp_clk != actual_clock) |
156 | dmcu->funcs->set_psr_wait_loop(dmcu, |
157 | actual_clock / 1000 / 7); |
158 | } |
159 | |
160 | clk_mgr->dfs_bypass_disp_clk = actual_clock; |
161 | return actual_clock; |
162 | |
163 | } |
164 | |
165 | int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) |
166 | { |
167 | struct bp_set_dce_clock_parameters dce_clk_params; |
168 | struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; |
169 | |
170 | memset(&dce_clk_params, 0, sizeof(dce_clk_params)); |
171 | |
172 | /*Program DP ref Clock*/ |
173 | /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ |
174 | dce_clk_params.target_clock_frequency = 0; |
175 | dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; |
176 | dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; |
177 | if (!((clk_mgr->base.ctx->asic_id.chip_family == FAMILY_AI) && |
178 | ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))) |
179 | dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = |
180 | (dce_clk_params.pll_id == |
181 | CLOCK_SOURCE_COMBO_DISPLAY_PLL0); |
182 | else |
183 | dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; |
184 | |
185 | bp->funcs->set_dce_clock(bp, &dce_clk_params); |
186 | |
187 | /* Returns the dp_refclk that was set */ |
188 | return dce_clk_params.target_clock_frequency; |
189 | } |
190 | |
191 | static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, |
192 | struct dc_state *context, |
193 | bool safe_to_lower) |
194 | { |
195 | struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); |
196 | struct dm_pp_power_level_change_request level_change_req; |
197 | int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; |
198 | |
199 | /*TODO: W/A for dal3 linux, investigate why this works */ |
200 | if (!clk_mgr_dce->dfs_bypass_active) |
201 | patched_disp_clk = patched_disp_clk * 115 / 100; |
202 | |
203 | level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); |
204 | /* get max clock state from PPLIB */ |
205 | if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) |
206 | || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { |
207 | if (dm_pp_apply_power_level_change_request(ctx: clk_mgr_base->ctx, level_change_req: &level_change_req)) |
208 | clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; |
209 | } |
210 | |
211 | if (should_set_clock(safe_to_lower, calc_clk: patched_disp_clk, cur_clk: clk_mgr_base->clks.dispclk_khz)) { |
212 | patched_disp_clk = dce112_set_clock(clk_mgr_base, requested_clk_khz: patched_disp_clk); |
213 | clk_mgr_base->clks.dispclk_khz = patched_disp_clk; |
214 | } |
215 | dce11_pplib_apply_display_requirements(dc: clk_mgr_base->ctx->dc, context); |
216 | } |
217 | |
218 | static struct clk_mgr_funcs dce112_funcs = { |
219 | .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, |
220 | .update_clocks = dce112_update_clocks |
221 | }; |
222 | |
223 | void dce112_clk_mgr_construct( |
224 | struct dc_context *ctx, |
225 | struct clk_mgr_internal *clk_mgr) |
226 | { |
227 | dce_clk_mgr_construct(ctx, clk_mgr_dce: clk_mgr); |
228 | |
229 | memcpy(clk_mgr->max_clks_by_state, |
230 | dce112_max_clks_by_state, |
231 | sizeof(dce112_max_clks_by_state)); |
232 | |
233 | clk_mgr->regs = &disp_clk_regs; |
234 | clk_mgr->clk_mgr_shift = &disp_clk_shift; |
235 | clk_mgr->clk_mgr_mask = &disp_clk_mask; |
236 | clk_mgr->base.funcs = &dce112_funcs; |
237 | } |
238 | |