1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
2 | /* Copyright(c) 2019-2022 Realtek Corporation |
3 | */ |
4 | |
5 | #include "coex.h" |
6 | #include "fw.h" |
7 | #include "mac.h" |
8 | #include "phy.h" |
9 | #include "reg.h" |
10 | #include "rtw8852b.h" |
11 | #include "rtw8852b_rfk.h" |
12 | #include "rtw8852b_table.h" |
13 | #include "txrx.h" |
14 | |
15 | #define RTW8852B_FW_FORMAT_MAX 1 |
16 | #define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw" |
17 | #define RTW8852B_MODULE_FIRMWARE \ |
18 | RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin" |
19 | |
20 | static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = { |
21 | {5, 341, grp_0}, /* ACH 0 */ |
22 | {5, 341, grp_0}, /* ACH 1 */ |
23 | {4, 342, grp_0}, /* ACH 2 */ |
24 | {4, 342, grp_0}, /* ACH 3 */ |
25 | {0, 0, grp_0}, /* ACH 4 */ |
26 | {0, 0, grp_0}, /* ACH 5 */ |
27 | {0, 0, grp_0}, /* ACH 6 */ |
28 | {0, 0, grp_0}, /* ACH 7 */ |
29 | {4, 342, grp_0}, /* B0MGQ */ |
30 | {4, 342, grp_0}, /* B0HIQ */ |
31 | {0, 0, grp_0}, /* B1MGQ */ |
32 | {0, 0, grp_0}, /* B1HIQ */ |
33 | {40, 0, 0} /* FWCMDQ */ |
34 | }; |
35 | |
36 | static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = { |
37 | 446, /* Group 0 */ |
38 | 0, /* Group 1 */ |
39 | 446, /* Public Max */ |
40 | 0 /* WP threshold */ |
41 | }; |
42 | |
43 | static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = { |
44 | [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie, |
45 | &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, |
46 | [RTW89_QTA_DLFW] = {NULL, NULL, .prec_cfg: &rtw89_mac_size.hfc_preccfg_pcie, |
47 | .mode: RTW89_HCIFC_POH}, |
48 | [RTW89_QTA_INVALID] = {NULL}, |
49 | }; |
50 | |
51 | static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = { |
52 | [RTW89_QTA_SCC] = {.mode: RTW89_QTA_SCC, .wde_size: &rtw89_mac_size.wde_size7, |
53 | .ple_size: &rtw89_mac_size.ple_size6, .wde_min_qt: &rtw89_mac_size.wde_qt7, |
54 | .wde_max_qt: &rtw89_mac_size.wde_qt7, .ple_min_qt: &rtw89_mac_size.ple_qt18, |
55 | .ple_max_qt: &rtw89_mac_size.ple_qt58}, |
56 | [RTW89_QTA_WOW] = {.mode: RTW89_QTA_WOW, .wde_size: &rtw89_mac_size.wde_size7, |
57 | .ple_size: &rtw89_mac_size.ple_size6, .wde_min_qt: &rtw89_mac_size.wde_qt7, |
58 | .wde_max_qt: &rtw89_mac_size.wde_qt7, .ple_min_qt: &rtw89_mac_size.ple_qt18, |
59 | .ple_max_qt: &rtw89_mac_size.ple_qt_52b_wow}, |
60 | [RTW89_QTA_DLFW] = {.mode: RTW89_QTA_DLFW, .wde_size: &rtw89_mac_size.wde_size9, |
61 | .ple_size: &rtw89_mac_size.ple_size8, .wde_min_qt: &rtw89_mac_size.wde_qt4, |
62 | .wde_max_qt: &rtw89_mac_size.wde_qt4, .ple_min_qt: &rtw89_mac_size.ple_qt13, |
63 | .ple_max_qt: &rtw89_mac_size.ple_qt13}, |
64 | [RTW89_QTA_INVALID] = {.mode: RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, |
65 | NULL}, |
66 | }; |
67 | |
68 | static const struct rtw89_reg3_def rtw8852b_pmac_ht20_mcs7_tbl[] = { |
69 | {0x4580, 0x0000ffff, 0x0}, |
70 | {0x4580, 0xffff0000, 0x0}, |
71 | {0x4584, 0x0000ffff, 0x0}, |
72 | {0x4584, 0xffff0000, 0x0}, |
73 | {0x4580, 0x0000ffff, 0x1}, |
74 | {0x4578, 0x00ffffff, 0x2018b}, |
75 | {0x4570, 0x03ffffff, 0x7}, |
76 | {0x4574, 0x03ffffff, 0x32407}, |
77 | {0x45b8, 0x00000010, 0x0}, |
78 | {0x45b8, 0x00000100, 0x0}, |
79 | {0x45b8, 0x00000080, 0x0}, |
80 | {0x45b8, 0x00000008, 0x0}, |
81 | {0x45a0, 0x0000ff00, 0x0}, |
82 | {0x45a0, 0xff000000, 0x1}, |
83 | {0x45a4, 0x0000ff00, 0x2}, |
84 | {0x45a4, 0xff000000, 0x3}, |
85 | {0x45b8, 0x00000020, 0x0}, |
86 | {0x4568, 0xe0000000, 0x0}, |
87 | {0x45b8, 0x00000002, 0x1}, |
88 | {0x456c, 0xe0000000, 0x0}, |
89 | {0x45b4, 0x00006000, 0x0}, |
90 | {0x45b4, 0x00001800, 0x1}, |
91 | {0x45b8, 0x00000040, 0x0}, |
92 | {0x45b8, 0x00000004, 0x0}, |
93 | {0x45b8, 0x00000200, 0x0}, |
94 | {0x4598, 0xf8000000, 0x0}, |
95 | {0x45b8, 0x00100000, 0x0}, |
96 | {0x45a8, 0x00000fc0, 0x0}, |
97 | {0x45b8, 0x00200000, 0x0}, |
98 | {0x45b0, 0x00000038, 0x0}, |
99 | {0x45b0, 0x000001c0, 0x0}, |
100 | {0x45a0, 0x000000ff, 0x0}, |
101 | {0x45b8, 0x00400000, 0x0}, |
102 | {0x4590, 0x000007ff, 0x0}, |
103 | {0x45b0, 0x00000e00, 0x0}, |
104 | {0x45ac, 0x0000001f, 0x0}, |
105 | {0x45b8, 0x00800000, 0x0}, |
106 | {0x45a8, 0x0003f000, 0x0}, |
107 | {0x45b8, 0x01000000, 0x0}, |
108 | {0x45b0, 0x00007000, 0x0}, |
109 | {0x45b0, 0x00038000, 0x0}, |
110 | {0x45a0, 0x00ff0000, 0x0}, |
111 | {0x45b8, 0x02000000, 0x0}, |
112 | {0x4590, 0x003ff800, 0x0}, |
113 | {0x45b0, 0x001c0000, 0x0}, |
114 | {0x45ac, 0x000003e0, 0x0}, |
115 | {0x45b8, 0x04000000, 0x0}, |
116 | {0x45a8, 0x00fc0000, 0x0}, |
117 | {0x45b8, 0x08000000, 0x0}, |
118 | {0x45b0, 0x00e00000, 0x0}, |
119 | {0x45b0, 0x07000000, 0x0}, |
120 | {0x45a4, 0x000000ff, 0x0}, |
121 | {0x45b8, 0x10000000, 0x0}, |
122 | {0x4594, 0x000007ff, 0x0}, |
123 | {0x45b0, 0x38000000, 0x0}, |
124 | {0x45ac, 0x00007c00, 0x0}, |
125 | {0x45b8, 0x20000000, 0x0}, |
126 | {0x45a8, 0x3f000000, 0x0}, |
127 | {0x45b8, 0x40000000, 0x0}, |
128 | {0x45b4, 0x00000007, 0x0}, |
129 | {0x45b4, 0x00000038, 0x0}, |
130 | {0x45a4, 0x00ff0000, 0x0}, |
131 | {0x45b8, 0x80000000, 0x0}, |
132 | {0x4594, 0x003ff800, 0x0}, |
133 | {0x45b4, 0x000001c0, 0x0}, |
134 | {0x4598, 0xf8000000, 0x0}, |
135 | {0x45b8, 0x00100000, 0x0}, |
136 | {0x45a8, 0x00000fc0, 0x7}, |
137 | {0x45b8, 0x00200000, 0x0}, |
138 | {0x45b0, 0x00000038, 0x0}, |
139 | {0x45b0, 0x000001c0, 0x0}, |
140 | {0x45a0, 0x000000ff, 0x0}, |
141 | {0x45b4, 0x06000000, 0x0}, |
142 | {0x45b0, 0x00000007, 0x0}, |
143 | {0x45b8, 0x00080000, 0x0}, |
144 | {0x45a8, 0x0000003f, 0x0}, |
145 | {0x457c, 0xffe00000, 0x1}, |
146 | {0x4530, 0xffffffff, 0x0}, |
147 | {0x4588, 0x00003fff, 0x0}, |
148 | {0x4598, 0x000001ff, 0x0}, |
149 | {0x4534, 0xffffffff, 0x0}, |
150 | {0x4538, 0xffffffff, 0x0}, |
151 | {0x453c, 0xffffffff, 0x0}, |
152 | {0x4588, 0x0fffc000, 0x0}, |
153 | {0x4598, 0x0003fe00, 0x0}, |
154 | {0x4540, 0xffffffff, 0x0}, |
155 | {0x4544, 0xffffffff, 0x0}, |
156 | {0x4548, 0xffffffff, 0x0}, |
157 | {0x458c, 0x00003fff, 0x0}, |
158 | {0x4598, 0x07fc0000, 0x0}, |
159 | {0x454c, 0xffffffff, 0x0}, |
160 | {0x4550, 0xffffffff, 0x0}, |
161 | {0x4554, 0xffffffff, 0x0}, |
162 | {0x458c, 0x0fffc000, 0x0}, |
163 | {0x459c, 0x000001ff, 0x0}, |
164 | {0x4558, 0xffffffff, 0x0}, |
165 | {0x455c, 0xffffffff, 0x0}, |
166 | {0x4530, 0xffffffff, 0x4e790001}, |
167 | {0x4588, 0x00003fff, 0x0}, |
168 | {0x4598, 0x000001ff, 0x1}, |
169 | {0x4534, 0xffffffff, 0x0}, |
170 | {0x4538, 0xffffffff, 0x4b}, |
171 | {0x45ac, 0x38000000, 0x7}, |
172 | {0x4588, 0xf0000000, 0x0}, |
173 | {0x459c, 0x7e000000, 0x0}, |
174 | {0x45b8, 0x00040000, 0x0}, |
175 | {0x45b8, 0x00020000, 0x0}, |
176 | {0x4590, 0xffc00000, 0x0}, |
177 | {0x45b8, 0x00004000, 0x0}, |
178 | {0x4578, 0xff000000, 0x0}, |
179 | {0x45b8, 0x00000400, 0x0}, |
180 | {0x45b8, 0x00000800, 0x0}, |
181 | {0x45b8, 0x00001000, 0x0}, |
182 | {0x45b8, 0x00002000, 0x0}, |
183 | {0x45b4, 0x00018000, 0x0}, |
184 | {0x45ac, 0x07800000, 0x0}, |
185 | {0x45b4, 0x00000600, 0x2}, |
186 | {0x459c, 0x0001fe00, 0x80}, |
187 | {0x45ac, 0x00078000, 0x3}, |
188 | {0x459c, 0x01fe0000, 0x1}, |
189 | }; |
190 | |
191 | static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = { |
192 | {0x46D0, GENMASK(1, 0), 0x3}, |
193 | {0x4790, GENMASK(1, 0), 0x3}, |
194 | {0x4AD4, GENMASK(31, 0), 0xf}, |
195 | {0x4AE0, GENMASK(31, 0), 0xf}, |
196 | {0x4688, GENMASK(31, 24), 0x80}, |
197 | {0x476C, GENMASK(31, 24), 0x80}, |
198 | {0x4694, GENMASK(7, 0), 0x80}, |
199 | {0x4694, GENMASK(15, 8), 0x80}, |
200 | {0x4778, GENMASK(7, 0), 0x80}, |
201 | {0x4778, GENMASK(15, 8), 0x80}, |
202 | {0x4AE4, GENMASK(23, 0), 0x780D1E}, |
203 | {0x4AEC, GENMASK(23, 0), 0x780D1E}, |
204 | {0x469C, GENMASK(31, 26), 0x34}, |
205 | {0x49F0, GENMASK(31, 26), 0x34}, |
206 | }; |
207 | |
208 | static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs); |
209 | |
210 | static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = { |
211 | {0x46D0, GENMASK(1, 0), 0x0}, |
212 | {0x4790, GENMASK(1, 0), 0x0}, |
213 | {0x4AD4, GENMASK(31, 0), 0x60}, |
214 | {0x4AE0, GENMASK(31, 0), 0x60}, |
215 | {0x4688, GENMASK(31, 24), 0x1a}, |
216 | {0x476C, GENMASK(31, 24), 0x1a}, |
217 | {0x4694, GENMASK(7, 0), 0x2a}, |
218 | {0x4694, GENMASK(15, 8), 0x2a}, |
219 | {0x4778, GENMASK(7, 0), 0x2a}, |
220 | {0x4778, GENMASK(15, 8), 0x2a}, |
221 | {0x4AE4, GENMASK(23, 0), 0x79E99E}, |
222 | {0x4AEC, GENMASK(23, 0), 0x79E99E}, |
223 | {0x469C, GENMASK(31, 26), 0x26}, |
224 | {0x49F0, GENMASK(31, 26), 0x26}, |
225 | }; |
226 | |
227 | static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs); |
228 | |
229 | static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = { |
230 | R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, |
231 | R_AX_H2CREG_DATA3 |
232 | }; |
233 | |
234 | static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = { |
235 | R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, |
236 | R_AX_C2HREG_DATA3 |
237 | }; |
238 | |
239 | static const struct rtw89_page_regs rtw8852b_page_regs = { |
240 | .hci_fc_ctrl = R_AX_HCI_FC_CTRL, |
241 | .ch_page_ctrl = R_AX_CH_PAGE_CTRL, |
242 | .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, |
243 | .ach_page_info = R_AX_ACH0_PAGE_INFO, |
244 | .pub_page_info3 = R_AX_PUB_PAGE_INFO3, |
245 | .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, |
246 | .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, |
247 | .pub_page_info1 = R_AX_PUB_PAGE_INFO1, |
248 | .pub_page_info2 = R_AX_PUB_PAGE_INFO2, |
249 | .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, |
250 | .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, |
251 | .wp_page_info1 = R_AX_WP_PAGE_INFO1, |
252 | }; |
253 | |
254 | static const struct rtw89_reg_def rtw8852b_dcfo_comp = { |
255 | R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK |
256 | }; |
257 | |
258 | static const struct rtw89_imr_info rtw8852b_imr_info = { |
259 | .wdrls_imr_set = B_AX_WDRLS_IMR_SET, |
260 | .wsec_imr_reg = R_AX_SEC_DEBUG, |
261 | .wsec_imr_set = B_AX_IMR_ERROR, |
262 | .mpdu_tx_imr_set = 0, |
263 | .mpdu_rx_imr_set = 0, |
264 | .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, |
265 | .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, |
266 | .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, |
267 | .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, |
268 | .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, |
269 | .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, |
270 | .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, |
271 | .wde_imr_clr = B_AX_WDE_IMR_CLR, |
272 | .wde_imr_set = B_AX_WDE_IMR_SET, |
273 | .ple_imr_clr = B_AX_PLE_IMR_CLR, |
274 | .ple_imr_set = B_AX_PLE_IMR_SET, |
275 | .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, |
276 | .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, |
277 | .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, |
278 | .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, |
279 | .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, |
280 | .other_disp_imr_set = 0, |
281 | .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, |
282 | .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, |
283 | .bbrpt_err_imr_set = 0, |
284 | .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, |
285 | .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, |
286 | .ptcl_imr_set = B_AX_PTCL_IMR_SET, |
287 | .cdma_imr_0_reg = R_AX_DLE_CTRL, |
288 | .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, |
289 | .cdma_imr_0_set = B_AX_DLE_IMR_SET, |
290 | .cdma_imr_1_reg = 0, |
291 | .cdma_imr_1_clr = 0, |
292 | .cdma_imr_1_set = 0, |
293 | .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, |
294 | .phy_intf_imr_clr = 0, |
295 | .phy_intf_imr_set = 0, |
296 | .rmac_imr_reg = R_AX_RMAC_ERR_ISR, |
297 | .rmac_imr_clr = B_AX_RMAC_IMR_CLR, |
298 | .rmac_imr_set = B_AX_RMAC_IMR_SET, |
299 | .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, |
300 | .tmac_imr_clr = B_AX_TMAC_IMR_CLR, |
301 | .tmac_imr_set = B_AX_TMAC_IMR_SET, |
302 | }; |
303 | |
304 | static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = { |
305 | .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, |
306 | .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, |
307 | }; |
308 | |
309 | static const struct rtw89_dig_regs rtw8852b_dig_regs = { |
310 | .seg0_pd_reg = R_SEG0R_PD_V1, |
311 | .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, |
312 | .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, |
313 | .bmode_pd_reg = R_BMODE_PDTH_EN_V1, |
314 | .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, |
315 | .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, |
316 | .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, |
317 | .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, |
318 | .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, |
319 | .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, |
320 | .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, |
321 | .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, |
322 | .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, |
323 | .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, |
324 | B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
325 | .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, |
326 | B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
327 | .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, |
328 | B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
329 | .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, |
330 | B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
331 | }; |
332 | |
333 | static const struct rtw89_edcca_regs rtw8852b_edcca_regs = { |
334 | .edcca_level = R_SEG0R_EDCCA_LVL_V1, |
335 | .edcca_mask = B_EDCCA_LVL_MSK0, |
336 | .edcca_p_mask = B_EDCCA_LVL_MSK1, |
337 | .ppdu_level = R_SEG0R_EDCCA_LVL_V1, |
338 | .ppdu_mask = B_EDCCA_LVL_MSK3, |
339 | .rpt_a = R_EDCCA_RPT_A, |
340 | .rpt_b = R_EDCCA_RPT_B, |
341 | .rpt_sel = R_EDCCA_RPT_SEL, |
342 | .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, |
343 | .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, |
344 | .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, |
345 | }; |
346 | |
347 | static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = { |
348 | {255, 0, 0, 7}, /* 0 -> original */ |
349 | {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ |
350 | {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ |
351 | {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ |
352 | {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ |
353 | {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ |
354 | {6, 1, 0, 7}, |
355 | {13, 1, 0, 7}, |
356 | {13, 1, 0, 7} |
357 | }; |
358 | |
359 | static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = { |
360 | {255, 0, 0, 7}, /* 0 -> original */ |
361 | {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ |
362 | {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ |
363 | {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ |
364 | {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ |
365 | {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ |
366 | {255, 1, 0, 7}, |
367 | {255, 1, 0, 7}, |
368 | {255, 1, 0, 7} |
369 | }; |
370 | |
371 | static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = { |
372 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), |
373 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), |
374 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), |
375 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), |
376 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), |
377 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), |
378 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), |
379 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), |
380 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), |
381 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), |
382 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), |
383 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), |
384 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), |
385 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), |
386 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), |
387 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), |
388 | }; |
389 | |
390 | static const u8 [BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; |
391 | static const u8 [BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; |
392 | |
393 | static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev) |
394 | { |
395 | u32 val32; |
396 | u32 ret; |
397 | |
398 | rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | |
399 | B_AX_AFSM_PCIE_SUS_EN); |
400 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); |
401 | rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); |
402 | rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); |
403 | rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); |
404 | |
405 | ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, |
406 | 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); |
407 | if (ret) |
408 | return ret; |
409 | |
410 | rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN); |
411 | ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN, |
412 | 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL); |
413 | if (ret) |
414 | return ret; |
415 | |
416 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, data: 0x1); |
417 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, data: 0x3); |
418 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); |
419 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); |
420 | |
421 | ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), |
422 | 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); |
423 | if (ret) |
424 | return ret; |
425 | |
426 | rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
427 | rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
428 | rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
429 | rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
430 | |
431 | rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
432 | rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); |
433 | |
434 | rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); |
435 | |
436 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, |
437 | XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); |
438 | if (ret) |
439 | return ret; |
440 | |
441 | rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); |
442 | |
443 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, |
444 | XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); |
445 | if (ret) |
446 | return ret; |
447 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, |
448 | XTAL_SI_OFF_WEI); |
449 | if (ret) |
450 | return ret; |
451 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, |
452 | XTAL_SI_OFF_EI); |
453 | if (ret) |
454 | return ret; |
455 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_RFC2RF); |
456 | if (ret) |
457 | return ret; |
458 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, |
459 | XTAL_SI_PON_WEI); |
460 | if (ret) |
461 | return ret; |
462 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, |
463 | XTAL_SI_PON_EI); |
464 | if (ret) |
465 | return ret; |
466 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_SRAM2RFC); |
467 | if (ret) |
468 | return ret; |
469 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_SRAM_CTRL, val: 0, XTAL_SI_SRAM_DIS); |
470 | if (ret) |
471 | return ret; |
472 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_XTAL_XMD_2, val: 0, XTAL_SI_LDO_LPS); |
473 | if (ret) |
474 | return ret; |
475 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_XTAL_XMD_4, val: 0, XTAL_SI_LPS_CAP); |
476 | if (ret) |
477 | return ret; |
478 | |
479 | rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
480 | rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); |
481 | rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); |
482 | |
483 | fsleep(usecs: 1000); |
484 | |
485 | rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); |
486 | rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
487 | |
488 | if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid) |
489 | goto func_en; |
490 | |
491 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, data: 0x9); |
492 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, data: 0xA); |
493 | |
494 | if (rtwdev->hal.cv == CHIP_CBV) { |
495 | rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
496 | rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, data: 0xA); |
497 | rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
498 | } |
499 | |
500 | func_en: |
501 | rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, |
502 | B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | |
503 | B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | |
504 | B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | |
505 | B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | |
506 | B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | |
507 | B_AX_DMACREG_GCKEN); |
508 | rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, |
509 | B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | |
510 | B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | |
511 | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | |
512 | B_AX_RMAC_EN); |
513 | |
514 | rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, |
515 | PINMUX_EESK_FUNC_SEL_BT_LOG); |
516 | |
517 | return 0; |
518 | } |
519 | |
520 | static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev) |
521 | { |
522 | u32 val32; |
523 | u32 ret; |
524 | |
525 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, |
526 | XTAL_SI_RFC2RF); |
527 | if (ret) |
528 | return ret; |
529 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_OFF_EI); |
530 | if (ret) |
531 | return ret; |
532 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_OFF_WEI); |
533 | if (ret) |
534 | return ret; |
535 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S0, val: 0, XTAL_SI_RF00); |
536 | if (ret) |
537 | return ret; |
538 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S1, val: 0, XTAL_SI_RF10); |
539 | if (ret) |
540 | return ret; |
541 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, |
542 | XTAL_SI_SRAM2RFC); |
543 | if (ret) |
544 | return ret; |
545 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_PON_EI); |
546 | if (ret) |
547 | return ret; |
548 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_PON_WEI); |
549 | if (ret) |
550 | return ret; |
551 | |
552 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); |
553 | rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); |
554 | rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); |
555 | |
556 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_SHDN_WL); |
557 | if (ret) |
558 | return ret; |
559 | |
560 | rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); |
561 | |
562 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_ANAPAR_WL, val: 0, XTAL_SI_GND_SHDN_WL); |
563 | if (ret) |
564 | return ret; |
565 | |
566 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); |
567 | |
568 | ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), |
569 | 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); |
570 | if (ret) |
571 | return ret; |
572 | |
573 | rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); |
574 | rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); |
575 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, data: 0x3); |
576 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); |
577 | |
578 | return 0; |
579 | } |
580 | |
581 | static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse, |
582 | struct rtw8852b_efuse *map) |
583 | { |
584 | ether_addr_copy(dst: efuse->addr, src: map->e.mac_addr); |
585 | efuse->rfe_type = map->rfe_type; |
586 | efuse->xtal_cap = map->xtal_k; |
587 | } |
588 | |
589 | static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev, |
590 | struct rtw8852b_efuse *map) |
591 | { |
592 | struct rtw89_tssi_info *tssi = &rtwdev->tssi; |
593 | struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; |
594 | u8 i, j; |
595 | |
596 | tssi->thermal[RF_PATH_A] = map->path_a_therm; |
597 | tssi->thermal[RF_PATH_B] = map->path_b_therm; |
598 | |
599 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
600 | memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, |
601 | sizeof(ofst[i]->cck_tssi)); |
602 | |
603 | for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) |
604 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, |
605 | fmt: "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n" , |
606 | i, j, tssi->tssi_cck[i][j]); |
607 | |
608 | memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, |
609 | sizeof(ofst[i]->bw40_tssi)); |
610 | memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, |
611 | ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); |
612 | |
613 | for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) |
614 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, |
615 | fmt: "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n" , |
616 | i, j, tssi->tssi_mcs[i][j]); |
617 | } |
618 | } |
619 | |
620 | static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) |
621 | { |
622 | if (high) |
623 | *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), index: 3); |
624 | if (low) |
625 | *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), index: 3); |
626 | |
627 | return data != 0xff; |
628 | } |
629 | |
630 | static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, |
631 | struct rtw8852b_efuse *map) |
632 | { |
633 | struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; |
634 | bool valid = false; |
635 | |
636 | valid |= _decode_efuse_gain(data: map->rx_gain_2g_cck, |
637 | high: &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], |
638 | low: &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); |
639 | valid |= _decode_efuse_gain(data: map->rx_gain_2g_ofdm, |
640 | high: &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], |
641 | low: &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); |
642 | valid |= _decode_efuse_gain(data: map->rx_gain_5g_low, |
643 | high: &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], |
644 | low: &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); |
645 | valid |= _decode_efuse_gain(data: map->rx_gain_5g_mid, |
646 | high: &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], |
647 | low: &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); |
648 | valid |= _decode_efuse_gain(data: map->rx_gain_5g_high, |
649 | high: &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], |
650 | low: &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); |
651 | |
652 | gain->offset_valid = valid; |
653 | } |
654 | |
655 | static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, |
656 | enum rtw89_efuse_block block) |
657 | { |
658 | struct rtw89_efuse *efuse = &rtwdev->efuse; |
659 | struct rtw8852b_efuse *map; |
660 | |
661 | map = (struct rtw8852b_efuse *)log_map; |
662 | |
663 | efuse->country_code[0] = map->country_code[0]; |
664 | efuse->country_code[1] = map->country_code[1]; |
665 | rtw8852b_efuse_parsing_tssi(rtwdev, map); |
666 | rtw8852b_efuse_parsing_gain_offset(rtwdev, map); |
667 | |
668 | switch (rtwdev->hci.type) { |
669 | case RTW89_HCI_TYPE_PCIE: |
670 | rtw8852be_efuse_parsing(efuse, map); |
671 | break; |
672 | default: |
673 | return -EOPNOTSUPP; |
674 | } |
675 | |
676 | rtw89_info(rtwdev, "chip rfe_type is %d\n" , efuse->rfe_type); |
677 | |
678 | return 0; |
679 | } |
680 | |
681 | static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map) |
682 | { |
683 | #define PWR_K_CHK_OFFSET 0x5E9 |
684 | #define PWR_K_CHK_VALUE 0xAA |
685 | u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr; |
686 | |
687 | if (phycap_map[offset] == PWR_K_CHK_VALUE) |
688 | rtwdev->efuse.power_k_valid = true; |
689 | } |
690 | |
691 | static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) |
692 | { |
693 | struct rtw89_tssi_info *tssi = &rtwdev->tssi; |
694 | static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB}; |
695 | u32 addr = rtwdev->chip->phycap_addr; |
696 | bool pg = false; |
697 | u32 ofst; |
698 | u8 i, j; |
699 | |
700 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
701 | for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { |
702 | /* addrs are in decreasing order */ |
703 | ofst = tssi_trim_addr[i] - addr - j; |
704 | tssi->tssi_trim[i][j] = phycap_map[ofst]; |
705 | |
706 | if (phycap_map[ofst] != 0xff) |
707 | pg = true; |
708 | } |
709 | } |
710 | |
711 | if (!pg) { |
712 | memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); |
713 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, |
714 | fmt: "[TSSI][TRIM] no PG, set all trim info to 0\n" ); |
715 | } |
716 | |
717 | for (i = 0; i < RF_PATH_NUM_8852B; i++) |
718 | for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) |
719 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, |
720 | fmt: "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n" , |
721 | i, j, tssi->tssi_trim[i][j], |
722 | tssi_trim_addr[i] - j); |
723 | } |
724 | |
725 | static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, |
726 | u8 *phycap_map) |
727 | { |
728 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
729 | static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC}; |
730 | u32 addr = rtwdev->chip->phycap_addr; |
731 | u8 i; |
732 | |
733 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
734 | info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; |
735 | |
736 | rtw89_debug(rtwdev, mask: RTW89_DBG_RFK, |
737 | fmt: "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n" , |
738 | i, info->thermal_trim[i]); |
739 | |
740 | if (info->thermal_trim[i] != 0xff) |
741 | info->pg_thermal_trim = true; |
742 | } |
743 | } |
744 | |
745 | static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev) |
746 | { |
747 | #define __thm_setting(raw) \ |
748 | ({ \ |
749 | u8 __v = (raw); \ |
750 | ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ |
751 | }) |
752 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
753 | u8 i, val; |
754 | |
755 | if (!info->pg_thermal_trim) { |
756 | rtw89_debug(rtwdev, mask: RTW89_DBG_RFK, |
757 | fmt: "[THERMAL][TRIM] no PG, do nothing\n" ); |
758 | |
759 | return; |
760 | } |
761 | |
762 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
763 | val = __thm_setting(info->thermal_trim[i]); |
764 | rtw89_write_rf(rtwdev, rf_path: i, RR_TM2, RR_TM2_OFF, data: val); |
765 | |
766 | rtw89_debug(rtwdev, mask: RTW89_DBG_RFK, |
767 | fmt: "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n" , |
768 | i, val); |
769 | } |
770 | #undef __thm_setting |
771 | } |
772 | |
773 | static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, |
774 | u8 *phycap_map) |
775 | { |
776 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
777 | static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB}; |
778 | u32 addr = rtwdev->chip->phycap_addr; |
779 | u8 i; |
780 | |
781 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
782 | info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; |
783 | |
784 | rtw89_debug(rtwdev, mask: RTW89_DBG_RFK, |
785 | fmt: "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n" , |
786 | i, info->pa_bias_trim[i]); |
787 | |
788 | if (info->pa_bias_trim[i] != 0xff) |
789 | info->pg_pa_bias_trim = true; |
790 | } |
791 | } |
792 | |
793 | static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev) |
794 | { |
795 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
796 | u8 pabias_2g, pabias_5g; |
797 | u8 i; |
798 | |
799 | if (!info->pg_pa_bias_trim) { |
800 | rtw89_debug(rtwdev, mask: RTW89_DBG_RFK, |
801 | fmt: "[PA_BIAS][TRIM] no PG, do nothing\n" ); |
802 | |
803 | return; |
804 | } |
805 | |
806 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
807 | pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); |
808 | pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); |
809 | |
810 | rtw89_debug(rtwdev, mask: RTW89_DBG_RFK, |
811 | fmt: "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n" , |
812 | i, pabias_2g, pabias_5g); |
813 | |
814 | rtw89_write_rf(rtwdev, rf_path: i, RR_BIASA, RR_BIASA_TXG, data: pabias_2g); |
815 | rtw89_write_rf(rtwdev, rf_path: i, RR_BIASA, RR_BIASA_TXA, data: pabias_5g); |
816 | } |
817 | } |
818 | |
819 | static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) |
820 | { |
821 | static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { |
822 | {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, |
823 | {0x590, 0x58F, 0, 0x58E, 0x58D}, |
824 | }; |
825 | struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; |
826 | u32 phycap_addr = rtwdev->chip->phycap_addr; |
827 | bool valid = false; |
828 | int path, i; |
829 | u8 data; |
830 | |
831 | for (path = 0; path < 2; path++) |
832 | for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { |
833 | if (comp_addrs[path][i] == 0) |
834 | continue; |
835 | |
836 | data = phycap_map[comp_addrs[path][i] - phycap_addr]; |
837 | valid |= _decode_efuse_gain(data, NULL, |
838 | low: &gain->comp[path][i]); |
839 | } |
840 | |
841 | gain->comp_valid = valid; |
842 | } |
843 | |
844 | static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) |
845 | { |
846 | rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map); |
847 | rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map); |
848 | rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map); |
849 | rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); |
850 | rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map); |
851 | |
852 | return 0; |
853 | } |
854 | |
855 | static void rtw8852b_power_trim(struct rtw89_dev *rtwdev) |
856 | { |
857 | rtw8852b_thermal_trim(rtwdev); |
858 | rtw8852b_pa_bias_trim(rtwdev); |
859 | } |
860 | |
861 | static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev, |
862 | const struct rtw89_chan *chan, |
863 | u8 mac_idx) |
864 | { |
865 | u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, band: mac_idx); |
866 | u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, band: mac_idx); |
867 | u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, band: mac_idx); |
868 | u8 txsc20 = 0, txsc40 = 0; |
869 | |
870 | switch (chan->band_width) { |
871 | case RTW89_CHANNEL_WIDTH_80: |
872 | txsc40 = rtw89_phy_get_txsc(rtwdev, chan, dbw: RTW89_CHANNEL_WIDTH_40); |
873 | fallthrough; |
874 | case RTW89_CHANNEL_WIDTH_40: |
875 | txsc20 = rtw89_phy_get_txsc(rtwdev, chan, dbw: RTW89_CHANNEL_WIDTH_20); |
876 | break; |
877 | default: |
878 | break; |
879 | } |
880 | |
881 | switch (chan->band_width) { |
882 | case RTW89_CHANNEL_WIDTH_80: |
883 | rtw89_write8_mask(rtwdev, addr: rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); |
884 | rtw89_write32(rtwdev, addr: sub_carr, data: txsc20 | (txsc40 << 4)); |
885 | break; |
886 | case RTW89_CHANNEL_WIDTH_40: |
887 | rtw89_write8_mask(rtwdev, addr: rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); |
888 | rtw89_write32(rtwdev, addr: sub_carr, data: txsc20); |
889 | break; |
890 | case RTW89_CHANNEL_WIDTH_20: |
891 | rtw89_write8_clr(rtwdev, addr: rf_mod, B_AX_WMAC_RFMOD_MASK); |
892 | rtw89_write32(rtwdev, addr: sub_carr, data: 0); |
893 | break; |
894 | default: |
895 | break; |
896 | } |
897 | |
898 | if (chan->channel > 14) { |
899 | rtw89_write8_clr(rtwdev, addr: chk_rate, B_AX_BAND_MODE); |
900 | rtw89_write8_set(rtwdev, addr: chk_rate, |
901 | B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); |
902 | } else { |
903 | rtw89_write8_set(rtwdev, addr: chk_rate, B_AX_BAND_MODE); |
904 | rtw89_write8_clr(rtwdev, addr: chk_rate, |
905 | B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); |
906 | } |
907 | } |
908 | |
909 | static const u32 rtw8852b_sco_barker_threshold[14] = { |
910 | 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, |
911 | 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 |
912 | }; |
913 | |
914 | static const u32 rtw8852b_sco_cck_threshold[14] = { |
915 | 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, |
916 | 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed |
917 | }; |
918 | |
919 | static void rtw8852b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) |
920 | { |
921 | u8 ch_element = primary_ch - 1; |
922 | |
923 | rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, |
924 | data: rtw8852b_sco_barker_threshold[ch_element]); |
925 | rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, |
926 | data: rtw8852b_sco_cck_threshold[ch_element]); |
927 | } |
928 | |
929 | static u8 rtw8852b_sco_mapping(u8 central_ch) |
930 | { |
931 | if (central_ch == 1) |
932 | return 109; |
933 | else if (central_ch >= 2 && central_ch <= 6) |
934 | return 108; |
935 | else if (central_ch >= 7 && central_ch <= 10) |
936 | return 107; |
937 | else if (central_ch >= 11 && central_ch <= 14) |
938 | return 106; |
939 | else if (central_ch == 36 || central_ch == 38) |
940 | return 51; |
941 | else if (central_ch >= 40 && central_ch <= 58) |
942 | return 50; |
943 | else if (central_ch >= 60 && central_ch <= 64) |
944 | return 49; |
945 | else if (central_ch == 100 || central_ch == 102) |
946 | return 48; |
947 | else if (central_ch >= 104 && central_ch <= 126) |
948 | return 47; |
949 | else if (central_ch >= 128 && central_ch <= 151) |
950 | return 46; |
951 | else if (central_ch >= 153 && central_ch <= 177) |
952 | return 45; |
953 | else |
954 | return 0; |
955 | } |
956 | |
957 | struct rtw8852b_bb_gain { |
958 | u32 gain_g[BB_PATH_NUM_8852B]; |
959 | u32 gain_a[BB_PATH_NUM_8852B]; |
960 | u32 gain_mask; |
961 | }; |
962 | |
963 | static const struct rtw8852b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { |
964 | { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, |
965 | .gain_mask = 0x00ff0000 }, |
966 | { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, |
967 | .gain_mask = 0xff000000 }, |
968 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
969 | .gain_mask = 0x000000ff }, |
970 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
971 | .gain_mask = 0x0000ff00 }, |
972 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
973 | .gain_mask = 0x00ff0000 }, |
974 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
975 | .gain_mask = 0xff000000 }, |
976 | { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, |
977 | .gain_mask = 0x000000ff }, |
978 | }; |
979 | |
980 | static const struct rtw8852b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { |
981 | { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, |
982 | .gain_mask = 0x00ff0000 }, |
983 | { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, |
984 | .gain_mask = 0xff000000 }, |
985 | }; |
986 | |
987 | static void rtw8852b_set_gain_error(struct rtw89_dev *rtwdev, |
988 | enum rtw89_subband subband, |
989 | enum rtw89_rf_path path) |
990 | { |
991 | const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; |
992 | u8 gain_band = rtw89_subband_to_bb_gain_band(subband); |
993 | s32 val; |
994 | u32 reg; |
995 | u32 mask; |
996 | int i; |
997 | |
998 | for (i = 0; i < LNA_GAIN_NUM; i++) { |
999 | if (subband == RTW89_CH_2G) |
1000 | reg = bb_gain_lna[i].gain_g[path]; |
1001 | else |
1002 | reg = bb_gain_lna[i].gain_a[path]; |
1003 | |
1004 | mask = bb_gain_lna[i].gain_mask; |
1005 | val = gain->lna_gain[gain_band][path][i]; |
1006 | rtw89_phy_write32_mask(rtwdev, addr: reg, mask, data: val); |
1007 | } |
1008 | |
1009 | for (i = 0; i < TIA_GAIN_NUM; i++) { |
1010 | if (subband == RTW89_CH_2G) |
1011 | reg = bb_gain_tia[i].gain_g[path]; |
1012 | else |
1013 | reg = bb_gain_tia[i].gain_a[path]; |
1014 | |
1015 | mask = bb_gain_tia[i].gain_mask; |
1016 | val = gain->tia_gain[gain_band][path][i]; |
1017 | rtw89_phy_write32_mask(rtwdev, addr: reg, mask, data: val); |
1018 | } |
1019 | } |
1020 | |
1021 | static void rtw8852b_set_gain_offset(struct rtw89_dev *rtwdev, |
1022 | enum rtw89_subband subband, |
1023 | enum rtw89_phy_idx phy_idx) |
1024 | { |
1025 | static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD}; |
1026 | static const u32 [2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1, |
1027 | R_PATH1_G_TIA1_LNA6_OP1DB_V1}; |
1028 | struct rtw89_hal *hal = &rtwdev->hal; |
1029 | struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; |
1030 | enum rtw89_gain_offset gain_ofdm_band; |
1031 | s32 offset_a, offset_b; |
1032 | s32 offset_ofdm, offset_cck; |
1033 | s32 tmp; |
1034 | u8 path; |
1035 | |
1036 | if (!efuse_gain->comp_valid) |
1037 | goto next; |
1038 | |
1039 | for (path = RF_PATH_A; path < BB_PATH_NUM_8852B; path++) { |
1040 | tmp = efuse_gain->comp[path][subband]; |
1041 | tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); |
1042 | rtw89_phy_write32_mask(rtwdev, addr: gain_err_addr[path], MASKBYTE0, data: tmp); |
1043 | } |
1044 | |
1045 | next: |
1046 | if (!efuse_gain->offset_valid) |
1047 | return; |
1048 | |
1049 | gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); |
1050 | |
1051 | offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; |
1052 | offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; |
1053 | |
1054 | tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); |
1055 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
1056 | rtw89_phy_write32_mask(rtwdev, addr: rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, data: tmp); |
1057 | |
1058 | tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); |
1059 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
1060 | rtw89_phy_write32_mask(rtwdev, addr: rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, data: tmp); |
1061 | |
1062 | if (hal->antenna_rx == RF_B) { |
1063 | offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; |
1064 | offset_cck = -efuse_gain->offset[RF_PATH_B][0]; |
1065 | } else { |
1066 | offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; |
1067 | offset_cck = -efuse_gain->offset[RF_PATH_A][0]; |
1068 | } |
1069 | |
1070 | tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; |
1071 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
1072 | rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, data: tmp, phy_idx); |
1073 | |
1074 | tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; |
1075 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
1076 | rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, data: tmp, phy_idx); |
1077 | |
1078 | if (subband == RTW89_CH_2G) { |
1079 | tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); |
1080 | tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); |
1081 | rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, |
1082 | B_RX_RPL_OFST_CCK_MASK, data: tmp); |
1083 | } |
1084 | } |
1085 | |
1086 | static |
1087 | void rtw8852b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) |
1088 | { |
1089 | const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; |
1090 | u8 band = rtw89_subband_to_bb_gain_band(subband); |
1091 | u32 val; |
1092 | |
1093 | val = FIELD_PREP(B_P0_RPL1_20_MASK, (gain->rpl_ofst_20[band][RF_PATH_A] + |
1094 | gain->rpl_ofst_20[band][RF_PATH_B]) / 2) | |
1095 | FIELD_PREP(B_P0_RPL1_40_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][0] + |
1096 | gain->rpl_ofst_40[band][RF_PATH_B][0]) / 2) | |
1097 | FIELD_PREP(B_P0_RPL1_41_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][1] + |
1098 | gain->rpl_ofst_40[band][RF_PATH_B][1]) / 2); |
1099 | val >>= B_P0_RPL1_SHIFT; |
1100 | rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, data: val); |
1101 | rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, data: val); |
1102 | |
1103 | val = FIELD_PREP(B_P0_RTL2_42_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][2] + |
1104 | gain->rpl_ofst_40[band][RF_PATH_B][2]) / 2) | |
1105 | FIELD_PREP(B_P0_RTL2_80_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][0] + |
1106 | gain->rpl_ofst_80[band][RF_PATH_B][0]) / 2) | |
1107 | FIELD_PREP(B_P0_RTL2_81_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][1] + |
1108 | gain->rpl_ofst_80[band][RF_PATH_B][1]) / 2) | |
1109 | FIELD_PREP(B_P0_RTL2_8A_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][10] + |
1110 | gain->rpl_ofst_80[band][RF_PATH_B][10]) / 2); |
1111 | rtw89_phy_write32(rtwdev, R_P0_RPL2, data: val); |
1112 | rtw89_phy_write32(rtwdev, R_P1_RPL2, data: val); |
1113 | |
1114 | val = FIELD_PREP(B_P0_RTL3_82_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][2] + |
1115 | gain->rpl_ofst_80[band][RF_PATH_B][2]) / 2) | |
1116 | FIELD_PREP(B_P0_RTL3_83_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][3] + |
1117 | gain->rpl_ofst_80[band][RF_PATH_B][3]) / 2) | |
1118 | FIELD_PREP(B_P0_RTL3_84_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][4] + |
1119 | gain->rpl_ofst_80[band][RF_PATH_B][4]) / 2) | |
1120 | FIELD_PREP(B_P0_RTL3_89_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][9] + |
1121 | gain->rpl_ofst_80[band][RF_PATH_B][9]) / 2); |
1122 | rtw89_phy_write32(rtwdev, R_P0_RPL3, data: val); |
1123 | rtw89_phy_write32(rtwdev, R_P1_RPL3, data: val); |
1124 | } |
1125 | |
1126 | static void rtw8852b_ctrl_ch(struct rtw89_dev *rtwdev, |
1127 | const struct rtw89_chan *chan, |
1128 | enum rtw89_phy_idx phy_idx) |
1129 | { |
1130 | u8 central_ch = chan->channel; |
1131 | u8 subband = chan->subband_type; |
1132 | u8 sco_comp; |
1133 | bool is_2g = central_ch <= 14; |
1134 | |
1135 | /* Path A */ |
1136 | if (is_2g) |
1137 | rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, |
1138 | B_PATH0_BAND_SEL_MSK_V1, data: 1, phy_idx); |
1139 | else |
1140 | rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, |
1141 | B_PATH0_BAND_SEL_MSK_V1, data: 0, phy_idx); |
1142 | |
1143 | /* Path B */ |
1144 | if (is_2g) |
1145 | rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, |
1146 | B_PATH1_BAND_SEL_MSK_V1, data: 1, phy_idx); |
1147 | else |
1148 | rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, |
1149 | B_PATH1_BAND_SEL_MSK_V1, data: 0, phy_idx); |
1150 | |
1151 | /* SCO compensate FC setting */ |
1152 | sco_comp = rtw8852b_sco_mapping(central_ch); |
1153 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, data: sco_comp, phy_idx); |
1154 | |
1155 | if (chan->band_type == RTW89_BAND_6G) |
1156 | return; |
1157 | |
1158 | /* CCK parameters */ |
1159 | if (central_ch == 14) { |
1160 | rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, data: 0x3b13ff); |
1161 | rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, data: 0x1c42de); |
1162 | rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, data: 0xfdb0ad); |
1163 | rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, data: 0xf60f6e); |
1164 | rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, data: 0xfd8f92); |
1165 | rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, data: 0x2d011); |
1166 | rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, data: 0x1c02c); |
1167 | rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, data: 0xfff00a); |
1168 | } else { |
1169 | rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, data: 0x3d23ff); |
1170 | rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, data: 0x29b354); |
1171 | rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, data: 0xfc1c8); |
1172 | rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, data: 0xfdb053); |
1173 | rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, data: 0xf86f9a); |
1174 | rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, data: 0xfaef92); |
1175 | rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, data: 0xfe5fcc); |
1176 | rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, data: 0xffdff5); |
1177 | } |
1178 | |
1179 | rtw8852b_set_gain_error(rtwdev, subband, path: RF_PATH_A); |
1180 | rtw8852b_set_gain_error(rtwdev, subband, path: RF_PATH_B); |
1181 | rtw8852b_set_gain_offset(rtwdev, subband, phy_idx); |
1182 | rtw8852b_set_rxsc_rpl_comp(rtwdev, subband); |
1183 | } |
1184 | |
1185 | static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) |
1186 | { |
1187 | static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; |
1188 | static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; |
1189 | |
1190 | switch (bw) { |
1191 | case RTW89_CHANNEL_WIDTH_5: |
1192 | rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x1); |
1193 | rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x0); |
1194 | break; |
1195 | case RTW89_CHANNEL_WIDTH_10: |
1196 | rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x2); |
1197 | rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x1); |
1198 | break; |
1199 | case RTW89_CHANNEL_WIDTH_20: |
1200 | rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x0); |
1201 | rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x2); |
1202 | break; |
1203 | case RTW89_CHANNEL_WIDTH_40: |
1204 | rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x0); |
1205 | rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x2); |
1206 | break; |
1207 | case RTW89_CHANNEL_WIDTH_80: |
1208 | rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x0); |
1209 | rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x2); |
1210 | break; |
1211 | default: |
1212 | rtw89_warn(rtwdev, "Fail to set ADC\n" ); |
1213 | } |
1214 | } |
1215 | |
1216 | static void rtw8852b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, |
1217 | enum rtw89_phy_idx phy_idx) |
1218 | { |
1219 | u32 rx_path_0; |
1220 | |
1221 | switch (bw) { |
1222 | case RTW89_CHANNEL_WIDTH_5: |
1223 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, data: 0x0, phy_idx); |
1224 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, data: 0x1, phy_idx); |
1225 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, data: 0x0, phy_idx); |
1226 | |
1227 | /*Set RF mode at 3 */ |
1228 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
1229 | B_P0_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1230 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
1231 | B_P1_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1232 | break; |
1233 | case RTW89_CHANNEL_WIDTH_10: |
1234 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, data: 0x0, phy_idx); |
1235 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, data: 0x2, phy_idx); |
1236 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, data: 0x0, phy_idx); |
1237 | |
1238 | /*Set RF mode at 3 */ |
1239 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
1240 | B_P0_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1241 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
1242 | B_P1_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1243 | break; |
1244 | case RTW89_CHANNEL_WIDTH_20: |
1245 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, data: 0x0, phy_idx); |
1246 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, data: 0x0, phy_idx); |
1247 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, data: 0x0, phy_idx); |
1248 | |
1249 | /*Set RF mode at 3 */ |
1250 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
1251 | B_P0_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1252 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
1253 | B_P1_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1254 | break; |
1255 | case RTW89_CHANNEL_WIDTH_40: |
1256 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, data: 0x1, phy_idx); |
1257 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, data: 0x0, phy_idx); |
1258 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, |
1259 | data: pri_ch, phy_idx); |
1260 | |
1261 | /*Set RF mode at 3 */ |
1262 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
1263 | B_P0_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1264 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
1265 | B_P1_RFMODE_ORI_RX_ALL, data: 0x333, phy_idx); |
1266 | /*CCK primary channel */ |
1267 | if (pri_ch == RTW89_SC_20_UPPER) |
1268 | rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, data: 1); |
1269 | else |
1270 | rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, data: 0); |
1271 | |
1272 | break; |
1273 | case RTW89_CHANNEL_WIDTH_80: |
1274 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, data: 0x2, phy_idx); |
1275 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, data: 0x0, phy_idx); |
1276 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, |
1277 | data: pri_ch, phy_idx); |
1278 | |
1279 | /*Set RF mode at A */ |
1280 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
1281 | B_P0_RFMODE_ORI_RX_ALL, data: 0xaaa, phy_idx); |
1282 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
1283 | B_P1_RFMODE_ORI_RX_ALL, data: 0xaaa, phy_idx); |
1284 | break; |
1285 | default: |
1286 | rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n" , bw, |
1287 | pri_ch); |
1288 | } |
1289 | |
1290 | rtw8852b_bw_setting(rtwdev, bw, path: RF_PATH_A); |
1291 | rtw8852b_bw_setting(rtwdev, bw, path: RF_PATH_B); |
1292 | |
1293 | rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, |
1294 | phy_idx); |
1295 | if (rx_path_0 == 0x1) |
1296 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
1297 | B_P1_RFMODE_ORI_RX_ALL, data: 0x111, phy_idx); |
1298 | else if (rx_path_0 == 0x2) |
1299 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
1300 | B_P0_RFMODE_ORI_RX_ALL, data: 0x111, phy_idx); |
1301 | } |
1302 | |
1303 | static void rtw8852b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) |
1304 | { |
1305 | if (cck_en) { |
1306 | rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, data: 1); |
1307 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, data: 0); |
1308 | } else { |
1309 | rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, data: 0); |
1310 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, data: 1); |
1311 | } |
1312 | } |
1313 | |
1314 | static void rtw8852b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, |
1315 | enum rtw89_phy_idx phy_idx) |
1316 | { |
1317 | u8 pri_ch = chan->pri_ch_idx; |
1318 | bool mask_5m_low; |
1319 | bool mask_5m_en; |
1320 | |
1321 | switch (chan->band_width) { |
1322 | case RTW89_CHANNEL_WIDTH_40: |
1323 | /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ |
1324 | mask_5m_en = true; |
1325 | mask_5m_low = pri_ch == RTW89_SC_20_LOWER; |
1326 | break; |
1327 | case RTW89_CHANNEL_WIDTH_80: |
1328 | /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ |
1329 | mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || |
1330 | pri_ch == RTW89_SC_20_LOWEST; |
1331 | mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; |
1332 | break; |
1333 | default: |
1334 | mask_5m_en = false; |
1335 | break; |
1336 | } |
1337 | |
1338 | if (!mask_5m_en) { |
1339 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, data: 0x0); |
1340 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, data: 0x0); |
1341 | rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, |
1342 | B_ASSIGN_SBD_OPT_EN_V1, data: 0x0, phy_idx); |
1343 | return; |
1344 | } |
1345 | |
1346 | if (mask_5m_low) { |
1347 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, data: 0x4); |
1348 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, data: 0x1); |
1349 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, data: 0x0); |
1350 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, data: 0x1); |
1351 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, data: 0x4); |
1352 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, data: 0x1); |
1353 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, data: 0x0); |
1354 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, data: 0x1); |
1355 | } else { |
1356 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, data: 0x4); |
1357 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, data: 0x1); |
1358 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, data: 0x1); |
1359 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, data: 0x0); |
1360 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, data: 0x4); |
1361 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, data: 0x1); |
1362 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, data: 0x1); |
1363 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, data: 0x0); |
1364 | } |
1365 | rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, |
1366 | B_ASSIGN_SBD_OPT_EN_V1, data: 0x1, phy_idx); |
1367 | } |
1368 | |
1369 | static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) |
1370 | { |
1371 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, data: 0x7, phy_idx); |
1372 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, data: 0x7, phy_idx); |
1373 | fsleep(usecs: 1); |
1374 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 1, phy_idx); |
1375 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 0, phy_idx); |
1376 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, data: 0x0, phy_idx); |
1377 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, data: 0x0, phy_idx); |
1378 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 1, phy_idx); |
1379 | } |
1380 | |
1381 | static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, |
1382 | enum rtw89_phy_idx phy_idx, bool en) |
1383 | { |
1384 | if (en) { |
1385 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, |
1386 | B_S0_HW_SI_DIS_W_R_TRIG, data: 0x0, phy_idx); |
1387 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, |
1388 | B_S1_HW_SI_DIS_W_R_TRIG, data: 0x0, phy_idx); |
1389 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 1, phy_idx); |
1390 | if (band == RTW89_BAND_2G) |
1391 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, data: 0x0); |
1392 | rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, data: 0x0); |
1393 | } else { |
1394 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, data: 0x1); |
1395 | rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, data: 0x1); |
1396 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, |
1397 | B_S0_HW_SI_DIS_W_R_TRIG, data: 0x7, phy_idx); |
1398 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, |
1399 | B_S1_HW_SI_DIS_W_R_TRIG, data: 0x7, phy_idx); |
1400 | fsleep(usecs: 1); |
1401 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 0, phy_idx); |
1402 | } |
1403 | } |
1404 | |
1405 | static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev, |
1406 | enum rtw89_phy_idx phy_idx) |
1407 | { |
1408 | rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); |
1409 | rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); |
1410 | rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); |
1411 | rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); |
1412 | rtw8852b_bb_reset_all(rtwdev, phy_idx); |
1413 | rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); |
1414 | rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); |
1415 | rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); |
1416 | rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); |
1417 | } |
1418 | |
1419 | static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, |
1420 | enum rtw89_phy_idx phy_idx) |
1421 | { |
1422 | u32 addr; |
1423 | |
1424 | for (addr = R_AX_PWR_MACID_LMT_TABLE0; |
1425 | addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) |
1426 | rtw89_mac_txpwr_write32(rtwdev, phy_idx, reg_base: addr, val: 0); |
1427 | } |
1428 | |
1429 | static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev) |
1430 | { |
1431 | struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; |
1432 | |
1433 | rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); |
1434 | rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); |
1435 | |
1436 | rtw8852b_bb_macid_ctrl_init(rtwdev, phy_idx: RTW89_PHY_0); |
1437 | |
1438 | /* read these registers after loading BB parameters */ |
1439 | gain->offset_base[RTW89_PHY_0] = |
1440 | rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); |
1441 | gain->rssi_base[RTW89_PHY_0] = |
1442 | rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); |
1443 | } |
1444 | |
1445 | static void rtw8852b_bb_set_pop(struct rtw89_dev *rtwdev) |
1446 | { |
1447 | if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) |
1448 | rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN); |
1449 | } |
1450 | |
1451 | static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, |
1452 | enum rtw89_phy_idx phy_idx) |
1453 | { |
1454 | bool cck_en = chan->channel <= 14; |
1455 | u8 pri_ch_idx = chan->pri_ch_idx; |
1456 | u8 band = chan->band_type, chan_idx; |
1457 | |
1458 | if (cck_en) |
1459 | rtw8852b_ctrl_sco_cck(rtwdev, primary_ch: chan->primary_channel); |
1460 | |
1461 | rtw8852b_ctrl_ch(rtwdev, chan, phy_idx); |
1462 | rtw8852b_ctrl_bw(rtwdev, pri_ch: pri_ch_idx, bw: chan->band_width, phy_idx); |
1463 | rtw8852b_ctrl_cck_en(rtwdev, cck_en); |
1464 | if (chan->band_type == RTW89_BAND_5G) { |
1465 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, |
1466 | B_PATH0_BT_SHARE_V1, data: 0x0); |
1467 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, |
1468 | B_PATH0_BTG_PATH_V1, data: 0x0); |
1469 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, |
1470 | B_PATH1_BT_SHARE_V1, data: 0x0); |
1471 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, |
1472 | B_PATH1_BTG_PATH_V1, data: 0x0); |
1473 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, data: 0x0); |
1474 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, data: 0x0); |
1475 | rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, |
1476 | B_BT_DYN_DC_EST_EN_MSK, data: 0x0); |
1477 | rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, data: 0x0); |
1478 | } |
1479 | chan_idx = rtw89_encode_chan_idx(rtwdev, central_ch: chan->primary_channel, band); |
1480 | rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, data: chan_idx); |
1481 | rtw8852b_5m_mask(rtwdev, chan, phy_idx); |
1482 | rtw8852b_bb_set_pop(rtwdev); |
1483 | rtw8852b_bb_reset_all(rtwdev, phy_idx); |
1484 | } |
1485 | |
1486 | static void rtw8852b_set_channel(struct rtw89_dev *rtwdev, |
1487 | const struct rtw89_chan *chan, |
1488 | enum rtw89_mac_idx mac_idx, |
1489 | enum rtw89_phy_idx phy_idx) |
1490 | { |
1491 | rtw8852b_set_channel_mac(rtwdev, chan, mac_idx); |
1492 | rtw8852b_set_channel_bb(rtwdev, chan, phy_idx); |
1493 | rtw8852b_set_channel_rf(rtwdev, chan, phy_idx); |
1494 | } |
1495 | |
1496 | static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, |
1497 | enum rtw89_rf_path path) |
1498 | { |
1499 | static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK}; |
1500 | static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB}; |
1501 | |
1502 | if (en) { |
1503 | rtw89_phy_write32_mask(rtwdev, addr: ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, data: 0x0); |
1504 | rtw89_phy_write32_mask(rtwdev, addr: tssi_trk[path], B_P0_TSSI_TRK_EN, data: 0x0); |
1505 | } else { |
1506 | rtw89_phy_write32_mask(rtwdev, addr: ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, data: 0x1); |
1507 | rtw89_phy_write32_mask(rtwdev, addr: tssi_trk[path], B_P0_TSSI_TRK_EN, data: 0x1); |
1508 | } |
1509 | } |
1510 | |
1511 | static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, |
1512 | u8 phy_idx) |
1513 | { |
1514 | if (!rtwdev->dbcc_en) { |
1515 | rtw8852b_tssi_cont_en(rtwdev, en, path: RF_PATH_A); |
1516 | rtw8852b_tssi_cont_en(rtwdev, en, path: RF_PATH_B); |
1517 | } else { |
1518 | if (phy_idx == RTW89_PHY_0) |
1519 | rtw8852b_tssi_cont_en(rtwdev, en, path: RF_PATH_A); |
1520 | else |
1521 | rtw8852b_tssi_cont_en(rtwdev, en, path: RF_PATH_B); |
1522 | } |
1523 | } |
1524 | |
1525 | static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en) |
1526 | { |
1527 | if (en) |
1528 | rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, data: 0x0); |
1529 | else |
1530 | rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, data: 0xf); |
1531 | } |
1532 | |
1533 | static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, |
1534 | struct rtw89_channel_help_params *p, |
1535 | const struct rtw89_chan *chan, |
1536 | enum rtw89_mac_idx mac_idx, |
1537 | enum rtw89_phy_idx phy_idx) |
1538 | { |
1539 | if (enter) { |
1540 | rtw89_chip_stop_sch_tx(rtwdev, mac_idx: RTW89_MAC_0, tx_en: &p->tx_en, sel: RTW89_SCH_TX_SEL_ALL); |
1541 | rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx: RTW89_MAC_0, enable: false); |
1542 | rtw8852b_tssi_cont_en_phyidx(rtwdev, en: false, phy_idx: RTW89_PHY_0); |
1543 | rtw8852b_adc_en(rtwdev, en: false); |
1544 | fsleep(usecs: 40); |
1545 | rtw8852b_bb_reset_en(rtwdev, band: chan->band_type, phy_idx, en: false); |
1546 | } else { |
1547 | rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx: RTW89_MAC_0, enable: true); |
1548 | rtw8852b_adc_en(rtwdev, en: true); |
1549 | rtw8852b_tssi_cont_en_phyidx(rtwdev, en: true, phy_idx: RTW89_PHY_0); |
1550 | rtw8852b_bb_reset_en(rtwdev, band: chan->band_type, phy_idx, en: true); |
1551 | rtw89_chip_resume_sch_tx(rtwdev, mac_idx: RTW89_MAC_0, tx_en: p->tx_en); |
1552 | } |
1553 | } |
1554 | |
1555 | static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev) |
1556 | { |
1557 | rtwdev->is_tssi_mode[RF_PATH_A] = false; |
1558 | rtwdev->is_tssi_mode[RF_PATH_B] = false; |
1559 | |
1560 | rtw8852b_dpk_init(rtwdev); |
1561 | rtw8852b_rck(rtwdev); |
1562 | rtw8852b_dack(rtwdev); |
1563 | rtw8852b_rx_dck(rtwdev, phy_idx: RTW89_PHY_0); |
1564 | } |
1565 | |
1566 | static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev) |
1567 | { |
1568 | enum rtw89_phy_idx phy_idx = RTW89_PHY_0; |
1569 | |
1570 | rtw8852b_rx_dck(rtwdev, phy_idx); |
1571 | rtw8852b_iqk(rtwdev, phy_idx); |
1572 | rtw8852b_tssi(rtwdev, phy: phy_idx, hwtx_en: true); |
1573 | rtw8852b_dpk(rtwdev, phy: phy_idx); |
1574 | } |
1575 | |
1576 | static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev, |
1577 | enum rtw89_phy_idx phy_idx) |
1578 | { |
1579 | rtw8852b_tssi_scan(rtwdev, phy: phy_idx); |
1580 | } |
1581 | |
1582 | static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start) |
1583 | { |
1584 | rtw8852b_wifi_scan_notify(rtwdev, scan_start: start, phy_idx: RTW89_PHY_0); |
1585 | } |
1586 | |
1587 | static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev) |
1588 | { |
1589 | rtw8852b_dpk_track(rtwdev); |
1590 | } |
1591 | |
1592 | static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, |
1593 | enum rtw89_phy_idx phy_idx, s16 ref) |
1594 | { |
1595 | const u16 tssi_16dbm_cw = 0x12c; |
1596 | const u8 base_cw_0db = 0x27; |
1597 | const s8 ofst_int = 0; |
1598 | s16 pwr_s10_3; |
1599 | s16 rf_pwr_cw; |
1600 | u16 bb_pwr_cw; |
1601 | u32 pwr_cw; |
1602 | u32 tssi_ofst_cw; |
1603 | |
1604 | pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); |
1605 | bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); |
1606 | rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); |
1607 | rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); |
1608 | pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; |
1609 | |
1610 | tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); |
1611 | rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, |
1612 | fmt: "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n" , |
1613 | tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); |
1614 | |
1615 | return FIELD_PREP(B_DPD_TSSI_CW, tssi_ofst_cw) | |
1616 | FIELD_PREP(B_DPD_PWR_CW, pwr_cw) | |
1617 | FIELD_PREP(B_DPD_REF, ref); |
1618 | } |
1619 | |
1620 | static void rtw8852b_set_txpwr_ref(struct rtw89_dev *rtwdev, |
1621 | enum rtw89_phy_idx phy_idx) |
1622 | { |
1623 | static const u32 addr[RF_PATH_NUM_8852B] = {0x5800, 0x7800}; |
1624 | const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; |
1625 | const u8 ofst_ofdm = 0x4; |
1626 | const u8 ofst_cck = 0x8; |
1627 | const s16 ref_ofdm = 0; |
1628 | const s16 ref_cck = 0; |
1629 | u32 val; |
1630 | u8 i; |
1631 | |
1632 | rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[TXPWR] set txpwr reference\n" ); |
1633 | |
1634 | rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, |
1635 | B_AX_PWR_REF, val: 0x0); |
1636 | |
1637 | rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[TXPWR] set bb ofdm txpwr ref\n" ); |
1638 | val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref: ref_ofdm); |
1639 | |
1640 | for (i = 0; i < RF_PATH_NUM_8852B; i++) |
1641 | rtw89_phy_write32_idx(rtwdev, addr: addr[i] + ofst_ofdm, mask, data: val, |
1642 | phy_idx); |
1643 | |
1644 | rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[TXPWR] set bb cck txpwr ref\n" ); |
1645 | val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref: ref_cck); |
1646 | |
1647 | for (i = 0; i < RF_PATH_NUM_8852B; i++) |
1648 | rtw89_phy_write32_idx(rtwdev, addr: addr[i] + ofst_cck, mask, data: val, |
1649 | phy_idx); |
1650 | } |
1651 | |
1652 | static void rtw8852b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, |
1653 | const struct rtw89_chan *chan, |
1654 | u8 tx_shape_idx, |
1655 | enum rtw89_phy_idx phy_idx) |
1656 | { |
1657 | #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) |
1658 | #define __DFIR_CFG_MASK 0xffffffff |
1659 | #define __DFIR_CFG_NR 8 |
1660 | #define __DECL_DFIR_PARAM(_name, _val...) \ |
1661 | static const u32 param_ ## _name[] = {_val}; \ |
1662 | static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) |
1663 | |
1664 | __DECL_DFIR_PARAM(flat, |
1665 | 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, |
1666 | 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); |
1667 | __DECL_DFIR_PARAM(sharp, |
1668 | 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, |
1669 | 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); |
1670 | __DECL_DFIR_PARAM(sharp_14, |
1671 | 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, |
1672 | 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); |
1673 | u8 ch = chan->channel; |
1674 | const u32 *param; |
1675 | u32 addr; |
1676 | int i; |
1677 | |
1678 | if (ch > 14) { |
1679 | rtw89_warn(rtwdev, |
1680 | "set tx shape dfir by unknown ch: %d on 2G\n" , ch); |
1681 | return; |
1682 | } |
1683 | |
1684 | if (ch == 14) |
1685 | param = param_sharp_14; |
1686 | else |
1687 | param = tx_shape_idx == 0 ? param_flat : param_sharp; |
1688 | |
1689 | for (i = 0; i < __DFIR_CFG_NR; i++) { |
1690 | addr = __DFIR_CFG_ADDR(i); |
1691 | rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, |
1692 | fmt: "set tx shape dfir: 0x%x: 0x%x\n" , addr, param[i]); |
1693 | rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, data: param[i], |
1694 | phy_idx); |
1695 | } |
1696 | |
1697 | #undef __DECL_DFIR_PARAM |
1698 | #undef __DFIR_CFG_NR |
1699 | #undef __DFIR_CFG_MASK |
1700 | #undef __DECL_CFG_ADDR |
1701 | } |
1702 | |
1703 | static void rtw8852b_set_tx_shape(struct rtw89_dev *rtwdev, |
1704 | const struct rtw89_chan *chan, |
1705 | enum rtw89_phy_idx phy_idx) |
1706 | { |
1707 | const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; |
1708 | u8 band = chan->band_type; |
1709 | u8 regd = rtw89_regd_get(rtwdev, band); |
1710 | u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; |
1711 | u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; |
1712 | |
1713 | if (band == RTW89_BAND_2G) |
1714 | rtw8852b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_idx: tx_shape_cck, phy_idx); |
1715 | |
1716 | rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, |
1717 | data: tx_shape_ofdm); |
1718 | } |
1719 | |
1720 | static void rtw8852b_set_txpwr(struct rtw89_dev *rtwdev, |
1721 | const struct rtw89_chan *chan, |
1722 | enum rtw89_phy_idx phy_idx) |
1723 | { |
1724 | rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); |
1725 | rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); |
1726 | rtw8852b_set_tx_shape(rtwdev, chan, phy_idx); |
1727 | rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); |
1728 | rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); |
1729 | } |
1730 | |
1731 | static void rtw8852b_set_txpwr_ctrl(struct rtw89_dev *rtwdev, |
1732 | enum rtw89_phy_idx phy_idx) |
1733 | { |
1734 | rtw8852b_set_txpwr_ref(rtwdev, phy_idx); |
1735 | } |
1736 | |
1737 | static |
1738 | void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, |
1739 | s8 pw_ofst, enum rtw89_mac_idx mac_idx) |
1740 | { |
1741 | u32 reg; |
1742 | |
1743 | if (pw_ofst < -16 || pw_ofst > 15) { |
1744 | rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n" , pw_ofst); |
1745 | return; |
1746 | } |
1747 | |
1748 | reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, band: mac_idx); |
1749 | rtw89_write32_set(rtwdev, addr: reg, B_AX_PWR_UL_TB_CTRL_EN); |
1750 | |
1751 | reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, band: mac_idx); |
1752 | rtw89_write32_mask(rtwdev, addr: reg, B_AX_PWR_UL_TB_1T_MASK, data: pw_ofst); |
1753 | |
1754 | pw_ofst = max_t(s8, pw_ofst - 3, -16); |
1755 | reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, band: mac_idx); |
1756 | rtw89_write32_mask(rtwdev, addr: reg, B_AX_PWR_UL_TB_2T_MASK, data: pw_ofst); |
1757 | } |
1758 | |
1759 | static int |
1760 | rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) |
1761 | { |
1762 | int ret; |
1763 | |
1764 | ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, val: 0x07763333); |
1765 | if (ret) |
1766 | return ret; |
1767 | |
1768 | ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, val: 0x01ebf000); |
1769 | if (ret) |
1770 | return ret; |
1771 | |
1772 | ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, val: 0x0002f8ff); |
1773 | if (ret) |
1774 | return ret; |
1775 | |
1776 | rtw8852b_set_txpwr_ul_tb_offset(rtwdev, pw_ofst: 0, mac_idx: phy_idx == RTW89_PHY_1 ? |
1777 | RTW89_MAC_1 : RTW89_MAC_0); |
1778 | |
1779 | return 0; |
1780 | } |
1781 | |
1782 | void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev) |
1783 | { |
1784 | const struct rtw89_reg3_def *def = rtw8852b_pmac_ht20_mcs7_tbl; |
1785 | u8 i; |
1786 | |
1787 | for (i = 0; i < ARRAY_SIZE(rtw8852b_pmac_ht20_mcs7_tbl); i++, def++) |
1788 | rtw89_phy_write32_mask(rtwdev, addr: def->addr, mask: def->mask, data: def->data); |
1789 | } |
1790 | |
1791 | static void rtw8852b_stop_pmac_tx(struct rtw89_dev *rtwdev, |
1792 | struct rtw8852b_bb_pmac_info *tx_info, |
1793 | enum rtw89_phy_idx idx) |
1794 | { |
1795 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC Stop Tx" ); |
1796 | if (tx_info->mode == CONT_TX) |
1797 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, data: 0, phy_idx: idx); |
1798 | else if (tx_info->mode == PKTS_TX) |
1799 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, data: 0, phy_idx: idx); |
1800 | } |
1801 | |
1802 | static void rtw8852b_start_pmac_tx(struct rtw89_dev *rtwdev, |
1803 | struct rtw8852b_bb_pmac_info *tx_info, |
1804 | enum rtw89_phy_idx idx) |
1805 | { |
1806 | enum rtw8852b_pmac_mode mode = tx_info->mode; |
1807 | u32 pkt_cnt = tx_info->tx_cnt; |
1808 | u16 period = tx_info->period; |
1809 | |
1810 | if (mode == CONT_TX && !tx_info->is_cck) { |
1811 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, data: 1, phy_idx: idx); |
1812 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC CTx Start" ); |
1813 | } else if (mode == PKTS_TX) { |
1814 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, data: 1, phy_idx: idx); |
1815 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, |
1816 | B_PMAC_TX_PRD_MSK, data: period, phy_idx: idx); |
1817 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, |
1818 | data: pkt_cnt, phy_idx: idx); |
1819 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC PTx Start" ); |
1820 | } |
1821 | |
1822 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, data: 1, phy_idx: idx); |
1823 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, data: 0, phy_idx: idx); |
1824 | } |
1825 | |
1826 | void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev, |
1827 | struct rtw8852b_bb_pmac_info *tx_info, |
1828 | enum rtw89_phy_idx idx) |
1829 | { |
1830 | const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx: RTW89_SUB_ENTITY_0); |
1831 | |
1832 | if (!tx_info->en_pmac_tx) { |
1833 | rtw8852b_stop_pmac_tx(rtwdev, tx_info, idx); |
1834 | rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, data: 0, phy_idx: idx); |
1835 | if (chan->band_type == RTW89_BAND_2G) |
1836 | rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); |
1837 | return; |
1838 | } |
1839 | |
1840 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC Tx Enable" ); |
1841 | |
1842 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, data: 1, phy_idx: idx); |
1843 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, data: 1, phy_idx: idx); |
1844 | rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, data: 0x3f, phy_idx: idx); |
1845 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 0, phy_idx: idx); |
1846 | rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, data: 1, phy_idx: idx); |
1847 | rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); |
1848 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 1, phy_idx: idx); |
1849 | |
1850 | rtw8852b_start_pmac_tx(rtwdev, tx_info, idx); |
1851 | } |
1852 | |
1853 | void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, |
1854 | u16 tx_cnt, u16 period, u16 tx_time, |
1855 | enum rtw89_phy_idx idx) |
1856 | { |
1857 | struct rtw8852b_bb_pmac_info tx_info = {0}; |
1858 | |
1859 | tx_info.en_pmac_tx = enable; |
1860 | tx_info.is_cck = 0; |
1861 | tx_info.mode = PKTS_TX; |
1862 | tx_info.tx_cnt = tx_cnt; |
1863 | tx_info.period = period; |
1864 | tx_info.tx_time = tx_time; |
1865 | |
1866 | rtw8852b_bb_set_pmac_tx(rtwdev, tx_info: &tx_info, idx); |
1867 | } |
1868 | |
1869 | void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, |
1870 | enum rtw89_phy_idx idx) |
1871 | { |
1872 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC CFG Tx PWR = %d" , pwr_dbm); |
1873 | |
1874 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, data: 1, phy_idx: idx); |
1875 | rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, data: pwr_dbm, phy_idx: idx); |
1876 | } |
1877 | |
1878 | void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) |
1879 | { |
1880 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 7, phy_idx: RTW89_PHY_0); |
1881 | |
1882 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC CFG Tx Path = %d" , tx_path); |
1883 | |
1884 | if (tx_path == RF_PATH_A) { |
1885 | rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, data: 1); |
1886 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, data: 0); |
1887 | } else if (tx_path == RF_PATH_B) { |
1888 | rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, data: 2); |
1889 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, data: 0); |
1890 | } else if (tx_path == RF_PATH_AB) { |
1891 | rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, data: 3); |
1892 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, data: 4); |
1893 | } else { |
1894 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "Error Tx Path" ); |
1895 | } |
1896 | } |
1897 | |
1898 | void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev, |
1899 | enum rtw89_phy_idx idx, u8 mode) |
1900 | { |
1901 | if (mode != 0) |
1902 | return; |
1903 | |
1904 | rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "Tx mode switch" ); |
1905 | |
1906 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, data: 0, phy_idx: idx); |
1907 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, data: 0, phy_idx: idx); |
1908 | rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, data: 0, phy_idx: idx); |
1909 | rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, data: 0, phy_idx: idx); |
1910 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, data: 0, phy_idx: idx); |
1911 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 0, phy_idx: idx); |
1912 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, data: 0, phy_idx: idx); |
1913 | } |
1914 | |
1915 | void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, |
1916 | struct rtw8852b_bb_tssi_bak *bak) |
1917 | { |
1918 | s32 tmp; |
1919 | |
1920 | bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, phy_idx: idx); |
1921 | bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, phy_idx: idx); |
1922 | bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, phy_idx: idx); |
1923 | bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, phy_idx: idx); |
1924 | bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, phy_idx: idx); |
1925 | bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, phy_idx: idx); |
1926 | tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, phy_idx: idx); |
1927 | bak->tx_pwr = sign_extend32(value: tmp, index: 8); |
1928 | } |
1929 | |
1930 | void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, |
1931 | const struct rtw8852b_bb_tssi_bak *bak) |
1932 | { |
1933 | rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, data: bak->tx_path, phy_idx: idx); |
1934 | if (bak->tx_path == RF_AB) |
1935 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, data: 0x4); |
1936 | else |
1937 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, data: 0x0); |
1938 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, data: bak->rx_path, phy_idx: idx); |
1939 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, data: 1, phy_idx: idx); |
1940 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, data: bak->p0_rfmode, phy_idx: idx); |
1941 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, data: bak->p0_rfmode_ftm, phy_idx: idx); |
1942 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, data: bak->p1_rfmode, phy_idx: idx); |
1943 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, data: bak->p1_rfmode_ftm, phy_idx: idx); |
1944 | rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, data: bak->tx_pwr, phy_idx: idx); |
1945 | } |
1946 | |
1947 | static void rtw8852b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, |
1948 | enum rtw89_phy_idx phy_idx) |
1949 | { |
1950 | rtw89_phy_write_reg3_tbl(rtwdev, tbl: en ? &rtw8852b_btc_preagc_en_defs_tbl : |
1951 | &rtw8852b_btc_preagc_dis_defs_tbl); |
1952 | } |
1953 | |
1954 | static void rtw8852b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, |
1955 | enum rtw89_phy_idx phy_idx) |
1956 | { |
1957 | if (en) { |
1958 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, |
1959 | B_PATH0_BT_SHARE_V1, data: 0x1); |
1960 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, |
1961 | B_PATH0_BTG_PATH_V1, data: 0x0); |
1962 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, |
1963 | B_PATH1_G_LNA6_OP1DB_V1, data: 0x20); |
1964 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, |
1965 | B_PATH1_G_TIA0_LNA6_OP1DB_V1, data: 0x30); |
1966 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, |
1967 | B_PATH1_BT_SHARE_V1, data: 0x1); |
1968 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, |
1969 | B_PATH1_BTG_PATH_V1, data: 0x1); |
1970 | rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, data: 0x0); |
1971 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, data: 0x1); |
1972 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, data: 0x2); |
1973 | rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, |
1974 | B_BT_DYN_DC_EST_EN_MSK, data: 0x1); |
1975 | rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, data: 0x1); |
1976 | } else { |
1977 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, |
1978 | B_PATH0_BT_SHARE_V1, data: 0x0); |
1979 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, |
1980 | B_PATH0_BTG_PATH_V1, data: 0x0); |
1981 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, |
1982 | B_PATH1_G_LNA6_OP1DB_V1, data: 0x1a); |
1983 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, |
1984 | B_PATH1_G_TIA0_LNA6_OP1DB_V1, data: 0x2a); |
1985 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, |
1986 | B_PATH1_BT_SHARE_V1, data: 0x0); |
1987 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, |
1988 | B_PATH1_BTG_PATH_V1, data: 0x0); |
1989 | rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, data: 0xc); |
1990 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, data: 0x0); |
1991 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, data: 0x0); |
1992 | rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, |
1993 | B_BT_DYN_DC_EST_EN_MSK, data: 0x1); |
1994 | rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, data: 0x0); |
1995 | } |
1996 | } |
1997 | |
1998 | void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, |
1999 | enum rtw89_rf_path_bit rx_path) |
2000 | { |
2001 | const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx: RTW89_SUB_ENTITY_0); |
2002 | u32 rst_mask0; |
2003 | u32 rst_mask1; |
2004 | |
2005 | if (rx_path == RF_A) { |
2006 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, data: 1); |
2007 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, data: 1); |
2008 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, data: 1); |
2009 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, data: 0); |
2010 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, data: 0); |
2011 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, data: 4); |
2012 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, data: 0); |
2013 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, data: 0); |
2014 | } else if (rx_path == RF_B) { |
2015 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, data: 2); |
2016 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, data: 2); |
2017 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, data: 2); |
2018 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, data: 0); |
2019 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, data: 0); |
2020 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, data: 4); |
2021 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, data: 0); |
2022 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, data: 0); |
2023 | } else if (rx_path == RF_AB) { |
2024 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, data: 3); |
2025 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, data: 3); |
2026 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, data: 3); |
2027 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, data: 1); |
2028 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, data: 1); |
2029 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, data: 4); |
2030 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, data: 1); |
2031 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, data: 1); |
2032 | } |
2033 | |
2034 | rtw8852b_set_gain_offset(rtwdev, subband: chan->subband_type, phy_idx: RTW89_PHY_0); |
2035 | |
2036 | if (chan->band_type == RTW89_BAND_2G && |
2037 | (rx_path == RF_B || rx_path == RF_AB)) |
2038 | rtw8852b_ctrl_btg_bt_rx(rtwdev, en: true, phy_idx: RTW89_PHY_0); |
2039 | else |
2040 | rtw8852b_ctrl_btg_bt_rx(rtwdev, en: false, phy_idx: RTW89_PHY_0); |
2041 | |
2042 | rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; |
2043 | rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; |
2044 | if (rx_path == RF_A) { |
2045 | rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask: rst_mask0, data: 1); |
2046 | rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask: rst_mask0, data: 3); |
2047 | } else { |
2048 | rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask: rst_mask1, data: 1); |
2049 | rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask: rst_mask1, data: 3); |
2050 | } |
2051 | } |
2052 | |
2053 | static void rtw8852b_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev, |
2054 | enum rtw89_rf_path_bit rx_path) |
2055 | { |
2056 | if (rx_path == RF_A) { |
2057 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, |
2058 | B_P0_RFMODE_ORI_TXRX_FTM_TX, data: 0x1233312); |
2059 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, |
2060 | B_P0_RFMODE_FTM_RX, data: 0x333); |
2061 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, |
2062 | B_P1_RFMODE_ORI_TXRX_FTM_TX, data: 0x1111111); |
2063 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, |
2064 | B_P1_RFMODE_FTM_RX, data: 0x111); |
2065 | } else if (rx_path == RF_B) { |
2066 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, |
2067 | B_P0_RFMODE_ORI_TXRX_FTM_TX, data: 0x1111111); |
2068 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, |
2069 | B_P0_RFMODE_FTM_RX, data: 0x111); |
2070 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, |
2071 | B_P1_RFMODE_ORI_TXRX_FTM_TX, data: 0x1233312); |
2072 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, |
2073 | B_P1_RFMODE_FTM_RX, data: 0x333); |
2074 | } else if (rx_path == RF_AB) { |
2075 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, |
2076 | B_P0_RFMODE_ORI_TXRX_FTM_TX, data: 0x1233312); |
2077 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, |
2078 | B_P0_RFMODE_FTM_RX, data: 0x333); |
2079 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, |
2080 | B_P1_RFMODE_ORI_TXRX_FTM_TX, data: 0x1233312); |
2081 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, |
2082 | B_P1_RFMODE_FTM_RX, data: 0x333); |
2083 | } |
2084 | } |
2085 | |
2086 | static void rtw8852b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) |
2087 | { |
2088 | struct rtw89_hal *hal = &rtwdev->hal; |
2089 | enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB; |
2090 | |
2091 | rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path); |
2092 | rtw8852b_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path); |
2093 | |
2094 | if (rtwdev->hal.rx_nss == 1) { |
2095 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, data: 0); |
2096 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, data: 0); |
2097 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, data: 0); |
2098 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, data: 0); |
2099 | } else { |
2100 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, data: 1); |
2101 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, data: 1); |
2102 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, data: 1); |
2103 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, data: 1); |
2104 | } |
2105 | |
2106 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 0x0, phy_idx: RTW89_PHY_0); |
2107 | } |
2108 | |
2109 | static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) |
2110 | { |
2111 | if (rtwdev->is_tssi_mode[rf_path]) { |
2112 | u32 addr = 0x1c10 + (rf_path << 13); |
2113 | |
2114 | return rtw89_phy_read32_mask(rtwdev, addr, mask: 0x3F000000); |
2115 | } |
2116 | |
2117 | rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, data: 0x1); |
2118 | rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, data: 0x0); |
2119 | rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, data: 0x1); |
2120 | |
2121 | fsleep(usecs: 200); |
2122 | |
2123 | return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); |
2124 | } |
2125 | |
2126 | static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) |
2127 | { |
2128 | const struct rtw89_btc_ver *ver = rtwdev->btc.ver; |
2129 | union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; |
2130 | |
2131 | if (ver->fcxinit == 7) { |
2132 | md->md_v7.rfe_type = rtwdev->efuse.rfe_type; |
2133 | md->md_v7.kt_ver = rtwdev->hal.cv; |
2134 | md->md_v7.bt_solo = 0; |
2135 | md->md_v7.switch_type = BTC_SWITCH_INTERNAL; |
2136 | |
2137 | if (md->md_v7.rfe_type > 0) |
2138 | md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); |
2139 | else |
2140 | md->md_v7.ant.num = 2; |
2141 | |
2142 | md->md_v7.ant.diversity = 0; |
2143 | md->md_v7.ant.isolation = 10; |
2144 | |
2145 | if (md->md_v7.ant.num == 3) { |
2146 | md->md_v7.ant.type = BTC_ANT_DEDICATED; |
2147 | md->md_v7.bt_pos = BTC_BT_ALONE; |
2148 | } else { |
2149 | md->md_v7.ant.type = BTC_ANT_SHARED; |
2150 | md->md_v7.bt_pos = BTC_BT_BTG; |
2151 | } |
2152 | rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; |
2153 | rtwdev->btc.ant_type = md->md_v7.ant.type; |
2154 | } else { |
2155 | md->md.rfe_type = rtwdev->efuse.rfe_type; |
2156 | md->md.cv = rtwdev->hal.cv; |
2157 | md->md.bt_solo = 0; |
2158 | md->md.switch_type = BTC_SWITCH_INTERNAL; |
2159 | |
2160 | if (md->md.rfe_type > 0) |
2161 | md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); |
2162 | else |
2163 | md->md.ant.num = 2; |
2164 | |
2165 | md->md.ant.diversity = 0; |
2166 | md->md.ant.isolation = 10; |
2167 | |
2168 | if (md->md.ant.num == 3) { |
2169 | md->md.ant.type = BTC_ANT_DEDICATED; |
2170 | md->md.bt_pos = BTC_BT_ALONE; |
2171 | } else { |
2172 | md->md.ant.type = BTC_ANT_SHARED; |
2173 | md->md.bt_pos = BTC_BT_BTG; |
2174 | } |
2175 | rtwdev->btc.btg_pos = md->md.ant.btg_pos; |
2176 | rtwdev->btc.ant_type = md->md.ant.type; |
2177 | } |
2178 | } |
2179 | |
2180 | static |
2181 | void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) |
2182 | { |
2183 | rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWE, RFREG_MASK, data: 0x20000); |
2184 | rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWA, RFREG_MASK, data: group); |
2185 | rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWD0, RFREG_MASK, data: val); |
2186 | rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWE, RFREG_MASK, data: 0x0); |
2187 | } |
2188 | |
2189 | static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev) |
2190 | { |
2191 | struct rtw89_btc *btc = &rtwdev->btc; |
2192 | const struct rtw89_chip_info *chip = rtwdev->chip; |
2193 | const struct rtw89_mac_ax_coex coex_params = { |
2194 | .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, |
2195 | .direction = RTW89_MAC_AX_COEX_INNER, |
2196 | }; |
2197 | |
2198 | /* PTA init */ |
2199 | rtw89_mac_coex_init(rtwdev, coex: &coex_params); |
2200 | |
2201 | /* set WL Tx response = Hi-Pri */ |
2202 | chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); |
2203 | chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); |
2204 | |
2205 | /* set rf gnt debug off */ |
2206 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_A, RR_WLSEL, RFREG_MASK, data: 0x0); |
2207 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_WLSEL, RFREG_MASK, data: 0x0); |
2208 | |
2209 | /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ |
2210 | if (btc->ant_type == BTC_ANT_SHARED) { |
2211 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_A, group: BTC_BT_SS_GROUP, val: 0x5ff); |
2212 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_B, group: BTC_BT_SS_GROUP, val: 0x5ff); |
2213 | /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ |
2214 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_A, group: BTC_BT_TX_GROUP, val: 0x5ff); |
2215 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_B, group: BTC_BT_TX_GROUP, val: 0x55f); |
2216 | } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ |
2217 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_A, group: BTC_BT_SS_GROUP, val: 0x5df); |
2218 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_B, group: BTC_BT_SS_GROUP, val: 0x5df); |
2219 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_A, group: BTC_BT_TX_GROUP, val: 0x5ff); |
2220 | rtw8852b_set_trx_mask(rtwdev, path: RF_PATH_B, group: BTC_BT_TX_GROUP, val: 0x5ff); |
2221 | } |
2222 | |
2223 | /* set PTA break table */ |
2224 | rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); |
2225 | |
2226 | /* enable BT counter 0xda40[16,2] = 2b'11 */ |
2227 | rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); |
2228 | btc->cx.wl.status.map.init_ok = true; |
2229 | } |
2230 | |
2231 | static |
2232 | void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) |
2233 | { |
2234 | u32 bitmap; |
2235 | u32 reg; |
2236 | |
2237 | switch (map) { |
2238 | case BTC_PRI_MASK_TX_RESP: |
2239 | reg = R_BTC_BT_COEX_MSK_TABLE; |
2240 | bitmap = B_BTC_PRI_MASK_TX_RESP_V1; |
2241 | break; |
2242 | case BTC_PRI_MASK_BEACON: |
2243 | reg = R_AX_WL_PRI_MSK; |
2244 | bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; |
2245 | break; |
2246 | case BTC_PRI_MASK_RX_CCK: |
2247 | reg = R_BTC_BT_COEX_MSK_TABLE; |
2248 | bitmap = B_BTC_PRI_MASK_RXCCK_V1; |
2249 | break; |
2250 | default: |
2251 | return; |
2252 | } |
2253 | |
2254 | if (state) |
2255 | rtw89_write32_set(rtwdev, addr: reg, bit: bitmap); |
2256 | else |
2257 | rtw89_write32_clr(rtwdev, addr: reg, bit: bitmap); |
2258 | } |
2259 | |
2260 | union rtw8852b_btc_wl_txpwr_ctrl { |
2261 | u32 txpwr_val; |
2262 | struct { |
2263 | union { |
2264 | u16 ctrl_all_time; |
2265 | struct { |
2266 | s16 data:9; |
2267 | u16 rsvd:6; |
2268 | u16 flag:1; |
2269 | } all_time; |
2270 | }; |
2271 | union { |
2272 | u16 ctrl_gnt_bt; |
2273 | struct { |
2274 | s16 data:9; |
2275 | u16 rsvd:7; |
2276 | } gnt_bt; |
2277 | }; |
2278 | }; |
2279 | } __packed; |
2280 | |
2281 | static void |
2282 | rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) |
2283 | { |
2284 | union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; |
2285 | s32 val; |
2286 | |
2287 | #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ |
2288 | do { \ |
2289 | u32 _wrt = FIELD_PREP(_msk, _val); \ |
2290 | BUILD_BUG_ON(!!(_msk & _en)); \ |
2291 | if (_cond) \ |
2292 | _wrt |= _en; \ |
2293 | else \ |
2294 | _wrt &= ~_en; \ |
2295 | rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ |
2296 | _msk | _en, _wrt); \ |
2297 | } while (0) |
2298 | |
2299 | switch (arg.ctrl_all_time) { |
2300 | case 0xffff: |
2301 | val = 0; |
2302 | break; |
2303 | default: |
2304 | val = arg.all_time.data; |
2305 | break; |
2306 | } |
2307 | |
2308 | __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, |
2309 | val, B_AX_FORCE_PWR_BY_RATE_EN, |
2310 | arg.ctrl_all_time != 0xffff); |
2311 | |
2312 | switch (arg.ctrl_gnt_bt) { |
2313 | case 0xffff: |
2314 | val = 0; |
2315 | break; |
2316 | default: |
2317 | val = arg.gnt_bt.data; |
2318 | break; |
2319 | } |
2320 | |
2321 | __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, |
2322 | B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); |
2323 | |
2324 | #undef __write_ctrl |
2325 | } |
2326 | |
2327 | static |
2328 | s8 (struct rtw89_dev *rtwdev, s8 val) |
2329 | { |
2330 | /* +6 for compensate offset */ |
2331 | return clamp_t(s8, val + 6, -100, 0) + 100; |
2332 | } |
2333 | |
2334 | static |
2335 | void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev) |
2336 | { |
2337 | /* Feature move to firmware */ |
2338 | } |
2339 | |
2340 | static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) |
2341 | { |
2342 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x80000); |
2343 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x1); |
2344 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD1, RFREG_MASK, data: 0x31); |
2345 | |
2346 | /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ |
2347 | if (state) |
2348 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x179); |
2349 | else |
2350 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x20); |
2351 | |
2352 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x0); |
2353 | } |
2354 | |
2355 | static void rtw8852b_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) |
2356 | { |
2357 | switch (level) { |
2358 | case 0: /* default */ |
2359 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x1000); |
2360 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x0); |
2361 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x15); |
2362 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x1); |
2363 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x17); |
2364 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x2); |
2365 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x15); |
2366 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x3); |
2367 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x17); |
2368 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x0); |
2369 | break; |
2370 | case 1: /* Fix LNA2=5 */ |
2371 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x1000); |
2372 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x0); |
2373 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x15); |
2374 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x1); |
2375 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x5); |
2376 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x2); |
2377 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x15); |
2378 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x3); |
2379 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x5); |
2380 | rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x0); |
2381 | break; |
2382 | } |
2383 | } |
2384 | |
2385 | static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) |
2386 | { |
2387 | struct rtw89_btc *btc = &rtwdev->btc; |
2388 | |
2389 | switch (level) { |
2390 | case 0: /* original */ |
2391 | default: |
2392 | rtw8852b_ctrl_nbtg_bt_tx(rtwdev, en: false, phy_idx: RTW89_PHY_0); |
2393 | btc->dm.wl_lna2 = 0; |
2394 | break; |
2395 | case 1: /* for FDD free-run */ |
2396 | rtw8852b_ctrl_nbtg_bt_tx(rtwdev, en: true, phy_idx: RTW89_PHY_0); |
2397 | btc->dm.wl_lna2 = 0; |
2398 | break; |
2399 | case 2: /* for BTG Co-Rx*/ |
2400 | rtw8852b_ctrl_nbtg_bt_tx(rtwdev, en: false, phy_idx: RTW89_PHY_0); |
2401 | btc->dm.wl_lna2 = 1; |
2402 | break; |
2403 | } |
2404 | |
2405 | rtw8852b_btc_set_wl_lna2(rtwdev, level: btc->dm.wl_lna2); |
2406 | } |
2407 | |
2408 | static void rtw8852b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, |
2409 | struct rtw89_rx_phy_ppdu *phy_ppdu, |
2410 | struct ieee80211_rx_status *status) |
2411 | { |
2412 | u16 chan = phy_ppdu->chan_idx; |
2413 | enum nl80211_band band; |
2414 | u8 ch; |
2415 | |
2416 | if (chan == 0) |
2417 | return; |
2418 | |
2419 | rtw89_decode_chan_idx(rtwdev, chan_idx: chan, ch: &ch, band: &band); |
2420 | status->freq = ieee80211_channel_to_frequency(chan: ch, band); |
2421 | status->band = band; |
2422 | } |
2423 | |
2424 | static void rtw8852b_query_ppdu(struct rtw89_dev *rtwdev, |
2425 | struct rtw89_rx_phy_ppdu *phy_ppdu, |
2426 | struct ieee80211_rx_status *status) |
2427 | { |
2428 | u8 path; |
2429 | u8 *rx_power = phy_ppdu->rssi; |
2430 | |
2431 | status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); |
2432 | for (path = 0; path < rtwdev->chip->rf_path_num; path++) { |
2433 | status->chains |= BIT(path); |
2434 | status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); |
2435 | } |
2436 | if (phy_ppdu->valid) |
2437 | rtw8852b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); |
2438 | } |
2439 | |
2440 | static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev) |
2441 | { |
2442 | int ret; |
2443 | |
2444 | rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, |
2445 | B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); |
2446 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, data: 0x1); |
2447 | rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); |
2448 | rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); |
2449 | rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); |
2450 | |
2451 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S0, val: 0xC7, |
2452 | FULL_BIT_MASK); |
2453 | if (ret) |
2454 | return ret; |
2455 | |
2456 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S1, val: 0xC7, |
2457 | FULL_BIT_MASK); |
2458 | if (ret) |
2459 | return ret; |
2460 | |
2461 | rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); |
2462 | |
2463 | return 0; |
2464 | } |
2465 | |
2466 | static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev) |
2467 | { |
2468 | u8 wl_rfc_s0; |
2469 | u8 wl_rfc_s1; |
2470 | int ret; |
2471 | |
2472 | rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, |
2473 | B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); |
2474 | |
2475 | ret = rtw89_mac_read_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S0, val: &wl_rfc_s0); |
2476 | if (ret) |
2477 | return ret; |
2478 | wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; |
2479 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S0, val: wl_rfc_s0, |
2480 | FULL_BIT_MASK); |
2481 | if (ret) |
2482 | return ret; |
2483 | |
2484 | ret = rtw89_mac_read_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S1, val: &wl_rfc_s1); |
2485 | if (ret) |
2486 | return ret; |
2487 | wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; |
2488 | ret = rtw89_mac_write_xtal_si(rtwdev, offset: XTAL_SI_WL_RFC_S1, val: wl_rfc_s1, |
2489 | FULL_BIT_MASK); |
2490 | return ret; |
2491 | } |
2492 | |
2493 | static const struct rtw89_chip_ops rtw8852b_chip_ops = { |
2494 | .enable_bb_rf = rtw8852b_mac_enable_bb_rf, |
2495 | .disable_bb_rf = rtw8852b_mac_disable_bb_rf, |
2496 | .bb_preinit = NULL, |
2497 | .bb_postinit = NULL, |
2498 | .bb_reset = rtw8852b_bb_reset, |
2499 | .bb_sethw = rtw8852b_bb_sethw, |
2500 | .read_rf = rtw89_phy_read_rf_v1, |
2501 | .write_rf = rtw89_phy_write_rf_v1, |
2502 | .set_channel = rtw8852b_set_channel, |
2503 | .set_channel_help = rtw8852b_set_channel_help, |
2504 | .read_efuse = rtw8852b_read_efuse, |
2505 | .read_phycap = rtw8852b_read_phycap, |
2506 | .fem_setup = NULL, |
2507 | .rfe_gpio = NULL, |
2508 | .rfk_hw_init = NULL, |
2509 | .rfk_init = rtw8852b_rfk_init, |
2510 | .rfk_init_late = NULL, |
2511 | .rfk_channel = rtw8852b_rfk_channel, |
2512 | .rfk_band_changed = rtw8852b_rfk_band_changed, |
2513 | .rfk_scan = rtw8852b_rfk_scan, |
2514 | .rfk_track = rtw8852b_rfk_track, |
2515 | .power_trim = rtw8852b_power_trim, |
2516 | .set_txpwr = rtw8852b_set_txpwr, |
2517 | .set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl, |
2518 | .init_txpwr_unit = rtw8852b_init_txpwr_unit, |
2519 | .get_thermal = rtw8852b_get_thermal, |
2520 | .ctrl_btg_bt_rx = rtw8852b_ctrl_btg_bt_rx, |
2521 | .query_ppdu = rtw8852b_query_ppdu, |
2522 | .ctrl_nbtg_bt_tx = rtw8852b_ctrl_nbtg_bt_tx, |
2523 | .cfg_txrx_path = rtw8852b_bb_cfg_txrx_path, |
2524 | .set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset, |
2525 | .pwr_on_func = rtw8852b_pwr_on_func, |
2526 | .pwr_off_func = rtw8852b_pwr_off_func, |
2527 | .query_rxdesc = rtw89_core_query_rxdesc, |
2528 | .fill_txdesc = rtw89_core_fill_txdesc, |
2529 | .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, |
2530 | .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, |
2531 | .mac_cfg_gnt = rtw89_mac_cfg_gnt, |
2532 | .stop_sch_tx = rtw89_mac_stop_sch_tx, |
2533 | .resume_sch_tx = rtw89_mac_resume_sch_tx, |
2534 | .h2c_dctl_sec_cam = NULL, |
2535 | .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, |
2536 | .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, |
2537 | .h2c_ampdu_cmac_tbl = NULL, |
2538 | .h2c_default_dmac_tbl = NULL, |
2539 | .h2c_update_beacon = rtw89_fw_h2c_update_beacon, |
2540 | .h2c_ba_cam = rtw89_fw_h2c_ba_cam, |
2541 | |
2542 | .btc_set_rfe = rtw8852b_btc_set_rfe, |
2543 | .btc_init_cfg = rtw8852b_btc_init_cfg, |
2544 | .btc_set_wl_pri = rtw8852b_btc_set_wl_pri, |
2545 | .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl, |
2546 | .btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi, |
2547 | .btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt, |
2548 | .btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby, |
2549 | .btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain, |
2550 | .btc_set_policy = rtw89_btc_set_policy_v1, |
2551 | }; |
2552 | |
2553 | #ifdef CONFIG_PM |
2554 | static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = { |
2555 | .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, |
2556 | .n_patterns = RTW89_MAX_PATTERN_NUM, |
2557 | .pattern_max_len = RTW89_MAX_PATTERN_SIZE, |
2558 | .pattern_min_len = 1, |
2559 | }; |
2560 | #endif |
2561 | |
2562 | const struct rtw89_chip_info rtw8852b_chip_info = { |
2563 | .chip_id = RTL8852B, |
2564 | .chip_gen = RTW89_CHIP_AX, |
2565 | .ops = &rtw8852b_chip_ops, |
2566 | .mac_def = &rtw89_mac_gen_ax, |
2567 | .phy_def = &rtw89_phy_gen_ax, |
2568 | .fw_basename = RTW8852B_FW_BASENAME, |
2569 | .fw_format_max = RTW8852B_FW_FORMAT_MAX, |
2570 | .try_ce_fw = true, |
2571 | .bbmcu_nr = 0, |
2572 | .needed_fw_elms = 0, |
2573 | .fifo_size = 196608, |
2574 | .small_fifo_size = true, |
2575 | .dle_scc_rsvd_size = 98304, |
2576 | .max_amsdu_limit = 3500, |
2577 | .dis_2g_40m_ul_ofdma = true, |
2578 | .rsvd_ple_ofst = 0x2f800, |
2579 | .hfc_param_ini = rtw8852b_hfc_param_ini_pcie, |
2580 | .dle_mem = rtw8852b_dle_mem_pcie, |
2581 | .wde_qempty_acq_grpnum = 4, |
2582 | .wde_qempty_mgq_grpsel = 4, |
2583 | .rf_base_addr = {0xe000, 0xf000}, |
2584 | .pwr_on_seq = NULL, |
2585 | .pwr_off_seq = NULL, |
2586 | .bb_table = &rtw89_8852b_phy_bb_table, |
2587 | .bb_gain_table = &rtw89_8852b_phy_bb_gain_table, |
2588 | .rf_table = {&rtw89_8852b_phy_radioa_table, |
2589 | &rtw89_8852b_phy_radiob_table,}, |
2590 | .nctl_table = &rtw89_8852b_phy_nctl_table, |
2591 | .nctl_post_table = NULL, |
2592 | .dflt_parms = &rtw89_8852b_dflt_parms, |
2593 | .rfe_parms_conf = NULL, |
2594 | .txpwr_factor_rf = 2, |
2595 | .txpwr_factor_mac = 1, |
2596 | .dig_table = NULL, |
2597 | .dig_regs = &rtw8852b_dig_regs, |
2598 | .tssi_dbw_table = NULL, |
2599 | .support_chanctx_num = 0, |
2600 | .support_bands = BIT(NL80211_BAND_2GHZ) | |
2601 | BIT(NL80211_BAND_5GHZ), |
2602 | .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | |
2603 | BIT(NL80211_CHAN_WIDTH_40) | |
2604 | BIT(NL80211_CHAN_WIDTH_80), |
2605 | .support_unii4 = true, |
2606 | .ul_tb_waveform_ctrl = true, |
2607 | .ul_tb_pwr_diff = false, |
2608 | .hw_sec_hdr = false, |
2609 | .rf_path_num = 2, |
2610 | .tx_nss = 2, |
2611 | .rx_nss = 2, |
2612 | .acam_num = 128, |
2613 | .bcam_num = 10, |
2614 | .scam_num = 128, |
2615 | .bacam_num = 2, |
2616 | .bacam_dynamic_num = 4, |
2617 | .bacam_ver = RTW89_BACAM_V0, |
2618 | .ppdu_max_usr = 4, |
2619 | .sec_ctrl_efuse_size = 4, |
2620 | .physical_efuse_size = 1216, |
2621 | .logical_efuse_size = 2048, |
2622 | .limit_efuse_size = 1280, |
2623 | .dav_phy_efuse_size = 96, |
2624 | .dav_log_efuse_size = 16, |
2625 | .efuse_blocks = NULL, |
2626 | .phycap_addr = 0x580, |
2627 | .phycap_size = 128, |
2628 | .para_ver = 0, |
2629 | .wlcx_desired = 0x05050000, |
2630 | .btcx_desired = 0x5, |
2631 | .scbd = 0x1, |
2632 | .mailbox = 0x1, |
2633 | |
2634 | .afh_guard_ch = 6, |
2635 | .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres, |
2636 | .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres, |
2637 | .rssi_tol = 2, |
2638 | .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg), |
2639 | .mon_reg = rtw89_btc_8852b_mon_reg, |
2640 | .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul), |
2641 | .rf_para_ulink = rtw89_btc_8852b_rf_ul, |
2642 | .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl), |
2643 | .rf_para_dlink = rtw89_btc_8852b_rf_dl, |
2644 | .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | |
2645 | BIT(RTW89_PS_MODE_CLK_GATED) | |
2646 | BIT(RTW89_PS_MODE_PWR_GATED), |
2647 | .low_power_hci_modes = 0, |
2648 | .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, |
2649 | .hci_func_en_addr = R_AX_HCI_FUNC_EN, |
2650 | .h2c_desc_size = sizeof(struct rtw89_txwd_body), |
2651 | .txwd_body_size = sizeof(struct rtw89_txwd_body), |
2652 | .txwd_info_size = sizeof(struct rtw89_txwd_info), |
2653 | .h2c_ctrl_reg = R_AX_H2CREG_CTRL, |
2654 | .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, |
2655 | .h2c_regs = rtw8852b_h2c_regs, |
2656 | .c2h_ctrl_reg = R_AX_C2HREG_CTRL, |
2657 | .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, |
2658 | .c2h_regs = rtw8852b_c2h_regs, |
2659 | .page_regs = &rtw8852b_page_regs, |
2660 | .wow_reason_reg = R_AX_C2HREG_DATA3 + 3, |
2661 | .cfo_src_fd = true, |
2662 | .cfo_hw_comp = true, |
2663 | .dcfo_comp = &rtw8852b_dcfo_comp, |
2664 | .dcfo_comp_sft = 10, |
2665 | .imr_info = &rtw8852b_imr_info, |
2666 | .imr_dmac_table = NULL, |
2667 | .imr_cmac_table = NULL, |
2668 | .rrsr_cfgs = &rtw8852b_rrsr_cfgs, |
2669 | .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, |
2670 | .bss_clr_map_reg = R_BSS_CLR_MAP_V1, |
2671 | .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | |
2672 | BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | |
2673 | BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), |
2674 | .edcca_regs = &rtw8852b_edcca_regs, |
2675 | #ifdef CONFIG_PM |
2676 | .wowlan_stub = &rtw_wowlan_stub_8852b, |
2677 | #endif |
2678 | .xtal_info = NULL, |
2679 | }; |
2680 | EXPORT_SYMBOL(rtw8852b_chip_info); |
2681 | |
2682 | MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE); |
2683 | MODULE_AUTHOR("Realtek Corporation" ); |
2684 | MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver" ); |
2685 | MODULE_LICENSE("Dual BSD/GPL" ); |
2686 | |