1 | //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | /// \file |
9 | /// This file declares the MachineIRBuilder class. |
10 | /// This is a helper class to build MachineInstr. |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H |
14 | #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H |
15 | |
16 | #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" |
17 | #include "llvm/CodeGen/MachineBasicBlock.h" |
18 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
19 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
20 | #include "llvm/CodeGen/TargetOpcodes.h" |
21 | #include "llvm/IR/DebugLoc.h" |
22 | #include "llvm/IR/Module.h" |
23 | |
24 | namespace llvm { |
25 | |
26 | // Forward declarations. |
27 | class APInt; |
28 | class BlockAddress; |
29 | class Constant; |
30 | class ConstantFP; |
31 | class ConstantInt; |
32 | class DataLayout; |
33 | class GISelCSEInfo; |
34 | class GlobalValue; |
35 | class TargetRegisterClass; |
36 | class MachineFunction; |
37 | class MachineInstr; |
38 | class TargetInstrInfo; |
39 | class GISelChangeObserver; |
40 | |
41 | /// Class which stores all the state required in a MachineIRBuilder. |
42 | /// Since MachineIRBuilders will only store state in this object, it allows |
43 | /// to transfer BuilderState between different kinds of MachineIRBuilders. |
44 | struct MachineIRBuilderState { |
45 | /// MachineFunction under construction. |
46 | MachineFunction *MF = nullptr; |
47 | /// Information used to access the description of the opcodes. |
48 | const TargetInstrInfo *TII = nullptr; |
49 | /// Information used to verify types are consistent and to create virtual registers. |
50 | MachineRegisterInfo *MRI = nullptr; |
51 | /// Debug location to be set to any instruction we create. |
52 | DebugLoc DL; |
53 | /// PC sections metadata to be set to any instruction we create. |
54 | MDNode *PCSections = nullptr; |
55 | |
56 | /// \name Fields describing the insertion point. |
57 | /// @{ |
58 | MachineBasicBlock *MBB = nullptr; |
59 | MachineBasicBlock::iterator II; |
60 | /// @} |
61 | |
62 | GISelChangeObserver *Observer = nullptr; |
63 | |
64 | GISelCSEInfo *CSEInfo = nullptr; |
65 | }; |
66 | |
67 | class DstOp { |
68 | union { |
69 | LLT LLTTy; |
70 | Register Reg; |
71 | const TargetRegisterClass *RC; |
72 | }; |
73 | |
74 | public: |
75 | enum class DstType { Ty_LLT, Ty_Reg, Ty_RC }; |
76 | DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} |
77 | DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} |
78 | DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} |
79 | DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} |
80 | DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} |
81 | |
82 | void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const { |
83 | switch (Ty) { |
84 | case DstType::Ty_Reg: |
85 | MIB.addDef(RegNo: Reg); |
86 | break; |
87 | case DstType::Ty_LLT: |
88 | MIB.addDef(RegNo: MRI.createGenericVirtualRegister(Ty: LLTTy)); |
89 | break; |
90 | case DstType::Ty_RC: |
91 | MIB.addDef(RegNo: MRI.createVirtualRegister(RegClass: RC)); |
92 | break; |
93 | } |
94 | } |
95 | |
96 | LLT getLLTTy(const MachineRegisterInfo &MRI) const { |
97 | switch (Ty) { |
98 | case DstType::Ty_RC: |
99 | return LLT{}; |
100 | case DstType::Ty_LLT: |
101 | return LLTTy; |
102 | case DstType::Ty_Reg: |
103 | return MRI.getType(Reg: Reg); |
104 | } |
105 | llvm_unreachable("Unrecognised DstOp::DstType enum" ); |
106 | } |
107 | |
108 | Register getReg() const { |
109 | assert(Ty == DstType::Ty_Reg && "Not a register" ); |
110 | return Reg; |
111 | } |
112 | |
113 | const TargetRegisterClass *getRegClass() const { |
114 | switch (Ty) { |
115 | case DstType::Ty_RC: |
116 | return RC; |
117 | default: |
118 | llvm_unreachable("Not a RC Operand" ); |
119 | } |
120 | } |
121 | |
122 | DstType getDstOpKind() const { return Ty; } |
123 | |
124 | private: |
125 | DstType Ty; |
126 | }; |
127 | |
128 | class SrcOp { |
129 | union { |
130 | MachineInstrBuilder SrcMIB; |
131 | Register Reg; |
132 | CmpInst::Predicate Pred; |
133 | int64_t Imm; |
134 | }; |
135 | |
136 | public: |
137 | enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm }; |
138 | SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} |
139 | SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} |
140 | SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} |
141 | SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} |
142 | /// Use of registers held in unsigned integer variables (or more rarely signed |
143 | /// integers) is no longer permitted to avoid ambiguity with upcoming support |
144 | /// for immediates. |
145 | SrcOp(unsigned) = delete; |
146 | SrcOp(int) = delete; |
147 | SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} |
148 | SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} |
149 | |
150 | void addSrcToMIB(MachineInstrBuilder &MIB) const { |
151 | switch (Ty) { |
152 | case SrcType::Ty_Predicate: |
153 | MIB.addPredicate(Pred: Pred); |
154 | break; |
155 | case SrcType::Ty_Reg: |
156 | MIB.addUse(RegNo: Reg); |
157 | break; |
158 | case SrcType::Ty_MIB: |
159 | MIB.addUse(RegNo: SrcMIB->getOperand(i: 0).getReg()); |
160 | break; |
161 | case SrcType::Ty_Imm: |
162 | MIB.addImm(Val: Imm); |
163 | break; |
164 | } |
165 | } |
166 | |
167 | LLT getLLTTy(const MachineRegisterInfo &MRI) const { |
168 | switch (Ty) { |
169 | case SrcType::Ty_Predicate: |
170 | case SrcType::Ty_Imm: |
171 | llvm_unreachable("Not a register operand" ); |
172 | case SrcType::Ty_Reg: |
173 | return MRI.getType(Reg: Reg); |
174 | case SrcType::Ty_MIB: |
175 | return MRI.getType(Reg: SrcMIB->getOperand(i: 0).getReg()); |
176 | } |
177 | llvm_unreachable("Unrecognised SrcOp::SrcType enum" ); |
178 | } |
179 | |
180 | Register getReg() const { |
181 | switch (Ty) { |
182 | case SrcType::Ty_Predicate: |
183 | case SrcType::Ty_Imm: |
184 | llvm_unreachable("Not a register operand" ); |
185 | case SrcType::Ty_Reg: |
186 | return Reg; |
187 | case SrcType::Ty_MIB: |
188 | return SrcMIB->getOperand(i: 0).getReg(); |
189 | } |
190 | llvm_unreachable("Unrecognised SrcOp::SrcType enum" ); |
191 | } |
192 | |
193 | CmpInst::Predicate getPredicate() const { |
194 | switch (Ty) { |
195 | case SrcType::Ty_Predicate: |
196 | return Pred; |
197 | default: |
198 | llvm_unreachable("Not a register operand" ); |
199 | } |
200 | } |
201 | |
202 | int64_t getImm() const { |
203 | switch (Ty) { |
204 | case SrcType::Ty_Imm: |
205 | return Imm; |
206 | default: |
207 | llvm_unreachable("Not an immediate" ); |
208 | } |
209 | } |
210 | |
211 | SrcType getSrcOpKind() const { return Ty; } |
212 | |
213 | private: |
214 | SrcType Ty; |
215 | }; |
216 | |
217 | /// Helper class to build MachineInstr. |
218 | /// It keeps internally the insertion point and debug location for all |
219 | /// the new instructions we want to create. |
220 | /// This information can be modified via the related setters. |
221 | class MachineIRBuilder { |
222 | |
223 | MachineIRBuilderState State; |
224 | |
225 | unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const; |
226 | |
227 | protected: |
228 | void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend); |
229 | |
230 | void validateUnaryOp(const LLT Res, const LLT Op0); |
231 | void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1); |
232 | void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1); |
233 | |
234 | void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, |
235 | const LLT Op1Ty); |
236 | |
237 | void recordInsertion(MachineInstr *InsertedInstr) const { |
238 | if (State.Observer) |
239 | State.Observer->createdInstr(MI&: *InsertedInstr); |
240 | } |
241 | |
242 | public: |
243 | /// Some constructors for easy use. |
244 | MachineIRBuilder() = default; |
245 | MachineIRBuilder(MachineFunction &MF) { setMF(MF); } |
246 | |
247 | MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) { |
248 | setMF(*MBB.getParent()); |
249 | setInsertPt(MBB, II: InsPt); |
250 | } |
251 | |
252 | MachineIRBuilder(MachineInstr &MI) : |
253 | MachineIRBuilder(*MI.getParent(), MI.getIterator()) { |
254 | setInstr(MI); |
255 | setDebugLoc(MI.getDebugLoc()); |
256 | } |
257 | |
258 | MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) : |
259 | MachineIRBuilder(MI) { |
260 | setChangeObserver(Observer); |
261 | } |
262 | |
263 | virtual ~MachineIRBuilder() = default; |
264 | |
265 | MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {} |
266 | |
267 | const TargetInstrInfo &getTII() { |
268 | assert(State.TII && "TargetInstrInfo is not set" ); |
269 | return *State.TII; |
270 | } |
271 | |
272 | /// Getter for the function we currently build. |
273 | MachineFunction &getMF() { |
274 | assert(State.MF && "MachineFunction is not set" ); |
275 | return *State.MF; |
276 | } |
277 | |
278 | const MachineFunction &getMF() const { |
279 | assert(State.MF && "MachineFunction is not set" ); |
280 | return *State.MF; |
281 | } |
282 | |
283 | const DataLayout &getDataLayout() const { |
284 | return getMF().getFunction().getParent()->getDataLayout(); |
285 | } |
286 | |
287 | LLVMContext &getContext() const { |
288 | return getMF().getFunction().getContext(); |
289 | } |
290 | |
291 | /// Getter for DebugLoc |
292 | const DebugLoc &getDL() { return State.DL; } |
293 | |
294 | /// Getter for MRI |
295 | MachineRegisterInfo *getMRI() { return State.MRI; } |
296 | const MachineRegisterInfo *getMRI() const { return State.MRI; } |
297 | |
298 | /// Getter for the State |
299 | MachineIRBuilderState &getState() { return State; } |
300 | |
301 | /// Setter for the State |
302 | void setState(const MachineIRBuilderState &NewState) { State = NewState; } |
303 | |
304 | /// Getter for the basic block we currently build. |
305 | const MachineBasicBlock &getMBB() const { |
306 | assert(State.MBB && "MachineBasicBlock is not set" ); |
307 | return *State.MBB; |
308 | } |
309 | |
310 | MachineBasicBlock &getMBB() { |
311 | return const_cast<MachineBasicBlock &>( |
312 | const_cast<const MachineIRBuilder *>(this)->getMBB()); |
313 | } |
314 | |
315 | GISelCSEInfo *getCSEInfo() { return State.CSEInfo; } |
316 | const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; } |
317 | |
318 | /// Current insertion point for new instructions. |
319 | MachineBasicBlock::iterator getInsertPt() { return State.II; } |
320 | |
321 | /// Set the insertion point before the specified position. |
322 | /// \pre MBB must be in getMF(). |
323 | /// \pre II must be a valid iterator in MBB. |
324 | void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) { |
325 | assert(MBB.getParent() == &getMF() && |
326 | "Basic block is in a different function" ); |
327 | State.MBB = &MBB; |
328 | State.II = II; |
329 | } |
330 | |
331 | /// @} |
332 | |
333 | void setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; } |
334 | |
335 | /// \name Setters for the insertion point. |
336 | /// @{ |
337 | /// Set the MachineFunction where to build instructions. |
338 | void setMF(MachineFunction &MF); |
339 | |
340 | /// Set the insertion point to the end of \p MBB. |
341 | /// \pre \p MBB must be contained by getMF(). |
342 | void setMBB(MachineBasicBlock &MBB) { |
343 | State.MBB = &MBB; |
344 | State.II = MBB.end(); |
345 | assert(&getMF() == MBB.getParent() && |
346 | "Basic block is in a different function" ); |
347 | } |
348 | |
349 | /// Set the insertion point to before MI. |
350 | /// \pre MI must be in getMF(). |
351 | void setInstr(MachineInstr &MI) { |
352 | assert(MI.getParent() && "Instruction is not part of a basic block" ); |
353 | setMBB(*MI.getParent()); |
354 | State.II = MI.getIterator(); |
355 | setPCSections(MI.getPCSections()); |
356 | } |
357 | /// @} |
358 | |
359 | /// Set the insertion point to before MI, and set the debug loc to MI's loc. |
360 | /// \pre MI must be in getMF(). |
361 | void setInstrAndDebugLoc(MachineInstr &MI) { |
362 | setInstr(MI); |
363 | setDebugLoc(MI.getDebugLoc()); |
364 | } |
365 | |
366 | void setChangeObserver(GISelChangeObserver &Observer) { |
367 | State.Observer = &Observer; |
368 | } |
369 | |
370 | GISelChangeObserver *getObserver() { return State.Observer; } |
371 | |
372 | void stopObservingChanges() { State.Observer = nullptr; } |
373 | |
374 | bool isObservingChanges() const { return State.Observer != nullptr; } |
375 | /// @} |
376 | |
377 | /// Set the debug location to \p DL for all the next build instructions. |
378 | void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; } |
379 | |
380 | /// Get the current instruction's debug location. |
381 | const DebugLoc &getDebugLoc() { return State.DL; } |
382 | |
383 | /// Set the PC sections metadata to \p MD for all the next build instructions. |
384 | void setPCSections(MDNode *MD) { State.PCSections = MD; } |
385 | |
386 | /// Get the current instruction's PC sections metadata. |
387 | MDNode *getPCSections() { return State.PCSections; } |
388 | |
389 | /// Build and insert <empty> = \p Opcode <empty>. |
390 | /// The insertion point is the one set by the last call of either |
391 | /// setBasicBlock or setMI. |
392 | /// |
393 | /// \pre setBasicBlock or setMI must have been called. |
394 | /// |
395 | /// \return a MachineInstrBuilder for the newly created instruction. |
396 | MachineInstrBuilder buildInstr(unsigned Opcode) { |
397 | return insertInstr(MIB: buildInstrNoInsert(Opcode)); |
398 | } |
399 | |
400 | /// Build but don't insert <empty> = \p Opcode <empty>. |
401 | /// |
402 | /// \pre setMF, setBasicBlock or setMI must have been called. |
403 | /// |
404 | /// \return a MachineInstrBuilder for the newly created instruction. |
405 | MachineInstrBuilder buildInstrNoInsert(unsigned Opcode); |
406 | |
407 | /// Insert an existing instruction at the insertion point. |
408 | MachineInstrBuilder insertInstr(MachineInstrBuilder MIB); |
409 | |
410 | /// Build and insert a DBG_VALUE instruction expressing the fact that the |
411 | /// associated \p Variable lives in \p Reg (suitably modified by \p Expr). |
412 | MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, |
413 | const MDNode *Expr); |
414 | |
415 | /// Build and insert a DBG_VALUE instruction expressing the fact that the |
416 | /// associated \p Variable lives in memory at \p Reg (suitably modified by \p |
417 | /// Expr). |
418 | MachineInstrBuilder buildIndirectDbgValue(Register Reg, |
419 | const MDNode *Variable, |
420 | const MDNode *Expr); |
421 | |
422 | /// Build and insert a DBG_VALUE instruction expressing the fact that the |
423 | /// associated \p Variable lives in the stack slot specified by \p FI |
424 | /// (suitably modified by \p Expr). |
425 | MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, |
426 | const MDNode *Expr); |
427 | |
428 | /// Build and insert a DBG_VALUE instructions specifying that \p Variable is |
429 | /// given by \p C (suitably modified by \p Expr). |
430 | MachineInstrBuilder buildConstDbgValue(const Constant &C, |
431 | const MDNode *Variable, |
432 | const MDNode *Expr); |
433 | |
434 | /// Build and insert a DBG_LABEL instructions specifying that \p Label is |
435 | /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label". |
436 | MachineInstrBuilder buildDbgLabel(const MDNode *Label); |
437 | |
438 | /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align |
439 | /// |
440 | /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of |
441 | /// the allocated memory into \p Res. |
442 | /// \pre setBasicBlock or setMI must have been called. |
443 | /// \pre \p Res must be a generic virtual register with pointer type. |
444 | /// |
445 | /// \return a MachineInstrBuilder for the newly created instruction. |
446 | MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, |
447 | Align Alignment); |
448 | |
449 | /// Build and insert \p Res = G_FRAME_INDEX \p Idx |
450 | /// |
451 | /// G_FRAME_INDEX materializes the address of an alloca value or other |
452 | /// stack-based object. |
453 | /// |
454 | /// \pre setBasicBlock or setMI must have been called. |
455 | /// \pre \p Res must be a generic virtual register with pointer type. |
456 | /// |
457 | /// \return a MachineInstrBuilder for the newly created instruction. |
458 | MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx); |
459 | |
460 | /// Build and insert \p Res = G_GLOBAL_VALUE \p GV |
461 | /// |
462 | /// G_GLOBAL_VALUE materializes the address of the specified global |
463 | /// into \p Res. |
464 | /// |
465 | /// \pre setBasicBlock or setMI must have been called. |
466 | /// \pre \p Res must be a generic virtual register with pointer type |
467 | /// in the same address space as \p GV. |
468 | /// |
469 | /// \return a MachineInstrBuilder for the newly created instruction. |
470 | MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV); |
471 | |
472 | /// Build and insert \p Res = G_CONSTANT_POOL \p Idx |
473 | /// |
474 | /// G_CONSTANT_POOL materializes the address of an object in the constant |
475 | /// pool. |
476 | /// |
477 | /// \pre setBasicBlock or setMI must have been called. |
478 | /// \pre \p Res must be a generic virtual register with pointer type. |
479 | /// |
480 | /// \return a MachineInstrBuilder for the newly created instruction. |
481 | MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx); |
482 | |
483 | /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1 |
484 | /// |
485 | /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0, |
486 | /// storing the resulting pointer in \p Res. Addressible units are typically |
487 | /// bytes but this can vary between targets. |
488 | /// |
489 | /// \pre setBasicBlock or setMI must have been called. |
490 | /// \pre \p Res and \p Op0 must be generic virtual registers with pointer |
491 | /// type. |
492 | /// \pre \p Op1 must be a generic virtual register with scalar type. |
493 | /// |
494 | /// \return a MachineInstrBuilder for the newly created instruction. |
495 | MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, |
496 | const SrcOp &Op1, |
497 | std::optional<unsigned> Flags = std::nullopt); |
498 | |
499 | /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value) |
500 | /// |
501 | /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0, |
502 | /// storing the resulting pointer in \p Res. If \p Value is zero then no |
503 | /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to |
504 | /// \p Res. |
505 | /// |
506 | /// \pre setBasicBlock or setMI must have been called. |
507 | /// \pre \p Op0 must be a generic virtual register with pointer type. |
508 | /// \pre \p ValueTy must be a scalar type. |
509 | /// \pre \p Res must be 0. This is to detect confusion between |
510 | /// materializePtrAdd() and buildPtrAdd(). |
511 | /// \post \p Res will either be a new generic virtual register of the same |
512 | /// type as \p Op0 or \p Op0 itself. |
513 | /// |
514 | /// \return a MachineInstrBuilder for the newly created instruction. |
515 | std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res, |
516 | Register Op0, |
517 | const LLT ValueTy, |
518 | uint64_t Value); |
519 | |
520 | /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1 |
521 | MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, |
522 | const SrcOp &Op1) { |
523 | return buildInstr(Opc: TargetOpcode::G_PTRMASK, DstOps: {Res}, SrcOps: {Op0, Op1}); |
524 | } |
525 | |
526 | /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1 |
527 | /// |
528 | /// This clears the low bits of a pointer operand without destroying its |
529 | /// pointer properties. This has the effect of rounding the address *down* to |
530 | /// a specified alignment in bits. |
531 | /// |
532 | /// \pre setBasicBlock or setMI must have been called. |
533 | /// \pre \p Res and \p Op0 must be generic virtual registers with pointer |
534 | /// type. |
535 | /// \pre \p NumBits must be an integer representing the number of low bits to |
536 | /// be cleared in \p Op0. |
537 | /// |
538 | /// \return a MachineInstrBuilder for the newly created instruction. |
539 | MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, |
540 | uint32_t NumBits); |
541 | |
542 | /// Build and insert |
543 | /// a, b, ..., x = G_UNMERGE_VALUES \p Op0 |
544 | /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef |
545 | /// |
546 | /// Pad \p Op0 with undef elements to match number of elements in \p Res. |
547 | /// |
548 | /// \pre setBasicBlock or setMI must have been called. |
549 | /// \pre \p Res and \p Op0 must be generic virtual registers with vector type, |
550 | /// same vector element type and Op0 must have fewer elements then Res. |
551 | /// |
552 | /// \return a MachineInstrBuilder for the newly created build vector instr. |
553 | MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, |
554 | const SrcOp &Op0); |
555 | |
556 | /// Build and insert |
557 | /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0 |
558 | /// \p Res = G_BUILD_VECTOR a, b, ..., x |
559 | /// |
560 | /// Delete trailing elements in \p Op0 to match number of elements in \p Res. |
561 | /// |
562 | /// \pre setBasicBlock or setMI must have been called. |
563 | /// \pre \p Res and \p Op0 must be generic virtual registers with vector type, |
564 | /// same vector element type and Op0 must have more elements then Res. |
565 | /// |
566 | /// \return a MachineInstrBuilder for the newly created build vector instr. |
567 | MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, |
568 | const SrcOp &Op0); |
569 | |
570 | /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1 |
571 | /// |
572 | /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and |
573 | /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic. |
574 | /// |
575 | /// \pre setBasicBlock or setMI must have been called. |
576 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the |
577 | /// same scalar type. |
578 | ////\pre \p CarryOut must be generic virtual register with scalar type |
579 | ///(typically s1) |
580 | /// |
581 | /// \return The newly created instruction. |
582 | MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, |
583 | const SrcOp &Op0, const SrcOp &Op1) { |
584 | return buildInstr(Opc: TargetOpcode::G_UADDO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1}); |
585 | } |
586 | |
587 | /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1 |
588 | MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, |
589 | const SrcOp &Op0, const SrcOp &Op1) { |
590 | return buildInstr(Opc: TargetOpcode::G_USUBO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1}); |
591 | } |
592 | |
593 | /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1 |
594 | MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, |
595 | const SrcOp &Op0, const SrcOp &Op1) { |
596 | return buildInstr(Opc: TargetOpcode::G_SADDO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1}); |
597 | } |
598 | |
599 | /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1 |
600 | MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, |
601 | const SrcOp &Op0, const SrcOp &Op1) { |
602 | return buildInstr(Opc: TargetOpcode::G_SSUBO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1}); |
603 | } |
604 | |
605 | /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0, |
606 | /// \p Op1, \p CarryIn |
607 | /// |
608 | /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit |
609 | /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned |
610 | /// arithmetic. |
611 | /// |
612 | /// \pre setBasicBlock or setMI must have been called. |
613 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers |
614 | /// with the same scalar type. |
615 | /// \pre \p CarryOut and \p CarryIn must be generic virtual |
616 | /// registers with the same scalar type (typically s1) |
617 | /// |
618 | /// \return The newly created instruction. |
619 | MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, |
620 | const SrcOp &Op0, const SrcOp &Op1, |
621 | const SrcOp &CarryIn) { |
622 | return buildInstr(Opc: TargetOpcode::G_UADDE, DstOps: {Res, CarryOut}, |
623 | SrcOps: {Op0, Op1, CarryIn}); |
624 | } |
625 | |
626 | /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp |
627 | MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, |
628 | const SrcOp &Op0, const SrcOp &Op1, |
629 | const SrcOp &CarryIn) { |
630 | return buildInstr(Opc: TargetOpcode::G_USUBE, DstOps: {Res, CarryOut}, |
631 | SrcOps: {Op0, Op1, CarryIn}); |
632 | } |
633 | |
634 | /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp |
635 | MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, |
636 | const SrcOp &Op0, const SrcOp &Op1, |
637 | const SrcOp &CarryIn) { |
638 | return buildInstr(Opc: TargetOpcode::G_SADDE, DstOps: {Res, CarryOut}, |
639 | SrcOps: {Op0, Op1, CarryIn}); |
640 | } |
641 | |
642 | /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp |
643 | MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, |
644 | const SrcOp &Op0, const SrcOp &Op1, |
645 | const SrcOp &CarryIn) { |
646 | return buildInstr(Opc: TargetOpcode::G_SSUBE, DstOps: {Res, CarryOut}, |
647 | SrcOps: {Op0, Op1, CarryIn}); |
648 | } |
649 | |
650 | /// Build and insert \p Res = G_ANYEXT \p Op0 |
651 | /// |
652 | /// G_ANYEXT produces a register of the specified width, with bits 0 to |
653 | /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified |
654 | /// (i.e. this is neither zero nor sign-extension). For a vector register, |
655 | /// each element is extended individually. |
656 | /// |
657 | /// \pre setBasicBlock or setMI must have been called. |
658 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
659 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
660 | /// \pre \p Op must be smaller than \p Res |
661 | /// |
662 | /// \return The newly created instruction. |
663 | |
664 | MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op); |
665 | |
666 | /// Build and insert \p Res = G_SEXT \p Op |
667 | /// |
668 | /// G_SEXT produces a register of the specified width, with bits 0 to |
669 | /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the |
670 | /// high bit of \p Op (i.e. 2s-complement sign extended). |
671 | /// |
672 | /// \pre setBasicBlock or setMI must have been called. |
673 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
674 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
675 | /// \pre \p Op must be smaller than \p Res |
676 | /// |
677 | /// \return The newly created instruction. |
678 | MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op); |
679 | |
680 | /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp |
681 | MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) { |
682 | return buildInstr(Opc: TargetOpcode::G_SEXT_INREG, DstOps: {Res}, SrcOps: {Op, SrcOp(ImmOp)}); |
683 | } |
684 | |
685 | /// Build and insert \p Res = G_FPEXT \p Op |
686 | MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, |
687 | std::optional<unsigned> Flags = std::nullopt) { |
688 | return buildInstr(Opc: TargetOpcode::G_FPEXT, DstOps: {Res}, SrcOps: {Op}, Flags); |
689 | } |
690 | |
691 | /// Build and insert a G_PTRTOINT instruction. |
692 | MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) { |
693 | return buildInstr(Opc: TargetOpcode::G_PTRTOINT, DstOps: {Dst}, SrcOps: {Src}); |
694 | } |
695 | |
696 | /// Build and insert a G_INTTOPTR instruction. |
697 | MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) { |
698 | return buildInstr(Opc: TargetOpcode::G_INTTOPTR, DstOps: {Dst}, SrcOps: {Src}); |
699 | } |
700 | |
701 | /// Build and insert \p Dst = G_BITCAST \p Src |
702 | MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { |
703 | return buildInstr(Opc: TargetOpcode::G_BITCAST, DstOps: {Dst}, SrcOps: {Src}); |
704 | } |
705 | |
706 | /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src |
707 | MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) { |
708 | return buildInstr(Opc: TargetOpcode::G_ADDRSPACE_CAST, DstOps: {Dst}, SrcOps: {Src}); |
709 | } |
710 | |
711 | /// \return The opcode of the extension the target wants to use for boolean |
712 | /// values. |
713 | unsigned getBoolExtOp(bool IsVec, bool IsFP) const; |
714 | |
715 | // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res |
716 | // = G_ZEXT \p Op depending on how the target wants to extend boolean values. |
717 | MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, |
718 | bool IsFP); |
719 | |
720 | // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1, |
721 | // or COPY depending on how the target wants to extend boolean values, using |
722 | // the original register size. |
723 | MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, |
724 | bool IsVector, |
725 | bool IsFP); |
726 | |
727 | /// Build and insert \p Res = G_ZEXT \p Op |
728 | /// |
729 | /// G_ZEXT produces a register of the specified width, with bits 0 to |
730 | /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector |
731 | /// register, each element is extended individually. |
732 | /// |
733 | /// \pre setBasicBlock or setMI must have been called. |
734 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
735 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
736 | /// \pre \p Op must be smaller than \p Res |
737 | /// |
738 | /// \return The newly created instruction. |
739 | MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op); |
740 | |
741 | /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or |
742 | /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. |
743 | /// /// |
744 | /// \pre setBasicBlock or setMI must have been called. |
745 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
746 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
747 | /// |
748 | /// \return The newly created instruction. |
749 | MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op); |
750 | |
751 | /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or |
752 | /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. |
753 | /// /// |
754 | /// \pre setBasicBlock or setMI must have been called. |
755 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
756 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
757 | /// |
758 | /// \return The newly created instruction. |
759 | MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op); |
760 | |
761 | // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or |
762 | /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. |
763 | /// /// |
764 | /// \pre setBasicBlock or setMI must have been called. |
765 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
766 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
767 | /// |
768 | /// \return The newly created instruction. |
769 | MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op); |
770 | |
771 | /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p |
772 | /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and |
773 | /// \p Op. |
774 | /// /// |
775 | /// \pre setBasicBlock or setMI must have been called. |
776 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
777 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
778 | /// |
779 | /// \return The newly created instruction. |
780 | MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, |
781 | const SrcOp &Op); |
782 | |
783 | /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp) |
784 | /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is |
785 | /// emulated using G_AND. |
786 | MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, |
787 | int64_t ImmOp); |
788 | |
789 | /// Build and insert an appropriate cast between two registers of equal size. |
790 | MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src); |
791 | |
792 | /// Build and insert G_BR \p Dest |
793 | /// |
794 | /// G_BR is an unconditional branch to \p Dest. |
795 | /// |
796 | /// \pre setBasicBlock or setMI must have been called. |
797 | /// |
798 | /// \return a MachineInstrBuilder for the newly created instruction. |
799 | MachineInstrBuilder buildBr(MachineBasicBlock &Dest); |
800 | |
801 | /// Build and insert G_BRCOND \p Tst, \p Dest |
802 | /// |
803 | /// G_BRCOND is a conditional branch to \p Dest. |
804 | /// |
805 | /// \pre setBasicBlock or setMI must have been called. |
806 | /// \pre \p Tst must be a generic virtual register with scalar |
807 | /// type. At the beginning of legalization, this will be a single |
808 | /// bit (s1). Targets with interesting flags registers may change |
809 | /// this. For a wider type, whether the branch is taken must only |
810 | /// depend on bit 0 (for now). |
811 | /// |
812 | /// \return The newly created instruction. |
813 | MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest); |
814 | |
815 | /// Build and insert G_BRINDIRECT \p Tgt |
816 | /// |
817 | /// G_BRINDIRECT is an indirect branch to \p Tgt. |
818 | /// |
819 | /// \pre setBasicBlock or setMI must have been called. |
820 | /// \pre \p Tgt must be a generic virtual register with pointer type. |
821 | /// |
822 | /// \return a MachineInstrBuilder for the newly created instruction. |
823 | MachineInstrBuilder buildBrIndirect(Register Tgt); |
824 | |
825 | /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg |
826 | /// |
827 | /// G_BRJT is a jump table branch using a table base pointer \p TablePtr, |
828 | /// jump table index \p JTI and index \p IndexReg |
829 | /// |
830 | /// \pre setBasicBlock or setMI must have been called. |
831 | /// \pre \p TablePtr must be a generic virtual register with pointer type. |
832 | /// \pre \p JTI must be a jump table index. |
833 | /// \pre \p IndexReg must be a generic virtual register with pointer type. |
834 | /// |
835 | /// \return a MachineInstrBuilder for the newly created instruction. |
836 | MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, |
837 | Register IndexReg); |
838 | |
839 | /// Build and insert \p Res = G_CONSTANT \p Val |
840 | /// |
841 | /// G_CONSTANT is an integer constant with the specified size and value. \p |
842 | /// Val will be extended or truncated to the size of \p Reg. |
843 | /// |
844 | /// \pre setBasicBlock or setMI must have been called. |
845 | /// \pre \p Res must be a generic virtual register with scalar or pointer |
846 | /// type. |
847 | /// |
848 | /// \return The newly created instruction. |
849 | virtual MachineInstrBuilder buildConstant(const DstOp &Res, |
850 | const ConstantInt &Val); |
851 | |
852 | /// Build and insert \p Res = G_CONSTANT \p Val |
853 | /// |
854 | /// G_CONSTANT is an integer constant with the specified size and value. |
855 | /// |
856 | /// \pre setBasicBlock or setMI must have been called. |
857 | /// \pre \p Res must be a generic virtual register with scalar type. |
858 | /// |
859 | /// \return The newly created instruction. |
860 | MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val); |
861 | MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val); |
862 | |
863 | /// Build and insert \p Res = G_FCONSTANT \p Val |
864 | /// |
865 | /// G_FCONSTANT is a floating-point constant with the specified size and |
866 | /// value. |
867 | /// |
868 | /// \pre setBasicBlock or setMI must have been called. |
869 | /// \pre \p Res must be a generic virtual register with scalar type. |
870 | /// |
871 | /// \return The newly created instruction. |
872 | virtual MachineInstrBuilder buildFConstant(const DstOp &Res, |
873 | const ConstantFP &Val); |
874 | |
875 | MachineInstrBuilder buildFConstant(const DstOp &Res, double Val); |
876 | MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val); |
877 | |
878 | /// Build and insert \p Res = COPY Op |
879 | /// |
880 | /// Register-to-register COPY sets \p Res to \p Op. |
881 | /// |
882 | /// \pre setBasicBlock or setMI must have been called. |
883 | /// |
884 | /// \return a MachineInstrBuilder for the newly created instruction. |
885 | MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op); |
886 | |
887 | |
888 | /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN |
889 | /// |
890 | /// \return a MachineInstrBuilder for the newly created instruction. |
891 | MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, |
892 | const SrcOp &Op, unsigned Val) { |
893 | return buildInstr(Opc, DstOps: Res, SrcOps: Op).addImm(Val); |
894 | } |
895 | |
896 | /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size |
897 | /// |
898 | /// \return a MachineInstrBuilder for the newly created instruction. |
899 | MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, |
900 | unsigned Size) { |
901 | return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_ZEXT, Res, Op, Val: Size); |
902 | } |
903 | |
904 | /// Build and insert \p Res = G_ASSERT_SEXT Op, Size |
905 | /// |
906 | /// \return a MachineInstrBuilder for the newly created instruction. |
907 | MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, |
908 | unsigned Size) { |
909 | return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_SEXT, Res, Op, Val: Size); |
910 | } |
911 | |
912 | /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal |
913 | /// |
914 | /// \return a MachineInstrBuilder for the newly created instruction. |
915 | MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, |
916 | Align AlignVal) { |
917 | return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_ALIGN, Res, Op, |
918 | Val: AlignVal.value()); |
919 | } |
920 | |
921 | /// Build and insert `Res = G_LOAD Addr, MMO`. |
922 | /// |
923 | /// Loads the value stored at \p Addr. Puts the result in \p Res. |
924 | /// |
925 | /// \pre setBasicBlock or setMI must have been called. |
926 | /// \pre \p Res must be a generic virtual register. |
927 | /// \pre \p Addr must be a generic virtual register with pointer type. |
928 | /// |
929 | /// \return a MachineInstrBuilder for the newly created instruction. |
930 | MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, |
931 | MachineMemOperand &MMO) { |
932 | return buildLoadInstr(Opcode: TargetOpcode::G_LOAD, Res, Addr, MMO); |
933 | } |
934 | |
935 | /// Build and insert a G_LOAD instruction, while constructing the |
936 | /// MachineMemOperand. |
937 | MachineInstrBuilder |
938 | buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo, |
939 | Align Alignment, |
940 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
941 | const AAMDNodes &AAInfo = AAMDNodes()); |
942 | |
943 | /// Build and insert `Res = <opcode> Addr, MMO`. |
944 | /// |
945 | /// Loads the value stored at \p Addr. Puts the result in \p Res. |
946 | /// |
947 | /// \pre setBasicBlock or setMI must have been called. |
948 | /// \pre \p Res must be a generic virtual register. |
949 | /// \pre \p Addr must be a generic virtual register with pointer type. |
950 | /// |
951 | /// \return a MachineInstrBuilder for the newly created instruction. |
952 | MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, |
953 | const SrcOp &Addr, MachineMemOperand &MMO); |
954 | |
955 | /// Helper to create a load from a constant offset given a base address. Load |
956 | /// the type of \p Dst from \p Offset from the given base address and memory |
957 | /// operand. |
958 | MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, |
959 | const SrcOp &BasePtr, |
960 | MachineMemOperand &BaseMMO, |
961 | int64_t Offset); |
962 | |
963 | /// Build and insert `G_STORE Val, Addr, MMO`. |
964 | /// |
965 | /// Stores the value \p Val to \p Addr. |
966 | /// |
967 | /// \pre setBasicBlock or setMI must have been called. |
968 | /// \pre \p Val must be a generic virtual register. |
969 | /// \pre \p Addr must be a generic virtual register with pointer type. |
970 | /// |
971 | /// \return a MachineInstrBuilder for the newly created instruction. |
972 | MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, |
973 | MachineMemOperand &MMO); |
974 | |
975 | /// Build and insert a G_STORE instruction, while constructing the |
976 | /// MachineMemOperand. |
977 | MachineInstrBuilder |
978 | buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo, |
979 | Align Alignment, |
980 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
981 | const AAMDNodes &AAInfo = AAMDNodes()); |
982 | |
983 | /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`. |
984 | /// |
985 | /// \pre setBasicBlock or setMI must have been called. |
986 | /// \pre \p Res and \p Src must be generic virtual registers. |
987 | /// |
988 | /// \return a MachineInstrBuilder for the newly created instruction. |
989 | MachineInstrBuilder (const DstOp &Res, const SrcOp &Src, uint64_t Index); |
990 | |
991 | /// Build and insert \p Res = IMPLICIT_DEF. |
992 | MachineInstrBuilder buildUndef(const DstOp &Res); |
993 | |
994 | /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ... |
995 | /// |
996 | /// G_MERGE_VALUES combines the input elements contiguously into a larger |
997 | /// register. It should only be used when the destination register is not a |
998 | /// vector. |
999 | /// |
1000 | /// \pre setBasicBlock or setMI must have been called. |
1001 | /// \pre The entire register \p Res (and no more) must be covered by the input |
1002 | /// registers. |
1003 | /// \pre The type of all \p Ops registers must be identical. |
1004 | /// |
1005 | /// \return a MachineInstrBuilder for the newly created instruction. |
1006 | MachineInstrBuilder buildMergeValues(const DstOp &Res, |
1007 | ArrayRef<Register> Ops); |
1008 | |
1009 | /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ... |
1010 | /// or \p Res = G_BUILD_VECTOR \p Op0, ... |
1011 | /// or \p Res = G_CONCAT_VECTORS \p Op0, ... |
1012 | /// |
1013 | /// G_MERGE_VALUES combines the input elements contiguously into a larger |
1014 | /// register. It is used when the destination register is not a vector. |
1015 | /// G_BUILD_VECTOR combines scalar inputs into a vector register. |
1016 | /// G_CONCAT_VECTORS combines vector inputs into a vector register. |
1017 | /// |
1018 | /// \pre setBasicBlock or setMI must have been called. |
1019 | /// \pre The entire register \p Res (and no more) must be covered by the input |
1020 | /// registers. |
1021 | /// \pre The type of all \p Ops registers must be identical. |
1022 | /// |
1023 | /// \return a MachineInstrBuilder for the newly created instruction. The |
1024 | /// opcode of the new instruction will depend on the types of both |
1025 | /// the destination and the sources. |
1026 | MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, |
1027 | ArrayRef<Register> Ops); |
1028 | MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, |
1029 | std::initializer_list<SrcOp> Ops); |
1030 | |
1031 | /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op |
1032 | /// |
1033 | /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple |
1034 | /// |
1035 | /// \pre setBasicBlock or setMI must have been called. |
1036 | /// \pre The entire register \p Res (and no more) must be covered by the input |
1037 | /// registers. |
1038 | /// \pre The type of all \p Res registers must be identical. |
1039 | /// |
1040 | /// \return a MachineInstrBuilder for the newly created instruction. |
1041 | MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op); |
1042 | MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op); |
1043 | |
1044 | /// Build and insert an unmerge of \p Res sized pieces to cover \p Op |
1045 | MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op); |
1046 | |
1047 | /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... |
1048 | /// |
1049 | /// G_BUILD_VECTOR creates a vector value from multiple scalar registers. |
1050 | /// \pre setBasicBlock or setMI must have been called. |
1051 | /// \pre The entire register \p Res (and no more) must be covered by the |
1052 | /// input scalar registers. |
1053 | /// \pre The type of all \p Ops registers must be identical. |
1054 | /// |
1055 | /// \return a MachineInstrBuilder for the newly created instruction. |
1056 | MachineInstrBuilder buildBuildVector(const DstOp &Res, |
1057 | ArrayRef<Register> Ops); |
1058 | |
1059 | /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is |
1060 | /// built with G_CONSTANT. |
1061 | MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, |
1062 | ArrayRef<APInt> Ops); |
1063 | |
1064 | /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill |
1065 | /// the number of elements |
1066 | MachineInstrBuilder buildSplatVector(const DstOp &Res, |
1067 | const SrcOp &Src); |
1068 | |
1069 | /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ... |
1070 | /// |
1071 | /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers |
1072 | /// which have types larger than the destination vector element type, and |
1073 | /// truncates the values to fit. |
1074 | /// |
1075 | /// If the operands given are already the same size as the vector elt type, |
1076 | /// then this method will instead create a G_BUILD_VECTOR instruction. |
1077 | /// |
1078 | /// \pre setBasicBlock or setMI must have been called. |
1079 | /// \pre The type of all \p Ops registers must be identical. |
1080 | /// |
1081 | /// \return a MachineInstrBuilder for the newly created instruction. |
1082 | MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, |
1083 | ArrayRef<Register> Ops); |
1084 | |
1085 | /// Build and insert a vector splat of a scalar \p Src using a |
1086 | /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom. |
1087 | /// |
1088 | /// \pre setBasicBlock or setMI must have been called. |
1089 | /// \pre \p Src must have the same type as the element type of \p Dst |
1090 | /// |
1091 | /// \return a MachineInstrBuilder for the newly created instruction. |
1092 | MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src); |
1093 | |
1094 | /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask |
1095 | /// |
1096 | /// \pre setBasicBlock or setMI must have been called. |
1097 | /// |
1098 | /// \return a MachineInstrBuilder for the newly created instruction. |
1099 | MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, |
1100 | const SrcOp &Src2, ArrayRef<int> Mask); |
1101 | |
1102 | /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ... |
1103 | /// |
1104 | /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more |
1105 | /// vectors. |
1106 | /// |
1107 | /// \pre setBasicBlock or setMI must have been called. |
1108 | /// \pre The entire register \p Res (and no more) must be covered by the input |
1109 | /// registers. |
1110 | /// \pre The type of all source operands must be identical. |
1111 | /// |
1112 | /// \return a MachineInstrBuilder for the newly created instruction. |
1113 | MachineInstrBuilder buildConcatVectors(const DstOp &Res, |
1114 | ArrayRef<Register> Ops); |
1115 | |
1116 | MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, |
1117 | const SrcOp &Op, unsigned Index); |
1118 | |
1119 | /// Build and insert a G_INTRINSIC instruction. |
1120 | /// |
1121 | /// There are four different opcodes based on combinations of whether the |
1122 | /// intrinsic has side effects and whether it is convergent. These properties |
1123 | /// can be specified as explicit parameters, or else they are retrieved from |
1124 | /// the MCID for the intrinsic. |
1125 | /// |
1126 | /// The parameter \p Res provides the Registers or MOs that will be defined by |
1127 | /// this instruction. |
1128 | /// |
1129 | /// \pre setBasicBlock or setMI must have been called. |
1130 | /// |
1131 | /// \return a MachineInstrBuilder for the newly created instruction. |
1132 | MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res, |
1133 | bool HasSideEffects, bool isConvergent); |
1134 | MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res); |
1135 | MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res, |
1136 | bool HasSideEffects, bool isConvergent); |
1137 | MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res); |
1138 | |
1139 | /// Build and insert \p Res = G_FPTRUNC \p Op |
1140 | /// |
1141 | /// G_FPTRUNC converts a floating-point value into one with a smaller type. |
1142 | /// |
1143 | /// \pre setBasicBlock or setMI must have been called. |
1144 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
1145 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
1146 | /// \pre \p Res must be smaller than \p Op |
1147 | /// |
1148 | /// \return The newly created instruction. |
1149 | MachineInstrBuilder |
1150 | buildFPTrunc(const DstOp &Res, const SrcOp &Op, |
1151 | std::optional<unsigned> Flags = std::nullopt); |
1152 | |
1153 | /// Build and insert \p Res = G_TRUNC \p Op |
1154 | /// |
1155 | /// G_TRUNC extracts the low bits of a type. For a vector type each element is |
1156 | /// truncated independently before being packed into the destination. |
1157 | /// |
1158 | /// \pre setBasicBlock or setMI must have been called. |
1159 | /// \pre \p Res must be a generic virtual register with scalar or vector type. |
1160 | /// \pre \p Op must be a generic virtual register with scalar or vector type. |
1161 | /// \pre \p Res must be smaller than \p Op |
1162 | /// |
1163 | /// \return The newly created instruction. |
1164 | MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op); |
1165 | |
1166 | /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1 |
1167 | /// |
1168 | /// \pre setBasicBlock or setMI must have been called. |
1169 | |
1170 | /// \pre \p Res must be a generic virtual register with scalar or |
1171 | /// vector type. Typically this starts as s1 or <N x s1>. |
1172 | /// \pre \p Op0 and Op1 must be generic virtual registers with the |
1173 | /// same number of elements as \p Res. If \p Res is a scalar, |
1174 | /// \p Op0 must be either a scalar or pointer. |
1175 | /// \pre \p Pred must be an integer predicate. |
1176 | /// |
1177 | /// \return a MachineInstrBuilder for the newly created instruction. |
1178 | MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, |
1179 | const SrcOp &Op0, const SrcOp &Op1); |
1180 | |
1181 | /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1 |
1182 | /// |
1183 | /// \pre setBasicBlock or setMI must have been called. |
1184 | |
1185 | /// \pre \p Res must be a generic virtual register with scalar or |
1186 | /// vector type. Typically this starts as s1 or <N x s1>. |
1187 | /// \pre \p Op0 and Op1 must be generic virtual registers with the |
1188 | /// same number of elements as \p Res (or scalar, if \p Res is |
1189 | /// scalar). |
1190 | /// \pre \p Pred must be a floating-point predicate. |
1191 | /// |
1192 | /// \return a MachineInstrBuilder for the newly created instruction. |
1193 | MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, |
1194 | const SrcOp &Op0, const SrcOp &Op1, |
1195 | std::optional<unsigned> Flags = std::nullopt); |
1196 | |
1197 | /// Build and insert a \p Res = G_IS_FPCLASS \p Src, \p Mask |
1198 | MachineInstrBuilder buildIsFPClass(const DstOp &Res, const SrcOp &Src, |
1199 | unsigned Mask) { |
1200 | return buildInstr(Opc: TargetOpcode::G_IS_FPCLASS, DstOps: {Res}, |
1201 | SrcOps: {Src, SrcOp(static_cast<int64_t>(Mask))}); |
1202 | } |
1203 | |
1204 | /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1 |
1205 | /// |
1206 | /// \pre setBasicBlock or setMI must have been called. |
1207 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers |
1208 | /// with the same type. |
1209 | /// \pre \p Tst must be a generic virtual register with scalar, pointer or |
1210 | /// vector type. If vector then it must have the same number of |
1211 | /// elements as the other parameters. |
1212 | /// |
1213 | /// \return a MachineInstrBuilder for the newly created instruction. |
1214 | MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, |
1215 | const SrcOp &Op0, const SrcOp &Op1, |
1216 | std::optional<unsigned> Flags = std::nullopt); |
1217 | |
1218 | /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val, |
1219 | /// \p Elt, \p Idx |
1220 | /// |
1221 | /// \pre setBasicBlock or setMI must have been called. |
1222 | /// \pre \p Res and \p Val must be a generic virtual register |
1223 | // with the same vector type. |
1224 | /// \pre \p Elt and \p Idx must be a generic virtual register |
1225 | /// with scalar type. |
1226 | /// |
1227 | /// \return The newly created instruction. |
1228 | MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, |
1229 | const SrcOp &Val, |
1230 | const SrcOp &Elt, |
1231 | const SrcOp &Idx); |
1232 | |
1233 | /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx |
1234 | /// |
1235 | /// \pre setBasicBlock or setMI must have been called. |
1236 | /// \pre \p Res must be a generic virtual register with scalar type. |
1237 | /// \pre \p Val must be a generic virtual register with vector type. |
1238 | /// |
1239 | /// \return The newly created instruction. |
1240 | MachineInstrBuilder (const DstOp &Res, |
1241 | const SrcOp &Val, |
1242 | const int Idx) { |
1243 | return buildExtractVectorElement(Res, Val, |
1244 | Idx: buildConstant(Res: LLT::scalar(SizeInBits: 64), Val: Idx)); |
1245 | } |
1246 | |
1247 | /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx |
1248 | /// |
1249 | /// \pre setBasicBlock or setMI must have been called. |
1250 | /// \pre \p Res must be a generic virtual register with scalar type. |
1251 | /// \pre \p Val must be a generic virtual register with vector type. |
1252 | /// \pre \p Idx must be a generic virtual register with scalar type. |
1253 | /// |
1254 | /// \return The newly created instruction. |
1255 | MachineInstrBuilder (const DstOp &Res, |
1256 | const SrcOp &Val, |
1257 | const SrcOp &Idx); |
1258 | |
1259 | /// Build and insert `OldValRes<def>, SuccessRes<def> = |
1260 | /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`. |
1261 | /// |
1262 | /// Atomically replace the value at \p Addr with \p NewVal if it is currently |
1263 | /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p |
1264 | /// Addr in \p Res, along with an s1 indicating whether it was replaced. |
1265 | /// |
1266 | /// \pre setBasicBlock or setMI must have been called. |
1267 | /// \pre \p OldValRes must be a generic virtual register of scalar type. |
1268 | /// \pre \p SuccessRes must be a generic virtual register of scalar type. It |
1269 | /// will be assigned 0 on failure and 1 on success. |
1270 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1271 | /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual |
1272 | /// registers of the same type. |
1273 | /// |
1274 | /// \return a MachineInstrBuilder for the newly created instruction. |
1275 | MachineInstrBuilder |
1276 | buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, |
1277 | Register Addr, Register CmpVal, Register NewVal, |
1278 | MachineMemOperand &MMO); |
1279 | |
1280 | /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, |
1281 | /// MMO`. |
1282 | /// |
1283 | /// Atomically replace the value at \p Addr with \p NewVal if it is currently |
1284 | /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p |
1285 | /// Addr in \p Res. |
1286 | /// |
1287 | /// \pre setBasicBlock or setMI must have been called. |
1288 | /// \pre \p OldValRes must be a generic virtual register of scalar type. |
1289 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1290 | /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual |
1291 | /// registers of the same type. |
1292 | /// |
1293 | /// \return a MachineInstrBuilder for the newly created instruction. |
1294 | MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, |
1295 | Register CmpVal, Register NewVal, |
1296 | MachineMemOperand &MMO); |
1297 | |
1298 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`. |
1299 | /// |
1300 | /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the |
1301 | /// original value from \p Addr in \p OldValRes. The modification is |
1302 | /// determined by the opcode. |
1303 | /// |
1304 | /// \pre setBasicBlock or setMI must have been called. |
1305 | /// \pre \p OldValRes must be a generic virtual register. |
1306 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1307 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1308 | /// same type. |
1309 | /// |
1310 | /// \return a MachineInstrBuilder for the newly created instruction. |
1311 | MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, |
1312 | const SrcOp &Addr, const SrcOp &Val, |
1313 | MachineMemOperand &MMO); |
1314 | |
1315 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`. |
1316 | /// |
1317 | /// Atomically replace the value at \p Addr with \p Val. Puts the original |
1318 | /// value from \p Addr in \p OldValRes. |
1319 | /// |
1320 | /// \pre setBasicBlock or setMI must have been called. |
1321 | /// \pre \p OldValRes must be a generic virtual register. |
1322 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1323 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1324 | /// same type. |
1325 | /// |
1326 | /// \return a MachineInstrBuilder for the newly created instruction. |
1327 | MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, |
1328 | Register Val, MachineMemOperand &MMO); |
1329 | |
1330 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`. |
1331 | /// |
1332 | /// Atomically replace the value at \p Addr with the addition of \p Val and |
1333 | /// the original value. Puts the original value from \p Addr in \p OldValRes. |
1334 | /// |
1335 | /// \pre setBasicBlock or setMI must have been called. |
1336 | /// \pre \p OldValRes must be a generic virtual register. |
1337 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1338 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1339 | /// same type. |
1340 | /// |
1341 | /// \return a MachineInstrBuilder for the newly created instruction. |
1342 | MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, |
1343 | Register Val, MachineMemOperand &MMO); |
1344 | |
1345 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`. |
1346 | /// |
1347 | /// Atomically replace the value at \p Addr with the subtraction of \p Val and |
1348 | /// the original value. Puts the original value from \p Addr in \p OldValRes. |
1349 | /// |
1350 | /// \pre setBasicBlock or setMI must have been called. |
1351 | /// \pre \p OldValRes must be a generic virtual register. |
1352 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1353 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1354 | /// same type. |
1355 | /// |
1356 | /// \return a MachineInstrBuilder for the newly created instruction. |
1357 | MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, |
1358 | Register Val, MachineMemOperand &MMO); |
1359 | |
1360 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`. |
1361 | /// |
1362 | /// Atomically replace the value at \p Addr with the bitwise and of \p Val and |
1363 | /// the original value. Puts the original value from \p Addr in \p OldValRes. |
1364 | /// |
1365 | /// \pre setBasicBlock or setMI must have been called. |
1366 | /// \pre \p OldValRes must be a generic virtual register. |
1367 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1368 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1369 | /// same type. |
1370 | /// |
1371 | /// \return a MachineInstrBuilder for the newly created instruction. |
1372 | MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, |
1373 | Register Val, MachineMemOperand &MMO); |
1374 | |
1375 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`. |
1376 | /// |
1377 | /// Atomically replace the value at \p Addr with the bitwise nand of \p Val |
1378 | /// and the original value. Puts the original value from \p Addr in \p |
1379 | /// OldValRes. |
1380 | /// |
1381 | /// \pre setBasicBlock or setMI must have been called. |
1382 | /// \pre \p OldValRes must be a generic virtual register. |
1383 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1384 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1385 | /// same type. |
1386 | /// |
1387 | /// \return a MachineInstrBuilder for the newly created instruction. |
1388 | MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, |
1389 | Register Val, MachineMemOperand &MMO); |
1390 | |
1391 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`. |
1392 | /// |
1393 | /// Atomically replace the value at \p Addr with the bitwise or of \p Val and |
1394 | /// the original value. Puts the original value from \p Addr in \p OldValRes. |
1395 | /// |
1396 | /// \pre setBasicBlock or setMI must have been called. |
1397 | /// \pre \p OldValRes must be a generic virtual register. |
1398 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1399 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1400 | /// same type. |
1401 | /// |
1402 | /// \return a MachineInstrBuilder for the newly created instruction. |
1403 | MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, |
1404 | Register Val, MachineMemOperand &MMO); |
1405 | |
1406 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`. |
1407 | /// |
1408 | /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and |
1409 | /// the original value. Puts the original value from \p Addr in \p OldValRes. |
1410 | /// |
1411 | /// \pre setBasicBlock or setMI must have been called. |
1412 | /// \pre \p OldValRes must be a generic virtual register. |
1413 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1414 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1415 | /// same type. |
1416 | /// |
1417 | /// \return a MachineInstrBuilder for the newly created instruction. |
1418 | MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, |
1419 | Register Val, MachineMemOperand &MMO); |
1420 | |
1421 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`. |
1422 | /// |
1423 | /// Atomically replace the value at \p Addr with the signed maximum of \p |
1424 | /// Val and the original value. Puts the original value from \p Addr in \p |
1425 | /// OldValRes. |
1426 | /// |
1427 | /// \pre setBasicBlock or setMI must have been called. |
1428 | /// \pre \p OldValRes must be a generic virtual register. |
1429 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1430 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1431 | /// same type. |
1432 | /// |
1433 | /// \return a MachineInstrBuilder for the newly created instruction. |
1434 | MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, |
1435 | Register Val, MachineMemOperand &MMO); |
1436 | |
1437 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`. |
1438 | /// |
1439 | /// Atomically replace the value at \p Addr with the signed minimum of \p |
1440 | /// Val and the original value. Puts the original value from \p Addr in \p |
1441 | /// OldValRes. |
1442 | /// |
1443 | /// \pre setBasicBlock or setMI must have been called. |
1444 | /// \pre \p OldValRes must be a generic virtual register. |
1445 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1446 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1447 | /// same type. |
1448 | /// |
1449 | /// \return a MachineInstrBuilder for the newly created instruction. |
1450 | MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, |
1451 | Register Val, MachineMemOperand &MMO); |
1452 | |
1453 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`. |
1454 | /// |
1455 | /// Atomically replace the value at \p Addr with the unsigned maximum of \p |
1456 | /// Val and the original value. Puts the original value from \p Addr in \p |
1457 | /// OldValRes. |
1458 | /// |
1459 | /// \pre setBasicBlock or setMI must have been called. |
1460 | /// \pre \p OldValRes must be a generic virtual register. |
1461 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1462 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1463 | /// same type. |
1464 | /// |
1465 | /// \return a MachineInstrBuilder for the newly created instruction. |
1466 | MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, |
1467 | Register Val, MachineMemOperand &MMO); |
1468 | |
1469 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`. |
1470 | /// |
1471 | /// Atomically replace the value at \p Addr with the unsigned minimum of \p |
1472 | /// Val and the original value. Puts the original value from \p Addr in \p |
1473 | /// OldValRes. |
1474 | /// |
1475 | /// \pre setBasicBlock or setMI must have been called. |
1476 | /// \pre \p OldValRes must be a generic virtual register. |
1477 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1478 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1479 | /// same type. |
1480 | /// |
1481 | /// \return a MachineInstrBuilder for the newly created instruction. |
1482 | MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, |
1483 | Register Val, MachineMemOperand &MMO); |
1484 | |
1485 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`. |
1486 | MachineInstrBuilder buildAtomicRMWFAdd( |
1487 | const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, |
1488 | MachineMemOperand &MMO); |
1489 | |
1490 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`. |
1491 | MachineInstrBuilder buildAtomicRMWFSub( |
1492 | const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, |
1493 | MachineMemOperand &MMO); |
1494 | |
1495 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`. |
1496 | /// |
1497 | /// Atomically replace the value at \p Addr with the floating point maximum of |
1498 | /// \p Val and the original value. Puts the original value from \p Addr in \p |
1499 | /// OldValRes. |
1500 | /// |
1501 | /// \pre setBasicBlock or setMI must have been called. |
1502 | /// \pre \p OldValRes must be a generic virtual register. |
1503 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1504 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1505 | /// same type. |
1506 | /// |
1507 | /// \return a MachineInstrBuilder for the newly created instruction. |
1508 | MachineInstrBuilder buildAtomicRMWFMax( |
1509 | const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, |
1510 | MachineMemOperand &MMO); |
1511 | |
1512 | /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`. |
1513 | /// |
1514 | /// Atomically replace the value at \p Addr with the floating point minimum of |
1515 | /// \p Val and the original value. Puts the original value from \p Addr in \p |
1516 | /// OldValRes. |
1517 | /// |
1518 | /// \pre setBasicBlock or setMI must have been called. |
1519 | /// \pre \p OldValRes must be a generic virtual register. |
1520 | /// \pre \p Addr must be a generic virtual register with pointer type. |
1521 | /// \pre \p OldValRes, and \p Val must be generic virtual registers of the |
1522 | /// same type. |
1523 | /// |
1524 | /// \return a MachineInstrBuilder for the newly created instruction. |
1525 | MachineInstrBuilder buildAtomicRMWFMin( |
1526 | const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, |
1527 | MachineMemOperand &MMO); |
1528 | |
1529 | /// Build and insert `G_FENCE Ordering, Scope`. |
1530 | MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope); |
1531 | |
1532 | /// Build and insert G_PREFETCH \p Addr, \p RW, \p Locality, \p CacheType |
1533 | MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW, |
1534 | unsigned Locality, unsigned CacheType, |
1535 | MachineMemOperand &MMO); |
1536 | |
1537 | /// Build and insert \p Dst = G_FREEZE \p Src |
1538 | MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) { |
1539 | return buildInstr(Opc: TargetOpcode::G_FREEZE, DstOps: {Dst}, SrcOps: {Src}); |
1540 | } |
1541 | |
1542 | /// Build and insert \p Res = G_BLOCK_ADDR \p BA |
1543 | /// |
1544 | /// G_BLOCK_ADDR computes the address of a basic block. |
1545 | /// |
1546 | /// \pre setBasicBlock or setMI must have been called. |
1547 | /// \pre \p Res must be a generic virtual register of a pointer type. |
1548 | /// |
1549 | /// \return The newly created instruction. |
1550 | MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA); |
1551 | |
1552 | /// Build and insert \p Res = G_ADD \p Op0, \p Op1 |
1553 | /// |
1554 | /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1, |
1555 | /// truncated to their width. |
1556 | /// |
1557 | /// \pre setBasicBlock or setMI must have been called. |
1558 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers |
1559 | /// with the same (scalar or vector) type). |
1560 | /// |
1561 | /// \return a MachineInstrBuilder for the newly created instruction. |
1562 | |
1563 | MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, |
1564 | const SrcOp &Src1, |
1565 | std::optional<unsigned> Flags = std::nullopt) { |
1566 | return buildInstr(Opc: TargetOpcode::G_ADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1567 | } |
1568 | |
1569 | /// Build and insert \p Res = G_SUB \p Op0, \p Op1 |
1570 | /// |
1571 | /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and |
1572 | /// \p Op1, truncated to their width. |
1573 | /// |
1574 | /// \pre setBasicBlock or setMI must have been called. |
1575 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers |
1576 | /// with the same (scalar or vector) type). |
1577 | /// |
1578 | /// \return a MachineInstrBuilder for the newly created instruction. |
1579 | |
1580 | MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, |
1581 | const SrcOp &Src1, |
1582 | std::optional<unsigned> Flags = std::nullopt) { |
1583 | return buildInstr(Opc: TargetOpcode::G_SUB, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1584 | } |
1585 | |
1586 | /// Build and insert \p Res = G_MUL \p Op0, \p Op1 |
1587 | /// |
1588 | /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1, |
1589 | /// truncated to their width. |
1590 | /// |
1591 | /// \pre setBasicBlock or setMI must have been called. |
1592 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers |
1593 | /// with the same (scalar or vector) type). |
1594 | /// |
1595 | /// \return a MachineInstrBuilder for the newly created instruction. |
1596 | MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, |
1597 | const SrcOp &Src1, |
1598 | std::optional<unsigned> Flags = std::nullopt) { |
1599 | return buildInstr(Opc: TargetOpcode::G_MUL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1600 | } |
1601 | |
1602 | MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, |
1603 | const SrcOp &Src1, |
1604 | std::optional<unsigned> Flags = std::nullopt) { |
1605 | return buildInstr(Opc: TargetOpcode::G_UMULH, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1606 | } |
1607 | |
1608 | MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, |
1609 | const SrcOp &Src1, |
1610 | std::optional<unsigned> Flags = std::nullopt) { |
1611 | return buildInstr(Opc: TargetOpcode::G_SMULH, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1612 | } |
1613 | |
1614 | /// Build and insert \p Res = G_UREM \p Op0, \p Op1 |
1615 | MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, |
1616 | const SrcOp &Src1, |
1617 | std::optional<unsigned> Flags = std::nullopt) { |
1618 | return buildInstr(Opc: TargetOpcode::G_UREM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1619 | } |
1620 | |
1621 | MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, |
1622 | const SrcOp &Src1, |
1623 | std::optional<unsigned> Flags = std::nullopt) { |
1624 | return buildInstr(Opc: TargetOpcode::G_FMUL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1625 | } |
1626 | |
1627 | MachineInstrBuilder |
1628 | buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, |
1629 | std::optional<unsigned> Flags = std::nullopt) { |
1630 | return buildInstr(Opc: TargetOpcode::G_FMINNUM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1631 | } |
1632 | |
1633 | MachineInstrBuilder |
1634 | buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, |
1635 | std::optional<unsigned> Flags = std::nullopt) { |
1636 | return buildInstr(Opc: TargetOpcode::G_FMAXNUM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1637 | } |
1638 | |
1639 | MachineInstrBuilder |
1640 | buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, |
1641 | std::optional<unsigned> Flags = std::nullopt) { |
1642 | return buildInstr(Opc: TargetOpcode::G_FMINNUM_IEEE, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1643 | } |
1644 | |
1645 | MachineInstrBuilder |
1646 | buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, |
1647 | std::optional<unsigned> Flags = std::nullopt) { |
1648 | return buildInstr(Opc: TargetOpcode::G_FMAXNUM_IEEE, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1649 | } |
1650 | |
1651 | MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, |
1652 | const SrcOp &Src1, |
1653 | std::optional<unsigned> Flags = std::nullopt) { |
1654 | return buildInstr(Opc: TargetOpcode::G_SHL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1655 | } |
1656 | |
1657 | MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, |
1658 | const SrcOp &Src1, |
1659 | std::optional<unsigned> Flags = std::nullopt) { |
1660 | return buildInstr(Opc: TargetOpcode::G_LSHR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1661 | } |
1662 | |
1663 | MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, |
1664 | const SrcOp &Src1, |
1665 | std::optional<unsigned> Flags = std::nullopt) { |
1666 | return buildInstr(Opc: TargetOpcode::G_ASHR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1667 | } |
1668 | |
1669 | /// Build and insert \p Res = G_AND \p Op0, \p Op1 |
1670 | /// |
1671 | /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p |
1672 | /// Op1. |
1673 | /// |
1674 | /// \pre setBasicBlock or setMI must have been called. |
1675 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers |
1676 | /// with the same (scalar or vector) type). |
1677 | /// |
1678 | /// \return a MachineInstrBuilder for the newly created instruction. |
1679 | |
1680 | MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, |
1681 | const SrcOp &Src1) { |
1682 | return buildInstr(Opc: TargetOpcode::G_AND, DstOps: {Dst}, SrcOps: {Src0, Src1}); |
1683 | } |
1684 | |
1685 | /// Build and insert \p Res = G_OR \p Op0, \p Op1 |
1686 | /// |
1687 | /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p |
1688 | /// Op1. |
1689 | /// |
1690 | /// \pre setBasicBlock or setMI must have been called. |
1691 | /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers |
1692 | /// with the same (scalar or vector) type). |
1693 | /// |
1694 | /// \return a MachineInstrBuilder for the newly created instruction. |
1695 | MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, |
1696 | const SrcOp &Src1, |
1697 | std::optional<unsigned> Flags = std::nullopt) { |
1698 | return buildInstr(Opc: TargetOpcode::G_OR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1699 | } |
1700 | |
1701 | /// Build and insert \p Res = G_XOR \p Op0, \p Op1 |
1702 | MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, |
1703 | const SrcOp &Src1) { |
1704 | return buildInstr(Opc: TargetOpcode::G_XOR, DstOps: {Dst}, SrcOps: {Src0, Src1}); |
1705 | } |
1706 | |
1707 | /// Build and insert a bitwise not, |
1708 | /// \p NegOne = G_CONSTANT -1 |
1709 | /// \p Res = G_OR \p Op0, NegOne |
1710 | MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { |
1711 | auto NegOne = buildConstant(Res: Dst.getLLTTy(MRI: *getMRI()), Val: -1); |
1712 | return buildInstr(Opc: TargetOpcode::G_XOR, DstOps: {Dst}, SrcOps: {Src0, NegOne}); |
1713 | } |
1714 | |
1715 | /// Build and insert integer negation |
1716 | /// \p Zero = G_CONSTANT 0 |
1717 | /// \p Res = G_SUB Zero, \p Op0 |
1718 | MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) { |
1719 | auto Zero = buildConstant(Res: Dst.getLLTTy(MRI: *getMRI()), Val: 0); |
1720 | return buildInstr(Opc: TargetOpcode::G_SUB, DstOps: {Dst}, SrcOps: {Zero, Src0}); |
1721 | } |
1722 | |
1723 | /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0 |
1724 | MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { |
1725 | return buildInstr(Opc: TargetOpcode::G_CTPOP, DstOps: {Dst}, SrcOps: {Src0}); |
1726 | } |
1727 | |
1728 | /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0 |
1729 | MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { |
1730 | return buildInstr(Opc: TargetOpcode::G_CTLZ, DstOps: {Dst}, SrcOps: {Src0}); |
1731 | } |
1732 | |
1733 | /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0 |
1734 | MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { |
1735 | return buildInstr(Opc: TargetOpcode::G_CTLZ_ZERO_UNDEF, DstOps: {Dst}, SrcOps: {Src0}); |
1736 | } |
1737 | |
1738 | /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0 |
1739 | MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { |
1740 | return buildInstr(Opc: TargetOpcode::G_CTTZ, DstOps: {Dst}, SrcOps: {Src0}); |
1741 | } |
1742 | |
1743 | /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0 |
1744 | MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { |
1745 | return buildInstr(Opc: TargetOpcode::G_CTTZ_ZERO_UNDEF, DstOps: {Dst}, SrcOps: {Src0}); |
1746 | } |
1747 | |
1748 | /// Build and insert \p Dst = G_BSWAP \p Src0 |
1749 | MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) { |
1750 | return buildInstr(Opc: TargetOpcode::G_BSWAP, DstOps: {Dst}, SrcOps: {Src0}); |
1751 | } |
1752 | |
1753 | /// Build and insert \p Res = G_FADD \p Op0, \p Op1 |
1754 | MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, |
1755 | const SrcOp &Src1, |
1756 | std::optional<unsigned> Flags = std::nullopt) { |
1757 | return buildInstr(Opc: TargetOpcode::G_FADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1758 | } |
1759 | |
1760 | /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1 |
1761 | MachineInstrBuilder |
1762 | buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, |
1763 | std::optional<unsigned> Flags = std::nullopt) { |
1764 | return buildInstr(Opc: TargetOpcode::G_STRICT_FADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1765 | } |
1766 | |
1767 | /// Build and insert \p Res = G_FSUB \p Op0, \p Op1 |
1768 | MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, |
1769 | const SrcOp &Src1, |
1770 | std::optional<unsigned> Flags = std::nullopt) { |
1771 | return buildInstr(Opc: TargetOpcode::G_FSUB, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1772 | } |
1773 | |
1774 | /// Build and insert \p Res = G_FDIV \p Op0, \p Op1 |
1775 | MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, |
1776 | const SrcOp &Src1, |
1777 | std::optional<unsigned> Flags = std::nullopt) { |
1778 | return buildInstr(Opc: TargetOpcode::G_FDIV, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1779 | } |
1780 | |
1781 | /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2 |
1782 | MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, |
1783 | const SrcOp &Src1, const SrcOp &Src2, |
1784 | std::optional<unsigned> Flags = std::nullopt) { |
1785 | return buildInstr(Opc: TargetOpcode::G_FMA, DstOps: {Dst}, SrcOps: {Src0, Src1, Src2}, Flags); |
1786 | } |
1787 | |
1788 | /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2 |
1789 | MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, |
1790 | const SrcOp &Src1, const SrcOp &Src2, |
1791 | std::optional<unsigned> Flags = std::nullopt) { |
1792 | return buildInstr(Opc: TargetOpcode::G_FMAD, DstOps: {Dst}, SrcOps: {Src0, Src1, Src2}, Flags); |
1793 | } |
1794 | |
1795 | /// Build and insert \p Res = G_FNEG \p Op0 |
1796 | MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, |
1797 | std::optional<unsigned> Flags = std::nullopt) { |
1798 | return buildInstr(Opc: TargetOpcode::G_FNEG, DstOps: {Dst}, SrcOps: {Src0}, Flags); |
1799 | } |
1800 | |
1801 | /// Build and insert \p Res = G_FABS \p Op0 |
1802 | MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, |
1803 | std::optional<unsigned> Flags = std::nullopt) { |
1804 | return buildInstr(Opc: TargetOpcode::G_FABS, DstOps: {Dst}, SrcOps: {Src0}, Flags); |
1805 | } |
1806 | |
1807 | /// Build and insert \p Dst = G_FCANONICALIZE \p Src0 |
1808 | MachineInstrBuilder |
1809 | buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, |
1810 | std::optional<unsigned> Flags = std::nullopt) { |
1811 | return buildInstr(Opc: TargetOpcode::G_FCANONICALIZE, DstOps: {Dst}, SrcOps: {Src0}, Flags); |
1812 | } |
1813 | |
1814 | /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0 |
1815 | MachineInstrBuilder |
1816 | buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, |
1817 | std::optional<unsigned> Flags = std::nullopt) { |
1818 | return buildInstr(Opc: TargetOpcode::G_INTRINSIC_TRUNC, DstOps: {Dst}, SrcOps: {Src0}, Flags); |
1819 | } |
1820 | |
1821 | /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1 |
1822 | MachineInstrBuilder |
1823 | buildFFloor(const DstOp &Dst, const SrcOp &Src0, |
1824 | std::optional<unsigned> Flags = std::nullopt) { |
1825 | return buildInstr(Opc: TargetOpcode::G_FFLOOR, DstOps: {Dst}, SrcOps: {Src0}, Flags); |
1826 | } |
1827 | |
1828 | /// Build and insert \p Dst = G_FLOG \p Src |
1829 | MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, |
1830 | std::optional<unsigned> Flags = std::nullopt) { |
1831 | return buildInstr(Opc: TargetOpcode::G_FLOG, DstOps: {Dst}, SrcOps: {Src}, Flags); |
1832 | } |
1833 | |
1834 | /// Build and insert \p Dst = G_FLOG2 \p Src |
1835 | MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, |
1836 | std::optional<unsigned> Flags = std::nullopt) { |
1837 | return buildInstr(Opc: TargetOpcode::G_FLOG2, DstOps: {Dst}, SrcOps: {Src}, Flags); |
1838 | } |
1839 | |
1840 | /// Build and insert \p Dst = G_FEXP2 \p Src |
1841 | MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, |
1842 | std::optional<unsigned> Flags = std::nullopt) { |
1843 | return buildInstr(Opc: TargetOpcode::G_FEXP2, DstOps: {Dst}, SrcOps: {Src}, Flags); |
1844 | } |
1845 | |
1846 | /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1 |
1847 | MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, |
1848 | const SrcOp &Src1, |
1849 | std::optional<unsigned> Flags = std::nullopt) { |
1850 | return buildInstr(Opc: TargetOpcode::G_FPOW, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1851 | } |
1852 | |
1853 | /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1 |
1854 | MachineInstrBuilder |
1855 | buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, |
1856 | std::optional<unsigned> Flags = std::nullopt) { |
1857 | return buildInstr(Opc: TargetOpcode::G_FLDEXP, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags); |
1858 | } |
1859 | |
1860 | /// Build and insert \p Fract, \p Exp = G_FFREXP \p Src |
1861 | MachineInstrBuilder |
1862 | buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src, |
1863 | std::optional<unsigned> Flags = std::nullopt) { |
1864 | return buildInstr(Opc: TargetOpcode::G_FFREXP, DstOps: {Fract, Exp}, SrcOps: {Src}, Flags); |
1865 | } |
1866 | |
1867 | /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1 |
1868 | MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, |
1869 | const SrcOp &Src1) { |
1870 | return buildInstr(Opc: TargetOpcode::G_FCOPYSIGN, DstOps: {Dst}, SrcOps: {Src0, Src1}); |
1871 | } |
1872 | |
1873 | /// Build and insert \p Res = G_UITOFP \p Src0 |
1874 | MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) { |
1875 | return buildInstr(Opc: TargetOpcode::G_UITOFP, DstOps: {Dst}, SrcOps: {Src0}); |
1876 | } |
1877 | |
1878 | /// Build and insert \p Res = G_SITOFP \p Src0 |
1879 | MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) { |
1880 | return buildInstr(Opc: TargetOpcode::G_SITOFP, DstOps: {Dst}, SrcOps: {Src0}); |
1881 | } |
1882 | |
1883 | /// Build and insert \p Res = G_FPTOUI \p Src0 |
1884 | MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) { |
1885 | return buildInstr(Opc: TargetOpcode::G_FPTOUI, DstOps: {Dst}, SrcOps: {Src0}); |
1886 | } |
1887 | |
1888 | /// Build and insert \p Res = G_FPTOSI \p Src0 |
1889 | MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) { |
1890 | return buildInstr(Opc: TargetOpcode::G_FPTOSI, DstOps: {Dst}, SrcOps: {Src0}); |
1891 | } |
1892 | |
1893 | /// Build and insert \p Dst = G_INTRINSIC_ROUNDEVEN \p Src0, \p Src1 |
1894 | MachineInstrBuilder |
1895 | buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0, |
1896 | std::optional<unsigned> Flags = std::nullopt) { |
1897 | return buildInstr(Opc: TargetOpcode::G_INTRINSIC_ROUNDEVEN, DstOps: {Dst}, SrcOps: {Src0}, |
1898 | Flags); |
1899 | } |
1900 | |
1901 | /// Build and insert \p Res = G_SMIN \p Op0, \p Op1 |
1902 | MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, |
1903 | const SrcOp &Src1) { |
1904 | return buildInstr(Opc: TargetOpcode::G_SMIN, DstOps: {Dst}, SrcOps: {Src0, Src1}); |
1905 | } |
1906 | |
1907 | /// Build and insert \p Res = G_SMAX \p Op0, \p Op1 |
1908 | MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, |
1909 | const SrcOp &Src1) { |
1910 | return buildInstr(Opc: TargetOpcode::G_SMAX, DstOps: {Dst}, SrcOps: {Src0, Src1}); |
1911 | } |
1912 | |
1913 | /// Build and insert \p Res = G_UMIN \p Op0, \p Op1 |
1914 | MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, |
1915 | const SrcOp &Src1) { |
1916 | return buildInstr(Opc: TargetOpcode::G_UMIN, DstOps: {Dst}, SrcOps: {Src0, Src1}); |
1917 | } |
1918 | |
1919 | /// Build and insert \p Res = G_UMAX \p Op0, \p Op1 |
1920 | MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, |
1921 | const SrcOp &Src1) { |
1922 | return buildInstr(Opc: TargetOpcode::G_UMAX, DstOps: {Dst}, SrcOps: {Src0, Src1}); |
1923 | } |
1924 | |
1925 | /// Build and insert \p Dst = G_ABS \p Src |
1926 | MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) { |
1927 | return buildInstr(Opc: TargetOpcode::G_ABS, DstOps: {Dst}, SrcOps: {Src}); |
1928 | } |
1929 | |
1930 | /// Build and insert \p Res = G_JUMP_TABLE \p JTI |
1931 | /// |
1932 | /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by |
1933 | /// the jump table index \p JTI. |
1934 | /// |
1935 | /// \return a MachineInstrBuilder for the newly created instruction. |
1936 | MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI); |
1937 | |
1938 | /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn |
1939 | /// |
1940 | /// \p ScalarIn is the scalar accumulator input to start the sequential |
1941 | /// reduction operation of \p VecIn. |
1942 | MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, |
1943 | const SrcOp &ScalarIn, |
1944 | const SrcOp &VecIn) { |
1945 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SEQ_FADD, DstOps: {Dst}, |
1946 | SrcOps: {ScalarIn, {VecIn}}); |
1947 | } |
1948 | |
1949 | /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn |
1950 | /// |
1951 | /// \p ScalarIn is the scalar accumulator input to start the sequential |
1952 | /// reduction operation of \p VecIn. |
1953 | MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, |
1954 | const SrcOp &ScalarIn, |
1955 | const SrcOp &VecIn) { |
1956 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SEQ_FMUL, DstOps: {Dst}, |
1957 | SrcOps: {ScalarIn, {VecIn}}); |
1958 | } |
1959 | |
1960 | /// Build and insert \p Res = G_VECREDUCE_FADD \p Src |
1961 | /// |
1962 | /// \p ScalarIn is the scalar accumulator input to the reduction operation of |
1963 | /// \p VecIn. |
1964 | MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, |
1965 | const SrcOp &ScalarIn, |
1966 | const SrcOp &VecIn) { |
1967 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FADD, DstOps: {Dst}, SrcOps: {ScalarIn, VecIn}); |
1968 | } |
1969 | |
1970 | /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src |
1971 | /// |
1972 | /// \p ScalarIn is the scalar accumulator input to the reduction operation of |
1973 | /// \p VecIn. |
1974 | MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, |
1975 | const SrcOp &ScalarIn, |
1976 | const SrcOp &VecIn) { |
1977 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMUL, DstOps: {Dst}, SrcOps: {ScalarIn, VecIn}); |
1978 | } |
1979 | |
1980 | /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src |
1981 | MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src) { |
1982 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMAX, DstOps: {Dst}, SrcOps: {Src}); |
1983 | } |
1984 | |
1985 | /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src |
1986 | MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src) { |
1987 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMIN, DstOps: {Dst}, SrcOps: {Src}); |
1988 | } |
1989 | |
1990 | /// Build and insert \p Res = G_VECREDUCE_FMAXIMUM \p Src |
1991 | MachineInstrBuilder buildVecReduceFMaximum(const DstOp &Dst, |
1992 | const SrcOp &Src) { |
1993 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMAXIMUM, DstOps: {Dst}, SrcOps: {Src}); |
1994 | } |
1995 | |
1996 | /// Build and insert \p Res = G_VECREDUCE_FMINIMUM \p Src |
1997 | MachineInstrBuilder buildVecReduceFMinimum(const DstOp &Dst, |
1998 | const SrcOp &Src) { |
1999 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMINIMUM, DstOps: {Dst}, SrcOps: {Src}); |
2000 | } |
2001 | |
2002 | /// Build and insert \p Res = G_VECREDUCE_ADD \p Src |
2003 | MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src) { |
2004 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_ADD, DstOps: {Dst}, SrcOps: {Src}); |
2005 | } |
2006 | |
2007 | /// Build and insert \p Res = G_VECREDUCE_MUL \p Src |
2008 | MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src) { |
2009 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_MUL, DstOps: {Dst}, SrcOps: {Src}); |
2010 | } |
2011 | |
2012 | /// Build and insert \p Res = G_VECREDUCE_AND \p Src |
2013 | MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src) { |
2014 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_AND, DstOps: {Dst}, SrcOps: {Src}); |
2015 | } |
2016 | |
2017 | /// Build and insert \p Res = G_VECREDUCE_OR \p Src |
2018 | MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src) { |
2019 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_OR, DstOps: {Dst}, SrcOps: {Src}); |
2020 | } |
2021 | |
2022 | /// Build and insert \p Res = G_VECREDUCE_XOR \p Src |
2023 | MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src) { |
2024 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_XOR, DstOps: {Dst}, SrcOps: {Src}); |
2025 | } |
2026 | |
2027 | /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src |
2028 | MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src) { |
2029 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SMAX, DstOps: {Dst}, SrcOps: {Src}); |
2030 | } |
2031 | |
2032 | /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src |
2033 | MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src) { |
2034 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SMIN, DstOps: {Dst}, SrcOps: {Src}); |
2035 | } |
2036 | |
2037 | /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src |
2038 | MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src) { |
2039 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_UMAX, DstOps: {Dst}, SrcOps: {Src}); |
2040 | } |
2041 | |
2042 | /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src |
2043 | MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src) { |
2044 | return buildInstr(Opc: TargetOpcode::G_VECREDUCE_UMIN, DstOps: {Dst}, SrcOps: {Src}); |
2045 | } |
2046 | |
2047 | /// Build and insert G_MEMCPY or G_MEMMOVE |
2048 | MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, |
2049 | const SrcOp &SrcPtr, |
2050 | const SrcOp &Size, |
2051 | MachineMemOperand &DstMMO, |
2052 | MachineMemOperand &SrcMMO) { |
2053 | auto MIB = buildInstr( |
2054 | Opc: Opcode, DstOps: {}, SrcOps: {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)}); |
2055 | MIB.addMemOperand(MMO: &DstMMO); |
2056 | MIB.addMemOperand(MMO: &SrcMMO); |
2057 | return MIB; |
2058 | } |
2059 | |
2060 | MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, |
2061 | const SrcOp &Size, MachineMemOperand &DstMMO, |
2062 | MachineMemOperand &SrcMMO) { |
2063 | return buildMemTransferInst(Opcode: TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size, |
2064 | DstMMO, SrcMMO); |
2065 | } |
2066 | |
2067 | /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width. |
2068 | MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, |
2069 | const SrcOp &LSB, const SrcOp &Width) { |
2070 | return buildInstr(Opc: TargetOpcode::G_SBFX, DstOps: {Dst}, SrcOps: {Src, LSB, Width}); |
2071 | } |
2072 | |
2073 | /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width. |
2074 | MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, |
2075 | const SrcOp &LSB, const SrcOp &Width) { |
2076 | return buildInstr(Opc: TargetOpcode::G_UBFX, DstOps: {Dst}, SrcOps: {Src, LSB, Width}); |
2077 | } |
2078 | |
2079 | /// Build and insert \p Dst = G_ROTR \p Src, \p Amt |
2080 | MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, |
2081 | const SrcOp &Amt) { |
2082 | return buildInstr(Opc: TargetOpcode::G_ROTR, DstOps: {Dst}, SrcOps: {Src, Amt}); |
2083 | } |
2084 | |
2085 | /// Build and insert \p Dst = G_ROTL \p Src, \p Amt |
2086 | MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, |
2087 | const SrcOp &Amt) { |
2088 | return buildInstr(Opc: TargetOpcode::G_ROTL, DstOps: {Dst}, SrcOps: {Src, Amt}); |
2089 | } |
2090 | |
2091 | /// Build and insert \p Dst = G_BITREVERSE \p Src |
2092 | MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src) { |
2093 | return buildInstr(Opc: TargetOpcode::G_BITREVERSE, DstOps: {Dst}, SrcOps: {Src}); |
2094 | } |
2095 | |
2096 | virtual MachineInstrBuilder |
2097 | buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps, |
2098 | std::optional<unsigned> Flags = std::nullopt); |
2099 | }; |
2100 | |
2101 | } // End namespace llvm. |
2102 | #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H |
2103 | |