1 | //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the PowerPC implementation of the TargetRegisterInfo |
10 | // class. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #include "PPCRegisterInfo.h" |
15 | #include "PPCFrameLowering.h" |
16 | #include "PPCInstrBuilder.h" |
17 | #include "PPCMachineFunctionInfo.h" |
18 | #include "PPCSubtarget.h" |
19 | #include "PPCTargetMachine.h" |
20 | #include "llvm/ADT/BitVector.h" |
21 | #include "llvm/ADT/STLExtras.h" |
22 | #include "llvm/ADT/Statistic.h" |
23 | #include "llvm/CodeGen/MachineFrameInfo.h" |
24 | #include "llvm/CodeGen/MachineFunction.h" |
25 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
26 | #include "llvm/CodeGen/MachineModuleInfo.h" |
27 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
28 | #include "llvm/CodeGen/RegisterScavenging.h" |
29 | #include "llvm/CodeGen/TargetFrameLowering.h" |
30 | #include "llvm/CodeGen/TargetInstrInfo.h" |
31 | #include "llvm/CodeGen/VirtRegMap.h" |
32 | #include "llvm/IR/CallingConv.h" |
33 | #include "llvm/IR/Constants.h" |
34 | #include "llvm/IR/Function.h" |
35 | #include "llvm/IR/Type.h" |
36 | #include "llvm/Support/CommandLine.h" |
37 | #include "llvm/Support/Debug.h" |
38 | #include "llvm/Support/ErrorHandling.h" |
39 | #include "llvm/Support/MathExtras.h" |
40 | #include "llvm/Support/raw_ostream.h" |
41 | #include "llvm/Target/TargetMachine.h" |
42 | #include "llvm/Target/TargetOptions.h" |
43 | #include <cstdlib> |
44 | |
45 | using namespace llvm; |
46 | |
47 | #define DEBUG_TYPE "reginfo" |
48 | |
49 | #define GET_REGINFO_TARGET_DESC |
50 | #include "PPCGenRegisterInfo.inc" |
51 | |
52 | STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass" ); |
53 | STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass" ); |
54 | |
55 | static cl::opt<bool> |
56 | EnableBasePointer("ppc-use-base-pointer" , cl::Hidden, cl::init(Val: true), |
57 | cl::desc("Enable use of a base pointer for complex stack frames" )); |
58 | |
59 | static cl::opt<bool> |
60 | AlwaysBasePointer("ppc-always-use-base-pointer" , cl::Hidden, cl::init(Val: false), |
61 | cl::desc("Force the use of a base pointer in every function" )); |
62 | |
63 | static cl::opt<bool> |
64 | EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills" , cl::Hidden, cl::init(Val: false), |
65 | cl::desc("Enable spills from gpr to vsr rather than stack" )); |
66 | |
67 | static cl::opt<bool> |
68 | StackPtrConst("ppc-stack-ptr-caller-preserved" , |
69 | cl::desc("Consider R1 caller preserved so stack saves of " |
70 | "caller preserved registers can be LICM candidates" ), |
71 | cl::init(Val: true), cl::Hidden); |
72 | |
73 | static cl::opt<unsigned> |
74 | MaxCRBitSpillDist("ppc-max-crbit-spill-dist" , |
75 | cl::desc("Maximum search distance for definition of CR bit " |
76 | "spill on ppc" ), |
77 | cl::Hidden, cl::init(Val: 100)); |
78 | |
79 | // Copies/moves of physical accumulators are expensive operations |
80 | // that should be avoided whenever possible. MMA instructions are |
81 | // meant to be used in performance-sensitive computational kernels. |
82 | // This option is provided, at least for the time being, to give the |
83 | // user a tool to detect this expensive operation and either rework |
84 | // their code or report a compiler bug if that turns out to be the |
85 | // cause. |
86 | #ifndef NDEBUG |
87 | static cl::opt<bool> |
88 | ReportAccMoves("ppc-report-acc-moves" , |
89 | cl::desc("Emit information about accumulator register spills " |
90 | "and copies" ), |
91 | cl::Hidden, cl::init(Val: false)); |
92 | #endif |
93 | |
94 | extern cl::opt<bool> DisableAutoPairedVecSt; |
95 | |
96 | static unsigned offsetMinAlignForOpcode(unsigned OpC); |
97 | |
98 | PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) |
99 | : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, |
100 | TM.isPPC64() ? 0 : 1, |
101 | TM.isPPC64() ? 0 : 1), |
102 | TM(TM) { |
103 | ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; |
104 | ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; |
105 | ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; |
106 | ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; |
107 | ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; |
108 | ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; |
109 | ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; |
110 | ImmToIdxMap[PPC::ADDI] = PPC::ADD4; |
111 | ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; |
112 | |
113 | // 64-bit |
114 | ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; |
115 | ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; |
116 | ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; |
117 | ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; |
118 | ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; |
119 | ImmToIdxMap[PPC::LQ] = PPC::LQX_PSEUDO; |
120 | ImmToIdxMap[PPC::STQ] = PPC::STQX_PSEUDO; |
121 | |
122 | // VSX |
123 | ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX; |
124 | ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX; |
125 | ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX; |
126 | ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX; |
127 | ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX; |
128 | ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX; |
129 | ImmToIdxMap[PPC::LXV] = PPC::LXVX; |
130 | ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; |
131 | ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX; |
132 | ImmToIdxMap[PPC::STXV] = PPC::STXVX; |
133 | ImmToIdxMap[PPC::STXSD] = PPC::STXSDX; |
134 | ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX; |
135 | |
136 | // SPE |
137 | ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX; |
138 | ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX; |
139 | ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX; |
140 | ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX; |
141 | |
142 | // Power10 |
143 | ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8; |
144 | ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8; |
145 | ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8; |
146 | ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8; |
147 | ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX; |
148 | ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX; |
149 | |
150 | ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8; |
151 | ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8; |
152 | ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8; |
153 | |
154 | ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX; |
155 | ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX; |
156 | ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX; |
157 | ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX; |
158 | ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX; |
159 | |
160 | ImmToIdxMap[PPC::LXVP] = PPC::LXVPX; |
161 | ImmToIdxMap[PPC::STXVP] = PPC::STXVPX; |
162 | ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX; |
163 | ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX; |
164 | } |
165 | |
166 | /// getPointerRegClass - Return the register class to use to hold pointers. |
167 | /// This is used for addressing modes. |
168 | const TargetRegisterClass * |
169 | PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) |
170 | const { |
171 | // Note that PPCInstrInfo::foldImmediate also directly uses this Kind value |
172 | // when it checks for ZERO folding. |
173 | if (Kind == 1) { |
174 | if (TM.isPPC64()) |
175 | return &PPC::G8RC_NOX0RegClass; |
176 | return &PPC::GPRC_NOR0RegClass; |
177 | } |
178 | |
179 | if (TM.isPPC64()) |
180 | return &PPC::G8RCRegClass; |
181 | return &PPC::GPRCRegClass; |
182 | } |
183 | |
184 | const MCPhysReg* |
185 | PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
186 | const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); |
187 | if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) { |
188 | if (!TM.isPPC64() && Subtarget.isAIXABI()) |
189 | report_fatal_error(reason: "AnyReg unimplemented on 32-bit AIX." ); |
190 | if (Subtarget.hasVSX()) { |
191 | if (Subtarget.pairedVectorMemops()) |
192 | return CSR_64_AllRegs_VSRP_SaveList; |
193 | if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) |
194 | return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList; |
195 | return CSR_64_AllRegs_VSX_SaveList; |
196 | } |
197 | if (Subtarget.hasAltivec()) { |
198 | if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) |
199 | return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList; |
200 | return CSR_64_AllRegs_Altivec_SaveList; |
201 | } |
202 | return CSR_64_AllRegs_SaveList; |
203 | } |
204 | |
205 | // On PPC64, we might need to save r2 (but only if it is not reserved). |
206 | // We do not need to treat R2 as callee-saved when using PC-Relative calls |
207 | // because any direct uses of R2 will cause it to be reserved. If the function |
208 | // is a leaf or the only uses of R2 are implicit uses for calls, the calls |
209 | // will use the @notoc relocation which will cause this function to set the |
210 | // st_other bit to 1, thereby communicating to its caller that it arbitrarily |
211 | // clobbers the TOC. |
212 | bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) && |
213 | !Subtarget.isUsingPCRelativeCalls(); |
214 | |
215 | // Cold calling convention CSRs. |
216 | if (MF->getFunction().getCallingConv() == CallingConv::Cold) { |
217 | if (Subtarget.isAIXABI()) |
218 | report_fatal_error(reason: "Cold calling unimplemented on AIX." ); |
219 | if (TM.isPPC64()) { |
220 | if (Subtarget.pairedVectorMemops()) |
221 | return SaveR2 ? CSR_SVR64_ColdCC_R2_VSRP_SaveList |
222 | : CSR_SVR64_ColdCC_VSRP_SaveList; |
223 | if (Subtarget.hasAltivec()) |
224 | return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList |
225 | : CSR_SVR64_ColdCC_Altivec_SaveList; |
226 | return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList |
227 | : CSR_SVR64_ColdCC_SaveList; |
228 | } |
229 | // 32-bit targets. |
230 | if (Subtarget.pairedVectorMemops()) |
231 | return CSR_SVR32_ColdCC_VSRP_SaveList; |
232 | else if (Subtarget.hasAltivec()) |
233 | return CSR_SVR32_ColdCC_Altivec_SaveList; |
234 | else if (Subtarget.hasSPE()) |
235 | return CSR_SVR32_ColdCC_SPE_SaveList; |
236 | return CSR_SVR32_ColdCC_SaveList; |
237 | } |
238 | // Standard calling convention CSRs. |
239 | if (TM.isPPC64()) { |
240 | if (Subtarget.pairedVectorMemops()) { |
241 | if (Subtarget.isAIXABI()) { |
242 | if (!TM.getAIXExtendedAltivecABI()) |
243 | return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList; |
244 | return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList; |
245 | } |
246 | return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList; |
247 | } |
248 | if (Subtarget.hasAltivec() && |
249 | (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) { |
250 | return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList |
251 | : CSR_PPC64_Altivec_SaveList; |
252 | } |
253 | return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList; |
254 | } |
255 | // 32-bit targets. |
256 | if (Subtarget.isAIXABI()) { |
257 | if (Subtarget.pairedVectorMemops()) |
258 | return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList |
259 | : CSR_AIX32_SaveList; |
260 | if (Subtarget.hasAltivec()) |
261 | return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList |
262 | : CSR_AIX32_SaveList; |
263 | return CSR_AIX32_SaveList; |
264 | } |
265 | if (Subtarget.pairedVectorMemops()) |
266 | return CSR_SVR432_VSRP_SaveList; |
267 | if (Subtarget.hasAltivec()) |
268 | return CSR_SVR432_Altivec_SaveList; |
269 | else if (Subtarget.hasSPE()) { |
270 | if (TM.isPositionIndependent() && !TM.isPPC64()) |
271 | return CSR_SVR432_SPE_NO_S30_31_SaveList; |
272 | return CSR_SVR432_SPE_SaveList; |
273 | } |
274 | return CSR_SVR432_SaveList; |
275 | } |
276 | |
277 | const uint32_t * |
278 | PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, |
279 | CallingConv::ID CC) const { |
280 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
281 | if (CC == CallingConv::AnyReg) { |
282 | if (Subtarget.hasVSX()) { |
283 | if (Subtarget.pairedVectorMemops()) |
284 | return CSR_64_AllRegs_VSRP_RegMask; |
285 | if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) |
286 | return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask; |
287 | return CSR_64_AllRegs_VSX_RegMask; |
288 | } |
289 | if (Subtarget.hasAltivec()) { |
290 | if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) |
291 | return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask; |
292 | return CSR_64_AllRegs_Altivec_RegMask; |
293 | } |
294 | return CSR_64_AllRegs_RegMask; |
295 | } |
296 | |
297 | if (Subtarget.isAIXABI()) { |
298 | if (Subtarget.pairedVectorMemops()) { |
299 | if (!TM.getAIXExtendedAltivecABI()) |
300 | return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask; |
301 | return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask; |
302 | } |
303 | return TM.isPPC64() |
304 | ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI()) |
305 | ? CSR_PPC64_Altivec_RegMask |
306 | : CSR_PPC64_RegMask) |
307 | : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI()) |
308 | ? CSR_AIX32_Altivec_RegMask |
309 | : CSR_AIX32_RegMask); |
310 | } |
311 | |
312 | if (CC == CallingConv::Cold) { |
313 | if (TM.isPPC64()) |
314 | return Subtarget.pairedVectorMemops() |
315 | ? CSR_SVR64_ColdCC_VSRP_RegMask |
316 | : (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask |
317 | : CSR_SVR64_ColdCC_RegMask); |
318 | else |
319 | return Subtarget.pairedVectorMemops() |
320 | ? CSR_SVR32_ColdCC_VSRP_RegMask |
321 | : (Subtarget.hasAltivec() |
322 | ? CSR_SVR32_ColdCC_Altivec_RegMask |
323 | : (Subtarget.hasSPE() ? CSR_SVR32_ColdCC_SPE_RegMask |
324 | : CSR_SVR32_ColdCC_RegMask)); |
325 | } |
326 | |
327 | if (TM.isPPC64()) |
328 | return Subtarget.pairedVectorMemops() |
329 | ? CSR_SVR464_VSRP_RegMask |
330 | : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask |
331 | : CSR_PPC64_RegMask); |
332 | else |
333 | return Subtarget.pairedVectorMemops() |
334 | ? CSR_SVR432_VSRP_RegMask |
335 | : (Subtarget.hasAltivec() |
336 | ? CSR_SVR432_Altivec_RegMask |
337 | : (Subtarget.hasSPE() |
338 | ? (TM.isPositionIndependent() |
339 | ? CSR_SVR432_SPE_NO_S30_31_RegMask |
340 | : CSR_SVR432_SPE_RegMask) |
341 | : CSR_SVR432_RegMask)); |
342 | } |
343 | |
344 | const uint32_t* |
345 | PPCRegisterInfo::getNoPreservedMask() const { |
346 | return CSR_NoRegs_RegMask; |
347 | } |
348 | |
349 | void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { |
350 | for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) |
351 | Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); |
352 | } |
353 | |
354 | BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
355 | BitVector Reserved(getNumRegs()); |
356 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
357 | const PPCFrameLowering *TFI = getFrameLowering(MF); |
358 | |
359 | // The ZERO register is not really a register, but the representation of r0 |
360 | // when used in instructions that treat r0 as the constant 0. |
361 | markSuperRegs(Reserved, PPC::ZERO); |
362 | |
363 | // The FP register is also not really a register, but is the representation |
364 | // of the frame pointer register used by ISD::FRAMEADDR. |
365 | markSuperRegs(Reserved, PPC::FP); |
366 | |
367 | // The BP register is also not really a register, but is the representation |
368 | // of the base pointer register used by setjmp. |
369 | markSuperRegs(Reserved, PPC::BP); |
370 | |
371 | // The counter registers must be reserved so that counter-based loops can |
372 | // be correctly formed (and the mtctr instructions are not DCE'd). |
373 | markSuperRegs(Reserved, PPC::CTR); |
374 | markSuperRegs(Reserved, PPC::CTR8); |
375 | |
376 | markSuperRegs(Reserved, PPC::R1); |
377 | markSuperRegs(Reserved, PPC::LR); |
378 | markSuperRegs(Reserved, PPC::LR8); |
379 | markSuperRegs(Reserved, PPC::RM); |
380 | |
381 | markSuperRegs(Reserved, PPC::VRSAVE); |
382 | |
383 | // The SVR4 ABI reserves r2 and r13 |
384 | if (Subtarget.isSVR4ABI()) { |
385 | // We only reserve r2 if we need to use the TOC pointer. If we have no |
386 | // explicit uses of the TOC pointer (meaning we're a leaf function with |
387 | // no constant-pool loads, etc.) and we have no potential uses inside an |
388 | // inline asm block, then we can treat r2 has an ordinary callee-saved |
389 | // register. |
390 | const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); |
391 | if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) |
392 | markSuperRegs(Reserved, PPC::R2); // System-reserved register |
393 | markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register |
394 | } |
395 | |
396 | // Always reserve r2 on AIX for now. |
397 | // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions. |
398 | if (Subtarget.isAIXABI()) |
399 | markSuperRegs(Reserved, PPC::R2); // System-reserved register |
400 | |
401 | // On PPC64, r13 is the thread pointer. Never allocate this register. |
402 | if (TM.isPPC64()) |
403 | markSuperRegs(Reserved, PPC::R13); |
404 | |
405 | if (TFI->needsFP(MF)) |
406 | markSuperRegs(Reserved, PPC::R31); |
407 | |
408 | bool IsPositionIndependent = TM.isPositionIndependent(); |
409 | if (hasBasePointer(MF)) { |
410 | if (Subtarget.is32BitELFABI() && IsPositionIndependent) |
411 | markSuperRegs(Reserved, PPC::R29); |
412 | else |
413 | markSuperRegs(Reserved, PPC::R30); |
414 | } |
415 | |
416 | if (Subtarget.is32BitELFABI() && IsPositionIndependent) |
417 | markSuperRegs(Reserved, PPC::R30); |
418 | |
419 | // Reserve Altivec registers when Altivec is unavailable. |
420 | if (!Subtarget.hasAltivec()) |
421 | for (MCRegister Reg : PPC::VRRCRegClass) |
422 | markSuperRegs(Reserved, Reg); |
423 | |
424 | if (Subtarget.isAIXABI() && Subtarget.hasAltivec() && |
425 | !TM.getAIXExtendedAltivecABI()) { |
426 | // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved |
427 | // and cannot be used. |
428 | for (auto Reg : CSR_Altivec_SaveList) { |
429 | if (Reg == 0) |
430 | break; |
431 | markSuperRegs(Reserved, Reg); |
432 | for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) { |
433 | Reserved.set(*AS); |
434 | } |
435 | } |
436 | } |
437 | |
438 | assert(checkAllSuperRegsMarked(Reserved)); |
439 | return Reserved; |
440 | } |
441 | |
442 | bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF, |
443 | MCRegister PhysReg) const { |
444 | // We cannot use getReservedRegs() to find the registers that are not asm |
445 | // clobberable because there are some reserved registers which can be |
446 | // clobbered by inline asm. For example, when LR is clobbered, the register is |
447 | // saved and restored. We will hardcode the registers that are not asm |
448 | // cloberable in this function. |
449 | |
450 | // The stack pointer (R1/X1) is not clobberable by inline asm |
451 | return PhysReg != PPC::R1 && PhysReg != PPC::X1; |
452 | } |
453 | |
454 | bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const { |
455 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
456 | const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo(); |
457 | const MachineFrameInfo &MFI = MF.getFrameInfo(); |
458 | const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo(); |
459 | |
460 | LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName() |
461 | << ".\n" ); |
462 | // If the callee saved info is invalid we have to default to true for safety. |
463 | if (!MFI.isCalleeSavedInfoValid()) { |
464 | LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n" ); |
465 | return true; |
466 | } |
467 | |
468 | // We will require the use of X-Forms because the frame is larger than what |
469 | // can be represented in signed 16 bits that fit in the immediate of a D-Form. |
470 | // If we need an X-Form then we need a register to store the address offset. |
471 | unsigned FrameSize = MFI.getStackSize(); |
472 | // Signed 16 bits means that the FrameSize cannot be more than 15 bits. |
473 | if (FrameSize & ~0x7FFF) { |
474 | LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n" ); |
475 | return true; |
476 | } |
477 | |
478 | // The callee saved info is valid so it can be traversed. |
479 | // Checking for registers that need saving that do not have load or store |
480 | // forms where the address offset is an immediate. |
481 | for (const CalleeSavedInfo &CSI : Info) { |
482 | // If the spill is to a register no scavenging is required. |
483 | if (CSI.isSpilledToReg()) |
484 | continue; |
485 | |
486 | int FrIdx = CSI.getFrameIdx(); |
487 | Register Reg = CSI.getReg(); |
488 | |
489 | const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg); |
490 | unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC); |
491 | if (!MFI.isFixedObjectIndex(ObjectIdx: FrIdx)) { |
492 | // This is not a fixed object. If it requires alignment then we may still |
493 | // need to use the XForm. |
494 | if (offsetMinAlignForOpcode(OpC: Opcode) > 1) { |
495 | LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode) |
496 | << " for register " << printReg(Reg, this) << ".\n" ); |
497 | LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires " |
498 | << "alignment.\n" ); |
499 | return true; |
500 | } |
501 | } |
502 | |
503 | // This is eiher: |
504 | // 1) A fixed frame index object which we know are aligned so |
505 | // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't |
506 | // need to consider the alignment here. |
507 | // 2) A not fixed object but in that case we now know that the min required |
508 | // alignment is no more than 1 based on the previous check. |
509 | if (InstrInfo->isXFormMemOp(Opcode)) { |
510 | LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode) |
511 | << " for register " << printReg(Reg, this) << ".\n" ); |
512 | LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n" ); |
513 | return true; |
514 | } |
515 | |
516 | // This is a spill/restore of a quadword. |
517 | if ((Opcode == PPC::RESTORE_QUADWORD) || (Opcode == PPC::SPILL_QUADWORD)) { |
518 | LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode) |
519 | << " for register " << printReg(Reg, this) << ".\n" ); |
520 | LLVM_DEBUG(dbgs() << "TRUE - Memory operand is a quadword.\n" ); |
521 | return true; |
522 | } |
523 | } |
524 | LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n" ); |
525 | return false; |
526 | } |
527 | |
528 | bool PPCRegisterInfo::requiresVirtualBaseRegisters( |
529 | const MachineFunction &MF) const { |
530 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
531 | // Do not use virtual base registers when ROP protection is turned on. |
532 | // Virtual base registers break the layout of the local variable space and may |
533 | // push the ROP Hash location past the 512 byte range of the ROP store |
534 | // instruction. |
535 | return !Subtarget.hasROPProtect(); |
536 | } |
537 | |
538 | bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg, |
539 | const MachineFunction &MF) const { |
540 | assert(Register::isPhysicalRegister(PhysReg)); |
541 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
542 | const MachineFrameInfo &MFI = MF.getFrameInfo(); |
543 | |
544 | if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI()) |
545 | return false; |
546 | if (PhysReg == Subtarget.getTOCPointerRegister()) |
547 | // X2/R2 is guaranteed to be preserved within a function if it is reserved. |
548 | // The reason it's reserved is that it's the TOC pointer (and the function |
549 | // uses the TOC). In functions where it isn't reserved (i.e. leaf functions |
550 | // with no TOC access), we can't claim that it is preserved. |
551 | return (getReservedRegs(MF).test(PhysReg)); |
552 | if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() && |
553 | !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment()) |
554 | // The value of the stack pointer does not change within a function after |
555 | // the prologue and before the epilogue if there are no dynamic allocations |
556 | // and no inline asm which clobbers X1/R1. |
557 | return true; |
558 | return false; |
559 | } |
560 | |
561 | bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg, |
562 | ArrayRef<MCPhysReg> Order, |
563 | SmallVectorImpl<MCPhysReg> &Hints, |
564 | const MachineFunction &MF, |
565 | const VirtRegMap *VRM, |
566 | const LiveRegMatrix *Matrix) const { |
567 | const MachineRegisterInfo *MRI = &MF.getRegInfo(); |
568 | |
569 | // Call the base implementation first to set any hints based on the usual |
570 | // heuristics and decide what the return value should be. We want to return |
571 | // the same value returned by the base implementation. If the base |
572 | // implementation decides to return true and force the allocation then we |
573 | // will leave it as such. On the other hand if the base implementation |
574 | // decides to return false the following code will not force the allocation |
575 | // as we are just looking to provide a hint. |
576 | bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints( |
577 | VirtReg, Order, Hints, MF, VRM, Matrix); |
578 | |
579 | // Don't use the allocation hints for ISAFuture. |
580 | // The WACC registers used in ISAFuture are unlike the ACC registers on |
581 | // Power 10 and so this logic to register allocation hints does not apply. |
582 | if (MF.getSubtarget<PPCSubtarget>().isISAFuture()) |
583 | return BaseImplRetVal; |
584 | |
585 | // We are interested in instructions that copy values to ACC/UACC. |
586 | // The copy into UACC will be simply a COPY to a subreg so we |
587 | // want to allocate the corresponding physical subreg for the source. |
588 | // The copy into ACC will be a BUILD_UACC so we want to allocate |
589 | // the same number UACC for the source. |
590 | const TargetRegisterClass *RegClass = MRI->getRegClass(Reg: VirtReg); |
591 | for (MachineInstr &Use : MRI->reg_nodbg_instructions(Reg: VirtReg)) { |
592 | const MachineOperand *ResultOp = nullptr; |
593 | Register ResultReg; |
594 | switch (Use.getOpcode()) { |
595 | case TargetOpcode::COPY: { |
596 | ResultOp = &Use.getOperand(i: 0); |
597 | ResultReg = ResultOp->getReg(); |
598 | if (ResultReg.isVirtual() && |
599 | MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && |
600 | VRM->hasPhys(ResultReg)) { |
601 | Register UACCPhys = VRM->getPhys(virtReg: ResultReg); |
602 | Register HintReg; |
603 | if (RegClass->contains(PPC::VSRp0)) { |
604 | HintReg = getSubReg(UACCPhys, ResultOp->getSubReg()); |
605 | // Ensure that the hint is a VSRp register. |
606 | if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31) |
607 | Hints.push_back(Elt: HintReg); |
608 | } else if (RegClass->contains(PPC::ACC0)) { |
609 | HintReg = PPC::ACC0 + (UACCPhys - PPC::UACC0); |
610 | if (HintReg >= PPC::ACC0 && HintReg <= PPC::ACC7) |
611 | Hints.push_back(Elt: HintReg); |
612 | } |
613 | } |
614 | break; |
615 | } |
616 | case PPC::BUILD_UACC: { |
617 | ResultOp = &Use.getOperand(i: 0); |
618 | ResultReg = ResultOp->getReg(); |
619 | if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && |
620 | VRM->hasPhys(ResultReg)) { |
621 | Register ACCPhys = VRM->getPhys(virtReg: ResultReg); |
622 | assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) && |
623 | "Expecting an ACC register for BUILD_UACC." ); |
624 | Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0); |
625 | Hints.push_back(Elt: HintReg); |
626 | } |
627 | break; |
628 | } |
629 | } |
630 | } |
631 | return BaseImplRetVal; |
632 | } |
633 | |
634 | unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, |
635 | MachineFunction &MF) const { |
636 | const PPCFrameLowering *TFI = getFrameLowering(MF); |
637 | const unsigned DefaultSafety = 1; |
638 | |
639 | switch (RC->getID()) { |
640 | default: |
641 | return 0; |
642 | case PPC::G8RC_NOX0RegClassID: |
643 | case PPC::GPRC_NOR0RegClassID: |
644 | case PPC::SPERCRegClassID: |
645 | case PPC::G8RCRegClassID: |
646 | case PPC::GPRCRegClassID: { |
647 | unsigned FP = TFI->hasFP(MF) ? 1 : 0; |
648 | return 32 - FP - DefaultSafety; |
649 | } |
650 | case PPC::F4RCRegClassID: |
651 | case PPC::F8RCRegClassID: |
652 | case PPC::VSLRCRegClassID: |
653 | return 32 - DefaultSafety; |
654 | case PPC::VFRCRegClassID: |
655 | case PPC::VRRCRegClassID: { |
656 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
657 | // Vector registers VR20-VR31 are reserved and cannot be used in the default |
658 | // Altivec ABI on AIX. |
659 | if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI()) |
660 | return 20 - DefaultSafety; |
661 | } |
662 | return 32 - DefaultSafety; |
663 | case PPC::VSFRCRegClassID: |
664 | case PPC::VSSRCRegClassID: |
665 | case PPC::VSRCRegClassID: { |
666 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
667 | if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI()) |
668 | // Vector registers VR20-VR31 are reserved and cannot be used in the |
669 | // default Altivec ABI on AIX. |
670 | return 52 - DefaultSafety; |
671 | } |
672 | return 64 - DefaultSafety; |
673 | case PPC::CRRCRegClassID: |
674 | return 8 - DefaultSafety; |
675 | } |
676 | } |
677 | |
678 | const TargetRegisterClass * |
679 | PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, |
680 | const MachineFunction &MF) const { |
681 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
682 | const auto *DefaultSuperclass = |
683 | TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); |
684 | if (Subtarget.hasVSX()) { |
685 | // With VSX, we can inflate various sub-register classes to the full VSX |
686 | // register set. |
687 | |
688 | // For Power9 we allow the user to enable GPR to vector spills. |
689 | // FIXME: Currently limited to spilling GP8RC. A follow on patch will add |
690 | // support to spill GPRC. |
691 | if (TM.isELFv2ABI() || Subtarget.isAIXABI()) { |
692 | if (Subtarget.hasP9Vector() && EnableGPRToVecSpills && |
693 | RC == &PPC::G8RCRegClass) { |
694 | InflateGP8RC++; |
695 | return &PPC::SPILLTOVSRRCRegClass; |
696 | } |
697 | if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills) |
698 | InflateGPRC++; |
699 | } |
700 | |
701 | for (const auto *I = RC->getSuperClasses(); *I; ++I) { |
702 | if (getRegSizeInBits(**I) != getRegSizeInBits(*RC)) |
703 | continue; |
704 | |
705 | switch ((*I)->getID()) { |
706 | case PPC::VSSRCRegClassID: |
707 | return Subtarget.hasP8Vector() ? *I : DefaultSuperclass; |
708 | case PPC::VSFRCRegClassID: |
709 | case PPC::VSRCRegClassID: |
710 | return *I; |
711 | case PPC::VSRpRCRegClassID: |
712 | return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass; |
713 | case PPC::ACCRCRegClassID: |
714 | case PPC::UACCRCRegClassID: |
715 | return Subtarget.hasMMA() ? *I : DefaultSuperclass; |
716 | } |
717 | } |
718 | } |
719 | |
720 | return DefaultSuperclass; |
721 | } |
722 | |
723 | //===----------------------------------------------------------------------===// |
724 | // Stack Frame Processing methods |
725 | //===----------------------------------------------------------------------===// |
726 | |
727 | /// lowerDynamicAlloc - Generate the code for allocating an object in the |
728 | /// current frame. The sequence of code will be in the general form |
729 | /// |
730 | /// addi R0, SP, \#frameSize ; get the address of the previous frame |
731 | /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size |
732 | /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation |
733 | /// |
734 | void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { |
735 | // Get the instruction. |
736 | MachineInstr &MI = *II; |
737 | // Get the instruction's basic block. |
738 | MachineBasicBlock &MBB = *MI.getParent(); |
739 | // Get the basic block's function. |
740 | MachineFunction &MF = *MBB.getParent(); |
741 | // Get the frame info. |
742 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
743 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
744 | // Get the instruction info. |
745 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
746 | // Determine whether 64-bit pointers are used. |
747 | bool LP64 = TM.isPPC64(); |
748 | DebugLoc dl = MI.getDebugLoc(); |
749 | |
750 | // Get the maximum call stack size. |
751 | unsigned maxCallFrameSize = MFI.getMaxCallFrameSize(); |
752 | Align MaxAlign = MFI.getMaxAlign(); |
753 | assert(isAligned(MaxAlign, maxCallFrameSize) && |
754 | "Maximum call-frame size not sufficiently aligned" ); |
755 | (void)MaxAlign; |
756 | |
757 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
758 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
759 | Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
760 | bool KillNegSizeReg = MI.getOperand(i: 1).isKill(); |
761 | Register NegSizeReg = MI.getOperand(i: 1).getReg(); |
762 | |
763 | prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, Reg); |
764 | // Grow the stack and update the stack pointer link, then determine the |
765 | // address of new allocated space. |
766 | if (LP64) { |
767 | BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) |
768 | .addReg(Reg, RegState::Kill) |
769 | .addReg(PPC::X1) |
770 | .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); |
771 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) |
772 | .addReg(PPC::X1) |
773 | .addImm(maxCallFrameSize); |
774 | } else { |
775 | BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) |
776 | .addReg(Reg, RegState::Kill) |
777 | .addReg(PPC::R1) |
778 | .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); |
779 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) |
780 | .addReg(PPC::R1) |
781 | .addImm(maxCallFrameSize); |
782 | } |
783 | |
784 | // Discard the DYNALLOC instruction. |
785 | MBB.erase(I: II); |
786 | } |
787 | |
788 | /// To accomplish dynamic stack allocation, we have to calculate exact size |
789 | /// subtracted from the stack pointer according alignment information and get |
790 | /// previous frame pointer. |
791 | void PPCRegisterInfo::prepareDynamicAlloca(MachineBasicBlock::iterator II, |
792 | Register &NegSizeReg, |
793 | bool &KillNegSizeReg, |
794 | Register &FramePointer) const { |
795 | // Get the instruction. |
796 | MachineInstr &MI = *II; |
797 | // Get the instruction's basic block. |
798 | MachineBasicBlock &MBB = *MI.getParent(); |
799 | // Get the basic block's function. |
800 | MachineFunction &MF = *MBB.getParent(); |
801 | // Get the frame info. |
802 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
803 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
804 | // Get the instruction info. |
805 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
806 | // Determine whether 64-bit pointers are used. |
807 | bool LP64 = TM.isPPC64(); |
808 | DebugLoc dl = MI.getDebugLoc(); |
809 | // Get the total frame size. |
810 | unsigned FrameSize = MFI.getStackSize(); |
811 | |
812 | // Get stack alignments. |
813 | const PPCFrameLowering *TFI = getFrameLowering(MF); |
814 | Align TargetAlign = TFI->getStackAlign(); |
815 | Align MaxAlign = MFI.getMaxAlign(); |
816 | |
817 | // Determine the previous frame's address. If FrameSize can't be |
818 | // represented as 16 bits or we need special alignment, then we load the |
819 | // previous frame's address from 0(SP). Why not do an addis of the hi? |
820 | // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. |
821 | // Constructing the constant and adding would take 3 instructions. |
822 | // Fortunately, a frame greater than 32K is rare. |
823 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
824 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
825 | |
826 | if (MaxAlign < TargetAlign && isInt<16>(x: FrameSize)) { |
827 | if (LP64) |
828 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer) |
829 | .addReg(PPC::X31) |
830 | .addImm(FrameSize); |
831 | else |
832 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) |
833 | .addReg(PPC::R31) |
834 | .addImm(FrameSize); |
835 | } else if (LP64) { |
836 | BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer) |
837 | .addImm(0) |
838 | .addReg(PPC::X1); |
839 | } else { |
840 | BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer) |
841 | .addImm(0) |
842 | .addReg(PPC::R1); |
843 | } |
844 | // Determine the actual NegSizeReg according to alignment info. |
845 | if (LP64) { |
846 | if (MaxAlign > TargetAlign) { |
847 | unsigned UnalNegSizeReg = NegSizeReg; |
848 | NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: G8RC); |
849 | |
850 | // Unfortunately, there is no andi, only andi., and we can't insert that |
851 | // here because we might clobber cr0 while it is live. |
852 | BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) |
853 | .addImm(~(MaxAlign.value() - 1)); |
854 | |
855 | unsigned NegSizeReg1 = NegSizeReg; |
856 | NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: G8RC); |
857 | BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) |
858 | .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) |
859 | .addReg(NegSizeReg1, RegState::Kill); |
860 | KillNegSizeReg = true; |
861 | } |
862 | } else { |
863 | if (MaxAlign > TargetAlign) { |
864 | unsigned UnalNegSizeReg = NegSizeReg; |
865 | NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: GPRC); |
866 | |
867 | // Unfortunately, there is no andi, only andi., and we can't insert that |
868 | // here because we might clobber cr0 while it is live. |
869 | BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) |
870 | .addImm(~(MaxAlign.value() - 1)); |
871 | |
872 | unsigned NegSizeReg1 = NegSizeReg; |
873 | NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: GPRC); |
874 | BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) |
875 | .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) |
876 | .addReg(NegSizeReg1, RegState::Kill); |
877 | KillNegSizeReg = true; |
878 | } |
879 | } |
880 | } |
881 | |
882 | void PPCRegisterInfo::lowerPrepareProbedAlloca( |
883 | MachineBasicBlock::iterator II) const { |
884 | MachineInstr &MI = *II; |
885 | // Get the instruction's basic block. |
886 | MachineBasicBlock &MBB = *MI.getParent(); |
887 | // Get the basic block's function. |
888 | MachineFunction &MF = *MBB.getParent(); |
889 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
890 | // Get the instruction info. |
891 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
892 | // Determine whether 64-bit pointers are used. |
893 | bool LP64 = TM.isPPC64(); |
894 | DebugLoc dl = MI.getDebugLoc(); |
895 | Register FramePointer = MI.getOperand(i: 0).getReg(); |
896 | const Register ActualNegSizeReg = MI.getOperand(i: 1).getReg(); |
897 | bool KillNegSizeReg = MI.getOperand(i: 2).isKill(); |
898 | Register NegSizeReg = MI.getOperand(i: 2).getReg(); |
899 | const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR); |
900 | // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg. |
901 | if (FramePointer == NegSizeReg) { |
902 | assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, " |
903 | "NegSizeReg should be killed" ); |
904 | // FramePointer is clobbered earlier than the use of NegSizeReg in |
905 | // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid |
906 | // misuse. |
907 | BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: CopyInst, DestReg: ActualNegSizeReg) |
908 | .addReg(RegNo: NegSizeReg) |
909 | .addReg(RegNo: NegSizeReg); |
910 | NegSizeReg = ActualNegSizeReg; |
911 | KillNegSizeReg = false; |
912 | } |
913 | prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer); |
914 | // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign > |
915 | // TargetAlign. |
916 | if (NegSizeReg != ActualNegSizeReg) |
917 | BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: CopyInst, DestReg: ActualNegSizeReg) |
918 | .addReg(RegNo: NegSizeReg) |
919 | .addReg(RegNo: NegSizeReg); |
920 | MBB.erase(I: II); |
921 | } |
922 | |
923 | void PPCRegisterInfo::lowerDynamicAreaOffset( |
924 | MachineBasicBlock::iterator II) const { |
925 | // Get the instruction. |
926 | MachineInstr &MI = *II; |
927 | // Get the instruction's basic block. |
928 | MachineBasicBlock &MBB = *MI.getParent(); |
929 | // Get the basic block's function. |
930 | MachineFunction &MF = *MBB.getParent(); |
931 | // Get the frame info. |
932 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
933 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
934 | // Get the instruction info. |
935 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
936 | |
937 | unsigned maxCallFrameSize = MFI.getMaxCallFrameSize(); |
938 | bool is64Bit = TM.isPPC64(); |
939 | DebugLoc dl = MI.getDebugLoc(); |
940 | BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), |
941 | MI.getOperand(0).getReg()) |
942 | .addImm(maxCallFrameSize); |
943 | MBB.erase(I: II); |
944 | } |
945 | |
946 | /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of |
947 | /// reserving a whole register (R0), we scrounge for one here. This generates |
948 | /// code like this: |
949 | /// |
950 | /// mfcr rA ; Move the conditional register into GPR rA. |
951 | /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. |
952 | /// stw rA, FI ; Store rA to the frame. |
953 | /// |
954 | void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, |
955 | unsigned FrameIndex) const { |
956 | // Get the instruction. |
957 | MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> |
958 | // Get the instruction's basic block. |
959 | MachineBasicBlock &MBB = *MI.getParent(); |
960 | MachineFunction &MF = *MBB.getParent(); |
961 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
962 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
963 | DebugLoc dl = MI.getDebugLoc(); |
964 | |
965 | bool LP64 = TM.isPPC64(); |
966 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
967 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
968 | |
969 | Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
970 | Register SrcReg = MI.getOperand(i: 0).getReg(); |
971 | |
972 | // We need to store the CR in the low 4-bits of the saved value. First, issue |
973 | // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. |
974 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) |
975 | .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); |
976 | |
977 | // If the saved register wasn't CR0, shift the bits left so that they are in |
978 | // CR0's slot. |
979 | if (SrcReg != PPC::CR0) { |
980 | Register Reg1 = Reg; |
981 | Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
982 | |
983 | // rlwinm rA, rA, ShiftBits, 0, 31. |
984 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) |
985 | .addReg(Reg1, RegState::Kill) |
986 | .addImm(getEncodingValue(SrcReg) * 4) |
987 | .addImm(0) |
988 | .addImm(31); |
989 | } |
990 | |
991 | addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) |
992 | .addReg(Reg, RegState::Kill), |
993 | FrameIndex); |
994 | |
995 | // Discard the pseudo instruction. |
996 | MBB.erase(I: II); |
997 | } |
998 | |
999 | void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, |
1000 | unsigned FrameIndex) const { |
1001 | // Get the instruction. |
1002 | MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> |
1003 | // Get the instruction's basic block. |
1004 | MachineBasicBlock &MBB = *MI.getParent(); |
1005 | MachineFunction &MF = *MBB.getParent(); |
1006 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1007 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1008 | DebugLoc dl = MI.getDebugLoc(); |
1009 | |
1010 | bool LP64 = TM.isPPC64(); |
1011 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
1012 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
1013 | |
1014 | Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
1015 | Register DestReg = MI.getOperand(i: 0).getReg(); |
1016 | assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && |
1017 | "RESTORE_CR does not define its destination" ); |
1018 | |
1019 | addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), |
1020 | Reg), FrameIndex); |
1021 | |
1022 | // If the reloaded register isn't CR0, shift the bits right so that they are |
1023 | // in the right CR's slot. |
1024 | if (DestReg != PPC::CR0) { |
1025 | Register Reg1 = Reg; |
1026 | Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
1027 | |
1028 | unsigned ShiftBits = getEncodingValue(DestReg)*4; |
1029 | // rlwinm r11, r11, 32-ShiftBits, 0, 31. |
1030 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) |
1031 | .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) |
1032 | .addImm(31); |
1033 | } |
1034 | |
1035 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) |
1036 | .addReg(Reg, RegState::Kill); |
1037 | |
1038 | // Discard the pseudo instruction. |
1039 | MBB.erase(I: II); |
1040 | } |
1041 | |
1042 | void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, |
1043 | unsigned FrameIndex) const { |
1044 | // Get the instruction. |
1045 | MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> |
1046 | // Get the instruction's basic block. |
1047 | MachineBasicBlock &MBB = *MI.getParent(); |
1048 | MachineFunction &MF = *MBB.getParent(); |
1049 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1050 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1051 | const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo(); |
1052 | DebugLoc dl = MI.getDebugLoc(); |
1053 | |
1054 | bool LP64 = TM.isPPC64(); |
1055 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
1056 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
1057 | |
1058 | Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
1059 | Register SrcReg = MI.getOperand(i: 0).getReg(); |
1060 | |
1061 | // Search up the BB to find the definition of the CR bit. |
1062 | MachineBasicBlock::reverse_iterator Ins = MI; |
1063 | MachineBasicBlock::reverse_iterator Rend = MBB.rend(); |
1064 | ++Ins; |
1065 | unsigned CRBitSpillDistance = 0; |
1066 | bool SeenUse = false; |
1067 | for (; Ins != Rend; ++Ins) { |
1068 | // Definition found. |
1069 | if (Ins->modifiesRegister(Reg: SrcReg, TRI)) |
1070 | break; |
1071 | // Use found. |
1072 | if (Ins->readsRegister(Reg: SrcReg, TRI)) |
1073 | SeenUse = true; |
1074 | // Unable to find CR bit definition within maximum search distance. |
1075 | if (CRBitSpillDistance == MaxCRBitSpillDist) { |
1076 | Ins = MI; |
1077 | break; |
1078 | } |
1079 | // Skip debug instructions when counting CR bit spill distance. |
1080 | if (!Ins->isDebugInstr()) |
1081 | CRBitSpillDistance++; |
1082 | } |
1083 | |
1084 | // Unable to find the definition of the CR bit in the MBB. |
1085 | if (Ins == MBB.rend()) |
1086 | Ins = MI; |
1087 | |
1088 | bool SpillsKnownBit = false; |
1089 | // There is no need to extract the CR bit if its value is already known. |
1090 | switch (Ins->getOpcode()) { |
1091 | case PPC::CRUNSET: |
1092 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg) |
1093 | .addImm(0); |
1094 | SpillsKnownBit = true; |
1095 | break; |
1096 | case PPC::CRSET: |
1097 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg) |
1098 | .addImm(-32768); |
1099 | SpillsKnownBit = true; |
1100 | break; |
1101 | default: |
1102 | // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all |
1103 | // bits (specifically, it produces a -1 if the CR bit is set). Ultimately, |
1104 | // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit |
1105 | // register), and SETNBC will set this. |
1106 | if (Subtarget.isISA3_1()) { |
1107 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg) |
1108 | .addReg(SrcReg, RegState::Undef); |
1109 | break; |
1110 | } |
1111 | |
1112 | // On Power9, we can use SETB to extract the LT bit. This only works for |
1113 | // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value |
1114 | // of the bit we care about (32-bit sign bit) will be set to the value of |
1115 | // the LT bit (regardless of the other bits in the CR field). |
1116 | if (Subtarget.isISA3_0()) { |
1117 | if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT || |
1118 | SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT || |
1119 | SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT || |
1120 | SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) { |
1121 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg) |
1122 | .addReg(getCRFromCRBit(SrcReg), RegState::Undef); |
1123 | break; |
1124 | } |
1125 | } |
1126 | |
1127 | // We need to move the CR field that contains the CR bit we are spilling. |
1128 | // The super register may not be explicitly defined (i.e. it can be defined |
1129 | // by a CR-logical that only defines the subreg) so we state that the CR |
1130 | // field is undef. Also, in order to preserve the kill flag on the CR bit, |
1131 | // we add it as an implicit use. |
1132 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) |
1133 | .addReg(getCRFromCRBit(SrcReg), RegState::Undef) |
1134 | .addReg(SrcReg, |
1135 | RegState::Implicit | getKillRegState(MI.getOperand(0).isKill())); |
1136 | |
1137 | // If the saved register wasn't CR0LT, shift the bits left so that the bit |
1138 | // to store is the first one. Mask all but that bit. |
1139 | Register Reg1 = Reg; |
1140 | Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
1141 | |
1142 | // rlwinm rA, rA, ShiftBits, 0, 0. |
1143 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) |
1144 | .addReg(Reg1, RegState::Kill) |
1145 | .addImm(getEncodingValue(SrcReg)) |
1146 | .addImm(0).addImm(0); |
1147 | } |
1148 | addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) |
1149 | .addReg(Reg, RegState::Kill), |
1150 | FrameIndex); |
1151 | |
1152 | bool KillsCRBit = MI.killsRegister(Reg: SrcReg, TRI); |
1153 | // Discard the pseudo instruction. |
1154 | MBB.erase(I: II); |
1155 | if (SpillsKnownBit && KillsCRBit && !SeenUse) { |
1156 | Ins->setDesc(TII.get(PPC::UNENCODED_NOP)); |
1157 | Ins->removeOperand(OpNo: 0); |
1158 | } |
1159 | } |
1160 | |
1161 | void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, |
1162 | unsigned FrameIndex) const { |
1163 | // Get the instruction. |
1164 | MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> |
1165 | // Get the instruction's basic block. |
1166 | MachineBasicBlock &MBB = *MI.getParent(); |
1167 | MachineFunction &MF = *MBB.getParent(); |
1168 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1169 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1170 | DebugLoc dl = MI.getDebugLoc(); |
1171 | |
1172 | bool LP64 = TM.isPPC64(); |
1173 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
1174 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
1175 | |
1176 | Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
1177 | Register DestReg = MI.getOperand(i: 0).getReg(); |
1178 | assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && |
1179 | "RESTORE_CRBIT does not define its destination" ); |
1180 | |
1181 | addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), |
1182 | Reg), FrameIndex); |
1183 | |
1184 | BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg); |
1185 | |
1186 | Register RegO = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC); |
1187 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) |
1188 | .addReg(getCRFromCRBit(DestReg)); |
1189 | |
1190 | unsigned ShiftBits = getEncodingValue(DestReg); |
1191 | // rlwimi r11, r10, 32-ShiftBits, ..., ... |
1192 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) |
1193 | .addReg(RegO, RegState::Kill) |
1194 | .addReg(Reg, RegState::Kill) |
1195 | .addImm(ShiftBits ? 32 - ShiftBits : 0) |
1196 | .addImm(ShiftBits) |
1197 | .addImm(ShiftBits); |
1198 | |
1199 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), |
1200 | getCRFromCRBit(DestReg)) |
1201 | .addReg(RegO, RegState::Kill) |
1202 | // Make sure we have a use dependency all the way through this |
1203 | // sequence of instructions. We can't have the other bits in the CR |
1204 | // modified in between the mfocrf and the mtocrf. |
1205 | .addReg(getCRFromCRBit(DestReg), RegState::Implicit); |
1206 | |
1207 | // Discard the pseudo instruction. |
1208 | MBB.erase(I: II); |
1209 | } |
1210 | |
1211 | void PPCRegisterInfo::emitAccCopyInfo(MachineBasicBlock &MBB, |
1212 | MCRegister DestReg, MCRegister SrcReg) { |
1213 | #ifdef NDEBUG |
1214 | return; |
1215 | #else |
1216 | if (ReportAccMoves) { |
1217 | std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc" ; |
1218 | std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc" ; |
1219 | dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n" ; |
1220 | MBB.dump(); |
1221 | } |
1222 | #endif |
1223 | } |
1224 | |
1225 | static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed, |
1226 | bool IsRestore) { |
1227 | #ifdef NDEBUG |
1228 | return; |
1229 | #else |
1230 | if (ReportAccMoves) { |
1231 | dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc" ) << " register " |
1232 | << (IsRestore ? "restore" : "spill" ) << ":\n" ; |
1233 | MBB.dump(); |
1234 | } |
1235 | #endif |
1236 | } |
1237 | |
1238 | static void spillRegPairs(MachineBasicBlock &MBB, |
1239 | MachineBasicBlock::iterator II, DebugLoc DL, |
1240 | const TargetInstrInfo &TII, Register SrcReg, |
1241 | unsigned FrameIndex, bool IsLittleEndian, |
1242 | bool IsKilled, bool TwoPairs) { |
1243 | unsigned Offset = 0; |
1244 | // The register arithmetic in this function does not support virtual |
1245 | // registers. |
1246 | assert(!SrcReg.isVirtual() && |
1247 | "Spilling register pairs does not support virtual registers." ); |
1248 | |
1249 | if (TwoPairs) |
1250 | Offset = IsLittleEndian ? 48 : 0; |
1251 | else |
1252 | Offset = IsLittleEndian ? 16 : 0; |
1253 | Register Reg = (SrcReg > PPC::VSRp15) ? PPC::V0 + (SrcReg - PPC::VSRp16) * 2 |
1254 | : PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2; |
1255 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) |
1256 | .addReg(Reg, getKillRegState(IsKilled)), |
1257 | FrameIndex, Offset); |
1258 | Offset += IsLittleEndian ? -16 : 16; |
1259 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) |
1260 | .addReg(Reg + 1, getKillRegState(IsKilled)), |
1261 | FrameIndex, Offset); |
1262 | if (TwoPairs) { |
1263 | Offset += IsLittleEndian ? -16 : 16; |
1264 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) |
1265 | .addReg(Reg + 2, getKillRegState(IsKilled)), |
1266 | FrameIndex, Offset); |
1267 | Offset += IsLittleEndian ? -16 : 16; |
1268 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) |
1269 | .addReg(Reg + 3, getKillRegState(IsKilled)), |
1270 | FrameIndex, Offset); |
1271 | } |
1272 | } |
1273 | |
1274 | /// Remove any STXVP[X] instructions and split them out into a pair of |
1275 | /// STXV[X] instructions if --disable-auto-paired-vec-st is specified on |
1276 | /// the command line. |
1277 | void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II, |
1278 | unsigned FrameIndex) const { |
1279 | assert(DisableAutoPairedVecSt && |
1280 | "Expecting to do this only if paired vector stores are disabled." ); |
1281 | MachineInstr &MI = *II; // STXVP <SrcReg>, <offset> |
1282 | MachineBasicBlock &MBB = *MI.getParent(); |
1283 | MachineFunction &MF = *MBB.getParent(); |
1284 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1285 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1286 | DebugLoc DL = MI.getDebugLoc(); |
1287 | Register SrcReg = MI.getOperand(i: 0).getReg(); |
1288 | bool IsLittleEndian = Subtarget.isLittleEndian(); |
1289 | bool IsKilled = MI.getOperand(i: 0).isKill(); |
1290 | spillRegPairs(MBB, II, DL, TII, SrcReg, FrameIndex, IsLittleEndian, IsKilled, |
1291 | /* TwoPairs */ false); |
1292 | // Discard the original instruction. |
1293 | MBB.erase(I: II); |
1294 | } |
1295 | |
1296 | static void emitWAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsRestore) { |
1297 | #ifdef NDEBUG |
1298 | return; |
1299 | #else |
1300 | if (ReportAccMoves) { |
1301 | dbgs() << "Emitting wacc register " << (IsRestore ? "restore" : "spill" ) |
1302 | << ":\n" ; |
1303 | MBB.dump(); |
1304 | } |
1305 | #endif |
1306 | } |
1307 | |
1308 | /// lowerACCSpilling - Generate the code for spilling the accumulator register. |
1309 | /// Similarly to other spills/reloads that use pseudo-ops, we do not actually |
1310 | /// eliminate the FrameIndex here nor compute the stack offset. We simply |
1311 | /// create a real instruction with an FI and rely on eliminateFrameIndex to |
1312 | /// handle the FI elimination. |
1313 | void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II, |
1314 | unsigned FrameIndex) const { |
1315 | MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset> |
1316 | MachineBasicBlock &MBB = *MI.getParent(); |
1317 | MachineFunction &MF = *MBB.getParent(); |
1318 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1319 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1320 | DebugLoc DL = MI.getDebugLoc(); |
1321 | Register SrcReg = MI.getOperand(i: 0).getReg(); |
1322 | bool IsKilled = MI.getOperand(i: 0).isKill(); |
1323 | |
1324 | bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg); |
1325 | Register Reg = |
1326 | PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; |
1327 | bool IsLittleEndian = Subtarget.isLittleEndian(); |
1328 | |
1329 | emitAccSpillRestoreInfo(MBB, IsPrimed, IsRestore: false); |
1330 | |
1331 | // De-prime the register being spilled, create two stores for the pair |
1332 | // subregisters accounting for endianness and then re-prime the register if |
1333 | // it isn't killed. This uses the Offset parameter to addFrameReference() to |
1334 | // adjust the offset of the store that is within the 64-byte stack slot. |
1335 | if (IsPrimed) |
1336 | BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg); |
1337 | if (DisableAutoPairedVecSt) |
1338 | spillRegPairs(MBB, II, DL, TII, SrcReg: Reg, FrameIndex, IsLittleEndian, IsKilled, |
1339 | /* TwoPairs */ true); |
1340 | else { |
1341 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) |
1342 | .addReg(Reg, getKillRegState(IsKilled)), |
1343 | FrameIndex, IsLittleEndian ? 32 : 0); |
1344 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) |
1345 | .addReg(Reg + 1, getKillRegState(IsKilled)), |
1346 | FrameIndex, IsLittleEndian ? 0 : 32); |
1347 | } |
1348 | if (IsPrimed && !IsKilled) |
1349 | BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg); |
1350 | |
1351 | // Discard the pseudo instruction. |
1352 | MBB.erase(I: II); |
1353 | } |
1354 | |
1355 | /// lowerACCRestore - Generate the code to restore the accumulator register. |
1356 | void PPCRegisterInfo::lowerACCRestore(MachineBasicBlock::iterator II, |
1357 | unsigned FrameIndex) const { |
1358 | MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset> |
1359 | MachineBasicBlock &MBB = *MI.getParent(); |
1360 | MachineFunction &MF = *MBB.getParent(); |
1361 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1362 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1363 | DebugLoc DL = MI.getDebugLoc(); |
1364 | |
1365 | Register DestReg = MI.getOperand(i: 0).getReg(); |
1366 | assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && |
1367 | "RESTORE_ACC does not define its destination" ); |
1368 | |
1369 | bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg); |
1370 | Register Reg = |
1371 | PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; |
1372 | bool IsLittleEndian = Subtarget.isLittleEndian(); |
1373 | |
1374 | emitAccSpillRestoreInfo(MBB, IsPrimed, IsRestore: true); |
1375 | |
1376 | // Create two loads for the pair subregisters accounting for endianness and |
1377 | // then prime the accumulator register being restored. |
1378 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg), |
1379 | FrameIndex, IsLittleEndian ? 32 : 0); |
1380 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1), |
1381 | FrameIndex, IsLittleEndian ? 0 : 32); |
1382 | if (IsPrimed) |
1383 | BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg); |
1384 | |
1385 | // Discard the pseudo instruction. |
1386 | MBB.erase(I: II); |
1387 | } |
1388 | |
1389 | /// lowerWACCSpilling - Generate the code for spilling the wide accumulator |
1390 | /// register. |
1391 | void PPCRegisterInfo::lowerWACCSpilling(MachineBasicBlock::iterator II, |
1392 | unsigned FrameIndex) const { |
1393 | MachineInstr &MI = *II; // SPILL_WACC <SrcReg>, <offset> |
1394 | MachineBasicBlock &MBB = *MI.getParent(); |
1395 | MachineFunction &MF = *MBB.getParent(); |
1396 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1397 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1398 | DebugLoc DL = MI.getDebugLoc(); |
1399 | bool IsLittleEndian = Subtarget.isLittleEndian(); |
1400 | |
1401 | emitWAccSpillRestoreInfo(MBB, IsRestore: false); |
1402 | |
1403 | const TargetRegisterClass *RC = &PPC::VSRpRCRegClass; |
1404 | Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC); |
1405 | Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC); |
1406 | Register SrcReg = MI.getOperand(i: 0).getReg(); |
1407 | |
1408 | BuildMI(MBB, II, DL, TII.get(PPC::DMXXEXTFDMR512), VSRpReg0) |
1409 | .addDef(VSRpReg1) |
1410 | .addReg(SrcReg); |
1411 | |
1412 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) |
1413 | .addReg(VSRpReg0, RegState::Kill), |
1414 | FrameIndex, IsLittleEndian ? 32 : 0); |
1415 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) |
1416 | .addReg(VSRpReg1, RegState::Kill), |
1417 | FrameIndex, IsLittleEndian ? 0 : 32); |
1418 | |
1419 | // Discard the pseudo instruction. |
1420 | MBB.erase(I: II); |
1421 | } |
1422 | |
1423 | /// lowerWACCRestore - Generate the code to restore the wide accumulator |
1424 | /// register. |
1425 | void PPCRegisterInfo::lowerWACCRestore(MachineBasicBlock::iterator II, |
1426 | unsigned FrameIndex) const { |
1427 | MachineInstr &MI = *II; // <DestReg> = RESTORE_WACC <offset> |
1428 | MachineBasicBlock &MBB = *MI.getParent(); |
1429 | MachineFunction &MF = *MBB.getParent(); |
1430 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1431 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1432 | DebugLoc DL = MI.getDebugLoc(); |
1433 | bool IsLittleEndian = Subtarget.isLittleEndian(); |
1434 | |
1435 | emitWAccSpillRestoreInfo(MBB, IsRestore: true); |
1436 | |
1437 | const TargetRegisterClass *RC = &PPC::VSRpRCRegClass; |
1438 | Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC); |
1439 | Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC); |
1440 | Register DestReg = MI.getOperand(i: 0).getReg(); |
1441 | |
1442 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg0), |
1443 | FrameIndex, IsLittleEndian ? 32 : 0); |
1444 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg1), |
1445 | FrameIndex, IsLittleEndian ? 0 : 32); |
1446 | |
1447 | // Kill VSRpReg0, VSRpReg1 (killedRegState::Killed) |
1448 | BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTFDMR512), DestReg) |
1449 | .addReg(VSRpReg0, RegState::Kill) |
1450 | .addReg(VSRpReg1, RegState::Kill); |
1451 | |
1452 | // Discard the pseudo instruction. |
1453 | MBB.erase(I: II); |
1454 | } |
1455 | |
1456 | /// lowerQuadwordSpilling - Generate code to spill paired general register. |
1457 | void PPCRegisterInfo::lowerQuadwordSpilling(MachineBasicBlock::iterator II, |
1458 | unsigned FrameIndex) const { |
1459 | MachineInstr &MI = *II; |
1460 | MachineBasicBlock &MBB = *MI.getParent(); |
1461 | MachineFunction &MF = *MBB.getParent(); |
1462 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1463 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1464 | DebugLoc DL = MI.getDebugLoc(); |
1465 | |
1466 | Register SrcReg = MI.getOperand(i: 0).getReg(); |
1467 | bool IsKilled = MI.getOperand(i: 0).isKill(); |
1468 | |
1469 | Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2; |
1470 | bool IsLittleEndian = Subtarget.isLittleEndian(); |
1471 | |
1472 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) |
1473 | .addReg(Reg, getKillRegState(IsKilled)), |
1474 | FrameIndex, IsLittleEndian ? 8 : 0); |
1475 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) |
1476 | .addReg(Reg + 1, getKillRegState(IsKilled)), |
1477 | FrameIndex, IsLittleEndian ? 0 : 8); |
1478 | |
1479 | // Discard the pseudo instruction. |
1480 | MBB.erase(I: II); |
1481 | } |
1482 | |
1483 | /// lowerQuadwordRestore - Generate code to restore paired general register. |
1484 | void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II, |
1485 | unsigned FrameIndex) const { |
1486 | MachineInstr &MI = *II; |
1487 | MachineBasicBlock &MBB = *MI.getParent(); |
1488 | MachineFunction &MF = *MBB.getParent(); |
1489 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1490 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1491 | DebugLoc DL = MI.getDebugLoc(); |
1492 | |
1493 | Register DestReg = MI.getOperand(i: 0).getReg(); |
1494 | assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && |
1495 | "RESTORE_QUADWORD does not define its destination" ); |
1496 | |
1497 | Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2; |
1498 | bool IsLittleEndian = Subtarget.isLittleEndian(); |
1499 | |
1500 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg), FrameIndex, |
1501 | IsLittleEndian ? 8 : 0); |
1502 | addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg + 1), FrameIndex, |
1503 | IsLittleEndian ? 0 : 8); |
1504 | |
1505 | // Discard the pseudo instruction. |
1506 | MBB.erase(I: II); |
1507 | } |
1508 | |
1509 | bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, |
1510 | Register Reg, int &FrameIdx) const { |
1511 | // For the nonvolatile condition registers (CR2, CR3, CR4) return true to |
1512 | // prevent allocating an additional frame slot. |
1513 | // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8, |
1514 | // for 32-bit AIX the CR save area is in the linkage area at SP+4. |
1515 | // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos |
1516 | // valid. |
1517 | // For 32-bit ELF, we have previously created the stack slot if needed, so |
1518 | // return its FrameIdx. |
1519 | if (PPC::CR2 <= Reg && Reg <= PPC::CR4) { |
1520 | FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex(); |
1521 | return true; |
1522 | } |
1523 | return false; |
1524 | } |
1525 | |
1526 | // If the offset must be a multiple of some value, return what that value is. |
1527 | static unsigned offsetMinAlignForOpcode(unsigned OpC) { |
1528 | switch (OpC) { |
1529 | default: |
1530 | return 1; |
1531 | case PPC::LWA: |
1532 | case PPC::LWA_32: |
1533 | case PPC::LD: |
1534 | case PPC::LDU: |
1535 | case PPC::STD: |
1536 | case PPC::STDU: |
1537 | case PPC::DFLOADf32: |
1538 | case PPC::DFLOADf64: |
1539 | case PPC::DFSTOREf32: |
1540 | case PPC::DFSTOREf64: |
1541 | case PPC::LXSD: |
1542 | case PPC::LXSSP: |
1543 | case PPC::STXSD: |
1544 | case PPC::STXSSP: |
1545 | case PPC::STQ: |
1546 | return 4; |
1547 | case PPC::EVLDD: |
1548 | case PPC::EVSTDD: |
1549 | return 8; |
1550 | case PPC::LXV: |
1551 | case PPC::STXV: |
1552 | case PPC::LQ: |
1553 | case PPC::LXVP: |
1554 | case PPC::STXVP: |
1555 | return 16; |
1556 | } |
1557 | } |
1558 | |
1559 | // If the offset must be a multiple of some value, return what that value is. |
1560 | static unsigned offsetMinAlign(const MachineInstr &MI) { |
1561 | unsigned OpC = MI.getOpcode(); |
1562 | return offsetMinAlignForOpcode(OpC); |
1563 | } |
1564 | |
1565 | // Return the OffsetOperandNo given the FIOperandNum (and the instruction). |
1566 | static unsigned getOffsetONFromFION(const MachineInstr &MI, |
1567 | unsigned FIOperandNum) { |
1568 | // Take into account whether it's an add or mem instruction |
1569 | unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; |
1570 | if (MI.isInlineAsm()) |
1571 | OffsetOperandNo = FIOperandNum - 1; |
1572 | else if (MI.getOpcode() == TargetOpcode::STACKMAP || |
1573 | MI.getOpcode() == TargetOpcode::PATCHPOINT) |
1574 | OffsetOperandNo = FIOperandNum + 1; |
1575 | |
1576 | return OffsetOperandNo; |
1577 | } |
1578 | |
1579 | bool |
1580 | PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
1581 | int SPAdj, unsigned FIOperandNum, |
1582 | RegScavenger *RS) const { |
1583 | assert(SPAdj == 0 && "Unexpected" ); |
1584 | |
1585 | // Get the instruction. |
1586 | MachineInstr &MI = *II; |
1587 | // Get the instruction's basic block. |
1588 | MachineBasicBlock &MBB = *MI.getParent(); |
1589 | // Get the basic block's function. |
1590 | MachineFunction &MF = *MBB.getParent(); |
1591 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1592 | // Get the instruction info. |
1593 | const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); |
1594 | // Get the frame info. |
1595 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
1596 | DebugLoc dl = MI.getDebugLoc(); |
1597 | |
1598 | unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); |
1599 | |
1600 | // Get the frame index. |
1601 | int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex(); |
1602 | |
1603 | // Get the frame pointer save index. Users of this index are primarily |
1604 | // DYNALLOC instructions. |
1605 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
1606 | int FPSI = FI->getFramePointerSaveIndex(); |
1607 | // Get the instruction opcode. |
1608 | unsigned OpC = MI.getOpcode(); |
1609 | |
1610 | if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) { |
1611 | lowerDynamicAreaOffset(II); |
1612 | // lowerDynamicAreaOffset erases II |
1613 | return true; |
1614 | } |
1615 | |
1616 | // Special case for dynamic alloca. |
1617 | if (FPSI && FrameIndex == FPSI && |
1618 | (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { |
1619 | lowerDynamicAlloc(II); |
1620 | // lowerDynamicAlloc erases II |
1621 | return true; |
1622 | } |
1623 | |
1624 | if (FPSI && FrameIndex == FPSI && |
1625 | (OpC == PPC::PREPARE_PROBED_ALLOCA_64 || |
1626 | OpC == PPC::PREPARE_PROBED_ALLOCA_32 || |
1627 | OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 || |
1628 | OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) { |
1629 | lowerPrepareProbedAlloca(II); |
1630 | // lowerPrepareProbedAlloca erases II |
1631 | return true; |
1632 | } |
1633 | |
1634 | // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. |
1635 | if (OpC == PPC::SPILL_CR) { |
1636 | lowerCRSpilling(II, FrameIndex); |
1637 | return true; |
1638 | } else if (OpC == PPC::RESTORE_CR) { |
1639 | lowerCRRestore(II, FrameIndex); |
1640 | return true; |
1641 | } else if (OpC == PPC::SPILL_CRBIT) { |
1642 | lowerCRBitSpilling(II, FrameIndex); |
1643 | return true; |
1644 | } else if (OpC == PPC::RESTORE_CRBIT) { |
1645 | lowerCRBitRestore(II, FrameIndex); |
1646 | return true; |
1647 | } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) { |
1648 | lowerACCSpilling(II, FrameIndex); |
1649 | return true; |
1650 | } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) { |
1651 | lowerACCRestore(II, FrameIndex); |
1652 | return true; |
1653 | } else if (OpC == PPC::STXVP && DisableAutoPairedVecSt) { |
1654 | lowerOctWordSpilling(II, FrameIndex); |
1655 | return true; |
1656 | } else if (OpC == PPC::SPILL_WACC) { |
1657 | lowerWACCSpilling(II, FrameIndex); |
1658 | return true; |
1659 | } else if (OpC == PPC::RESTORE_WACC) { |
1660 | lowerWACCRestore(II, FrameIndex); |
1661 | return true; |
1662 | } else if (OpC == PPC::SPILL_QUADWORD) { |
1663 | lowerQuadwordSpilling(II, FrameIndex); |
1664 | return true; |
1665 | } else if (OpC == PPC::RESTORE_QUADWORD) { |
1666 | lowerQuadwordRestore(II, FrameIndex); |
1667 | return true; |
1668 | } |
1669 | |
1670 | // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). |
1671 | MI.getOperand(FIOperandNum).ChangeToRegister( |
1672 | FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); |
1673 | |
1674 | // If the instruction is not present in ImmToIdxMap, then it has no immediate |
1675 | // form (and must be r+r). |
1676 | bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && |
1677 | OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); |
1678 | |
1679 | // Now add the frame object offset to the offset from r1. |
1680 | int64_t Offset = MFI.getObjectOffset(ObjectIdx: FrameIndex); |
1681 | Offset += MI.getOperand(i: OffsetOperandNo).getImm(); |
1682 | |
1683 | // If we're not using a Frame Pointer that has been set to the value of the |
1684 | // SP before having the stack size subtracted from it, then add the stack size |
1685 | // to Offset to get the correct offset. |
1686 | // Naked functions have stack size 0, although getStackSize may not reflect |
1687 | // that because we didn't call all the pieces that compute it for naked |
1688 | // functions. |
1689 | if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) { |
1690 | if (!(hasBasePointer(MF) && FrameIndex < 0)) |
1691 | Offset += MFI.getStackSize(); |
1692 | } |
1693 | |
1694 | // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can |
1695 | // transform it to the prefixed version so we don't have to use the XForm. |
1696 | if ((OpC == PPC::LXVP || OpC == PPC::STXVP) && |
1697 | (!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) && |
1698 | Subtarget.hasPrefixInstrs()) { |
1699 | unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP; |
1700 | MI.setDesc(TII.get(NewOpc)); |
1701 | OpC = NewOpc; |
1702 | } |
1703 | |
1704 | // If we can, encode the offset directly into the instruction. If this is a |
1705 | // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If |
1706 | // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits |
1707 | // clear can be encoded. This is extremely uncommon, because normally you |
1708 | // only "std" to a stack slot that is at least 4-byte aligned, but it can |
1709 | // happen in invalid code. |
1710 | assert(OpC != PPC::DBG_VALUE && |
1711 | "This should be handled in a target-independent way" ); |
1712 | // FIXME: This should be factored out to a separate function as prefixed |
1713 | // instructions add a number of opcodes for which we can use 34-bit imm. |
1714 | bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ? |
1715 | isUInt<8>(Offset) : |
1716 | isInt<16>(Offset); |
1717 | if (TII.isPrefixed(Opcode: MI.getOpcode())) |
1718 | OffsetFitsMnemonic = isInt<34>(x: Offset); |
1719 | if (!noImmForm && ((OffsetFitsMnemonic && |
1720 | ((Offset % offsetMinAlign(MI)) == 0)) || |
1721 | OpC == TargetOpcode::STACKMAP || |
1722 | OpC == TargetOpcode::PATCHPOINT)) { |
1723 | MI.getOperand(i: OffsetOperandNo).ChangeToImmediate(ImmVal: Offset); |
1724 | return false; |
1725 | } |
1726 | |
1727 | // The offset doesn't fit into a single register, scavenge one to build the |
1728 | // offset in. |
1729 | |
1730 | bool is64Bit = TM.isPPC64(); |
1731 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
1732 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
1733 | const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; |
1734 | unsigned NewOpcode = 0u; |
1735 | bool ScavengingFailed = RS && RS->getRegsAvailable(RC).none() && |
1736 | RS->getRegsAvailable(&PPC::VSFRCRegClass).any(); |
1737 | Register SRegHi, SReg, VSReg; |
1738 | |
1739 | // The register scavenger is unable to get a GPR but can get a VSR. We |
1740 | // need to stash a GPR into a VSR so that we can free one up. |
1741 | if (ScavengingFailed && Subtarget.hasDirectMove()) { |
1742 | // Pick a volatile register and if we are spilling/restoring that |
1743 | // particular one, pick the next one. |
1744 | SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4; |
1745 | if (MI.getOperand(i: 0).getReg() == SReg) |
1746 | SRegHi = SReg = SReg + 1; |
1747 | VSReg = MF.getRegInfo().createVirtualRegister(&PPC::VSFRCRegClass); |
1748 | BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::MTVSRD : PPC::MTVSRWZ), VSReg) |
1749 | .addReg(SReg); |
1750 | } else { |
1751 | SRegHi = MF.getRegInfo().createVirtualRegister(RegClass: RC); |
1752 | SReg = MF.getRegInfo().createVirtualRegister(RegClass: RC); |
1753 | } |
1754 | |
1755 | // Insert a set of rA with the full offset value before the ld, st, or add |
1756 | if (isInt<16>(x: Offset)) |
1757 | BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) |
1758 | .addImm(Offset); |
1759 | else if (isInt<32>(x: Offset)) { |
1760 | BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) |
1761 | .addImm(Offset >> 16); |
1762 | BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) |
1763 | .addReg(SRegHi, RegState::Kill) |
1764 | .addImm(Offset); |
1765 | } else { |
1766 | assert(is64Bit && "Huge stack is only supported on PPC64" ); |
1767 | TII.materializeImmPostRA(MBB, MBBI: II, DL: dl, Reg: SReg, Imm: Offset); |
1768 | } |
1769 | |
1770 | // Convert into indexed form of the instruction: |
1771 | // |
1772 | // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 |
1773 | // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 |
1774 | unsigned OperandBase; |
1775 | |
1776 | if (noImmForm) |
1777 | OperandBase = 1; |
1778 | else if (OpC != TargetOpcode::INLINEASM && |
1779 | OpC != TargetOpcode::INLINEASM_BR) { |
1780 | assert(ImmToIdxMap.count(OpC) && |
1781 | "No indexed form of load or store available!" ); |
1782 | NewOpcode = ImmToIdxMap.find(OpC)->second; |
1783 | MI.setDesc(TII.get(NewOpcode)); |
1784 | OperandBase = 1; |
1785 | } else { |
1786 | OperandBase = OffsetOperandNo; |
1787 | } |
1788 | |
1789 | Register StackReg = MI.getOperand(i: FIOperandNum).getReg(); |
1790 | MI.getOperand(i: OperandBase).ChangeToRegister(Reg: StackReg, isDef: false); |
1791 | MI.getOperand(i: OperandBase + 1).ChangeToRegister(Reg: SReg, isDef: false, isImp: false, isKill: true); |
1792 | |
1793 | // If we stashed a value from a GPR into a VSR, we need to get it back after |
1794 | // spilling the register. |
1795 | if (ScavengingFailed && Subtarget.hasDirectMove()) |
1796 | BuildMI(MBB, ++II, dl, TII.get(is64Bit ? PPC::MFVSRD : PPC::MFVSRWZ), SReg) |
1797 | .addReg(VSReg); |
1798 | |
1799 | // Since these are not real X-Form instructions, we must |
1800 | // add the registers and access 0(NewReg) rather than |
1801 | // emitting the X-Form pseudo. |
1802 | if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) { |
1803 | assert(is64Bit && "Quadword loads/stores only supported in 64-bit mode" ); |
1804 | Register NewReg = MF.getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); |
1805 | BuildMI(MBB, II, dl, TII.get(PPC::ADD8), NewReg) |
1806 | .addReg(SReg, RegState::Kill) |
1807 | .addReg(StackReg); |
1808 | MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ)); |
1809 | MI.getOperand(i: OperandBase + 1).ChangeToRegister(Reg: NewReg, isDef: false); |
1810 | MI.getOperand(i: OperandBase).ChangeToImmediate(ImmVal: 0); |
1811 | } |
1812 | return false; |
1813 | } |
1814 | |
1815 | Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
1816 | const PPCFrameLowering *TFI = getFrameLowering(MF); |
1817 | |
1818 | if (!TM.isPPC64()) |
1819 | return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; |
1820 | else |
1821 | return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; |
1822 | } |
1823 | |
1824 | Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { |
1825 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1826 | if (!hasBasePointer(MF)) |
1827 | return getFrameRegister(MF); |
1828 | |
1829 | if (TM.isPPC64()) |
1830 | return PPC::X30; |
1831 | |
1832 | if (Subtarget.isSVR4ABI() && TM.isPositionIndependent()) |
1833 | return PPC::R29; |
1834 | |
1835 | return PPC::R30; |
1836 | } |
1837 | |
1838 | bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { |
1839 | if (!EnableBasePointer) |
1840 | return false; |
1841 | if (AlwaysBasePointer) |
1842 | return true; |
1843 | |
1844 | // If we need to realign the stack, then the stack pointer can no longer |
1845 | // serve as an offset into the caller's stack space. As a result, we need a |
1846 | // base pointer. |
1847 | return hasStackRealignment(MF); |
1848 | } |
1849 | |
1850 | /// Returns true if the instruction's frame index |
1851 | /// reference would be better served by a base register other than FP |
1852 | /// or SP. Used by LocalStackFrameAllocation to determine which frame index |
1853 | /// references it should create new base registers for. |
1854 | bool PPCRegisterInfo:: |
1855 | needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { |
1856 | assert(Offset < 0 && "Local offset must be negative" ); |
1857 | |
1858 | // It's the load/store FI references that cause issues, as it can be difficult |
1859 | // to materialize the offset if it won't fit in the literal field. Estimate |
1860 | // based on the size of the local frame and some conservative assumptions |
1861 | // about the rest of the stack frame (note, this is pre-regalloc, so |
1862 | // we don't know everything for certain yet) whether this offset is likely |
1863 | // to be out of range of the immediate. Return true if so. |
1864 | |
1865 | // We only generate virtual base registers for loads and stores that have |
1866 | // an r+i form. Return false for everything else. |
1867 | unsigned OpC = MI->getOpcode(); |
1868 | if (!ImmToIdxMap.count(OpC)) |
1869 | return false; |
1870 | |
1871 | // Don't generate a new virtual base register just to add zero to it. |
1872 | if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && |
1873 | MI->getOperand(2).getImm() == 0) |
1874 | return false; |
1875 | |
1876 | MachineBasicBlock &MBB = *MI->getParent(); |
1877 | MachineFunction &MF = *MBB.getParent(); |
1878 | const PPCFrameLowering *TFI = getFrameLowering(MF); |
1879 | unsigned StackEst = TFI->determineFrameLayout(MF, UseEstimate: true); |
1880 | |
1881 | // If we likely don't need a stack frame, then we probably don't need a |
1882 | // virtual base register either. |
1883 | if (!StackEst) |
1884 | return false; |
1885 | |
1886 | // Estimate an offset from the stack pointer. |
1887 | // The incoming offset is relating to the SP at the start of the function, |
1888 | // but when we access the local it'll be relative to the SP after local |
1889 | // allocation, so adjust our SP-relative offset by that allocation size. |
1890 | Offset += StackEst; |
1891 | |
1892 | // The frame pointer will point to the end of the stack, so estimate the |
1893 | // offset as the difference between the object offset and the FP location. |
1894 | return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset); |
1895 | } |
1896 | |
1897 | /// Insert defining instruction(s) for BaseReg to |
1898 | /// be a pointer to FrameIdx at the beginning of the basic block. |
1899 | Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, |
1900 | int FrameIdx, |
1901 | int64_t Offset) const { |
1902 | unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; |
1903 | |
1904 | MachineBasicBlock::iterator Ins = MBB->begin(); |
1905 | DebugLoc DL; // Defaults to "unknown" |
1906 | if (Ins != MBB->end()) |
1907 | DL = Ins->getDebugLoc(); |
1908 | |
1909 | const MachineFunction &MF = *MBB->getParent(); |
1910 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1911 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1912 | const MCInstrDesc &MCID = TII.get(Opcode: ADDriOpc); |
1913 | MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); |
1914 | const TargetRegisterClass *RC = getPointerRegClass(MF); |
1915 | Register BaseReg = MRI.createVirtualRegister(RegClass: RC); |
1916 | MRI.constrainRegClass(Reg: BaseReg, RC: TII.getRegClass(MCID, 0, this, MF)); |
1917 | |
1918 | BuildMI(BB&: *MBB, I: Ins, MIMD: DL, MCID, DestReg: BaseReg) |
1919 | .addFrameIndex(Idx: FrameIdx).addImm(Val: Offset); |
1920 | |
1921 | return BaseReg; |
1922 | } |
1923 | |
1924 | void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, |
1925 | int64_t Offset) const { |
1926 | unsigned FIOperandNum = 0; |
1927 | while (!MI.getOperand(i: FIOperandNum).isFI()) { |
1928 | ++FIOperandNum; |
1929 | assert(FIOperandNum < MI.getNumOperands() && |
1930 | "Instr doesn't have FrameIndex operand!" ); |
1931 | } |
1932 | |
1933 | MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false); |
1934 | unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); |
1935 | Offset += MI.getOperand(i: OffsetOperandNo).getImm(); |
1936 | MI.getOperand(i: OffsetOperandNo).ChangeToImmediate(ImmVal: Offset); |
1937 | |
1938 | MachineBasicBlock &MBB = *MI.getParent(); |
1939 | MachineFunction &MF = *MBB.getParent(); |
1940 | const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); |
1941 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1942 | const MCInstrDesc &MCID = MI.getDesc(); |
1943 | MachineRegisterInfo &MRI = MF.getRegInfo(); |
1944 | MRI.constrainRegClass(Reg: BaseReg, |
1945 | RC: TII.getRegClass(MCID, FIOperandNum, this, MF)); |
1946 | } |
1947 | |
1948 | bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, |
1949 | Register BaseReg, |
1950 | int64_t Offset) const { |
1951 | unsigned FIOperandNum = 0; |
1952 | while (!MI->getOperand(i: FIOperandNum).isFI()) { |
1953 | ++FIOperandNum; |
1954 | assert(FIOperandNum < MI->getNumOperands() && |
1955 | "Instr doesn't have FrameIndex operand!" ); |
1956 | } |
1957 | |
1958 | unsigned OffsetOperandNo = getOffsetONFromFION(MI: *MI, FIOperandNum); |
1959 | Offset += MI->getOperand(i: OffsetOperandNo).getImm(); |
1960 | |
1961 | return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm |
1962 | MI->getOpcode() == TargetOpcode::STACKMAP || |
1963 | MI->getOpcode() == TargetOpcode::PATCHPOINT || |
1964 | (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0); |
1965 | } |
1966 | |