1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This header defines architecture specific interfaces, x86 version
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See
7 * the COPYING file in the top-level directory.
8 *
9 */
10
11#ifndef _ASM_X86_KVM_HOST_H
12#define _ASM_X86_KVM_HOST_H
13
14#include <linux/types.h>
15#include <linux/mm.h>
16#include <linux/mmu_notifier.h>
17#include <linux/tracepoint.h>
18#include <linux/cpumask.h>
19#include <linux/irq_work.h>
20#include <linux/irq.h>
21
22#include <linux/kvm.h>
23#include <linux/kvm_para.h>
24#include <linux/kvm_types.h>
25#include <linux/perf_event.h>
26#include <linux/pvclock_gtod.h>
27#include <linux/clocksource.h>
28#include <linux/irqbypass.h>
29#include <linux/hyperv.h>
30
31#include <asm/apic.h>
32#include <asm/pvclock-abi.h>
33#include <asm/desc.h>
34#include <asm/mtrr.h>
35#include <asm/msr-index.h>
36#include <asm/asm.h>
37#include <asm/kvm_page_track.h>
38#include <asm/kvm_vcpu_regs.h>
39#include <asm/hyperv-tlfs.h>
40
41#define KVM_MAX_VCPUS 288
42#define KVM_SOFT_MAX_VCPUS 240
43#define KVM_MAX_VCPU_ID 1023
44#define KVM_USER_MEM_SLOTS 509
45/* memory slots that are not exposed to userspace */
46#define KVM_PRIVATE_MEM_SLOTS 3
47#define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS)
48
49#define KVM_HALT_POLL_NS_DEFAULT 200000
50
51#define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
52
53/* x86-specific vcpu->requests bit members */
54#define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0)
55#define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1)
56#define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2)
57#define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3)
58#define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4)
59#define KVM_REQ_LOAD_CR3 KVM_ARCH_REQ(5)
60#define KVM_REQ_EVENT KVM_ARCH_REQ(6)
61#define KVM_REQ_APF_HALT KVM_ARCH_REQ(7)
62#define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8)
63#define KVM_REQ_NMI KVM_ARCH_REQ(9)
64#define KVM_REQ_PMU KVM_ARCH_REQ(10)
65#define KVM_REQ_PMI KVM_ARCH_REQ(11)
66#define KVM_REQ_SMI KVM_ARCH_REQ(12)
67#define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13)
68#define KVM_REQ_MCLOCK_INPROGRESS \
69 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
70#define KVM_REQ_SCAN_IOAPIC \
71 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
72#define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16)
73#define KVM_REQ_APIC_PAGE_RELOAD \
74 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
75#define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18)
76#define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19)
77#define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
78#define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
79#define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
80#define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
81#define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24)
82
83#define CR0_RESERVED_BITS \
84 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
85 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
86 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
87
88#define CR4_RESERVED_BITS \
89 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
90 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
91 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
92 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
93 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
94 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
95
96#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
97
98
99
100#define INVALID_PAGE (~(hpa_t)0)
101#define VALID_PAGE(x) ((x) != INVALID_PAGE)
102
103#define UNMAPPED_GVA (~(gpa_t)0)
104
105/* KVM Hugepage definitions for x86 */
106enum {
107 PT_PAGE_TABLE_LEVEL = 1,
108 PT_DIRECTORY_LEVEL = 2,
109 PT_PDPE_LEVEL = 3,
110 /* set max level to the biggest one */
111 PT_MAX_HUGEPAGE_LEVEL = PT_PDPE_LEVEL,
112};
113#define KVM_NR_PAGE_SIZES (PT_MAX_HUGEPAGE_LEVEL - \
114 PT_PAGE_TABLE_LEVEL + 1)
115#define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
116#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
117#define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
118#define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
119#define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
120
121static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
122{
123 /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */
124 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
125 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
126}
127
128#define KVM_PERMILLE_MMU_PAGES 20
129#define KVM_MIN_ALLOC_MMU_PAGES 64
130#define KVM_MMU_HASH_SHIFT 12
131#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
132#define KVM_MIN_FREE_MMU_PAGES 5
133#define KVM_REFILL_PAGES 25
134#define KVM_MAX_CPUID_ENTRIES 80
135#define KVM_NR_FIXED_MTRR_REGION 88
136#define KVM_NR_VAR_MTRR 8
137
138#define ASYNC_PF_PER_VCPU 64
139
140enum kvm_reg {
141 VCPU_REGS_RAX = __VCPU_REGS_RAX,
142 VCPU_REGS_RCX = __VCPU_REGS_RCX,
143 VCPU_REGS_RDX = __VCPU_REGS_RDX,
144 VCPU_REGS_RBX = __VCPU_REGS_RBX,
145 VCPU_REGS_RSP = __VCPU_REGS_RSP,
146 VCPU_REGS_RBP = __VCPU_REGS_RBP,
147 VCPU_REGS_RSI = __VCPU_REGS_RSI,
148 VCPU_REGS_RDI = __VCPU_REGS_RDI,
149#ifdef CONFIG_X86_64
150 VCPU_REGS_R8 = __VCPU_REGS_R8,
151 VCPU_REGS_R9 = __VCPU_REGS_R9,
152 VCPU_REGS_R10 = __VCPU_REGS_R10,
153 VCPU_REGS_R11 = __VCPU_REGS_R11,
154 VCPU_REGS_R12 = __VCPU_REGS_R12,
155 VCPU_REGS_R13 = __VCPU_REGS_R13,
156 VCPU_REGS_R14 = __VCPU_REGS_R14,
157 VCPU_REGS_R15 = __VCPU_REGS_R15,
158#endif
159 VCPU_REGS_RIP,
160 NR_VCPU_REGS
161};
162
163enum kvm_reg_ex {
164 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
165 VCPU_EXREG_CR3,
166 VCPU_EXREG_RFLAGS,
167 VCPU_EXREG_SEGMENTS,
168};
169
170enum {
171 VCPU_SREG_ES,
172 VCPU_SREG_CS,
173 VCPU_SREG_SS,
174 VCPU_SREG_DS,
175 VCPU_SREG_FS,
176 VCPU_SREG_GS,
177 VCPU_SREG_TR,
178 VCPU_SREG_LDTR,
179};
180
181#include <asm/kvm_emulate.h>
182
183#define KVM_NR_MEM_OBJS 40
184
185#define KVM_NR_DB_REGS 4
186
187#define DR6_BD (1 << 13)
188#define DR6_BS (1 << 14)
189#define DR6_BT (1 << 15)
190#define DR6_RTM (1 << 16)
191#define DR6_FIXED_1 0xfffe0ff0
192#define DR6_INIT 0xffff0ff0
193#define DR6_VOLATILE 0x0001e00f
194
195#define DR7_BP_EN_MASK 0x000000ff
196#define DR7_GE (1 << 9)
197#define DR7_GD (1 << 13)
198#define DR7_FIXED_1 0x00000400
199#define DR7_VOLATILE 0xffff2bff
200
201#define PFERR_PRESENT_BIT 0
202#define PFERR_WRITE_BIT 1
203#define PFERR_USER_BIT 2
204#define PFERR_RSVD_BIT 3
205#define PFERR_FETCH_BIT 4
206#define PFERR_PK_BIT 5
207#define PFERR_GUEST_FINAL_BIT 32
208#define PFERR_GUEST_PAGE_BIT 33
209
210#define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
211#define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
212#define PFERR_USER_MASK (1U << PFERR_USER_BIT)
213#define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
214#define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
215#define PFERR_PK_MASK (1U << PFERR_PK_BIT)
216#define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT)
217#define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT)
218
219#define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \
220 PFERR_WRITE_MASK | \
221 PFERR_PRESENT_MASK)
222
223/*
224 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or
225 * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting
226 * with the SVE bit in EPT PTEs.
227 */
228#define SPTE_SPECIAL_MASK (1ULL << 62)
229
230/* apic attention bits */
231#define KVM_APIC_CHECK_VAPIC 0
232/*
233 * The following bit is set with PV-EOI, unset on EOI.
234 * We detect PV-EOI changes by guest by comparing
235 * this bit with PV-EOI in guest memory.
236 * See the implementation in apic_update_pv_eoi.
237 */
238#define KVM_APIC_PV_EOI_PENDING 1
239
240struct kvm_kernel_irq_routing_entry;
241
242/*
243 * We don't want allocation failures within the mmu code, so we preallocate
244 * enough memory for a single page fault in a cache.
245 */
246struct kvm_mmu_memory_cache {
247 int nobjs;
248 void *objects[KVM_NR_MEM_OBJS];
249};
250
251/*
252 * the pages used as guest page table on soft mmu are tracked by
253 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used
254 * by indirect shadow page can not be more than 15 bits.
255 *
256 * Currently, we used 14 bits that are @level, @cr4_pae, @quadrant, @access,
257 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp.
258 */
259union kvm_mmu_page_role {
260 u32 word;
261 struct {
262 unsigned level:4;
263 unsigned cr4_pae:1;
264 unsigned quadrant:2;
265 unsigned direct:1;
266 unsigned access:3;
267 unsigned invalid:1;
268 unsigned nxe:1;
269 unsigned cr0_wp:1;
270 unsigned smep_andnot_wp:1;
271 unsigned smap_andnot_wp:1;
272 unsigned ad_disabled:1;
273 unsigned guest_mode:1;
274 unsigned :6;
275
276 /*
277 * This is left at the top of the word so that
278 * kvm_memslots_for_spte_role can extract it with a
279 * simple shift. While there is room, give it a whole
280 * byte so it is also faster to load it from memory.
281 */
282 unsigned smm:8;
283 };
284};
285
286union kvm_mmu_extended_role {
287/*
288 * This structure complements kvm_mmu_page_role caching everything needed for
289 * MMU configuration. If nothing in both these structures changed, MMU
290 * re-configuration can be skipped. @valid bit is set on first usage so we don't
291 * treat all-zero structure as valid data.
292 */
293 u32 word;
294 struct {
295 unsigned int valid:1;
296 unsigned int execonly:1;
297 unsigned int cr0_pg:1;
298 unsigned int cr4_pse:1;
299 unsigned int cr4_pke:1;
300 unsigned int cr4_smap:1;
301 unsigned int cr4_smep:1;
302 unsigned int cr4_la57:1;
303 unsigned int maxphyaddr:6;
304 };
305};
306
307union kvm_mmu_role {
308 u64 as_u64;
309 struct {
310 union kvm_mmu_page_role base;
311 union kvm_mmu_extended_role ext;
312 };
313};
314
315struct kvm_rmap_head {
316 unsigned long val;
317};
318
319struct kvm_mmu_page {
320 struct list_head link;
321 struct hlist_node hash_link;
322 bool unsync;
323 bool mmio_cached;
324
325 /*
326 * The following two entries are used to key the shadow page in the
327 * hash table.
328 */
329 union kvm_mmu_page_role role;
330 gfn_t gfn;
331
332 u64 *spt;
333 /* hold the gfn of each spte inside spt */
334 gfn_t *gfns;
335 int root_count; /* Currently serving as active root */
336 unsigned int unsync_children;
337 struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */
338 DECLARE_BITMAP(unsync_child_bitmap, 512);
339
340#ifdef CONFIG_X86_32
341 /*
342 * Used out of the mmu-lock to avoid reading spte values while an
343 * update is in progress; see the comments in __get_spte_lockless().
344 */
345 int clear_spte_count;
346#endif
347
348 /* Number of writes since the last time traversal visited this page. */
349 atomic_t write_flooding_count;
350};
351
352struct kvm_pio_request {
353 unsigned long count;
354 int in;
355 int port;
356 int size;
357};
358
359#define PT64_ROOT_MAX_LEVEL 5
360
361struct rsvd_bits_validate {
362 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
363 u64 bad_mt_xwr;
364};
365
366struct kvm_mmu_root_info {
367 gpa_t cr3;
368 hpa_t hpa;
369};
370
371#define KVM_MMU_ROOT_INFO_INVALID \
372 ((struct kvm_mmu_root_info) { .cr3 = INVALID_PAGE, .hpa = INVALID_PAGE })
373
374#define KVM_MMU_NUM_PREV_ROOTS 3
375
376/*
377 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit,
378 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the
379 * current mmu mode.
380 */
381struct kvm_mmu {
382 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root);
383 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu);
384 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
385 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err,
386 bool prefault);
387 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
388 struct x86_exception *fault);
389 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access,
390 struct x86_exception *exception);
391 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
392 struct x86_exception *exception);
393 int (*sync_page)(struct kvm_vcpu *vcpu,
394 struct kvm_mmu_page *sp);
395 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa);
396 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
397 u64 *spte, const void *pte);
398 hpa_t root_hpa;
399 gpa_t root_cr3;
400 union kvm_mmu_role mmu_role;
401 u8 root_level;
402 u8 shadow_root_level;
403 u8 ept_ad;
404 bool direct_map;
405 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS];
406
407 /*
408 * Bitmap; bit set = permission fault
409 * Byte index: page fault error code [4:1]
410 * Bit index: pte permissions in ACC_* format
411 */
412 u8 permissions[16];
413
414 /*
415 * The pkru_mask indicates if protection key checks are needed. It
416 * consists of 16 domains indexed by page fault error code bits [4:1],
417 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
418 * Each domain has 2 bits which are ANDed with AD and WD from PKRU.
419 */
420 u32 pkru_mask;
421
422 u64 *pae_root;
423 u64 *lm_root;
424
425 /*
426 * check zero bits on shadow page table entries, these
427 * bits include not only hardware reserved bits but also
428 * the bits spte never used.
429 */
430 struct rsvd_bits_validate shadow_zero_check;
431
432 struct rsvd_bits_validate guest_rsvd_check;
433
434 /* Can have large pages at levels 2..last_nonleaf_level-1. */
435 u8 last_nonleaf_level;
436
437 bool nx;
438
439 u64 pdptrs[4]; /* pae */
440};
441
442struct kvm_tlb_range {
443 u64 start_gfn;
444 u64 pages;
445};
446
447enum pmc_type {
448 KVM_PMC_GP = 0,
449 KVM_PMC_FIXED,
450};
451
452struct kvm_pmc {
453 enum pmc_type type;
454 u8 idx;
455 u64 counter;
456 u64 eventsel;
457 struct perf_event *perf_event;
458 struct kvm_vcpu *vcpu;
459};
460
461struct kvm_pmu {
462 unsigned nr_arch_gp_counters;
463 unsigned nr_arch_fixed_counters;
464 unsigned available_event_types;
465 u64 fixed_ctr_ctrl;
466 u64 global_ctrl;
467 u64 global_status;
468 u64 global_ovf_ctrl;
469 u64 counter_bitmask[2];
470 u64 global_ctrl_mask;
471 u64 reserved_bits;
472 u8 version;
473 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
474 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
475 struct irq_work irq_work;
476 u64 reprogram_pmi;
477};
478
479struct kvm_pmu_ops;
480
481enum {
482 KVM_DEBUGREG_BP_ENABLED = 1,
483 KVM_DEBUGREG_WONT_EXIT = 2,
484 KVM_DEBUGREG_RELOAD = 4,
485};
486
487struct kvm_mtrr_range {
488 u64 base;
489 u64 mask;
490 struct list_head node;
491};
492
493struct kvm_mtrr {
494 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR];
495 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION];
496 u64 deftype;
497
498 struct list_head head;
499};
500
501/* Hyper-V SynIC timer */
502struct kvm_vcpu_hv_stimer {
503 struct hrtimer timer;
504 int index;
505 union hv_stimer_config config;
506 u64 count;
507 u64 exp_time;
508 struct hv_message msg;
509 bool msg_pending;
510};
511
512/* Hyper-V synthetic interrupt controller (SynIC)*/
513struct kvm_vcpu_hv_synic {
514 u64 version;
515 u64 control;
516 u64 msg_page;
517 u64 evt_page;
518 atomic64_t sint[HV_SYNIC_SINT_COUNT];
519 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT];
520 DECLARE_BITMAP(auto_eoi_bitmap, 256);
521 DECLARE_BITMAP(vec_bitmap, 256);
522 bool active;
523 bool dont_zero_synic_pages;
524};
525
526/* Hyper-V per vcpu emulation context */
527struct kvm_vcpu_hv {
528 u32 vp_index;
529 u64 hv_vapic;
530 s64 runtime_offset;
531 struct kvm_vcpu_hv_synic synic;
532 struct kvm_hyperv_exit exit;
533 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT];
534 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT);
535 cpumask_t tlb_flush;
536};
537
538struct kvm_vcpu_arch {
539 /*
540 * rip and regs accesses must go through
541 * kvm_{register,rip}_{read,write} functions.
542 */
543 unsigned long regs[NR_VCPU_REGS];
544 u32 regs_avail;
545 u32 regs_dirty;
546
547 unsigned long cr0;
548 unsigned long cr0_guest_owned_bits;
549 unsigned long cr2;
550 unsigned long cr3;
551 unsigned long cr4;
552 unsigned long cr4_guest_owned_bits;
553 unsigned long cr8;
554 u32 pkru;
555 u32 hflags;
556 u64 efer;
557 u64 apic_base;
558 struct kvm_lapic *apic; /* kernel irqchip context */
559 bool apicv_active;
560 bool load_eoi_exitmap_pending;
561 DECLARE_BITMAP(ioapic_handled_vectors, 256);
562 unsigned long apic_attention;
563 int32_t apic_arb_prio;
564 int mp_state;
565 u64 ia32_misc_enable_msr;
566 u64 smbase;
567 u64 smi_count;
568 bool tpr_access_reporting;
569 u64 ia32_xss;
570 u64 microcode_version;
571
572 /*
573 * Paging state of the vcpu
574 *
575 * If the vcpu runs in guest mode with two level paging this still saves
576 * the paging mode of the l1 guest. This context is always used to
577 * handle faults.
578 */
579 struct kvm_mmu *mmu;
580
581 /* Non-nested MMU for L1 */
582 struct kvm_mmu root_mmu;
583
584 /* L1 MMU when running nested */
585 struct kvm_mmu guest_mmu;
586
587 /*
588 * Paging state of an L2 guest (used for nested npt)
589 *
590 * This context will save all necessary information to walk page tables
591 * of the an L2 guest. This context is only initialized for page table
592 * walking and not for faulting since we never handle l2 page faults on
593 * the host.
594 */
595 struct kvm_mmu nested_mmu;
596
597 /*
598 * Pointer to the mmu context currently used for
599 * gva_to_gpa translations.
600 */
601 struct kvm_mmu *walk_mmu;
602
603 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
604 struct kvm_mmu_memory_cache mmu_page_cache;
605 struct kvm_mmu_memory_cache mmu_page_header_cache;
606
607 /*
608 * QEMU userspace and the guest each have their own FPU state.
609 * In vcpu_run, we switch between the user, maintained in the
610 * task_struct struct, and guest FPU contexts. While running a VCPU,
611 * the VCPU thread will have the guest FPU context.
612 *
613 * Note that while the PKRU state lives inside the fpu registers,
614 * it is switched out separately at VMENTER and VMEXIT time. The
615 * "guest_fpu" state here contains the guest FPU context, with the
616 * host PRKU bits.
617 */
618 struct fpu *guest_fpu;
619
620 u64 xcr0;
621 u64 guest_supported_xcr0;
622 u32 guest_xstate_size;
623
624 struct kvm_pio_request pio;
625 void *pio_data;
626
627 u8 event_exit_inst_len;
628
629 struct kvm_queued_exception {
630 bool pending;
631 bool injected;
632 bool has_error_code;
633 u8 nr;
634 u32 error_code;
635 unsigned long payload;
636 bool has_payload;
637 u8 nested_apf;
638 } exception;
639
640 struct kvm_queued_interrupt {
641 bool injected;
642 bool soft;
643 u8 nr;
644 } interrupt;
645
646 int halt_request; /* real mode on Intel only */
647
648 int cpuid_nent;
649 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES];
650
651 int maxphyaddr;
652
653 /* emulate context */
654
655 struct x86_emulate_ctxt emulate_ctxt;
656 bool emulate_regs_need_sync_to_vcpu;
657 bool emulate_regs_need_sync_from_vcpu;
658 int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
659
660 gpa_t time;
661 struct pvclock_vcpu_time_info hv_clock;
662 unsigned int hw_tsc_khz;
663 struct gfn_to_hva_cache pv_time;
664 bool pv_time_enabled;
665 /* set guest stopped flag in pvclock flags field */
666 bool pvclock_set_guest_stopped_request;
667
668 struct {
669 u64 msr_val;
670 u64 last_steal;
671 struct gfn_to_hva_cache stime;
672 struct kvm_steal_time steal;
673 } st;
674
675 u64 tsc_offset;
676 u64 last_guest_tsc;
677 u64 last_host_tsc;
678 u64 tsc_offset_adjustment;
679 u64 this_tsc_nsec;
680 u64 this_tsc_write;
681 u64 this_tsc_generation;
682 bool tsc_catchup;
683 bool tsc_always_catchup;
684 s8 virtual_tsc_shift;
685 u32 virtual_tsc_mult;
686 u32 virtual_tsc_khz;
687 s64 ia32_tsc_adjust_msr;
688 u64 tsc_scaling_ratio;
689
690 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
691 unsigned nmi_pending; /* NMI queued after currently running handler */
692 bool nmi_injected; /* Trying to inject an NMI this entry */
693 bool smi_pending; /* SMI queued after currently running handler */
694
695 struct kvm_mtrr mtrr_state;
696 u64 pat;
697
698 unsigned switch_db_regs;
699 unsigned long db[KVM_NR_DB_REGS];
700 unsigned long dr6;
701 unsigned long dr7;
702 unsigned long eff_db[KVM_NR_DB_REGS];
703 unsigned long guest_debug_dr7;
704 u64 msr_platform_info;
705 u64 msr_misc_features_enables;
706
707 u64 mcg_cap;
708 u64 mcg_status;
709 u64 mcg_ctl;
710 u64 mcg_ext_ctl;
711 u64 *mce_banks;
712
713 /* Cache MMIO info */
714 u64 mmio_gva;
715 unsigned access;
716 gfn_t mmio_gfn;
717 u64 mmio_gen;
718
719 struct kvm_pmu pmu;
720
721 /* used for guest single stepping over the given code position */
722 unsigned long singlestep_rip;
723
724 struct kvm_vcpu_hv hyperv;
725
726 cpumask_var_t wbinvd_dirty_mask;
727
728 unsigned long last_retry_eip;
729 unsigned long last_retry_addr;
730
731 struct {
732 bool halted;
733 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)];
734 struct gfn_to_hva_cache data;
735 u64 msr_val;
736 u32 id;
737 bool send_user_only;
738 u32 host_apf_reason;
739 unsigned long nested_apf_token;
740 bool delivery_as_pf_vmexit;
741 } apf;
742
743 /* OSVW MSRs (AMD only) */
744 struct {
745 u64 length;
746 u64 status;
747 } osvw;
748
749 struct {
750 u64 msr_val;
751 struct gfn_to_hva_cache data;
752 } pv_eoi;
753
754 /*
755 * Indicate whether the access faults on its page table in guest
756 * which is set when fix page fault and used to detect unhandeable
757 * instruction.
758 */
759 bool write_fault_to_shadow_pgtable;
760
761 /* set at EPT violation at this point */
762 unsigned long exit_qualification;
763
764 /* pv related host specific info */
765 struct {
766 bool pv_unhalted;
767 } pv;
768
769 int pending_ioapic_eoi;
770 int pending_external_vector;
771
772 /* GPA available */
773 bool gpa_available;
774 gpa_t gpa_val;
775
776 /* be preempted when it's in kernel-mode(cpl=0) */
777 bool preempted_in_kernel;
778
779 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */
780 bool l1tf_flush_l1d;
781};
782
783struct kvm_lpage_info {
784 int disallow_lpage;
785};
786
787struct kvm_arch_memory_slot {
788 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
789 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
790 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX];
791};
792
793/*
794 * We use as the mode the number of bits allocated in the LDR for the
795 * logical processor ID. It happens that these are all powers of two.
796 * This makes it is very easy to detect cases where the APICs are
797 * configured for multiple modes; in that case, we cannot use the map and
798 * hence cannot use kvm_irq_delivery_to_apic_fast either.
799 */
800#define KVM_APIC_MODE_XAPIC_CLUSTER 4
801#define KVM_APIC_MODE_XAPIC_FLAT 8
802#define KVM_APIC_MODE_X2APIC 16
803
804struct kvm_apic_map {
805 struct rcu_head rcu;
806 u8 mode;
807 u32 max_apic_id;
808 union {
809 struct kvm_lapic *xapic_flat_map[8];
810 struct kvm_lapic *xapic_cluster_map[16][4];
811 };
812 struct kvm_lapic *phys_map[];
813};
814
815/* Hyper-V emulation context */
816struct kvm_hv {
817 struct mutex hv_lock;
818 u64 hv_guest_os_id;
819 u64 hv_hypercall;
820 u64 hv_tsc_page;
821
822 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */
823 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS];
824 u64 hv_crash_ctl;
825
826 HV_REFERENCE_TSC_PAGE tsc_ref;
827
828 struct idr conn_to_evt;
829
830 u64 hv_reenlightenment_control;
831 u64 hv_tsc_emulation_control;
832 u64 hv_tsc_emulation_status;
833
834 /* How many vCPUs have VP index != vCPU index */
835 atomic_t num_mismatched_vp_indexes;
836};
837
838enum kvm_irqchip_mode {
839 KVM_IRQCHIP_NONE,
840 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */
841 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */
842};
843
844struct kvm_arch {
845 unsigned int n_used_mmu_pages;
846 unsigned int n_requested_mmu_pages;
847 unsigned int n_max_mmu_pages;
848 unsigned int indirect_shadow_pages;
849 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
850 /*
851 * Hash table of struct kvm_mmu_page.
852 */
853 struct list_head active_mmu_pages;
854 struct kvm_page_track_notifier_node mmu_sp_tracker;
855 struct kvm_page_track_notifier_head track_notifier_head;
856
857 struct list_head assigned_dev_head;
858 struct iommu_domain *iommu_domain;
859 bool iommu_noncoherent;
860#define __KVM_HAVE_ARCH_NONCOHERENT_DMA
861 atomic_t noncoherent_dma_count;
862#define __KVM_HAVE_ARCH_ASSIGNED_DEVICE
863 atomic_t assigned_device_count;
864 struct kvm_pic *vpic;
865 struct kvm_ioapic *vioapic;
866 struct kvm_pit *vpit;
867 atomic_t vapics_in_nmi_mode;
868 struct mutex apic_map_lock;
869 struct kvm_apic_map *apic_map;
870
871 bool apic_access_page_done;
872
873 gpa_t wall_clock;
874
875 bool mwait_in_guest;
876 bool hlt_in_guest;
877 bool pause_in_guest;
878
879 unsigned long irq_sources_bitmap;
880 s64 kvmclock_offset;
881 raw_spinlock_t tsc_write_lock;
882 u64 last_tsc_nsec;
883 u64 last_tsc_write;
884 u32 last_tsc_khz;
885 u64 cur_tsc_nsec;
886 u64 cur_tsc_write;
887 u64 cur_tsc_offset;
888 u64 cur_tsc_generation;
889 int nr_vcpus_matched_tsc;
890
891 spinlock_t pvclock_gtod_sync_lock;
892 bool use_master_clock;
893 u64 master_kernel_ns;
894 u64 master_cycle_now;
895 struct delayed_work kvmclock_update_work;
896 struct delayed_work kvmclock_sync_work;
897
898 struct kvm_xen_hvm_config xen_hvm_config;
899
900 /* reads protected by irq_srcu, writes by irq_lock */
901 struct hlist_head mask_notifier_list;
902
903 struct kvm_hv hyperv;
904
905 #ifdef CONFIG_KVM_MMU_AUDIT
906 int audit_point;
907 #endif
908
909 bool backwards_tsc_observed;
910 bool boot_vcpu_runs_old_kvmclock;
911 u32 bsp_vcpu_id;
912
913 u64 disabled_quirks;
914
915 enum kvm_irqchip_mode irqchip_mode;
916 u8 nr_reserved_ioapic_pins;
917
918 bool disabled_lapic_found;
919
920 bool x2apic_format;
921 bool x2apic_broadcast_quirk_disabled;
922
923 bool guest_can_read_msr_platform_info;
924 bool exception_payload_enabled;
925};
926
927struct kvm_vm_stat {
928 ulong mmu_shadow_zapped;
929 ulong mmu_pte_write;
930 ulong mmu_pte_updated;
931 ulong mmu_pde_zapped;
932 ulong mmu_flooded;
933 ulong mmu_recycled;
934 ulong mmu_cache_miss;
935 ulong mmu_unsync;
936 ulong remote_tlb_flush;
937 ulong lpages;
938 ulong max_mmu_page_hash_collisions;
939};
940
941struct kvm_vcpu_stat {
942 u64 pf_fixed;
943 u64 pf_guest;
944 u64 tlb_flush;
945 u64 invlpg;
946
947 u64 exits;
948 u64 io_exits;
949 u64 mmio_exits;
950 u64 signal_exits;
951 u64 irq_window_exits;
952 u64 nmi_window_exits;
953 u64 l1d_flush;
954 u64 halt_exits;
955 u64 halt_successful_poll;
956 u64 halt_attempted_poll;
957 u64 halt_poll_invalid;
958 u64 halt_wakeup;
959 u64 request_irq_exits;
960 u64 irq_exits;
961 u64 host_state_reload;
962 u64 fpu_reload;
963 u64 insn_emulation;
964 u64 insn_emulation_fail;
965 u64 hypercalls;
966 u64 irq_injections;
967 u64 nmi_injections;
968 u64 req_event;
969};
970
971struct x86_instruction_info;
972
973struct msr_data {
974 bool host_initiated;
975 u32 index;
976 u64 data;
977};
978
979struct kvm_lapic_irq {
980 u32 vector;
981 u16 delivery_mode;
982 u16 dest_mode;
983 bool level;
984 u16 trig_mode;
985 u32 shorthand;
986 u32 dest_id;
987 bool msi_redir_hint;
988};
989
990struct kvm_x86_ops {
991 int (*cpu_has_kvm_support)(void); /* __init */
992 int (*disabled_by_bios)(void); /* __init */
993 int (*hardware_enable)(void);
994 void (*hardware_disable)(void);
995 void (*check_processor_compatibility)(void *rtn);
996 int (*hardware_setup)(void); /* __init */
997 void (*hardware_unsetup)(void); /* __exit */
998 bool (*cpu_has_accelerated_tpr)(void);
999 bool (*has_emulated_msr)(int index);
1000 void (*cpuid_update)(struct kvm_vcpu *vcpu);
1001
1002 struct kvm *(*vm_alloc)(void);
1003 void (*vm_free)(struct kvm *);
1004 int (*vm_init)(struct kvm *kvm);
1005 void (*vm_destroy)(struct kvm *kvm);
1006
1007 /* Create, but do not attach this VCPU */
1008 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
1009 void (*vcpu_free)(struct kvm_vcpu *vcpu);
1010 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
1011
1012 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
1013 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
1014 void (*vcpu_put)(struct kvm_vcpu *vcpu);
1015
1016 void (*update_bp_intercept)(struct kvm_vcpu *vcpu);
1017 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1018 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1019 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
1020 void (*get_segment)(struct kvm_vcpu *vcpu,
1021 struct kvm_segment *var, int seg);
1022 int (*get_cpl)(struct kvm_vcpu *vcpu);
1023 void (*set_segment)(struct kvm_vcpu *vcpu,
1024 struct kvm_segment *var, int seg);
1025 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
1026 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu);
1027 void (*decache_cr3)(struct kvm_vcpu *vcpu);
1028 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
1029 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
1030 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
1031 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
1032 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
1033 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1034 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1035 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1036 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1037 u64 (*get_dr6)(struct kvm_vcpu *vcpu);
1038 void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value);
1039 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
1040 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
1041 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
1042 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
1043 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
1044
1045 void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa);
1046 int (*tlb_remote_flush)(struct kvm *kvm);
1047 int (*tlb_remote_flush_with_range)(struct kvm *kvm,
1048 struct kvm_tlb_range *range);
1049
1050 /*
1051 * Flush any TLB entries associated with the given GVA.
1052 * Does not need to flush GPA->HPA mappings.
1053 * Can potentially get non-canonical addresses through INVLPGs, which
1054 * the implementation may choose to ignore if appropriate.
1055 */
1056 void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr);
1057
1058 void (*run)(struct kvm_vcpu *vcpu);
1059 int (*handle_exit)(struct kvm_vcpu *vcpu);
1060 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
1061 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
1062 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
1063 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
1064 unsigned char *hypercall_addr);
1065 void (*set_irq)(struct kvm_vcpu *vcpu);
1066 void (*set_nmi)(struct kvm_vcpu *vcpu);
1067 void (*queue_exception)(struct kvm_vcpu *vcpu);
1068 void (*cancel_injection)(struct kvm_vcpu *vcpu);
1069 int (*interrupt_allowed)(struct kvm_vcpu *vcpu);
1070 int (*nmi_allowed)(struct kvm_vcpu *vcpu);
1071 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
1072 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
1073 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
1074 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
1075 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
1076 bool (*get_enable_apicv)(struct kvm_vcpu *vcpu);
1077 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
1078 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
1079 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr);
1080 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu);
1081 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
1082 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
1083 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa);
1084 void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
1085 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
1086 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
1087 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);
1088 int (*get_tdp_level)(struct kvm_vcpu *vcpu);
1089 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
1090 int (*get_lpage_level)(void);
1091 bool (*rdtscp_supported)(void);
1092 bool (*invpcid_supported)(void);
1093
1094 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
1095
1096 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry);
1097
1098 bool (*has_wbinvd_exit)(void);
1099
1100 u64 (*read_l1_tsc_offset)(struct kvm_vcpu *vcpu);
1101 /* Returns actual tsc_offset set in active VMCS */
1102 u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
1103
1104 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2);
1105
1106 int (*check_intercept)(struct kvm_vcpu *vcpu,
1107 struct x86_instruction_info *info,
1108 enum x86_intercept_stage stage);
1109 void (*handle_external_intr)(struct kvm_vcpu *vcpu);
1110 bool (*mpx_supported)(void);
1111 bool (*xsaves_supported)(void);
1112 bool (*umip_emulated)(void);
1113 bool (*pt_supported)(void);
1114
1115 int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr);
1116 void (*request_immediate_exit)(struct kvm_vcpu *vcpu);
1117
1118 void (*sched_in)(struct kvm_vcpu *kvm, int cpu);
1119
1120 /*
1121 * Arch-specific dirty logging hooks. These hooks are only supposed to
1122 * be valid if the specific arch has hardware-accelerated dirty logging
1123 * mechanism. Currently only for PML on VMX.
1124 *
1125 * - slot_enable_log_dirty:
1126 * called when enabling log dirty mode for the slot.
1127 * - slot_disable_log_dirty:
1128 * called when disabling log dirty mode for the slot.
1129 * also called when slot is created with log dirty disabled.
1130 * - flush_log_dirty:
1131 * called before reporting dirty_bitmap to userspace.
1132 * - enable_log_dirty_pt_masked:
1133 * called when reenabling log dirty for the GFNs in the mask after
1134 * corresponding bits are cleared in slot->dirty_bitmap.
1135 */
1136 void (*slot_enable_log_dirty)(struct kvm *kvm,
1137 struct kvm_memory_slot *slot);
1138 void (*slot_disable_log_dirty)(struct kvm *kvm,
1139 struct kvm_memory_slot *slot);
1140 void (*flush_log_dirty)(struct kvm *kvm);
1141 void (*enable_log_dirty_pt_masked)(struct kvm *kvm,
1142 struct kvm_memory_slot *slot,
1143 gfn_t offset, unsigned long mask);
1144 int (*write_log_dirty)(struct kvm_vcpu *vcpu);
1145
1146 /* pmu operations of sub-arch */
1147 const struct kvm_pmu_ops *pmu_ops;
1148
1149 /*
1150 * Architecture specific hooks for vCPU blocking due to
1151 * HLT instruction.
1152 * Returns for .pre_block():
1153 * - 0 means continue to block the vCPU.
1154 * - 1 means we cannot block the vCPU since some event
1155 * happens during this period, such as, 'ON' bit in
1156 * posted-interrupts descriptor is set.
1157 */
1158 int (*pre_block)(struct kvm_vcpu *vcpu);
1159 void (*post_block)(struct kvm_vcpu *vcpu);
1160
1161 void (*vcpu_blocking)(struct kvm_vcpu *vcpu);
1162 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu);
1163
1164 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq,
1165 uint32_t guest_irq, bool set);
1166 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu);
1167
1168 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc);
1169 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu);
1170
1171 void (*setup_mce)(struct kvm_vcpu *vcpu);
1172
1173 int (*get_nested_state)(struct kvm_vcpu *vcpu,
1174 struct kvm_nested_state __user *user_kvm_nested_state,
1175 unsigned user_data_size);
1176 int (*set_nested_state)(struct kvm_vcpu *vcpu,
1177 struct kvm_nested_state __user *user_kvm_nested_state,
1178 struct kvm_nested_state *kvm_state);
1179 void (*get_vmcs12_pages)(struct kvm_vcpu *vcpu);
1180
1181 int (*smi_allowed)(struct kvm_vcpu *vcpu);
1182 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate);
1183 int (*pre_leave_smm)(struct kvm_vcpu *vcpu, u64 smbase);
1184 int (*enable_smi_window)(struct kvm_vcpu *vcpu);
1185
1186 int (*mem_enc_op)(struct kvm *kvm, void __user *argp);
1187 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1188 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1189
1190 int (*get_msr_feature)(struct kvm_msr_entry *entry);
1191
1192 int (*nested_enable_evmcs)(struct kvm_vcpu *vcpu,
1193 uint16_t *vmcs_version);
1194 uint16_t (*nested_get_evmcs_version)(struct kvm_vcpu *vcpu);
1195};
1196
1197struct kvm_arch_async_pf {
1198 u32 token;
1199 gfn_t gfn;
1200 unsigned long cr3;
1201 bool direct_map;
1202};
1203
1204extern struct kvm_x86_ops *kvm_x86_ops;
1205extern struct kmem_cache *x86_fpu_cache;
1206
1207#define __KVM_HAVE_ARCH_VM_ALLOC
1208static inline struct kvm *kvm_arch_alloc_vm(void)
1209{
1210 return kvm_x86_ops->vm_alloc();
1211}
1212
1213static inline void kvm_arch_free_vm(struct kvm *kvm)
1214{
1215 return kvm_x86_ops->vm_free(kvm);
1216}
1217
1218#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB
1219static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm)
1220{
1221 if (kvm_x86_ops->tlb_remote_flush &&
1222 !kvm_x86_ops->tlb_remote_flush(kvm))
1223 return 0;
1224 else
1225 return -ENOTSUPP;
1226}
1227
1228int kvm_mmu_module_init(void);
1229void kvm_mmu_module_exit(void);
1230
1231void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
1232int kvm_mmu_create(struct kvm_vcpu *vcpu);
1233void kvm_mmu_init_vm(struct kvm *kvm);
1234void kvm_mmu_uninit_vm(struct kvm *kvm);
1235void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
1236 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
1237 u64 acc_track_mask, u64 me_mask);
1238
1239void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
1240void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
1241 struct kvm_memory_slot *memslot);
1242void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
1243 const struct kvm_memory_slot *memslot);
1244void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
1245 struct kvm_memory_slot *memslot);
1246void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
1247 struct kvm_memory_slot *memslot);
1248void kvm_mmu_slot_set_dirty(struct kvm *kvm,
1249 struct kvm_memory_slot *memslot);
1250void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1251 struct kvm_memory_slot *slot,
1252 gfn_t gfn_offset, unsigned long mask);
1253void kvm_mmu_zap_all(struct kvm *kvm);
1254void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
1255unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
1256void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
1257
1258int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
1259bool pdptrs_changed(struct kvm_vcpu *vcpu);
1260
1261int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
1262 const void *val, int bytes);
1263
1264struct kvm_irq_mask_notifier {
1265 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked);
1266 int irq;
1267 struct hlist_node link;
1268};
1269
1270void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
1271 struct kvm_irq_mask_notifier *kimn);
1272void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
1273 struct kvm_irq_mask_notifier *kimn);
1274void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
1275 bool mask);
1276
1277extern bool tdp_enabled;
1278
1279u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
1280
1281/* control of guest tsc rate supported? */
1282extern bool kvm_has_tsc_control;
1283/* maximum supported tsc_khz for guests */
1284extern u32 kvm_max_guest_tsc_khz;
1285/* number of bits of the fractional part of the TSC scaling ratio */
1286extern u8 kvm_tsc_scaling_ratio_frac_bits;
1287/* maximum allowed value of TSC scaling ratio */
1288extern u64 kvm_max_tsc_scaling_ratio;
1289/* 1ull << kvm_tsc_scaling_ratio_frac_bits */
1290extern u64 kvm_default_tsc_scaling_ratio;
1291
1292extern u64 kvm_mce_cap_supported;
1293
1294enum emulation_result {
1295 EMULATE_DONE, /* no further processing */
1296 EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */
1297 EMULATE_FAIL, /* can't emulate this instruction */
1298};
1299
1300#define EMULTYPE_NO_DECODE (1 << 0)
1301#define EMULTYPE_TRAP_UD (1 << 1)
1302#define EMULTYPE_SKIP (1 << 2)
1303#define EMULTYPE_ALLOW_RETRY (1 << 3)
1304#define EMULTYPE_NO_UD_ON_FAIL (1 << 4)
1305#define EMULTYPE_VMWARE (1 << 5)
1306int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type);
1307int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
1308 void *insn, int insn_len);
1309
1310void kvm_enable_efer_bits(u64);
1311bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
1312int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr);
1313int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr);
1314
1315struct x86_emulate_ctxt;
1316
1317int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in);
1318int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
1319int kvm_emulate_halt(struct kvm_vcpu *vcpu);
1320int kvm_vcpu_halt(struct kvm_vcpu *vcpu);
1321int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
1322
1323void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
1324int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
1325void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
1326
1327int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
1328 int reason, bool has_error_code, u32 error_code);
1329
1330int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
1331int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
1332int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1333int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
1334int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
1335int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
1336unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
1337void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
1338void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
1339int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr);
1340
1341int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1342int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1343
1344unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
1345void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
1346bool kvm_rdpmc(struct kvm_vcpu *vcpu);
1347
1348void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1349void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1350void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1351void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1352void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
1353int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
1354 gfn_t gfn, void *data, int offset, int len,
1355 u32 access);
1356bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
1357bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
1358
1359static inline int __kvm_irq_line_state(unsigned long *irq_state,
1360 int irq_source_id, int level)
1361{
1362 /* Logical OR for level trig interrupt */
1363 if (level)
1364 __set_bit(irq_source_id, irq_state);
1365 else
1366 __clear_bit(irq_source_id, irq_state);
1367
1368 return !!(*irq_state);
1369}
1370
1371#define KVM_MMU_ROOT_CURRENT BIT(0)
1372#define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i)
1373#define KVM_MMU_ROOTS_ALL (~0UL)
1374
1375int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
1376void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
1377
1378void kvm_inject_nmi(struct kvm_vcpu *vcpu);
1379
1380int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
1381int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
1382void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
1383int kvm_mmu_load(struct kvm_vcpu *vcpu);
1384void kvm_mmu_unload(struct kvm_vcpu *vcpu);
1385void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
1386void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
1387 ulong roots_to_free);
1388gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
1389 struct x86_exception *exception);
1390gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
1391 struct x86_exception *exception);
1392gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
1393 struct x86_exception *exception);
1394gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
1395 struct x86_exception *exception);
1396gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
1397 struct x86_exception *exception);
1398
1399void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu);
1400
1401int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
1402
1403int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code,
1404 void *insn, int insn_len);
1405void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
1406void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid);
1407void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush);
1408
1409void kvm_enable_tdp(void);
1410void kvm_disable_tdp(void);
1411
1412static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
1413 struct x86_exception *exception)
1414{
1415 return gpa;
1416}
1417
1418static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
1419{
1420 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
1421
1422 return (struct kvm_mmu_page *)page_private(page);
1423}
1424
1425static inline u16 kvm_read_ldt(void)
1426{
1427 u16 ldt;
1428 asm("sldt %0" : "=g"(ldt));
1429 return ldt;
1430}
1431
1432static inline void kvm_load_ldt(u16 sel)
1433{
1434 asm("lldt %0" : : "rm"(sel));
1435}
1436
1437#ifdef CONFIG_X86_64
1438static inline unsigned long read_msr(unsigned long msr)
1439{
1440 u64 value;
1441
1442 rdmsrl(msr, value);
1443 return value;
1444}
1445#endif
1446
1447static inline u32 get_rdx_init_val(void)
1448{
1449 return 0x600; /* P6 family */
1450}
1451
1452static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
1453{
1454 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1455}
1456
1457#define TSS_IOPB_BASE_OFFSET 0x66
1458#define TSS_BASE_SIZE 0x68
1459#define TSS_IOPB_SIZE (65536 / 8)
1460#define TSS_REDIRECTION_SIZE (256 / 8)
1461#define RMODE_TSS_SIZE \
1462 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
1463
1464enum {
1465 TASK_SWITCH_CALL = 0,
1466 TASK_SWITCH_IRET = 1,
1467 TASK_SWITCH_JMP = 2,
1468 TASK_SWITCH_GATE = 3,
1469};
1470
1471#define HF_GIF_MASK (1 << 0)
1472#define HF_HIF_MASK (1 << 1)
1473#define HF_VINTR_MASK (1 << 2)
1474#define HF_NMI_MASK (1 << 3)
1475#define HF_IRET_MASK (1 << 4)
1476#define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
1477#define HF_SMM_MASK (1 << 6)
1478#define HF_SMM_INSIDE_NMI_MASK (1 << 7)
1479
1480#define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE
1481#define KVM_ADDRESS_SPACE_NUM 2
1482
1483#define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0)
1484#define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm)
1485
1486/*
1487 * Hardware virtualization extension instructions may fault if a
1488 * reboot turns off virtualization while processes are running.
1489 * Trap the fault and ignore the instruction if that happens.
1490 */
1491asmlinkage void kvm_spurious_fault(void);
1492
1493#define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \
1494 "666: " insn "\n\t" \
1495 "668: \n\t" \
1496 ".pushsection .fixup, \"ax\" \n" \
1497 "667: \n\t" \
1498 cleanup_insn "\n\t" \
1499 "cmpb $0, kvm_rebooting \n\t" \
1500 "jne 668b \n\t" \
1501 __ASM_SIZE(push) " $666b \n\t" \
1502 "jmp kvm_spurious_fault \n\t" \
1503 ".popsection \n\t" \
1504 _ASM_EXTABLE(666b, 667b)
1505
1506#define __kvm_handle_fault_on_reboot(insn) \
1507 ____kvm_handle_fault_on_reboot(insn, "")
1508
1509#define KVM_ARCH_WANT_MMU_NOTIFIER
1510int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end);
1511int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
1512int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
1513int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
1514int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
1515int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
1516int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
1517int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
1518void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
1519void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu);
1520
1521int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
1522 unsigned long ipi_bitmap_high, u32 min,
1523 unsigned long icr, int op_64_bit);
1524
1525u64 kvm_get_arch_capabilities(void);
1526void kvm_define_shared_msr(unsigned index, u32 msr);
1527int kvm_set_shared_msr(unsigned index, u64 val, u64 mask);
1528
1529u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc);
1530u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
1531
1532unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu);
1533bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
1534
1535void kvm_make_mclock_inprogress_request(struct kvm *kvm);
1536void kvm_make_scan_ioapic_request(struct kvm *kvm);
1537
1538void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
1539 struct kvm_async_pf *work);
1540void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
1541 struct kvm_async_pf *work);
1542void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
1543 struct kvm_async_pf *work);
1544bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu);
1545extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
1546
1547int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
1548int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
1549void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu);
1550
1551int kvm_is_in_guest(void);
1552
1553int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size);
1554int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size);
1555bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu);
1556bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu);
1557
1558bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
1559 struct kvm_vcpu **dest_vcpu);
1560
1561void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
1562 struct kvm_lapic_irq *irq);
1563
1564static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
1565{
1566 if (kvm_x86_ops->vcpu_blocking)
1567 kvm_x86_ops->vcpu_blocking(vcpu);
1568}
1569
1570static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
1571{
1572 if (kvm_x86_ops->vcpu_unblocking)
1573 kvm_x86_ops->vcpu_unblocking(vcpu);
1574}
1575
1576static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1577
1578static inline int kvm_cpu_get_apicid(int mps_cpu)
1579{
1580#ifdef CONFIG_X86_LOCAL_APIC
1581 return default_cpu_present_to_apicid(mps_cpu);
1582#else
1583 WARN_ON_ONCE(1);
1584 return BAD_APICID;
1585#endif
1586}
1587
1588#define put_smstate(type, buf, offset, val) \
1589 *(type *)((buf) + (offset) - 0x7e00) = val
1590
1591#endif /* _ASM_X86_KVM_HOST_H */
1592