1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_10_1_0_offset.h"
34#include "gc/gc_10_1_0_sh_mask.h"
35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37
38#include "soc15_common.h"
39#include "soc15.h"
40#include "navi10_sdma_pkt_open.h"
41#include "nbio_v2_3.h"
42#include "sdma_common.h"
43#include "sdma_v5_0.h"
44
45MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
47
48MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
50
51MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
53
54MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
55MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
56
57#define SDMA1_REG_OFFSET 0x600
58#define SDMA0_HYP_DEC_REG_START 0x5880
59#define SDMA0_HYP_DEC_REG_END 0x5893
60#define SDMA1_HYP_DEC_REG_OFFSET 0x20
61
62static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
63static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
64static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
65static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
66
67static const struct soc15_reg_golden golden_settings_sdma_5[] = {
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
92};
93
94static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
115};
116
117static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
120};
121
122static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
125};
126
127static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
134};
135
136static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
165};
166
167static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
168{
169 u32 base;
170
171 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
172 internal_offset <= SDMA0_HYP_DEC_REG_END) {
173 base = adev->reg_offset[GC_HWIP][0][1];
174 if (instance == 1)
175 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
176 } else {
177 base = adev->reg_offset[GC_HWIP][0][0];
178 if (instance == 1)
179 internal_offset += SDMA1_REG_OFFSET;
180 }
181
182 return base + internal_offset;
183}
184
185static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
186{
187 switch (amdgpu_ip_version(adev, ip: SDMA0_HWIP, inst: 0)) {
188 case IP_VERSION(5, 0, 0):
189 soc15_program_register_sequence(adev,
190 registers: golden_settings_sdma_5,
191 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5));
192 soc15_program_register_sequence(adev,
193 registers: golden_settings_sdma_nv10,
194 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
195 break;
196 case IP_VERSION(5, 0, 2):
197 soc15_program_register_sequence(adev,
198 registers: golden_settings_sdma_5,
199 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5));
200 soc15_program_register_sequence(adev,
201 registers: golden_settings_sdma_nv14,
202 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
203 break;
204 case IP_VERSION(5, 0, 5):
205 if (amdgpu_sriov_vf(adev))
206 soc15_program_register_sequence(adev,
207 registers: golden_settings_sdma_5_sriov,
208 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
209 else
210 soc15_program_register_sequence(adev,
211 registers: golden_settings_sdma_5,
212 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5));
213 soc15_program_register_sequence(adev,
214 registers: golden_settings_sdma_nv12,
215 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
216 break;
217 case IP_VERSION(5, 0, 1):
218 soc15_program_register_sequence(adev,
219 registers: golden_settings_sdma_cyan_skillfish,
220 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
221 break;
222 default:
223 break;
224 }
225}
226
227/**
228 * sdma_v5_0_init_microcode - load ucode images from disk
229 *
230 * @adev: amdgpu_device pointer
231 *
232 * Use the firmware interface to load the ucode images into
233 * the driver (not loaded into hw).
234 * Returns 0 on success, error on failure.
235 */
236
237// emulation only, won't work on real chip
238// navi10 real chip need to use PSP to load firmware
239static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
240{
241 int ret, i;
242
243 for (i = 0; i < adev->sdma.num_instances; i++) {
244 ret = amdgpu_sdma_init_microcode(adev, instance: i, duplicate: false);
245 if (ret)
246 return ret;
247 }
248
249 return ret;
250}
251
252static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring,
253 uint64_t addr)
254{
255 unsigned ret;
256
257 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
258 amdgpu_ring_write(ring, lower_32_bits(addr));
259 amdgpu_ring_write(ring, upper_32_bits(addr));
260 amdgpu_ring_write(ring, v: 1);
261 /* this is the offset we need patch later */
262 ret = ring->wptr & ring->buf_mask;
263 /* insert dummy here and patch it later */
264 amdgpu_ring_write(ring, v: 0);
265
266 return ret;
267}
268
269/**
270 * sdma_v5_0_ring_get_rptr - get the current read pointer
271 *
272 * @ring: amdgpu ring pointer
273 *
274 * Get the current rptr from the hardware (NAVI10+).
275 */
276static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
277{
278 u64 *rptr;
279
280 /* XXX check if swapping is necessary on BE */
281 rptr = (u64 *)ring->rptr_cpu_addr;
282
283 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
284 return ((*rptr) >> 2);
285}
286
287/**
288 * sdma_v5_0_ring_get_wptr - get the current write pointer
289 *
290 * @ring: amdgpu ring pointer
291 *
292 * Get the current wptr from the hardware (NAVI10+).
293 */
294static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
295{
296 struct amdgpu_device *adev = ring->adev;
297 u64 wptr;
298
299 if (ring->use_doorbell) {
300 /* XXX check if swapping is necessary on BE */
301 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
302 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
303 } else {
304 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
305 wptr = wptr << 32;
306 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
307 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
308 }
309
310 return wptr >> 2;
311}
312
313/**
314 * sdma_v5_0_ring_set_wptr - commit the write pointer
315 *
316 * @ring: amdgpu ring pointer
317 *
318 * Write the wptr back to the hardware (NAVI10+).
319 */
320static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
321{
322 struct amdgpu_device *adev = ring->adev;
323 uint32_t *wptr_saved;
324 uint32_t *is_queue_unmap;
325 uint64_t aggregated_db_index;
326 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
327
328 DRM_DEBUG("Setting write pointer\n");
329 if (ring->is_mes_queue) {
330 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
331 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
332 sizeof(uint32_t));
333 aggregated_db_index =
334 amdgpu_mes_get_aggregated_doorbell_index(adev,
335 prio: AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
336
337 atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr,
338 i: ring->wptr << 2);
339 *wptr_saved = ring->wptr << 2;
340 if (*is_queue_unmap) {
341 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
342 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
343 ring->doorbell_index, ring->wptr << 2);
344 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
345 } else {
346 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
347 ring->doorbell_index, ring->wptr << 2);
348 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
349
350 if (*is_queue_unmap)
351 WDOORBELL64(aggregated_db_index,
352 ring->wptr << 2);
353 }
354 } else {
355 if (ring->use_doorbell) {
356 DRM_DEBUG("Using doorbell -- "
357 "wptr_offs == 0x%08x "
358 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
359 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
360 ring->wptr_offs,
361 lower_32_bits(ring->wptr << 2),
362 upper_32_bits(ring->wptr << 2));
363 /* XXX check if swapping is necessary on BE */
364 atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr,
365 i: ring->wptr << 2);
366 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
367 ring->doorbell_index, ring->wptr << 2);
368 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
369 } else {
370 DRM_DEBUG("Not using doorbell -- "
371 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
372 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
373 ring->me,
374 lower_32_bits(ring->wptr << 2),
375 ring->me,
376 upper_32_bits(ring->wptr << 2));
377 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
378 ring->me, mmSDMA0_GFX_RB_WPTR),
379 lower_32_bits(ring->wptr << 2));
380 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
381 ring->me, mmSDMA0_GFX_RB_WPTR_HI),
382 upper_32_bits(ring->wptr << 2));
383 }
384 }
385}
386
387static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
388{
389 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
390 int i;
391
392 for (i = 0; i < count; i++)
393 if (sdma && sdma->burst_nop && (i == 0))
394 amdgpu_ring_write(ring, v: ring->funcs->nop |
395 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
396 else
397 amdgpu_ring_write(ring, v: ring->funcs->nop);
398}
399
400/**
401 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
402 *
403 * @ring: amdgpu ring pointer
404 * @job: job to retrieve vmid from
405 * @ib: IB object to schedule
406 * @flags: unused
407 *
408 * Schedule an IB in the DMA ring (NAVI10).
409 */
410static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
411 struct amdgpu_job *job,
412 struct amdgpu_ib *ib,
413 uint32_t flags)
414{
415 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
416 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
417
418 /* An IB packet must end on a 8 DW boundary--the next dword
419 * must be on a 8-dword boundary. Our IB packet below is 6
420 * dwords long, thus add x number of NOPs, such that, in
421 * modular arithmetic,
422 * wptr + 6 + x = 8k, k >= 0, which in C is,
423 * (wptr + 6 + x) % 8 = 0.
424 * The expression below, is a solution of x.
425 */
426 sdma_v5_0_ring_insert_nop(ring, count: (2 - lower_32_bits(ring->wptr)) & 7);
427
428 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
429 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
430 /* base must be 32 byte aligned */
431 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
432 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
433 amdgpu_ring_write(ring, v: ib->length_dw);
434 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
435 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
436}
437
438/**
439 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
440 *
441 * @ring: amdgpu ring pointer
442 *
443 * flush the IB by graphics cache rinse.
444 */
445static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
446{
447 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
448 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
449 SDMA_GCR_GLI_INV(1);
450
451 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
452 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
453 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
454 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
455 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
456 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
457 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
458 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
459 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
460}
461
462/**
463 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
464 *
465 * @ring: amdgpu ring pointer
466 *
467 * Emit an hdp flush packet on the requested DMA ring.
468 */
469static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
470{
471 struct amdgpu_device *adev = ring->adev;
472 u32 ref_and_mask = 0;
473 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
474
475 if (ring->me == 0)
476 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
477 else
478 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
479
480 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
481 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
482 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
483 amdgpu_ring_write(ring, v: (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
484 amdgpu_ring_write(ring, v: (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
485 amdgpu_ring_write(ring, v: ref_and_mask); /* reference */
486 amdgpu_ring_write(ring, v: ref_and_mask); /* mask */
487 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
488 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
489}
490
491/**
492 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
493 *
494 * @ring: amdgpu ring pointer
495 * @addr: address
496 * @seq: sequence number
497 * @flags: fence related flags
498 *
499 * Add a DMA fence packet to the ring to write
500 * the fence seq number and DMA trap packet to generate
501 * an interrupt if needed (NAVI10).
502 */
503static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
504 unsigned flags)
505{
506 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
507 /* write the fence */
508 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
509 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
510 /* zero in first two bits */
511 BUG_ON(addr & 0x3);
512 amdgpu_ring_write(ring, lower_32_bits(addr));
513 amdgpu_ring_write(ring, upper_32_bits(addr));
514 amdgpu_ring_write(ring, lower_32_bits(seq));
515
516 /* optionally write high bits as well */
517 if (write64bit) {
518 addr += 4;
519 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
520 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
521 /* zero in first two bits */
522 BUG_ON(addr & 0x3);
523 amdgpu_ring_write(ring, lower_32_bits(addr));
524 amdgpu_ring_write(ring, upper_32_bits(addr));
525 amdgpu_ring_write(ring, upper_32_bits(seq));
526 }
527
528 if (flags & AMDGPU_FENCE_FLAG_INT) {
529 uint32_t ctx = ring->is_mes_queue ?
530 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
531 /* generate an interrupt */
532 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
533 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
534 }
535}
536
537
538/**
539 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
540 *
541 * @adev: amdgpu_device pointer
542 *
543 * Stop the gfx async dma ring buffers (NAVI10).
544 */
545static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
546{
547 u32 rb_cntl, ib_cntl;
548 int i;
549
550 for (i = 0; i < adev->sdma.num_instances; i++) {
551 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
552 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
553 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
554 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
555 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
556 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
557 }
558}
559
560/**
561 * sdma_v5_0_rlc_stop - stop the compute async dma engines
562 *
563 * @adev: amdgpu_device pointer
564 *
565 * Stop the compute async dma queues (NAVI10).
566 */
567static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
568{
569 /* XXX todo */
570}
571
572/**
573 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
574 *
575 * @adev: amdgpu_device pointer
576 * @enable: enable/disable the DMA MEs context switch.
577 *
578 * Halt or unhalt the async dma engines context switch (NAVI10).
579 */
580static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
581{
582 u32 f32_cntl = 0, phase_quantum = 0;
583 int i;
584
585 if (amdgpu_sdma_phase_quantum) {
586 unsigned value = amdgpu_sdma_phase_quantum;
587 unsigned unit = 0;
588
589 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
590 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
591 value = (value + 1) >> 1;
592 unit++;
593 }
594 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
595 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
596 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
597 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
598 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
599 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
600 WARN_ONCE(1,
601 "clamping sdma_phase_quantum to %uK clock cycles\n",
602 value << unit);
603 }
604 phase_quantum =
605 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
606 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
607 }
608
609 for (i = 0; i < adev->sdma.num_instances; i++) {
610 if (!amdgpu_sriov_vf(adev)) {
611 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
612 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
613 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
614 }
615
616 if (enable && amdgpu_sdma_phase_quantum) {
617 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
618 phase_quantum);
619 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
620 phase_quantum);
621 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
622 phase_quantum);
623 }
624 if (!amdgpu_sriov_vf(adev))
625 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
626 }
627
628}
629
630/**
631 * sdma_v5_0_enable - stop the async dma engines
632 *
633 * @adev: amdgpu_device pointer
634 * @enable: enable/disable the DMA MEs.
635 *
636 * Halt or unhalt the async dma engines (NAVI10).
637 */
638static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
639{
640 u32 f32_cntl;
641 int i;
642
643 if (!enable) {
644 sdma_v5_0_gfx_stop(adev);
645 sdma_v5_0_rlc_stop(adev);
646 }
647
648 if (amdgpu_sriov_vf(adev))
649 return;
650
651 for (i = 0; i < adev->sdma.num_instances; i++) {
652 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
653 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
654 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
655 }
656}
657
658/**
659 * sdma_v5_0_gfx_resume - setup and start the async dma engines
660 *
661 * @adev: amdgpu_device pointer
662 *
663 * Set up the gfx DMA ring buffers and enable them (NAVI10).
664 * Returns 0 for success, error for failure.
665 */
666static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
667{
668 struct amdgpu_ring *ring;
669 u32 rb_cntl, ib_cntl;
670 u32 rb_bufsz;
671 u32 doorbell;
672 u32 doorbell_offset;
673 u32 temp;
674 u32 wptr_poll_cntl;
675 u64 wptr_gpu_addr;
676 int i, r;
677
678 for (i = 0; i < adev->sdma.num_instances; i++) {
679 ring = &adev->sdma.instance[i].ring;
680
681 if (!amdgpu_sriov_vf(adev))
682 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
683
684 /* Set ring buffer size in dwords */
685 rb_bufsz = order_base_2(ring->ring_size / 4);
686 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
687 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
688#ifdef __BIG_ENDIAN
689 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
690 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
691 RPTR_WRITEBACK_SWAP_ENABLE, 1);
692#endif
693 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
694
695 /* Initialize the ring buffer's read and write pointers */
696 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
697 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
698 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
699 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
700
701 /* setup the wptr shadow polling */
702 wptr_gpu_addr = ring->wptr_gpu_addr;
703 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
704 lower_32_bits(wptr_gpu_addr));
705 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
706 upper_32_bits(wptr_gpu_addr));
707 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
708 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
709 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
710 SDMA0_GFX_RB_WPTR_POLL_CNTL,
711 F32_POLL_ENABLE, 1);
712 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
713 wptr_poll_cntl);
714
715 /* set the wb address whether it's enabled or not */
716 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
717 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
718 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
719 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
720
721 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
722
723 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
724 ring->gpu_addr >> 8);
725 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
726 ring->gpu_addr >> 40);
727
728 ring->wptr = 0;
729
730 /* before programing wptr to a less value, need set minor_ptr_update first */
731 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
732
733 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
734 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
735 lower_32_bits(ring->wptr << 2));
736 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
737 upper_32_bits(ring->wptr << 2));
738 }
739
740 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
741 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
742 mmSDMA0_GFX_DOORBELL_OFFSET));
743
744 if (ring->use_doorbell) {
745 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
746 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
747 OFFSET, ring->doorbell_index);
748 } else {
749 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
750 }
751 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
752 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
753 doorbell_offset);
754
755 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
756 ring->doorbell_index, 20);
757
758 if (amdgpu_sriov_vf(adev))
759 sdma_v5_0_ring_set_wptr(ring);
760
761 /* set minor_ptr_update to 0 after wptr programed */
762 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
763
764 if (!amdgpu_sriov_vf(adev)) {
765 /* set utc l1 enable flag always to 1 */
766 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
767 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
768
769 /* enable MCBP */
770 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
771 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
772
773 /* Set up RESP_MODE to non-copy addresses */
774 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
775 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
776 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
777 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
778
779 /* program default cache read and write policy */
780 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
781 /* clean read policy and write policy bits */
782 temp &= 0xFF0FFF;
783 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
784 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
785 }
786
787 if (!amdgpu_sriov_vf(adev)) {
788 /* unhalt engine */
789 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
790 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
791 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
792 }
793
794 /* enable DMA RB */
795 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
796 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
797
798 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
799 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
800#ifdef __BIG_ENDIAN
801 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
802#endif
803 /* enable DMA IBs */
804 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
805
806 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
807 sdma_v5_0_ctx_switch_enable(adev, enable: true);
808 sdma_v5_0_enable(adev, enable: true);
809 }
810
811 r = amdgpu_ring_test_helper(ring);
812 if (r)
813 return r;
814 }
815
816 return 0;
817}
818
819/**
820 * sdma_v5_0_rlc_resume - setup and start the async dma engines
821 *
822 * @adev: amdgpu_device pointer
823 *
824 * Set up the compute DMA queues and enable them (NAVI10).
825 * Returns 0 for success, error for failure.
826 */
827static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
828{
829 return 0;
830}
831
832/**
833 * sdma_v5_0_load_microcode - load the sDMA ME ucode
834 *
835 * @adev: amdgpu_device pointer
836 *
837 * Loads the sDMA0/1 ucode.
838 * Returns 0 for success, -EINVAL if the ucode is not available.
839 */
840static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
841{
842 const struct sdma_firmware_header_v1_0 *hdr;
843 const __le32 *fw_data;
844 u32 fw_size;
845 int i, j;
846
847 /* halt the MEs */
848 sdma_v5_0_enable(adev, enable: false);
849
850 for (i = 0; i < adev->sdma.num_instances; i++) {
851 if (!adev->sdma.instance[i].fw)
852 return -EINVAL;
853
854 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
855 amdgpu_ucode_print_sdma_hdr(hdr: &hdr->header);
856 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
857
858 fw_data = (const __le32 *)
859 (adev->sdma.instance[i].fw->data +
860 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
861
862 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
863
864 for (j = 0; j < fw_size; j++) {
865 if (amdgpu_emu_mode == 1 && j % 500 == 0)
866 msleep(msecs: 1);
867 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
868 }
869
870 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
871 }
872
873 return 0;
874}
875
876/**
877 * sdma_v5_0_start - setup and start the async dma engines
878 *
879 * @adev: amdgpu_device pointer
880 *
881 * Set up the DMA engines and enable them (NAVI10).
882 * Returns 0 for success, error for failure.
883 */
884static int sdma_v5_0_start(struct amdgpu_device *adev)
885{
886 int r = 0;
887
888 if (amdgpu_sriov_vf(adev)) {
889 sdma_v5_0_ctx_switch_enable(adev, enable: false);
890 sdma_v5_0_enable(adev, enable: false);
891
892 /* set RB registers */
893 r = sdma_v5_0_gfx_resume(adev);
894 return r;
895 }
896
897 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
898 r = sdma_v5_0_load_microcode(adev);
899 if (r)
900 return r;
901 }
902
903 /* unhalt the MEs */
904 sdma_v5_0_enable(adev, enable: true);
905 /* enable sdma ring preemption */
906 sdma_v5_0_ctx_switch_enable(adev, enable: true);
907
908 /* start the gfx rings and rlc compute queues */
909 r = sdma_v5_0_gfx_resume(adev);
910 if (r)
911 return r;
912 r = sdma_v5_0_rlc_resume(adev);
913
914 return r;
915}
916
917static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
918 struct amdgpu_mqd_prop *prop)
919{
920 struct v10_sdma_mqd *m = mqd;
921 uint64_t wb_gpu_addr;
922
923 m->sdmax_rlcx_rb_cntl =
924 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
925 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
926 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
927 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
928
929 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
930 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
931
932 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
933 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
934
935 wb_gpu_addr = prop->wptr_gpu_addr;
936 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
937 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
938
939 wb_gpu_addr = prop->rptr_gpu_addr;
940 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
941 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
942
943 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
944 mmSDMA0_GFX_IB_CNTL));
945
946 m->sdmax_rlcx_doorbell_offset =
947 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
948
949 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
950
951 return 0;
952}
953
954static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
955{
956 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
957 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
958}
959
960/**
961 * sdma_v5_0_ring_test_ring - simple async dma engine test
962 *
963 * @ring: amdgpu_ring structure holding ring information
964 *
965 * Test the DMA engine by writing using it to write an
966 * value to memory. (NAVI10).
967 * Returns 0 for success, error for failure.
968 */
969static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
970{
971 struct amdgpu_device *adev = ring->adev;
972 unsigned i;
973 unsigned index;
974 int r;
975 u32 tmp;
976 u64 gpu_addr;
977 volatile uint32_t *cpu_ptr = NULL;
978
979 tmp = 0xCAFEDEAD;
980
981 if (ring->is_mes_queue) {
982 uint32_t offset = 0;
983 offset = amdgpu_mes_ctx_get_offs(ring,
984 id_offs: AMDGPU_MES_CTX_PADDING_OFFS);
985 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
986 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
987 *cpu_ptr = tmp;
988 } else {
989 r = amdgpu_device_wb_get(adev, wb: &index);
990 if (r) {
991 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
992 return r;
993 }
994
995 gpu_addr = adev->wb.gpu_addr + (index * 4);
996 adev->wb.wb[index] = cpu_to_le32(tmp);
997 }
998
999 r = amdgpu_ring_alloc(ring, ndw: 20);
1000 if (r) {
1001 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1002 amdgpu_device_wb_free(adev, wb: index);
1003 return r;
1004 }
1005
1006 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1007 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1008 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1009 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1010 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1011 amdgpu_ring_write(ring, v: 0xDEADBEEF);
1012 amdgpu_ring_commit(ring);
1013
1014 for (i = 0; i < adev->usec_timeout; i++) {
1015 if (ring->is_mes_queue)
1016 tmp = le32_to_cpu(*cpu_ptr);
1017 else
1018 tmp = le32_to_cpu(adev->wb.wb[index]);
1019 if (tmp == 0xDEADBEEF)
1020 break;
1021 if (amdgpu_emu_mode == 1)
1022 msleep(msecs: 1);
1023 else
1024 udelay(1);
1025 }
1026
1027 if (i >= adev->usec_timeout)
1028 r = -ETIMEDOUT;
1029
1030 if (!ring->is_mes_queue)
1031 amdgpu_device_wb_free(adev, wb: index);
1032
1033 return r;
1034}
1035
1036/**
1037 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1038 *
1039 * @ring: amdgpu_ring structure holding ring information
1040 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1041 *
1042 * Test a simple IB in the DMA ring (NAVI10).
1043 * Returns 0 on success, error on failure.
1044 */
1045static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1046{
1047 struct amdgpu_device *adev = ring->adev;
1048 struct amdgpu_ib ib;
1049 struct dma_fence *f = NULL;
1050 unsigned index;
1051 long r;
1052 u32 tmp = 0;
1053 u64 gpu_addr;
1054 volatile uint32_t *cpu_ptr = NULL;
1055
1056 tmp = 0xCAFEDEAD;
1057 memset(&ib, 0, sizeof(ib));
1058
1059 if (ring->is_mes_queue) {
1060 uint32_t offset = 0;
1061 offset = amdgpu_mes_ctx_get_offs(ring, id_offs: AMDGPU_MES_CTX_IB_OFFS);
1062 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1063 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1064
1065 offset = amdgpu_mes_ctx_get_offs(ring,
1066 id_offs: AMDGPU_MES_CTX_PADDING_OFFS);
1067 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1068 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1069 *cpu_ptr = tmp;
1070 } else {
1071 r = amdgpu_device_wb_get(adev, wb: &index);
1072 if (r) {
1073 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1074 return r;
1075 }
1076
1077 gpu_addr = adev->wb.gpu_addr + (index * 4);
1078 adev->wb.wb[index] = cpu_to_le32(tmp);
1079
1080 r = amdgpu_ib_get(adev, NULL, size: 256,
1081 pool: AMDGPU_IB_POOL_DIRECT, ib: &ib);
1082 if (r) {
1083 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1084 goto err0;
1085 }
1086 }
1087
1088 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1089 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1090 ib.ptr[1] = lower_32_bits(gpu_addr);
1091 ib.ptr[2] = upper_32_bits(gpu_addr);
1092 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1093 ib.ptr[4] = 0xDEADBEEF;
1094 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1095 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1096 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1097 ib.length_dw = 8;
1098
1099 r = amdgpu_ib_schedule(ring, num_ibs: 1, ibs: &ib, NULL, f: &f);
1100 if (r)
1101 goto err1;
1102
1103 r = dma_fence_wait_timeout(f, intr: false, timeout);
1104 if (r == 0) {
1105 DRM_ERROR("amdgpu: IB test timed out\n");
1106 r = -ETIMEDOUT;
1107 goto err1;
1108 } else if (r < 0) {
1109 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1110 goto err1;
1111 }
1112
1113 if (ring->is_mes_queue)
1114 tmp = le32_to_cpu(*cpu_ptr);
1115 else
1116 tmp = le32_to_cpu(adev->wb.wb[index]);
1117
1118 if (tmp == 0xDEADBEEF)
1119 r = 0;
1120 else
1121 r = -EINVAL;
1122
1123err1:
1124 amdgpu_ib_free(adev, ib: &ib, NULL);
1125 dma_fence_put(fence: f);
1126err0:
1127 if (!ring->is_mes_queue)
1128 amdgpu_device_wb_free(adev, wb: index);
1129 return r;
1130}
1131
1132
1133/**
1134 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1135 *
1136 * @ib: indirect buffer to fill with commands
1137 * @pe: addr of the page entry
1138 * @src: src addr to copy from
1139 * @count: number of page entries to update
1140 *
1141 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1142 */
1143static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1144 uint64_t pe, uint64_t src,
1145 unsigned count)
1146{
1147 unsigned bytes = count * 8;
1148
1149 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1150 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1151 ib->ptr[ib->length_dw++] = bytes - 1;
1152 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1153 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1154 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1155 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1156 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1157
1158}
1159
1160/**
1161 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1162 *
1163 * @ib: indirect buffer to fill with commands
1164 * @pe: addr of the page entry
1165 * @value: dst addr to write into pe
1166 * @count: number of page entries to update
1167 * @incr: increase next addr by incr bytes
1168 *
1169 * Update PTEs by writing them manually using sDMA (NAVI10).
1170 */
1171static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1172 uint64_t value, unsigned count,
1173 uint32_t incr)
1174{
1175 unsigned ndw = count * 2;
1176
1177 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1178 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1179 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1180 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1181 ib->ptr[ib->length_dw++] = ndw - 1;
1182 for (; ndw > 0; ndw -= 2) {
1183 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1184 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1185 value += incr;
1186 }
1187}
1188
1189/**
1190 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1191 *
1192 * @ib: indirect buffer to fill with commands
1193 * @pe: addr of the page entry
1194 * @addr: dst addr to write into pe
1195 * @count: number of page entries to update
1196 * @incr: increase next addr by incr bytes
1197 * @flags: access flags
1198 *
1199 * Update the page tables using sDMA (NAVI10).
1200 */
1201static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1202 uint64_t pe,
1203 uint64_t addr, unsigned count,
1204 uint32_t incr, uint64_t flags)
1205{
1206 /* for physically contiguous pages (vram) */
1207 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1208 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1209 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1210 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1211 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1212 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1213 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1214 ib->ptr[ib->length_dw++] = incr; /* increment size */
1215 ib->ptr[ib->length_dw++] = 0;
1216 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1217}
1218
1219/**
1220 * sdma_v5_0_ring_pad_ib - pad the IB
1221 * @ring: amdgpu_ring structure holding ring information
1222 * @ib: indirect buffer to fill with padding
1223 *
1224 * Pad the IB with NOPs to a boundary multiple of 8.
1225 */
1226static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1227{
1228 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1229 u32 pad_count;
1230 int i;
1231
1232 pad_count = (-ib->length_dw) & 0x7;
1233 for (i = 0; i < pad_count; i++)
1234 if (sdma && sdma->burst_nop && (i == 0))
1235 ib->ptr[ib->length_dw++] =
1236 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1237 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1238 else
1239 ib->ptr[ib->length_dw++] =
1240 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1241}
1242
1243
1244/**
1245 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1246 *
1247 * @ring: amdgpu_ring pointer
1248 *
1249 * Make sure all previous operations are completed (CIK).
1250 */
1251static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1252{
1253 uint32_t seq = ring->fence_drv.sync_seq;
1254 uint64_t addr = ring->fence_drv.gpu_addr;
1255
1256 /* wait for idle */
1257 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1258 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1259 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1260 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1261 amdgpu_ring_write(ring, v: addr & 0xfffffffc);
1262 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1263 amdgpu_ring_write(ring, v: seq); /* reference */
1264 amdgpu_ring_write(ring, v: 0xffffffff); /* mask */
1265 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1266 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1267}
1268
1269
1270/**
1271 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1272 *
1273 * @ring: amdgpu_ring pointer
1274 * @vmid: vmid number to use
1275 * @pd_addr: address
1276 *
1277 * Update the page table base and flush the VM TLB
1278 * using sDMA (NAVI10).
1279 */
1280static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1281 unsigned vmid, uint64_t pd_addr)
1282{
1283 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1284}
1285
1286static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1287 uint32_t reg, uint32_t val)
1288{
1289 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1290 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1291 amdgpu_ring_write(ring, v: reg);
1292 amdgpu_ring_write(ring, v: val);
1293}
1294
1295static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1296 uint32_t val, uint32_t mask)
1297{
1298 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1299 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1300 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1301 amdgpu_ring_write(ring, v: reg << 2);
1302 amdgpu_ring_write(ring, v: 0);
1303 amdgpu_ring_write(ring, v: val); /* reference */
1304 amdgpu_ring_write(ring, v: mask); /* mask */
1305 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1306 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1307}
1308
1309static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1310 uint32_t reg0, uint32_t reg1,
1311 uint32_t ref, uint32_t mask)
1312{
1313 amdgpu_ring_emit_wreg(ring, reg0, ref);
1314 /* wait for a cycle to reset vm_inv_eng*_ack */
1315 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1316 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1317}
1318
1319static int sdma_v5_0_early_init(void *handle)
1320{
1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322 int r;
1323
1324 r = sdma_v5_0_init_microcode(adev);
1325 if (r)
1326 return r;
1327
1328 sdma_v5_0_set_ring_funcs(adev);
1329 sdma_v5_0_set_buffer_funcs(adev);
1330 sdma_v5_0_set_vm_pte_funcs(adev);
1331 sdma_v5_0_set_irq_funcs(adev);
1332 sdma_v5_0_set_mqd_funcs(adev);
1333
1334 return 0;
1335}
1336
1337
1338static int sdma_v5_0_sw_init(void *handle)
1339{
1340 struct amdgpu_ring *ring;
1341 int r, i;
1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1343
1344 /* SDMA trap event */
1345 r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_SDMA0,
1346 SDMA0_5_0__SRCID__SDMA_TRAP,
1347 source: &adev->sdma.trap_irq);
1348 if (r)
1349 return r;
1350
1351 /* SDMA trap event */
1352 r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_SDMA1,
1353 SDMA1_5_0__SRCID__SDMA_TRAP,
1354 source: &adev->sdma.trap_irq);
1355 if (r)
1356 return r;
1357
1358 for (i = 0; i < adev->sdma.num_instances; i++) {
1359 ring = &adev->sdma.instance[i].ring;
1360 ring->ring_obj = NULL;
1361 ring->use_doorbell = true;
1362
1363 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1364 ring->use_doorbell?"true":"false");
1365
1366 ring->doorbell_index = (i == 0) ?
1367 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1368 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1369
1370 ring->vm_hub = AMDGPU_GFXHUB(0);
1371 sprintf(buf: ring->name, fmt: "sdma%d", i);
1372 r = amdgpu_ring_init(adev, ring, max_dw: 1024, irq_src: &adev->sdma.trap_irq,
1373 irq_type: (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1374 AMDGPU_SDMA_IRQ_INSTANCE1,
1375 hw_prio: AMDGPU_RING_PRIO_DEFAULT, NULL);
1376 if (r)
1377 return r;
1378 }
1379
1380 return r;
1381}
1382
1383static int sdma_v5_0_sw_fini(void *handle)
1384{
1385 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1386 int i;
1387
1388 for (i = 0; i < adev->sdma.num_instances; i++)
1389 amdgpu_ring_fini(ring: &adev->sdma.instance[i].ring);
1390
1391 amdgpu_sdma_destroy_inst_ctx(adev, duplicate: false);
1392
1393 return 0;
1394}
1395
1396static int sdma_v5_0_hw_init(void *handle)
1397{
1398 int r;
1399 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1400
1401 sdma_v5_0_init_golden_registers(adev);
1402
1403 r = sdma_v5_0_start(adev);
1404
1405 return r;
1406}
1407
1408static int sdma_v5_0_hw_fini(void *handle)
1409{
1410 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1411
1412 if (amdgpu_sriov_vf(adev))
1413 return 0;
1414
1415 sdma_v5_0_ctx_switch_enable(adev, enable: false);
1416 sdma_v5_0_enable(adev, enable: false);
1417
1418 return 0;
1419}
1420
1421static int sdma_v5_0_suspend(void *handle)
1422{
1423 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1424
1425 return sdma_v5_0_hw_fini(handle: adev);
1426}
1427
1428static int sdma_v5_0_resume(void *handle)
1429{
1430 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1431
1432 return sdma_v5_0_hw_init(handle: adev);
1433}
1434
1435static bool sdma_v5_0_is_idle(void *handle)
1436{
1437 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1438 u32 i;
1439
1440 for (i = 0; i < adev->sdma.num_instances; i++) {
1441 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1442
1443 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1444 return false;
1445 }
1446
1447 return true;
1448}
1449
1450static int sdma_v5_0_wait_for_idle(void *handle)
1451{
1452 unsigned i;
1453 u32 sdma0, sdma1;
1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1455
1456 for (i = 0; i < adev->usec_timeout; i++) {
1457 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1458 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1459
1460 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1461 return 0;
1462 udelay(1);
1463 }
1464 return -ETIMEDOUT;
1465}
1466
1467static int sdma_v5_0_soft_reset(void *handle)
1468{
1469 /* todo */
1470
1471 return 0;
1472}
1473
1474static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1475{
1476 int i, r = 0;
1477 struct amdgpu_device *adev = ring->adev;
1478 u32 index = 0;
1479 u64 sdma_gfx_preempt;
1480
1481 amdgpu_sdma_get_index_from_ring(ring, index: &index);
1482 if (index == 0)
1483 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1484 else
1485 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1486
1487 /* assert preemption condition */
1488 amdgpu_ring_set_preempt_cond_exec(ring, cond_exec: false);
1489
1490 /* emit the trailing fence */
1491 ring->trail_seq += 1;
1492 amdgpu_ring_alloc(ring, ndw: 10);
1493 sdma_v5_0_ring_emit_fence(ring, addr: ring->trail_fence_gpu_addr,
1494 seq: ring->trail_seq, flags: 0);
1495 amdgpu_ring_commit(ring);
1496
1497 /* assert IB preemption */
1498 WREG32(sdma_gfx_preempt, 1);
1499
1500 /* poll the trailing fence */
1501 for (i = 0; i < adev->usec_timeout; i++) {
1502 if (ring->trail_seq ==
1503 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1504 break;
1505 udelay(1);
1506 }
1507
1508 if (i >= adev->usec_timeout) {
1509 r = -EINVAL;
1510 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1511 }
1512
1513 /* deassert IB preemption */
1514 WREG32(sdma_gfx_preempt, 0);
1515
1516 /* deassert the preemption condition */
1517 amdgpu_ring_set_preempt_cond_exec(ring, cond_exec: true);
1518 return r;
1519}
1520
1521static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1522 struct amdgpu_irq_src *source,
1523 unsigned type,
1524 enum amdgpu_interrupt_state state)
1525{
1526 u32 sdma_cntl;
1527
1528 if (!amdgpu_sriov_vf(adev)) {
1529 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1530 sdma_v5_0_get_reg_offset(adev, instance: 0, mmSDMA0_CNTL) :
1531 sdma_v5_0_get_reg_offset(adev, instance: 1, mmSDMA0_CNTL);
1532
1533 sdma_cntl = RREG32(reg_offset);
1534 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1535 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1536 WREG32(reg_offset, sdma_cntl);
1537 }
1538
1539 return 0;
1540}
1541
1542static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1543 struct amdgpu_irq_src *source,
1544 struct amdgpu_iv_entry *entry)
1545{
1546 uint32_t mes_queue_id = entry->src_data[0];
1547
1548 DRM_DEBUG("IH: SDMA trap\n");
1549
1550 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1551 struct amdgpu_mes_queue *queue;
1552
1553 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1554
1555 spin_lock(lock: &adev->mes.queue_id_lock);
1556 queue = idr_find(&adev->mes.queue_id_idr, id: mes_queue_id);
1557 if (queue) {
1558 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1559 amdgpu_fence_process(ring: queue->ring);
1560 }
1561 spin_unlock(lock: &adev->mes.queue_id_lock);
1562 return 0;
1563 }
1564
1565 switch (entry->client_id) {
1566 case SOC15_IH_CLIENTID_SDMA0:
1567 switch (entry->ring_id) {
1568 case 0:
1569 amdgpu_fence_process(ring: &adev->sdma.instance[0].ring);
1570 break;
1571 case 1:
1572 /* XXX compute */
1573 break;
1574 case 2:
1575 /* XXX compute */
1576 break;
1577 case 3:
1578 /* XXX page queue*/
1579 break;
1580 }
1581 break;
1582 case SOC15_IH_CLIENTID_SDMA1:
1583 switch (entry->ring_id) {
1584 case 0:
1585 amdgpu_fence_process(ring: &adev->sdma.instance[1].ring);
1586 break;
1587 case 1:
1588 /* XXX compute */
1589 break;
1590 case 2:
1591 /* XXX compute */
1592 break;
1593 case 3:
1594 /* XXX page queue*/
1595 break;
1596 }
1597 break;
1598 }
1599 return 0;
1600}
1601
1602static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1603 struct amdgpu_irq_src *source,
1604 struct amdgpu_iv_entry *entry)
1605{
1606 return 0;
1607}
1608
1609static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1610 bool enable)
1611{
1612 uint32_t data, def;
1613 int i;
1614
1615 for (i = 0; i < adev->sdma.num_instances; i++) {
1616 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1617 /* Enable sdma clock gating */
1618 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1619 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1620 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1621 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1622 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1623 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1624 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1625 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1626 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1627 if (def != data)
1628 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1629 } else {
1630 /* Disable sdma clock gating */
1631 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1632 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1633 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1634 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1635 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1636 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1637 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1638 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1639 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1640 if (def != data)
1641 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1642 }
1643 }
1644}
1645
1646static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1647 bool enable)
1648{
1649 uint32_t data, def;
1650 int i;
1651
1652 for (i = 0; i < adev->sdma.num_instances; i++) {
1653 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1654 /* Enable sdma mem light sleep */
1655 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1656 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1657 if (def != data)
1658 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1659
1660 } else {
1661 /* Disable sdma mem light sleep */
1662 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1663 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1664 if (def != data)
1665 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1666
1667 }
1668 }
1669}
1670
1671static int sdma_v5_0_set_clockgating_state(void *handle,
1672 enum amd_clockgating_state state)
1673{
1674 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1675
1676 if (amdgpu_sriov_vf(adev))
1677 return 0;
1678
1679 switch (amdgpu_ip_version(adev, ip: SDMA0_HWIP, inst: 0)) {
1680 case IP_VERSION(5, 0, 0):
1681 case IP_VERSION(5, 0, 2):
1682 case IP_VERSION(5, 0, 5):
1683 sdma_v5_0_update_medium_grain_clock_gating(adev,
1684 enable: state == AMD_CG_STATE_GATE);
1685 sdma_v5_0_update_medium_grain_light_sleep(adev,
1686 enable: state == AMD_CG_STATE_GATE);
1687 break;
1688 default:
1689 break;
1690 }
1691
1692 return 0;
1693}
1694
1695static int sdma_v5_0_set_powergating_state(void *handle,
1696 enum amd_powergating_state state)
1697{
1698 return 0;
1699}
1700
1701static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1702{
1703 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1704 int data;
1705
1706 if (amdgpu_sriov_vf(adev))
1707 *flags = 0;
1708
1709 /* AMD_CG_SUPPORT_SDMA_MGCG */
1710 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1711 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1712 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1713
1714 /* AMD_CG_SUPPORT_SDMA_LS */
1715 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1716 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1717 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1718}
1719
1720const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1721 .name = "sdma_v5_0",
1722 .early_init = sdma_v5_0_early_init,
1723 .late_init = NULL,
1724 .sw_init = sdma_v5_0_sw_init,
1725 .sw_fini = sdma_v5_0_sw_fini,
1726 .hw_init = sdma_v5_0_hw_init,
1727 .hw_fini = sdma_v5_0_hw_fini,
1728 .suspend = sdma_v5_0_suspend,
1729 .resume = sdma_v5_0_resume,
1730 .is_idle = sdma_v5_0_is_idle,
1731 .wait_for_idle = sdma_v5_0_wait_for_idle,
1732 .soft_reset = sdma_v5_0_soft_reset,
1733 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1734 .set_powergating_state = sdma_v5_0_set_powergating_state,
1735 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1736};
1737
1738static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1739 .type = AMDGPU_RING_TYPE_SDMA,
1740 .align_mask = 0xf,
1741 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1742 .support_64bit_ptrs = true,
1743 .secure_submission_supported = true,
1744 .get_rptr = sdma_v5_0_ring_get_rptr,
1745 .get_wptr = sdma_v5_0_ring_get_wptr,
1746 .set_wptr = sdma_v5_0_ring_set_wptr,
1747 .emit_frame_size =
1748 5 + /* sdma_v5_0_ring_init_cond_exec */
1749 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1750 3 + /* hdp_invalidate */
1751 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1752 /* sdma_v5_0_ring_emit_vm_flush */
1753 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1754 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1755 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1756 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1757 .emit_ib = sdma_v5_0_ring_emit_ib,
1758 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1759 .emit_fence = sdma_v5_0_ring_emit_fence,
1760 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1761 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1762 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1763 .test_ring = sdma_v5_0_ring_test_ring,
1764 .test_ib = sdma_v5_0_ring_test_ib,
1765 .insert_nop = sdma_v5_0_ring_insert_nop,
1766 .pad_ib = sdma_v5_0_ring_pad_ib,
1767 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1768 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1769 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1770 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1771 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1772};
1773
1774static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1775{
1776 int i;
1777
1778 for (i = 0; i < adev->sdma.num_instances; i++) {
1779 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1780 adev->sdma.instance[i].ring.me = i;
1781 }
1782}
1783
1784static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1785 .set = sdma_v5_0_set_trap_irq_state,
1786 .process = sdma_v5_0_process_trap_irq,
1787};
1788
1789static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1790 .process = sdma_v5_0_process_illegal_inst_irq,
1791};
1792
1793static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1794{
1795 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1796 adev->sdma.num_instances;
1797 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1798 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1799}
1800
1801/**
1802 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1803 *
1804 * @ib: indirect buffer to copy to
1805 * @src_offset: src GPU address
1806 * @dst_offset: dst GPU address
1807 * @byte_count: number of bytes to xfer
1808 * @tmz: if a secure copy should be used
1809 *
1810 * Copy GPU buffers using the DMA engine (NAVI10).
1811 * Used by the amdgpu ttm implementation to move pages if
1812 * registered as the asic copy callback.
1813 */
1814static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1815 uint64_t src_offset,
1816 uint64_t dst_offset,
1817 uint32_t byte_count,
1818 bool tmz)
1819{
1820 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1821 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1822 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1823 ib->ptr[ib->length_dw++] = byte_count - 1;
1824 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1825 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1826 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1827 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1828 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1829}
1830
1831/**
1832 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1833 *
1834 * @ib: indirect buffer to fill
1835 * @src_data: value to write to buffer
1836 * @dst_offset: dst GPU address
1837 * @byte_count: number of bytes to xfer
1838 *
1839 * Fill GPU buffers using the DMA engine (NAVI10).
1840 */
1841static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1842 uint32_t src_data,
1843 uint64_t dst_offset,
1844 uint32_t byte_count)
1845{
1846 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1847 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1848 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1849 ib->ptr[ib->length_dw++] = src_data;
1850 ib->ptr[ib->length_dw++] = byte_count - 1;
1851}
1852
1853static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1854 .copy_max_bytes = 0x400000,
1855 .copy_num_dw = 7,
1856 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1857
1858 .fill_max_bytes = 0x400000,
1859 .fill_num_dw = 5,
1860 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1861};
1862
1863static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1864{
1865 if (adev->mman.buffer_funcs == NULL) {
1866 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1867 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1868 }
1869}
1870
1871static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1872 .copy_pte_num_dw = 7,
1873 .copy_pte = sdma_v5_0_vm_copy_pte,
1874 .write_pte = sdma_v5_0_vm_write_pte,
1875 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1876};
1877
1878static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1879{
1880 unsigned i;
1881
1882 if (adev->vm_manager.vm_pte_funcs == NULL) {
1883 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1884 for (i = 0; i < adev->sdma.num_instances; i++) {
1885 adev->vm_manager.vm_pte_scheds[i] =
1886 &adev->sdma.instance[i].ring.sched;
1887 }
1888 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1889 }
1890}
1891
1892const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1893 .type = AMD_IP_BLOCK_TYPE_SDMA,
1894 .major = 5,
1895 .minor = 0,
1896 .rev = 0,
1897 .funcs = &sdma_v5_0_ip_funcs,
1898};
1899

source code of linux/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c