1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __AMDGPU_DM_H__
27#define __AMDGPU_DM_H__
28
29#include <drm/drmP.h>
30#include <drm/drm_atomic.h>
31
32/*
33 * This file contains the definition for amdgpu_display_manager
34 * and its API for amdgpu driver's use.
35 * This component provides all the display related functionality
36 * and this is the only component that calls DAL API.
37 * The API contained here intended for amdgpu driver use.
38 * The API that is called directly from KMS framework is located
39 * in amdgpu_dm_kms.h file
40 */
41
42#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
43/*
44#include "include/amdgpu_dal_power_if.h"
45#include "amdgpu_dm_irq.h"
46*/
47
48#include "irq_types.h"
49#include "signal_types.h"
50
51/* Forward declarations */
52struct amdgpu_device;
53struct drm_device;
54struct amdgpu_dm_irq_handler_data;
55struct dc;
56
57struct common_irq_params {
58 struct amdgpu_device *adev;
59 enum dc_irq_source irq_src;
60};
61
62/**
63 * struct irq_list_head - Linked-list for low context IRQ handlers.
64 *
65 * @head: The list_head within &struct handler_data
66 * @work: A work_struct containing the deferred handler work
67 */
68struct irq_list_head {
69 struct list_head head;
70 /* In case this interrupt needs post-processing, 'work' will be queued*/
71 struct work_struct work;
72};
73
74/**
75 * struct dm_compressor_info - Buffer info used by frame buffer compression
76 * @cpu_addr: MMIO cpu addr
77 * @bo_ptr: Pointer to the buffer object
78 * @gpu_addr: MMIO gpu addr
79 */
80struct dm_comressor_info {
81 void *cpu_addr;
82 struct amdgpu_bo *bo_ptr;
83 uint64_t gpu_addr;
84};
85
86/**
87 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI
88 * @min_input_signal: minimum possible input in range 0-255
89 * @max_input_signal: maximum possible input in range 0-255
90 * @caps_valid: true if these values are from the ACPI interface
91 */
92struct amdgpu_dm_backlight_caps {
93 int min_input_signal;
94 int max_input_signal;
95 bool caps_valid;
96};
97
98/**
99 * struct amdgpu_display_manager - Central amdgpu display manager device
100 *
101 * @dc: Display Core control structure
102 * @adev: AMDGPU base driver structure
103 * @ddev: DRM base driver structure
104 * @display_indexes_num: Max number of display streams supported
105 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
106 * @backlight_dev: Backlight control device
107 * @cached_state: Caches device atomic state for suspend/resume
108 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
109 */
110struct amdgpu_display_manager {
111
112 struct dc *dc;
113
114 /**
115 * @cgs_device:
116 *
117 * The Common Graphics Services device. It provides an interface for
118 * accessing registers.
119 */
120 struct cgs_device *cgs_device;
121
122 struct amdgpu_device *adev;
123 struct drm_device *ddev;
124 u16 display_indexes_num;
125
126 /**
127 * @atomic_obj
128 *
129 * In combination with &dm_atomic_state it helps manage
130 * global atomic state that doesn't map cleanly into existing
131 * drm resources, like &dc_context.
132 */
133 struct drm_private_obj atomic_obj;
134
135 struct drm_modeset_lock atomic_obj_lock;
136
137 /**
138 * @dc_lock:
139 *
140 * Guards access to DC functions that can issue register write
141 * sequences.
142 */
143 struct mutex dc_lock;
144
145 /**
146 * @irq_handler_list_low_tab:
147 *
148 * Low priority IRQ handler table.
149 *
150 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
151 * source. Low priority IRQ handlers are deferred to a workqueue to be
152 * processed. Hence, they can sleep.
153 *
154 * Note that handlers are called in the same order as they were
155 * registered (FIFO).
156 */
157 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
158
159 /**
160 * @irq_handler_list_high_tab:
161 *
162 * High priority IRQ handler table.
163 *
164 * It is a n*m table, same as &irq_handler_list_low_tab. However,
165 * handlers in this table are not deferred and are called immediately.
166 */
167 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
168
169 /**
170 * @pflip_params:
171 *
172 * Page flip IRQ parameters, passed to registered handlers when
173 * triggered.
174 */
175 struct common_irq_params
176 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
177
178 /**
179 * @vblank_params:
180 *
181 * Vertical blanking IRQ parameters, passed to registered handlers when
182 * triggered.
183 */
184 struct common_irq_params
185 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
186
187 spinlock_t irq_handler_list_table_lock;
188
189 struct backlight_device *backlight_dev;
190
191 const struct dc_link *backlight_link;
192 struct amdgpu_dm_backlight_caps backlight_caps;
193
194 struct mod_freesync *freesync_module;
195
196 struct drm_atomic_state *cached_state;
197
198 struct dm_comressor_info compressor;
199
200 const struct firmware *fw_dmcu;
201 uint32_t dmcu_fw_version;
202};
203
204struct amdgpu_dm_connector {
205
206 struct drm_connector base;
207 uint32_t connector_id;
208
209 /* we need to mind the EDID between detect
210 and get modes due to analog/digital/tvencoder */
211 struct edid *edid;
212
213 /* shared with amdgpu */
214 struct amdgpu_hpd hpd;
215
216 /* number of modes generated from EDID at 'dc_sink' */
217 int num_modes;
218
219 /* The 'old' sink - before an HPD.
220 * The 'current' sink is in dc_link->sink. */
221 struct dc_sink *dc_sink;
222 struct dc_link *dc_link;
223 struct dc_sink *dc_em_sink;
224
225 /* DM only */
226 struct drm_dp_mst_topology_mgr mst_mgr;
227 struct amdgpu_dm_dp_aux dm_dp_aux;
228 struct drm_dp_mst_port *port;
229 struct amdgpu_dm_connector *mst_port;
230 struct amdgpu_encoder *mst_encoder;
231
232 /* TODO see if we can merge with ddc_bus or make a dm_connector */
233 struct amdgpu_i2c_adapter *i2c;
234
235 /* Monitor range limits */
236 int min_vfreq ;
237 int max_vfreq ;
238 int pixel_clock_mhz;
239
240 struct mutex hpd_lock;
241
242 bool fake_enable;
243};
244
245#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
246
247extern const struct amdgpu_ip_block_version dm_ip_block;
248
249struct amdgpu_framebuffer;
250struct amdgpu_display_manager;
251struct dc_validation_set;
252struct dc_plane_state;
253
254struct dm_plane_state {
255 struct drm_plane_state base;
256 struct dc_plane_state *dc_state;
257};
258
259struct dm_crtc_state {
260 struct drm_crtc_state base;
261 struct dc_stream_state *stream;
262
263 int crc_skip_count;
264 bool crc_enabled;
265
266 bool freesync_timing_changed;
267 bool freesync_vrr_info_changed;
268
269 bool vrr_supported;
270 struct mod_freesync_config freesync_config;
271 struct mod_vrr_params vrr_params;
272 struct dc_info_packet vrr_infopacket;
273
274 int abm_level;
275};
276
277#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
278
279struct dm_atomic_state {
280 struct drm_private_state base;
281
282 struct dc_state *context;
283};
284
285#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
286
287struct dm_connector_state {
288 struct drm_connector_state base;
289
290 enum amdgpu_rmx_type scaling;
291 uint8_t underscan_vborder;
292 uint8_t underscan_hborder;
293 uint8_t max_bpc;
294 bool underscan_enable;
295 bool freesync_capable;
296 uint8_t abm_level;
297};
298
299#define to_dm_connector_state(x)\
300 container_of((x), struct dm_connector_state, base)
301
302void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
303struct drm_connector_state *
304amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
305int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
306 struct drm_connector_state *state,
307 struct drm_property *property,
308 uint64_t val);
309
310int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
311 const struct drm_connector_state *state,
312 struct drm_property *property,
313 uint64_t *val);
314
315int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
316
317void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
318 struct amdgpu_dm_connector *aconnector,
319 int connector_type,
320 struct dc_link *link,
321 int link_index);
322
323enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
324 struct drm_display_mode *mode);
325
326void dm_restore_drm_connector_state(struct drm_device *dev,
327 struct drm_connector *connector);
328
329void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
330 struct edid *edid);
331
332/* amdgpu_dm_crc.c */
333#ifdef CONFIG_DEBUG_FS
334int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
335int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
336 const char *src_name,
337 size_t *values_cnt);
338void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
339#else
340#define amdgpu_dm_crtc_set_crc_source NULL
341#define amdgpu_dm_crtc_verify_crc_source NULL
342#define amdgpu_dm_crtc_handle_crc_irq(x)
343#endif
344
345#define MAX_COLOR_LUT_ENTRIES 4096
346/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
347#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
348
349void amdgpu_dm_init_color_mod(void);
350int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
351 struct dc_plane_state *dc_plane_state);
352void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
353int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);
354
355extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
356
357#endif /* __AMDGPU_DM_H__ */
358