1 | /* |
2 | * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __AMDGPU_DM_H__ |
27 | #define __AMDGPU_DM_H__ |
28 | |
29 | #include <drm/display/drm_dp_mst_helper.h> |
30 | #include <drm/drm_atomic.h> |
31 | #include <drm/drm_connector.h> |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_plane.h> |
34 | #include "link_service_types.h" |
35 | |
36 | /* |
37 | * This file contains the definition for amdgpu_display_manager |
38 | * and its API for amdgpu driver's use. |
39 | * This component provides all the display related functionality |
40 | * and this is the only component that calls DAL API. |
41 | * The API contained here intended for amdgpu driver use. |
42 | * The API that is called directly from KMS framework is located |
43 | * in amdgpu_dm_kms.h file |
44 | */ |
45 | |
46 | #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 |
47 | |
48 | #define AMDGPU_DM_MAX_CRTC 6 |
49 | |
50 | #define AMDGPU_DM_MAX_NUM_EDP 2 |
51 | |
52 | #define AMDGPU_DMUB_NOTIFICATION_MAX 5 |
53 | |
54 | #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A |
55 | #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 |
56 | #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 |
57 | /* |
58 | #include "include/amdgpu_dal_power_if.h" |
59 | #include "amdgpu_dm_irq.h" |
60 | */ |
61 | |
62 | #include "irq_types.h" |
63 | #include "signal_types.h" |
64 | #include "amdgpu_dm_crc.h" |
65 | #include "mod_info_packet.h" |
66 | struct aux_payload; |
67 | struct set_config_cmd_payload; |
68 | enum aux_return_code_type; |
69 | enum set_config_status; |
70 | |
71 | /* Forward declarations */ |
72 | struct amdgpu_device; |
73 | struct amdgpu_crtc; |
74 | struct drm_device; |
75 | struct dc; |
76 | struct amdgpu_bo; |
77 | struct dmub_srv; |
78 | struct dc_plane_state; |
79 | struct dmub_notification; |
80 | |
81 | struct amd_vsdb_block { |
82 | unsigned char ieee_id[3]; |
83 | unsigned char version; |
84 | unsigned char feature_caps; |
85 | }; |
86 | |
87 | struct common_irq_params { |
88 | struct amdgpu_device *adev; |
89 | enum dc_irq_source irq_src; |
90 | atomic64_t previous_timestamp; |
91 | }; |
92 | |
93 | /** |
94 | * struct dm_compressor_info - Buffer info used by frame buffer compression |
95 | * @cpu_addr: MMIO cpu addr |
96 | * @bo_ptr: Pointer to the buffer object |
97 | * @gpu_addr: MMIO gpu addr |
98 | */ |
99 | struct dm_compressor_info { |
100 | void *cpu_addr; |
101 | struct amdgpu_bo *bo_ptr; |
102 | uint64_t gpu_addr; |
103 | }; |
104 | |
105 | typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); |
106 | |
107 | /** |
108 | * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ |
109 | * |
110 | * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq |
111 | * @dmub_notify: notification for callback function |
112 | * @adev: amdgpu_device pointer |
113 | */ |
114 | struct dmub_hpd_work { |
115 | struct work_struct handle_hpd_work; |
116 | struct dmub_notification *dmub_notify; |
117 | struct amdgpu_device *adev; |
118 | }; |
119 | |
120 | /** |
121 | * struct vblank_control_work - Work data for vblank control |
122 | * @work: Kernel work data for the work event |
123 | * @dm: amdgpu display manager device |
124 | * @acrtc: amdgpu CRTC instance for which the event has occurred |
125 | * @stream: DC stream for which the event has occurred |
126 | * @enable: true if enabling vblank |
127 | */ |
128 | struct vblank_control_work { |
129 | struct work_struct work; |
130 | struct amdgpu_display_manager *dm; |
131 | struct amdgpu_crtc *acrtc; |
132 | struct dc_stream_state *stream; |
133 | bool enable; |
134 | }; |
135 | |
136 | /** |
137 | * struct amdgpu_dm_backlight_caps - Information about backlight |
138 | * |
139 | * Describe the backlight support for ACPI or eDP AUX. |
140 | */ |
141 | struct amdgpu_dm_backlight_caps { |
142 | /** |
143 | * @ext_caps: Keep the data struct with all the information about the |
144 | * display support for HDR. |
145 | */ |
146 | union dpcd_sink_ext_caps *ext_caps; |
147 | /** |
148 | * @aux_min_input_signal: Min brightness value supported by the display |
149 | */ |
150 | u32 aux_min_input_signal; |
151 | /** |
152 | * @aux_max_input_signal: Max brightness value supported by the display |
153 | * in nits. |
154 | */ |
155 | u32 aux_max_input_signal; |
156 | /** |
157 | * @min_input_signal: minimum possible input in range 0-255. |
158 | */ |
159 | int min_input_signal; |
160 | /** |
161 | * @max_input_signal: maximum possible input in range 0-255. |
162 | */ |
163 | int max_input_signal; |
164 | /** |
165 | * @caps_valid: true if these values are from the ACPI interface. |
166 | */ |
167 | bool caps_valid; |
168 | /** |
169 | * @aux_support: Describes if the display supports AUX backlight. |
170 | */ |
171 | bool aux_support; |
172 | }; |
173 | |
174 | /** |
175 | * struct dal_allocation - Tracks mapped FB memory for SMU communication |
176 | * @list: list of dal allocations |
177 | * @bo: GPU buffer object |
178 | * @cpu_ptr: CPU virtual address of the GPU buffer object |
179 | * @gpu_addr: GPU virtual address of the GPU buffer object |
180 | */ |
181 | struct dal_allocation { |
182 | struct list_head list; |
183 | struct amdgpu_bo *bo; |
184 | void *cpu_ptr; |
185 | u64 gpu_addr; |
186 | }; |
187 | |
188 | /** |
189 | * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq |
190 | * offload work |
191 | */ |
192 | struct hpd_rx_irq_offload_work_queue { |
193 | /** |
194 | * @wq: workqueue structure to queue offload work. |
195 | */ |
196 | struct workqueue_struct *wq; |
197 | /** |
198 | * @offload_lock: To protect fields of offload work queue. |
199 | */ |
200 | spinlock_t offload_lock; |
201 | /** |
202 | * @is_handling_link_loss: Used to prevent inserting link loss event when |
203 | * we're handling link loss |
204 | */ |
205 | bool is_handling_link_loss; |
206 | /** |
207 | * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message |
208 | * ready event when we're already handling mst message ready event |
209 | */ |
210 | bool is_handling_mst_msg_rdy_event; |
211 | /** |
212 | * @aconnector: The aconnector that this work queue is attached to |
213 | */ |
214 | struct amdgpu_dm_connector *aconnector; |
215 | }; |
216 | |
217 | /** |
218 | * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure |
219 | */ |
220 | struct hpd_rx_irq_offload_work { |
221 | /** |
222 | * @work: offload work |
223 | */ |
224 | struct work_struct work; |
225 | /** |
226 | * @data: reference irq data which is used while handling offload work |
227 | */ |
228 | union hpd_irq_data data; |
229 | /** |
230 | * @offload_wq: offload work queue that this work is queued to |
231 | */ |
232 | struct hpd_rx_irq_offload_work_queue *offload_wq; |
233 | }; |
234 | |
235 | /** |
236 | * struct amdgpu_display_manager - Central amdgpu display manager device |
237 | * |
238 | * @dc: Display Core control structure |
239 | * @adev: AMDGPU base driver structure |
240 | * @ddev: DRM base driver structure |
241 | * @display_indexes_num: Max number of display streams supported |
242 | * @irq_handler_list_table_lock: Synchronizes access to IRQ tables |
243 | * @backlight_dev: Backlight control device |
244 | * @backlight_link: Link on which to control backlight |
245 | * @backlight_caps: Capabilities of the backlight device |
246 | * @freesync_module: Module handling freesync calculations |
247 | * @hdcp_workqueue: AMDGPU content protection queue |
248 | * @fw_dmcu: Reference to DMCU firmware |
249 | * @dmcu_fw_version: Version of the DMCU firmware |
250 | * @soc_bounding_box: SOC bounding box values provided by gpu_info FW |
251 | * @cached_state: Caches device atomic state for suspend/resume |
252 | * @cached_dc_state: Cached state of content streams |
253 | * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info |
254 | * @force_timing_sync: set via debugfs. When set, indicates that all connected |
255 | * displays will be forced to synchronize. |
256 | * @dmcub_trace_event_en: enable dmcub trace events |
257 | * @dmub_outbox_params: DMUB Outbox parameters |
258 | * @num_of_edps: number of backlight eDPs |
259 | * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the |
260 | * driver when true |
261 | * @dmub_aux_transfer_done: struct completion used to indicate when DMUB |
262 | * transfers are done |
263 | * @delayed_hpd_wq: work queue used to delay DMUB HPD work |
264 | */ |
265 | struct amdgpu_display_manager { |
266 | |
267 | struct dc *dc; |
268 | |
269 | /** |
270 | * @dmub_srv: |
271 | * |
272 | * DMUB service, used for controlling the DMUB on hardware |
273 | * that supports it. The pointer to the dmub_srv will be |
274 | * NULL on hardware that does not support it. |
275 | */ |
276 | struct dmub_srv *dmub_srv; |
277 | |
278 | /** |
279 | * @dmub_notify: |
280 | * |
281 | * Notification from DMUB. |
282 | */ |
283 | |
284 | struct dmub_notification *dmub_notify; |
285 | |
286 | /** |
287 | * @dmub_callback: |
288 | * |
289 | * Callback functions to handle notification from DMUB. |
290 | */ |
291 | |
292 | dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; |
293 | |
294 | /** |
295 | * @dmub_thread_offload: |
296 | * |
297 | * Flag to indicate if callback is offload. |
298 | */ |
299 | |
300 | bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; |
301 | |
302 | /** |
303 | * @dmub_fb_info: |
304 | * |
305 | * Framebuffer regions for the DMUB. |
306 | */ |
307 | struct dmub_srv_fb_info *dmub_fb_info; |
308 | |
309 | /** |
310 | * @dmub_fw: |
311 | * |
312 | * DMUB firmware, required on hardware that has DMUB support. |
313 | */ |
314 | const struct firmware *dmub_fw; |
315 | |
316 | /** |
317 | * @dmub_bo: |
318 | * |
319 | * Buffer object for the DMUB. |
320 | */ |
321 | struct amdgpu_bo *dmub_bo; |
322 | |
323 | /** |
324 | * @dmub_bo_gpu_addr: |
325 | * |
326 | * GPU virtual address for the DMUB buffer object. |
327 | */ |
328 | u64 dmub_bo_gpu_addr; |
329 | |
330 | /** |
331 | * @dmub_bo_cpu_addr: |
332 | * |
333 | * CPU address for the DMUB buffer object. |
334 | */ |
335 | void *dmub_bo_cpu_addr; |
336 | |
337 | /** |
338 | * @dmcub_fw_version: |
339 | * |
340 | * DMCUB firmware version. |
341 | */ |
342 | uint32_t dmcub_fw_version; |
343 | |
344 | /** |
345 | * @cgs_device: |
346 | * |
347 | * The Common Graphics Services device. It provides an interface for |
348 | * accessing registers. |
349 | */ |
350 | struct cgs_device *cgs_device; |
351 | |
352 | struct amdgpu_device *adev; |
353 | struct drm_device *ddev; |
354 | u16 display_indexes_num; |
355 | |
356 | /** |
357 | * @atomic_obj: |
358 | * |
359 | * In combination with &dm_atomic_state it helps manage |
360 | * global atomic state that doesn't map cleanly into existing |
361 | * drm resources, like &dc_context. |
362 | */ |
363 | struct drm_private_obj atomic_obj; |
364 | |
365 | /** |
366 | * @dc_lock: |
367 | * |
368 | * Guards access to DC functions that can issue register write |
369 | * sequences. |
370 | */ |
371 | struct mutex dc_lock; |
372 | |
373 | /** |
374 | * @audio_lock: |
375 | * |
376 | * Guards access to audio instance changes. |
377 | */ |
378 | struct mutex audio_lock; |
379 | |
380 | /** |
381 | * @audio_component: |
382 | * |
383 | * Used to notify ELD changes to sound driver. |
384 | */ |
385 | struct drm_audio_component *audio_component; |
386 | |
387 | /** |
388 | * @audio_registered: |
389 | * |
390 | * True if the audio component has been registered |
391 | * successfully, false otherwise. |
392 | */ |
393 | bool audio_registered; |
394 | |
395 | /** |
396 | * @irq_handler_list_low_tab: |
397 | * |
398 | * Low priority IRQ handler table. |
399 | * |
400 | * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ |
401 | * source. Low priority IRQ handlers are deferred to a workqueue to be |
402 | * processed. Hence, they can sleep. |
403 | * |
404 | * Note that handlers are called in the same order as they were |
405 | * registered (FIFO). |
406 | */ |
407 | struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; |
408 | |
409 | /** |
410 | * @irq_handler_list_high_tab: |
411 | * |
412 | * High priority IRQ handler table. |
413 | * |
414 | * It is a n*m table, same as &irq_handler_list_low_tab. However, |
415 | * handlers in this table are not deferred and are called immediately. |
416 | */ |
417 | struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; |
418 | |
419 | /** |
420 | * @pflip_params: |
421 | * |
422 | * Page flip IRQ parameters, passed to registered handlers when |
423 | * triggered. |
424 | */ |
425 | struct common_irq_params |
426 | pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; |
427 | |
428 | /** |
429 | * @vblank_params: |
430 | * |
431 | * Vertical blanking IRQ parameters, passed to registered handlers when |
432 | * triggered. |
433 | */ |
434 | struct common_irq_params |
435 | vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; |
436 | |
437 | /** |
438 | * @vline0_params: |
439 | * |
440 | * OTG vertical interrupt0 IRQ parameters, passed to registered |
441 | * handlers when triggered. |
442 | */ |
443 | struct common_irq_params |
444 | vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; |
445 | |
446 | /** |
447 | * @vupdate_params: |
448 | * |
449 | * Vertical update IRQ parameters, passed to registered handlers when |
450 | * triggered. |
451 | */ |
452 | struct common_irq_params |
453 | vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; |
454 | |
455 | /** |
456 | * @dmub_trace_params: |
457 | * |
458 | * DMUB trace event IRQ parameters, passed to registered handlers when |
459 | * triggered. |
460 | */ |
461 | struct common_irq_params |
462 | dmub_trace_params[1]; |
463 | |
464 | struct common_irq_params |
465 | dmub_outbox_params[1]; |
466 | |
467 | spinlock_t irq_handler_list_table_lock; |
468 | |
469 | struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; |
470 | |
471 | const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; |
472 | |
473 | uint8_t num_of_edps; |
474 | |
475 | struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; |
476 | |
477 | struct mod_freesync *freesync_module; |
478 | struct hdcp_workqueue *hdcp_workqueue; |
479 | |
480 | /** |
481 | * @vblank_control_workqueue: |
482 | * |
483 | * Deferred work for vblank control events. |
484 | */ |
485 | struct workqueue_struct *vblank_control_workqueue; |
486 | |
487 | struct drm_atomic_state *cached_state; |
488 | struct dc_state *cached_dc_state; |
489 | |
490 | struct dm_compressor_info compressor; |
491 | |
492 | const struct firmware *fw_dmcu; |
493 | uint32_t dmcu_fw_version; |
494 | /** |
495 | * @soc_bounding_box: |
496 | * |
497 | * gpu_info FW provided soc bounding box struct or 0 if not |
498 | * available in FW |
499 | */ |
500 | const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; |
501 | |
502 | /** |
503 | * @active_vblank_irq_count: |
504 | * |
505 | * number of currently active vblank irqs |
506 | */ |
507 | uint32_t active_vblank_irq_count; |
508 | |
509 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
510 | /** |
511 | * @secure_display_ctxs: |
512 | * |
513 | * Store the ROI information and the work_struct to command dmub and psp for |
514 | * all crtcs. |
515 | */ |
516 | struct secure_display_context *secure_display_ctxs; |
517 | #endif |
518 | /** |
519 | * @hpd_rx_offload_wq: |
520 | * |
521 | * Work queue to offload works of hpd_rx_irq |
522 | */ |
523 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; |
524 | /** |
525 | * @mst_encoders: |
526 | * |
527 | * fake encoders used for DP MST. |
528 | */ |
529 | struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; |
530 | bool force_timing_sync; |
531 | bool disable_hpd_irq; |
532 | bool dmcub_trace_event_en; |
533 | /** |
534 | * @da_list: |
535 | * |
536 | * DAL fb memory allocation list, for communication with SMU. |
537 | */ |
538 | struct list_head da_list; |
539 | struct completion dmub_aux_transfer_done; |
540 | struct workqueue_struct *delayed_hpd_wq; |
541 | |
542 | /** |
543 | * @brightness: |
544 | * |
545 | * cached backlight values. |
546 | */ |
547 | u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; |
548 | /** |
549 | * @actual_brightness: |
550 | * |
551 | * last successfully applied backlight values. |
552 | */ |
553 | u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; |
554 | |
555 | /** |
556 | * @aux_hpd_discon_quirk: |
557 | * |
558 | * quirk for hpd discon while aux is on-going. |
559 | * occurred on certain intel platform |
560 | */ |
561 | bool aux_hpd_discon_quirk; |
562 | |
563 | /** |
564 | * @dpia_aux_lock: |
565 | * |
566 | * Guards access to DPIA AUX |
567 | */ |
568 | struct mutex dpia_aux_lock; |
569 | }; |
570 | |
571 | enum dsc_clock_force_state { |
572 | DSC_CLK_FORCE_DEFAULT = 0, |
573 | DSC_CLK_FORCE_ENABLE, |
574 | DSC_CLK_FORCE_DISABLE, |
575 | }; |
576 | |
577 | struct dsc_preferred_settings { |
578 | enum dsc_clock_force_state dsc_force_enable; |
579 | uint32_t dsc_num_slices_v; |
580 | uint32_t dsc_num_slices_h; |
581 | uint32_t dsc_bits_per_pixel; |
582 | bool dsc_force_disable_passthrough; |
583 | }; |
584 | |
585 | enum mst_progress_status { |
586 | MST_STATUS_DEFAULT = 0, |
587 | MST_PROBE = BIT(0), |
588 | MST_REMOTE_EDID = BIT(1), |
589 | MST_ALLOCATE_NEW_PAYLOAD = BIT(2), |
590 | MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), |
591 | }; |
592 | |
593 | /** |
594 | * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info |
595 | * |
596 | * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this |
597 | * struct is useful to keep track of the display-specific information about |
598 | * FreeSync. |
599 | */ |
600 | struct amdgpu_hdmi_vsdb_info { |
601 | /** |
602 | * @amd_vsdb_version: Vendor Specific Data Block Version, should be |
603 | * used to determine which Vendor Specific InfoFrame (VSIF) to send. |
604 | */ |
605 | unsigned int amd_vsdb_version; |
606 | |
607 | /** |
608 | * @freesync_supported: FreeSync Supported. |
609 | */ |
610 | bool freesync_supported; |
611 | |
612 | /** |
613 | * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. |
614 | */ |
615 | unsigned int min_refresh_rate_hz; |
616 | |
617 | /** |
618 | * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz |
619 | */ |
620 | unsigned int max_refresh_rate_hz; |
621 | |
622 | /** |
623 | * @replay_mode: Replay supported |
624 | */ |
625 | bool replay_mode; |
626 | }; |
627 | |
628 | struct amdgpu_dm_connector { |
629 | |
630 | struct drm_connector base; |
631 | uint32_t connector_id; |
632 | int bl_idx; |
633 | |
634 | /* we need to mind the EDID between detect |
635 | and get modes due to analog/digital/tvencoder */ |
636 | struct edid *edid; |
637 | |
638 | /* shared with amdgpu */ |
639 | struct amdgpu_hpd hpd; |
640 | |
641 | /* number of modes generated from EDID at 'dc_sink' */ |
642 | int num_modes; |
643 | |
644 | /* The 'old' sink - before an HPD. |
645 | * The 'current' sink is in dc_link->sink. */ |
646 | struct dc_sink *dc_sink; |
647 | struct dc_link *dc_link; |
648 | |
649 | /** |
650 | * @dc_em_sink: Reference to the emulated (virtual) sink. |
651 | */ |
652 | struct dc_sink *dc_em_sink; |
653 | |
654 | /* DM only */ |
655 | struct drm_dp_mst_topology_mgr mst_mgr; |
656 | struct amdgpu_dm_dp_aux dm_dp_aux; |
657 | struct drm_dp_mst_port *mst_output_port; |
658 | struct amdgpu_dm_connector *mst_root; |
659 | struct drm_dp_aux *dsc_aux; |
660 | struct mutex handle_mst_msg_ready; |
661 | |
662 | /* TODO see if we can merge with ddc_bus or make a dm_connector */ |
663 | struct amdgpu_i2c_adapter *i2c; |
664 | |
665 | /* Monitor range limits */ |
666 | /** |
667 | * @min_vfreq: Minimal frequency supported by the display in Hz. This |
668 | * value is set to zero when there is no FreeSync support. |
669 | */ |
670 | int min_vfreq; |
671 | |
672 | /** |
673 | * @max_vfreq: Maximum frequency supported by the display in Hz. This |
674 | * value is set to zero when there is no FreeSync support. |
675 | */ |
676 | int max_vfreq ; |
677 | int pixel_clock_mhz; |
678 | |
679 | /* Audio instance - protected by audio_lock. */ |
680 | int audio_inst; |
681 | |
682 | struct mutex hpd_lock; |
683 | |
684 | bool fake_enable; |
685 | bool force_yuv420_output; |
686 | struct dsc_preferred_settings dsc_settings; |
687 | union dp_downstream_port_present mst_downstream_port_present; |
688 | /* Cached display modes */ |
689 | struct drm_display_mode freesync_vid_base; |
690 | |
691 | int psr_skip_count; |
692 | |
693 | /* Record progress status of mst*/ |
694 | uint8_t mst_status; |
695 | |
696 | /* Automated testing */ |
697 | bool timing_changed; |
698 | struct dc_crtc_timing *timing_requested; |
699 | |
700 | /* Adaptive Sync */ |
701 | bool pack_sdp_v1_3; |
702 | enum adaptive_sync_type as_type; |
703 | struct amdgpu_hdmi_vsdb_info vsdb_info; |
704 | }; |
705 | |
706 | static inline void amdgpu_dm_set_mst_status(uint8_t *status, |
707 | uint8_t flags, bool set) |
708 | { |
709 | if (set) |
710 | *status |= flags; |
711 | else |
712 | *status &= ~flags; |
713 | } |
714 | |
715 | #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) |
716 | |
717 | extern const struct amdgpu_ip_block_version dm_ip_block; |
718 | |
719 | struct dm_plane_state { |
720 | struct drm_plane_state base; |
721 | struct dc_plane_state *dc_state; |
722 | }; |
723 | |
724 | struct dm_crtc_state { |
725 | struct drm_crtc_state base; |
726 | struct dc_stream_state *stream; |
727 | |
728 | bool cm_has_degamma; |
729 | bool cm_is_degamma_srgb; |
730 | |
731 | bool mpo_requested; |
732 | |
733 | int update_type; |
734 | int active_planes; |
735 | |
736 | int crc_skip_count; |
737 | |
738 | bool freesync_vrr_info_changed; |
739 | |
740 | bool dsc_force_changed; |
741 | bool vrr_supported; |
742 | struct mod_freesync_config freesync_config; |
743 | struct dc_info_packet vrr_infopacket; |
744 | |
745 | int abm_level; |
746 | }; |
747 | |
748 | #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) |
749 | |
750 | struct dm_atomic_state { |
751 | struct drm_private_state base; |
752 | |
753 | struct dc_state *context; |
754 | }; |
755 | |
756 | #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) |
757 | |
758 | struct dm_connector_state { |
759 | struct drm_connector_state base; |
760 | |
761 | enum amdgpu_rmx_type scaling; |
762 | uint8_t underscan_vborder; |
763 | uint8_t underscan_hborder; |
764 | bool underscan_enable; |
765 | bool freesync_capable; |
766 | bool update_hdcp; |
767 | uint8_t abm_level; |
768 | int vcpi_slots; |
769 | uint64_t pbn; |
770 | }; |
771 | |
772 | #define to_dm_connector_state(x)\ |
773 | container_of((x), struct dm_connector_state, base) |
774 | |
775 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); |
776 | struct drm_connector_state * |
777 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); |
778 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
779 | struct drm_connector_state *state, |
780 | struct drm_property *property, |
781 | uint64_t val); |
782 | |
783 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
784 | const struct drm_connector_state *state, |
785 | struct drm_property *property, |
786 | uint64_t *val); |
787 | |
788 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); |
789 | |
790 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
791 | struct amdgpu_dm_connector *aconnector, |
792 | int connector_type, |
793 | struct dc_link *link, |
794 | int link_index); |
795 | |
796 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
797 | struct drm_display_mode *mode); |
798 | |
799 | void dm_restore_drm_connector_state(struct drm_device *dev, |
800 | struct drm_connector *connector); |
801 | |
802 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
803 | struct edid *edid); |
804 | |
805 | void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); |
806 | |
807 | #define MAX_COLOR_LUT_ENTRIES 4096 |
808 | /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ |
809 | #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 |
810 | |
811 | void amdgpu_dm_init_color_mod(void); |
812 | int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); |
813 | int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); |
814 | int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, |
815 | struct dc_plane_state *dc_plane_state); |
816 | |
817 | void amdgpu_dm_update_connector_after_detect( |
818 | struct amdgpu_dm_connector *aconnector); |
819 | |
820 | extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; |
821 | |
822 | int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, |
823 | struct aux_payload *payload, enum aux_return_code_type *operation_result); |
824 | |
825 | int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, |
826 | struct set_config_cmd_payload *payload, enum set_config_status *operation_result); |
827 | |
828 | struct dc_stream_state * |
829 | create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
830 | const struct drm_display_mode *drm_mode, |
831 | const struct dm_connector_state *dm_state, |
832 | const struct dc_stream_state *old_stream); |
833 | |
834 | int dm_atomic_get_state(struct drm_atomic_state *state, |
835 | struct dm_atomic_state **dm_state); |
836 | |
837 | struct amdgpu_dm_connector * |
838 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, |
839 | struct drm_crtc *crtc); |
840 | |
841 | int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); |
842 | #endif /* __AMDGPU_DM_H__ */ |
843 | |