1	/*
2	* Copyright 2012-15 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*
22	* Authors: AMD
23	*
24	*/
25
26	#include "dm_services.h"
27
28	#include "resource.h"
29	#include "include/irq_service_interface.h"
30	#include "link_encoder.h"
31	#include "stream_encoder.h"
32	#include "opp.h"
33	#include "timing_generator.h"
34	#include "transform.h"
35	#include "dccg.h"
36	#include "dchubbub.h"
37	#include "dpp.h"
38	#include "core_types.h"
39	#include "set_mode_types.h"
40	#include "virtual/virtual_stream_encoder.h"
41	#include "dpcd_defs.h"
42	#include "link_enc_cfg.h"
43	#include "link.h"
44	#include "clk_mgr.h"
45	#include "virtual/virtual_link_hwss.h"
46	#include "link/hwss/link_hwss_dio.h"
47	#include "link/hwss/link_hwss_dpia.h"
48	#include "link/hwss/link_hwss_hpo_dp.h"
49	#include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h"
50	#include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
51
52	#if defined(CONFIG_DRM_AMD_DC_SI)
53	#include "dce60/dce60_resource.h"
54	#endif
55	#include "dce80/dce80_resource.h"
56	#include "dce100/dce100_resource.h"
57	#include "dce110/dce110_resource.h"
58	#include "dce112/dce112_resource.h"
59	#include "dce120/dce120_resource.h"
60	#include "dcn10/dcn10_resource.h"
61	#include "dcn20/dcn20_resource.h"
62	#include "dcn21/dcn21_resource.h"
63	#include "dcn201/dcn201_resource.h"
64	#include "dcn30/dcn30_resource.h"
65	#include "dcn301/dcn301_resource.h"
66	#include "dcn302/dcn302_resource.h"
67	#include "dcn303/dcn303_resource.h"
68	#include "dcn31/dcn31_resource.h"
69	#include "dcn314/dcn314_resource.h"
70	#include "dcn315/dcn315_resource.h"
71	#include "dcn316/dcn316_resource.h"
72	#include "../dcn32/dcn32_resource.h"
73	#include "../dcn321/dcn321_resource.h"
74	#include "dcn35/dcn35_resource.h"
75
76	#define VISUAL_CONFIRM_BASE_DEFAULT 3
77	#define VISUAL_CONFIRM_BASE_MIN 1
78	#define VISUAL_CONFIRM_BASE_MAX 10
79	/* we choose 240 because it is a common denominator of common v addressable
80	* such as 2160, 1440, 1200, 960. So we take 1/240 portion of v addressable as
81	* the visual confirm dpp offset height. So visual confirm height can stay
82	* relatively the same independent from timing used.
83	*/
84	#define VISUAL_CONFIRM_DPP_OFFSET_DENO 240
85
86	#define DC_LOGGER \
87	dc->ctx->logger
88	#define DC_LOGGER_INIT(logger)
89
90	#include "dml2/dml2_wrapper.h"
91
92	#define UNABLE_TO_SPLIT -1
93
94	enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
95	{
96	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
97
98	switch (asic_id.chip_family) {
99
100	#if defined(CONFIG_DRM_AMD_DC_SI)
101	case FAMILY_SI:
102	if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
103	ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
104	ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
105	dc_version = DCE_VERSION_6_0;
106	else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
107	dc_version = DCE_VERSION_6_4;
108	else
109	dc_version = DCE_VERSION_6_1;
110	break;
111	#endif
112	case FAMILY_CI:
113	dc_version = DCE_VERSION_8_0;
114	break;
115	case FAMILY_KV:
116	if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
117	ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
118	ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
119	dc_version = DCE_VERSION_8_3;
120	else
121	dc_version = DCE_VERSION_8_1;
122	break;
123	case FAMILY_CZ:
124	dc_version = DCE_VERSION_11_0;
125	break;
126
127	case FAMILY_VI:
128	if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
129	ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
130	dc_version = DCE_VERSION_10_0;
131	break;
132	}
133	if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
134	ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
135	ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
136	dc_version = DCE_VERSION_11_2;
137	}
138	if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
139	dc_version = DCE_VERSION_11_22;
140	break;
141	case FAMILY_AI:
142	if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
143	dc_version = DCE_VERSION_12_1;
144	else
145	dc_version = DCE_VERSION_12_0;
146	break;
147	case FAMILY_RV:
148	dc_version = DCN_VERSION_1_0;
149	if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
150	dc_version = DCN_VERSION_1_01;
151	if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
152	dc_version = DCN_VERSION_2_1;
153	if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
154	dc_version = DCN_VERSION_2_1;
155	break;
156
157	case FAMILY_NV:
158	dc_version = DCN_VERSION_2_0;
159	if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {
160	dc_version = DCN_VERSION_2_01;
161	break;
162	}
163	if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
164	dc_version = DCN_VERSION_3_0;
165	if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
166	dc_version = DCN_VERSION_3_02;
167	if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
168	dc_version = DCN_VERSION_3_03;
169	break;
170
171	case FAMILY_VGH:
172	dc_version = DCN_VERSION_3_01;
173	break;
174
175	case FAMILY_YELLOW_CARP:
176	if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
177	dc_version = DCN_VERSION_3_1;
178	break;
179	case AMDGPU_FAMILY_GC_10_3_6:
180	if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
181	dc_version = DCN_VERSION_3_15;
182	break;
183	case AMDGPU_FAMILY_GC_10_3_7:
184	if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
185	dc_version = DCN_VERSION_3_16;
186	break;
187	case AMDGPU_FAMILY_GC_11_0_0:
188	dc_version = DCN_VERSION_3_2;
189	if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
190	dc_version = DCN_VERSION_3_21;
191	break;
192	case AMDGPU_FAMILY_GC_11_0_1:
193	dc_version = DCN_VERSION_3_14;
194	break;
195	case AMDGPU_FAMILY_GC_11_5_0:
196	dc_version = DCN_VERSION_3_5;
197	break;
198	default:
199	dc_version = DCE_VERSION_UNKNOWN;
200	break;
201	}
202	return dc_version;
203	}
204
205	struct resource_pool *dc_create_resource_pool(struct dc *dc,
206	const struct dc_init_data *init_data,
207	enum dce_version dc_version)
208	{
209	struct resource_pool *res_pool = NULL;
210
211	switch (dc_version) {
212	#if defined(CONFIG_DRM_AMD_DC_SI)
213	case DCE_VERSION_6_0:
214	res_pool = dce60_create_resource_pool(
215	num_virtual_links: init_data->num_virtual_links, dc);
216	break;
217	case DCE_VERSION_6_1:
218	res_pool = dce61_create_resource_pool(
219	num_virtual_links: init_data->num_virtual_links, dc);
220	break;
221	case DCE_VERSION_6_4:
222	res_pool = dce64_create_resource_pool(
223	num_virtual_links: init_data->num_virtual_links, dc);
224	break;
225	#endif
226	case DCE_VERSION_8_0:
227	res_pool = dce80_create_resource_pool(
228	num_virtual_links: init_data->num_virtual_links, dc);
229	break;
230	case DCE_VERSION_8_1:
231	res_pool = dce81_create_resource_pool(
232	num_virtual_links: init_data->num_virtual_links, dc);
233	break;
234	case DCE_VERSION_8_3:
235	res_pool = dce83_create_resource_pool(
236	num_virtual_links: init_data->num_virtual_links, dc);
237	break;
238	case DCE_VERSION_10_0:
239	res_pool = dce100_create_resource_pool(
240	num_virtual_links: init_data->num_virtual_links, dc);
241	break;
242	case DCE_VERSION_11_0:
243	res_pool = dce110_create_resource_pool(
244	num_virtual_links: init_data->num_virtual_links, dc,
245	asic_id: init_data->asic_id);
246	break;
247	case DCE_VERSION_11_2:
248	case DCE_VERSION_11_22:
249	res_pool = dce112_create_resource_pool(
250	num_virtual_links: init_data->num_virtual_links, dc);
251	break;
252	case DCE_VERSION_12_0:
253	case DCE_VERSION_12_1:
254	res_pool = dce120_create_resource_pool(
255	num_virtual_links: init_data->num_virtual_links, dc);
256	break;
257
258	#if defined(CONFIG_DRM_AMD_DC_FP)
259	case DCN_VERSION_1_0:
260	case DCN_VERSION_1_01:
261	res_pool = dcn10_create_resource_pool(init_data, dc);
262	break;
263	case DCN_VERSION_2_0:
264	res_pool = dcn20_create_resource_pool(init_data, dc);
265	break;
266	case DCN_VERSION_2_1:
267	res_pool = dcn21_create_resource_pool(init_data, dc);
268	break;
269	case DCN_VERSION_2_01:
270	res_pool = dcn201_create_resource_pool(init_data, dc);
271	break;
272	case DCN_VERSION_3_0:
273	res_pool = dcn30_create_resource_pool(init_data, dc);
274	break;
275	case DCN_VERSION_3_01:
276	res_pool = dcn301_create_resource_pool(init_data, dc);
277	break;
278	case DCN_VERSION_3_02:
279	res_pool = dcn302_create_resource_pool(init_data, dc);
280	break;
281	case DCN_VERSION_3_03:
282	res_pool = dcn303_create_resource_pool(init_data, dc);
283	break;
284	case DCN_VERSION_3_1:
285	res_pool = dcn31_create_resource_pool(init_data, dc);
286	break;
287	case DCN_VERSION_3_14:
288	res_pool = dcn314_create_resource_pool(init_data, dc);
289	break;
290	case DCN_VERSION_3_15:
291	res_pool = dcn315_create_resource_pool(init_data, dc);
292	break;
293	case DCN_VERSION_3_16:
294	res_pool = dcn316_create_resource_pool(init_data, dc);
295	break;
296	case DCN_VERSION_3_2:
297	res_pool = dcn32_create_resource_pool(init_data, dc);
298	break;
299	case DCN_VERSION_3_21:
300	res_pool = dcn321_create_resource_pool(init_data, dc);
301	break;
302	case DCN_VERSION_3_5:
303	res_pool = dcn35_create_resource_pool(init_data, dc);
304	break;
305	#endif /* CONFIG_DRM_AMD_DC_FP */
306	default:
307	break;
308	}
309
310	if (res_pool != NULL) {
311	if (dc->ctx->dc_bios->fw_info_valid) {
312	res_pool->ref_clocks.xtalin_clock_inKhz =
313	dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
314	/* initialize with firmware data first, no all
315	* ASIC have DCCG SW component. FPGA or
316	* simulation need initialization of
317	* dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
318	* with xtalin_clock_inKhz
319	*/
320	res_pool->ref_clocks.dccg_ref_clock_inKhz =
321	res_pool->ref_clocks.xtalin_clock_inKhz;
322	res_pool->ref_clocks.dchub_ref_clock_inKhz =
323	res_pool->ref_clocks.xtalin_clock_inKhz;
324	if (dc->debug.using_dml2)
325	if (res_pool->hubbub && res_pool->hubbub->funcs->get_dchub_ref_freq)
326	res_pool->hubbub->funcs->get_dchub_ref_freq(res_pool->hubbub,
327	res_pool->ref_clocks.dccg_ref_clock_inKhz,
328	&res_pool->ref_clocks.dchub_ref_clock_inKhz);
329	} else
330	ASSERT_CRITICAL(false);
331	}
332
333	return res_pool;
334	}
335
336	void dc_destroy_resource_pool(struct dc *dc)
337	{
338	if (dc) {
339	if (dc->res_pool)
340	dc->res_pool->funcs->destroy(&dc->res_pool);
341
342	kfree(objp: dc->hwseq);
343	}
344	}
345
346	static void update_num_audio(
347	const struct resource_straps *straps,
348	unsigned int *num_audio,
349	struct audio_support *aud_support)
350	{
351	aud_support->dp_audio = true;
352	aud_support->hdmi_audio_native = false;
353	aud_support->hdmi_audio_on_dongle = false;
354
355	if (straps->hdmi_disable == 0) {
356	if (straps->dc_pinstraps_audio & 0x2) {
357	aud_support->hdmi_audio_on_dongle = true;
358	aud_support->hdmi_audio_native = true;
359	}
360	}
361
362	switch (straps->audio_stream_number) {
363	case 0: /* multi streams supported */
364	break;
365	case 1: /* multi streams not supported */
366	*num_audio = 1;
367	break;
368	default:
369	DC_ERR("DC: unexpected audio fuse!\n");
370	}
371	}
372
373	bool resource_construct(
374	unsigned int num_virtual_links,
375	struct dc *dc,
376	struct resource_pool *pool,
377	const struct resource_create_funcs *create_funcs)
378	{
379	struct dc_context *ctx = dc->ctx;
380	const struct resource_caps *caps = pool->res_cap;
381	int i;
382	unsigned int num_audio = caps->num_audio;
383	struct resource_straps straps = {0};
384
385	if (create_funcs->read_dce_straps)
386	create_funcs->read_dce_straps(dc->ctx, &straps);
387
388	pool->audio_count = 0;
389	if (create_funcs->create_audio) {
390	/* find the total number of streams available via the
391	* AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
392	* registers (one for each pin) starting from pin 1
393	* up to the max number of audio pins.
394	* We stop on the first pin where
395	* PORT_CONNECTIVITY == 1 (as instructed by HW team).
396	*/
397	update_num_audio(straps: &straps, num_audio: &num_audio, aud_support: &pool->audio_support);
398	for (i = 0; i < caps->num_audio; i++) {
399	struct audio *aud = create_funcs->create_audio(ctx, i);
400
401	if (aud == NULL) {
402	DC_ERR("DC: failed to create audio!\n");
403	return false;
404	}
405	if (!aud->funcs->endpoint_valid(aud)) {
406	aud->funcs->destroy(&aud);
407	break;
408	}
409	pool->audios[i] = aud;
410	pool->audio_count++;
411	}
412	}
413
414	pool->stream_enc_count = 0;
415	if (create_funcs->create_stream_encoder) {
416	for (i = 0; i < caps->num_stream_encoder; i++) {
417	pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
418	if (pool->stream_enc[i] == NULL)
419	DC_ERR("DC: failed to create stream_encoder!\n");
420	pool->stream_enc_count++;
421	}
422	}
423
424	pool->hpo_dp_stream_enc_count = 0;
425	if (create_funcs->create_hpo_dp_stream_encoder) {
426	for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
427	pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);
428	if (pool->hpo_dp_stream_enc[i] == NULL)
429	DC_ERR("DC: failed to create HPO DP stream encoder!\n");
430	pool->hpo_dp_stream_enc_count++;
431
432	}
433	}
434
435	pool->hpo_dp_link_enc_count = 0;
436	if (create_funcs->create_hpo_dp_link_encoder) {
437	for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
438	pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
439	if (pool->hpo_dp_link_enc[i] == NULL)
440	DC_ERR("DC: failed to create HPO DP link encoder!\n");
441	pool->hpo_dp_link_enc_count++;
442	}
443	}
444
445	for (i = 0; i < caps->num_mpc_3dlut; i++) {
446	pool->mpc_lut[i] = dc_create_3dlut_func();
447	if (pool->mpc_lut[i] == NULL)
448	DC_ERR("DC: failed to create MPC 3dlut!\n");
449	pool->mpc_shaper[i] = dc_create_transfer_func();
450	if (pool->mpc_shaper[i] == NULL)
451	DC_ERR("DC: failed to create MPC shaper!\n");
452	}
453
454	dc->caps.dynamic_audio = false;
455	if (pool->audio_count < pool->stream_enc_count) {
456	dc->caps.dynamic_audio = true;
457	}
458	for (i = 0; i < num_virtual_links; i++) {
459	pool->stream_enc[pool->stream_enc_count] =
460	virtual_stream_encoder_create(
461	ctx, bp: ctx->dc_bios);
462	if (pool->stream_enc[pool->stream_enc_count] == NULL) {
463	DC_ERR("DC: failed to create stream_encoder!\n");
464	return false;
465	}
466	pool->stream_enc_count++;
467	}
468
469	dc->hwseq = create_funcs->create_hwseq(ctx);
470
471	return true;
472	}
473	static int find_matching_clock_source(
474	const struct resource_pool *pool,
475	struct clock_source *clock_source)
476	{
477
478	int i;
479
480	for (i = 0; i < pool->clk_src_count; i++) {
481	if (pool->clock_sources[i] == clock_source)
482	return i;
483	}
484	return -1;
485	}
486
487	void resource_unreference_clock_source(
488	struct resource_context *res_ctx,
489	const struct resource_pool *pool,
490	struct clock_source *clock_source)
491	{
492	int i = find_matching_clock_source(pool, clock_source);
493
494	if (i > -1)
495	res_ctx->clock_source_ref_count[i]--;
496
497	if (pool->dp_clock_source == clock_source)
498	res_ctx->dp_clock_source_ref_count--;
499	}
500
501	void resource_reference_clock_source(
502	struct resource_context *res_ctx,
503	const struct resource_pool *pool,
504	struct clock_source *clock_source)
505	{
506	int i = find_matching_clock_source(pool, clock_source);
507
508	if (i > -1)
509	res_ctx->clock_source_ref_count[i]++;
510
511	if (pool->dp_clock_source == clock_source)
512	res_ctx->dp_clock_source_ref_count++;
513	}
514
515	int resource_get_clock_source_reference(
516	struct resource_context *res_ctx,
517	const struct resource_pool *pool,
518	struct clock_source *clock_source)
519	{
520	int i = find_matching_clock_source(pool, clock_source);
521
522	if (i > -1)
523	return res_ctx->clock_source_ref_count[i];
524
525	if (pool->dp_clock_source == clock_source)
526	return res_ctx->dp_clock_source_ref_count;
527
528	return -1;
529	}
530
531	bool resource_are_vblanks_synchronizable(
532	struct dc_stream_state *stream1,
533	struct dc_stream_state *stream2)
534	{
535	uint32_t base60_refresh_rates[] = {10, 20, 5};
536	uint8_t i;
537	uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
538	uint64_t frame_time_diff;
539
540	if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
541	stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
542	dc_is_dp_signal(signal: stream1->signal) &&
543	dc_is_dp_signal(signal: stream2->signal) &&
544	false == stream1->has_non_synchronizable_pclk &&
545	false == stream2->has_non_synchronizable_pclk &&
546	stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
547	stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
548	/* disable refresh rates higher than 60Hz for now */
549	if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
550	stream1->timing.v_total > 60)
551	return false;
552	if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
553	stream2->timing.v_total > 60)
554	return false;
555	frame_time_diff = (uint64_t)10000 *
556	stream1->timing.h_total *
557	stream1->timing.v_total *
558	stream2->timing.pix_clk_100hz;
559	frame_time_diff = div_u64(dividend: frame_time_diff, divisor: stream1->timing.pix_clk_100hz);
560	frame_time_diff = div_u64(dividend: frame_time_diff, divisor: stream2->timing.h_total);
561	frame_time_diff = div_u64(dividend: frame_time_diff, divisor: stream2->timing.v_total);
562	for (i = 0; i < rr_count; i++) {
563	int64_t diff = (int64_t)div_u64(dividend: frame_time_diff * base60_refresh_rates[i], divisor: 10) - 10000;
564
565	if (diff < 0)
566	diff = -diff;
567	if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
568	return true;
569	}
570	}
571	return false;
572	}
573
574	bool resource_are_streams_timing_synchronizable(
575	struct dc_stream_state *stream1,
576	struct dc_stream_state *stream2)
577	{
578	if (stream1->timing.h_total != stream2->timing.h_total)
579	return false;
580
581	if (stream1->timing.v_total != stream2->timing.v_total)
582	return false;
583
584	if (stream1->timing.h_addressable
585	!= stream2->timing.h_addressable)
586	return false;
587
588	if (stream1->timing.v_addressable
589	!= stream2->timing.v_addressable)
590	return false;
591
592	if (stream1->timing.v_front_porch
593	!= stream2->timing.v_front_porch)
594	return false;
595
596	if (stream1->timing.pix_clk_100hz
597	!= stream2->timing.pix_clk_100hz)
598	return false;
599
600	if (stream1->clamping.c_depth != stream2->clamping.c_depth)
601	return false;
602
603	if (stream1->phy_pix_clk != stream2->phy_pix_clk
604	&& (!dc_is_dp_signal(signal: stream1->signal)
605	|| !dc_is_dp_signal(signal: stream2->signal)))
606	return false;
607
608	if (stream1->view_format != stream2->view_format)
609	return false;
610
611	if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
612	return false;
613
614	return true;
615	}
616	static bool is_dp_and_hdmi_sharable(
617	struct dc_stream_state *stream1,
618	struct dc_stream_state *stream2)
619	{
620	if (stream1->ctx->dc->caps.disable_dp_clk_share)
621	return false;
622
623	if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
624	stream2->clamping.c_depth != COLOR_DEPTH_888)
625	return false;
626
627	return true;
628
629	}
630
631	static bool is_sharable_clk_src(
632	const struct pipe_ctx *pipe_with_clk_src,
633	const struct pipe_ctx *pipe)
634	{
635	if (pipe_with_clk_src->clock_source == NULL)
636	return false;
637
638	if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
639	return false;
640
641	if (dc_is_dp_signal(signal: pipe_with_clk_src->stream->signal) ||
642	(dc_is_dp_signal(signal: pipe->stream->signal) &&
643	!is_dp_and_hdmi_sharable(stream1: pipe_with_clk_src->stream,
644	stream2: pipe->stream)))
645	return false;
646
647	if (dc_is_hdmi_signal(signal: pipe_with_clk_src->stream->signal)
648	&& dc_is_dual_link_signal(signal: pipe->stream->signal))
649	return false;
650
651	if (dc_is_hdmi_signal(signal: pipe->stream->signal)
652	&& dc_is_dual_link_signal(signal: pipe_with_clk_src->stream->signal))
653	return false;
654
655	if (!resource_are_streams_timing_synchronizable(
656	stream1: pipe_with_clk_src->stream, stream2: pipe->stream))
657	return false;
658
659	return true;
660	}
661
662	struct clock_source *resource_find_used_clk_src_for_sharing(
663	struct resource_context *res_ctx,
664	struct pipe_ctx *pipe_ctx)
665	{
666	int i;
667
668	for (i = 0; i < MAX_PIPES; i++) {
669	if (is_sharable_clk_src(pipe_with_clk_src: &res_ctx->pipe_ctx[i], pipe: pipe_ctx))
670	return res_ctx->pipe_ctx[i].clock_source;
671	}
672
673	return NULL;
674	}
675
676	static enum pixel_format convert_pixel_format_to_dalsurface(
677	enum surface_pixel_format surface_pixel_format)
678	{
679	enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
680
681	switch (surface_pixel_format) {
682	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
683	dal_pixel_format = PIXEL_FORMAT_INDEX8;
684	break;
685	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
686	dal_pixel_format = PIXEL_FORMAT_RGB565;
687	break;
688	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
689	dal_pixel_format = PIXEL_FORMAT_RGB565;
690	break;
691	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
692	dal_pixel_format = PIXEL_FORMAT_ARGB8888;
693	break;
694	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
695	dal_pixel_format = PIXEL_FORMAT_ARGB8888;
696	break;
697	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
698	dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
699	break;
700	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
701	dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
702	break;
703	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
704	dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
705	break;
706	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
707	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
708	dal_pixel_format = PIXEL_FORMAT_FP16;
709	break;
710	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
711	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
712	dal_pixel_format = PIXEL_FORMAT_420BPP8;
713	break;
714	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
715	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
716	dal_pixel_format = PIXEL_FORMAT_420BPP10;
717	break;
718	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
719	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
720	default:
721	dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
722	break;
723	}
724	return dal_pixel_format;
725	}
726
727	static inline void get_vp_scan_direction(
728	enum dc_rotation_angle rotation,
729	bool horizontal_mirror,
730	bool *orthogonal_rotation,
731	bool *flip_vert_scan_dir,
732	bool *flip_horz_scan_dir)
733	{
734	*orthogonal_rotation = false;
735	*flip_vert_scan_dir = false;
736	*flip_horz_scan_dir = false;
737	if (rotation == ROTATION_ANGLE_180) {
738	*flip_vert_scan_dir = true;
739	*flip_horz_scan_dir = true;
740	} else if (rotation == ROTATION_ANGLE_90) {
741	*orthogonal_rotation = true;
742	*flip_horz_scan_dir = true;
743	} else if (rotation == ROTATION_ANGLE_270) {
744	*orthogonal_rotation = true;
745	*flip_vert_scan_dir = true;
746	}
747
748	if (horizontal_mirror)
749	*flip_horz_scan_dir = !*flip_horz_scan_dir;
750	}
751
752	/*
753	* This is a preliminary vp size calculation to allow us to check taps support.
754	* The result is completely overridden afterwards.
755	*/
756	static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
757	{
758	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
759
760	data->viewport.width = dc_fixpt_ceil(arg: dc_fixpt_mul_int(arg1: data->ratios.horz, arg2: data->recout.width));
761	data->viewport.height = dc_fixpt_ceil(arg: dc_fixpt_mul_int(arg1: data->ratios.vert, arg2: data->recout.height));
762	data->viewport_c.width = dc_fixpt_ceil(arg: dc_fixpt_mul_int(arg1: data->ratios.horz_c, arg2: data->recout.width));
763	data->viewport_c.height = dc_fixpt_ceil(arg: dc_fixpt_mul_int(arg1: data->ratios.vert_c, arg2: data->recout.height));
764	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
765	pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
766	swap(data->viewport.width, data->viewport.height);
767	swap(data->viewport_c.width, data->viewport_c.height);
768	}
769	}
770
771	static struct rect intersect_rec(const struct rect *r0, const struct rect *r1)
772	{
773	struct rect rec;
774	int r0_x_end = r0->x + r0->width;
775	int r1_x_end = r1->x + r1->width;
776	int r0_y_end = r0->y + r0->height;
777	int r1_y_end = r1->y + r1->height;
778
779	rec.x = r0->x > r1->x ? r0->x : r1->x;
780	rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x;
781	rec.y = r0->y > r1->y ? r0->y : r1->y;
782	rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y;
783
784	/* in case that there is no intersection */
785	if (rec.width < 0 || rec.height < 0)
786	memset(&rec, 0, sizeof(rec));
787
788	return rec;
789	}
790
791	static struct rect shift_rec(const struct rect *rec_in, int x, int y)
792	{
793	struct rect rec_out = *rec_in;
794
795	rec_out.x += x;
796	rec_out.y += y;
797
798	return rec_out;
799	}
800
801	static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ctx)
802	{
803	const struct dc_stream_state *stream = pipe_ctx->stream;
804	int odm_slice_count = resource_get_odm_slice_count(otg_master: pipe_ctx);
805	int odm_slice_idx = resource_get_odm_slice_index(opp_head: pipe_ctx);
806	bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;
807	int h_active = stream->timing.h_addressable +
808	stream->timing.h_border_left +
809	stream->timing.h_border_right;
810	int odm_slice_width = h_active / odm_slice_count;
811	struct rect odm_rec;
812
813	odm_rec.x = odm_slice_width * odm_slice_idx;
814	odm_rec.width = is_last_odm_slice ?
815	/* last slice width is the reminder of h_active */
816	h_active - odm_slice_width * (odm_slice_count - 1) :
817	/* odm slice width is the floor of h_active / count */
818	odm_slice_width;
819	odm_rec.y = 0;
820	odm_rec.height = stream->timing.v_addressable +
821	stream->timing.v_border_bottom +
822	stream->timing.v_border_top;
823
824	return odm_rec;
825	}
826
827	static struct rect calculate_plane_rec_in_timing_active(
828	struct pipe_ctx *pipe_ctx,
829	const struct rect *rec_in)
830	{
831	/*
832	* The following diagram shows an example where we map a 1920x1200
833	* desktop to a 2560x1440 timing with a plane rect in the middle
834	* of the screen. To map a plane rect from Stream Source to Timing
835	* Active space, we first multiply stream scaling ratios (i.e 2304/1920
836	* horizontal and 1440/1200 vertical) to the plane's x and y, then
837	* we add stream destination offsets (i.e 128 horizontal, 0 vertical).
838	* This will give us a plane rect's position in Timing Active. However
839	* we have to remove the fractional. The rule is that we find left/right
840	* and top/bottom positions and round the value to the adjacent integer.
841	*
842	* Stream Source Space
843	* ------------
844	* __________________________________________________
845	* |Stream Source (1920 x 1200) ^ |
846	* | y |
847	* | <------- w --------|> |
848	* | __________________V |
849	* |<-- x -->|Plane//////////////| ^ |
850	* | |(pre scale)////////| | |
851	* | |///////////////////| | |
852	* | |///////////////////| h |
853	* | |///////////////////| | |
854	* | |///////////////////| | |
855	* | |///////////////////| V |
856	* | |
857	* | |
858	* |__________________________________________________|
859	*
860	*
861	* Timing Active Space
862	* ---------------------------------
863	*
864	* Timing Active (2560 x 1440)
865	* __________________________________________________
866	* |*****| Stteam Destination (2304 x 1440) |*****|
867	* |*****| |*****|
868	* |<128>| |*****|
869	* |*****| __________________ |*****|
870	* |*****| |Plane/////////////| |*****|
871	* |*****| |(post scale)//////| |*****|
872	* |*****| |//////////////////| |*****|
873	* |*****| |//////////////////| |*****|
874	* |*****| |//////////////////| |*****|
875	* |*****| |//////////////////| |*****|
876	* |*****| |*****|
877	* |*****| |*****|
878	* |*****| |*****|
879	* |*****|______________________________________|*****|
880	*
881	* So the resulting formulas are shown below:
882	*
883	* recout_x = 128 + round(plane_x * 2304 / 1920)
884	* recout_w = 128 + round((plane_x + plane_w) * 2304 / 1920) - recout_x
885	* recout_y = 0 + round(plane_y * 1440 / 1280)
886	* recout_h = 0 + round((plane_y + plane_h) * 1440 / 1200) - recout_y
887	*
888	* NOTE: fixed point division is not error free. To reduce errors
889	* introduced by fixed point division, we divide only after
890	* multiplication is complete.
891	*/
892	const struct dc_stream_state *stream = pipe_ctx->stream;
893	struct rect rec_out = {0};
894	struct fixed31_32 temp;
895
896	temp = dc_fixpt_from_fraction(numerator: rec_in->x * stream->dst.width,
897	denominator: stream->src.width);
898	rec_out.x = stream->dst.x + dc_fixpt_round(arg: temp);
899
900	temp = dc_fixpt_from_fraction(
901	numerator: (rec_in->x + rec_in->width) * stream->dst.width,
902	denominator: stream->src.width);
903	rec_out.width = stream->dst.x + dc_fixpt_round(arg: temp) - rec_out.x;
904
905	temp = dc_fixpt_from_fraction(numerator: rec_in->y * stream->dst.height,
906	denominator: stream->src.height);
907	rec_out.y = stream->dst.y + dc_fixpt_round(arg: temp);
908
909	temp = dc_fixpt_from_fraction(
910	numerator: (rec_in->y + rec_in->height) * stream->dst.height,
911	denominator: stream->src.height);
912	rec_out.height = stream->dst.y + dc_fixpt_round(arg: temp) - rec_out.y;
913
914	return rec_out;
915	}
916
917	static struct rect calculate_mpc_slice_in_timing_active(
918	struct pipe_ctx *pipe_ctx,
919	struct rect *plane_clip_rec)
920	{
921	const struct dc_stream_state *stream = pipe_ctx->stream;
922	int mpc_slice_count = resource_get_mpc_slice_count(opp_head: pipe_ctx);
923	int mpc_slice_idx = resource_get_mpc_slice_index(dpp_pipe: pipe_ctx);
924	int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1;
925	struct rect mpc_rec;
926
927	mpc_rec.width = plane_clip_rec->width / mpc_slice_count;
928	mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx;
929	mpc_rec.height = plane_clip_rec->height;
930	mpc_rec.y = plane_clip_rec->y;
931	ASSERT(mpc_slice_count == 1 ||
932	stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE ||
933	mpc_rec.width % 2 == 0);
934
935	/* extra pixels in the division remainder need to go to pipes after
936	* the extra pixel index minus one(epimo) defined here as:
937	*/
938	if (mpc_slice_idx > epimo) {
939	mpc_rec.x += mpc_slice_idx - epimo - 1;
940	mpc_rec.width += 1;
941	}
942
943	if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
944	ASSERT(mpc_rec.height % 2 == 0);
945	mpc_rec.height /= 2;
946	}
947	return mpc_rec;
948	}
949
950	static void adjust_recout_for_visual_confirm(struct rect *recout,
951	struct pipe_ctx *pipe_ctx)
952	{
953	struct dc *dc = pipe_ctx->stream->ctx->dc;
954	int dpp_offset, base_offset;
955
956	if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)
957	return;
958
959	dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;
960	dpp_offset *= pipe_ctx->plane_res.dpp->inst;
961
962	if ((dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_BASE_MIN) &&
963	dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_BASE_MAX)
964	base_offset = dc->debug.visual_confirm_rect_height;
965	else
966	base_offset = VISUAL_CONFIRM_BASE_DEFAULT;
967
968	recout->height -= base_offset;
969	recout->height -= dpp_offset;
970	}
971
972	/*
973	* The function maps a plane clip from Stream Source Space to ODM Slice Space
974	* and calculates the rec of the overlapping area of MPC slice of the plane
975	* clip, ODM slice associated with the pipe context and stream destination rec.
976	*/
977	static void calculate_recout(struct pipe_ctx *pipe_ctx)
978	{
979	/*
980	* A plane clip represents the desired plane size and position in Stream
981	* Source Space. Stream Source is the destination where all planes are
982	* blended (i.e. positioned, scaled and overlaid). It is a canvas where
983	* all planes associated with the current stream are drawn together.
984	* After Stream Source is completed, we will further scale and
985	* reposition the entire canvas of the stream source to Stream
986	* Destination in Timing Active Space. This could be due to display
987	* overscan adjustment where we will need to rescale and reposition all
988	* the planes so they can fit into a TV with overscan or downscale
989	* upscale features such as GPU scaling or VSR.
990	*
991	* This two step blending is a virtual procedure in software. In
992	* hardware there is no such thing as Stream Source. all planes are
993	* blended once in Timing Active Space. Software virtualizes a Stream
994	* Source space to decouple the math complicity so scaling param
995	* calculation focuses on one step at a time.
996	*
997	* In the following two diagrams, user applied 10% overscan adjustment
998	* so the Stream Source needs to be scaled down a little before mapping
999	* to Timing Active Space. As a result the Plane Clip is also scaled
1000	* down by the same ratio, Plane Clip position (i.e. x and y) with
1001	* respect to Stream Source is also scaled down. To map it in Timing
1002	* Active Space additional x and y offsets from Stream Destination are
1003	* added to Plane Clip as well.
1004	*
1005	* Stream Source Space
1006	* ------------
1007	* __________________________________________________
1008	* |Stream Source (3840 x 2160) ^ |
1009	* | y |
1010	* | | |
1011	* | __________________V |
1012	* |<-- x -->|Plane Clip/////////| |
1013	* | |(pre scale)////////| |
1014	* | |///////////////////| |
1015	* | |///////////////////| |
1016	* | |///////////////////| |
1017	* | |///////////////////| |
1018	* | |///////////////////| |
1019	* | |
1020	* | |
1021	* |__________________________________________________|
1022	*
1023	*
1024	* Timing Active Space (3840 x 2160)
1025	* ---------------------------------
1026	*
1027	* Timing Active
1028	* __________________________________________________
1029	* | y_____________________________________________ |
1030	* |x |Stream Destination (3456 x 1944) | |
1031	* | | | |
1032	* | | __________________ | |
1033	* | | |Plane Clip////////| | |
1034	* | | |(post scale)//////| | |
1035	* | | |//////////////////| | |
1036	* | | |//////////////////| | |
1037	* | | |//////////////////| | |
1038	* | | |//////////////////| | |
1039	* | | | |
1040	* | | | |
1041	* | |____________________________________________| |
1042	* |__________________________________________________|
1043	*
1044	*
1045	* In Timing Active Space a plane clip could be further sliced into
1046	* pieces called MPC slices. Each Pipe Context is responsible for
1047	* processing only one MPC slice so the plane processing workload can be
1048	* distributed to multiple DPP Pipes. MPC slices could be blended
1049	* together to a single ODM slice. Each ODM slice is responsible for
1050	* processing a portion of Timing Active divided horizontally so the
1051	* output pixel processing workload can be distributed to multiple OPP
1052	* pipes. All ODM slices are mapped together in ODM block so all MPC
1053	* slices belong to different ODM slices could be pieced together to
1054	* form a single image in Timing Active. MPC slices must belong to
1055	* single ODM slice. If an MPC slice goes across ODM slice boundary, it
1056	* needs to be divided into two MPC slices one for each ODM slice.
1057	*
1058	* In the following diagram the output pixel processing workload is
1059	* divided horizontally into two ODM slices one for each OPP blend tree.
1060	* OPP0 blend tree is responsible for processing left half of Timing
1061	* Active, while OPP2 blend tree is responsible for processing right
1062	* half.
1063	*
1064	* The plane has two MPC slices. However since the right MPC slice goes
1065	* across ODM boundary, two DPP pipes are needed one for each OPP blend
1066	* tree. (i.e. DPP1 for OPP0 blend tree and DPP2 for OPP2 blend tree).
1067	*
1068	* Assuming that we have a Pipe Context associated with OPP0 and DPP1
1069	* working on processing the plane in the diagram. We want to know the
1070	* width and height of the shaded rectangle and its relative position
1071	* with respect to the ODM slice0. This is called the recout of the pipe
1072	* context.
1073	*
1074	* Planes can be at arbitrary size and position and there could be an
1075	* arbitrary number of MPC and ODM slices. The algorithm needs to take
1076	* all scenarios into account.
1077	*
1078	* Timing Active Space (3840 x 2160)
1079	* ---------------------------------
1080	*
1081	* Timing Active
1082	* __________________________________________________
1083	* |OPP0(ODM slice0)^ |OPP2(ODM slice1) |
1084	* | y | |
1085	* | | <- w -> |
1086	* | _____V________|____ |
1087	* | |DPP0 ^ |DPP1 |DPP2| |
1088	* |<------ x |-----|->|/////| | |
1089	* | | | |/////| | |
1090	* | | h |/////| | |
1091	* | | | |/////| | |
1092	* | |_____V__|/////|____| |
1093	* | | |
1094	* | | |
1095	* | | |
1096	* |_________________________|________________________|
1097	*
1098	*
1099	*/
1100	struct rect plane_clip;
1101	struct rect mpc_slice_of_plane_clip;
1102	struct rect odm_slice;
1103	struct rect overlapping_area;
1104
1105	plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,
1106	rec_in: &pipe_ctx->plane_state->clip_rect);
1107	/* guard plane clip from drawing beyond stream dst here */
1108	plane_clip = intersect_rec(r0: &plane_clip,
1109	r1: &pipe_ctx->stream->dst);
1110	mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active(
1111	pipe_ctx, plane_clip_rec: &plane_clip);
1112	odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);
1113	overlapping_area = intersect_rec(r0: &mpc_slice_of_plane_clip, r1: &odm_slice);
1114	if (overlapping_area.height > 0 &&
1115	overlapping_area.width > 0) {
1116	/* shift the overlapping area so it is with respect to current
1117	* ODM slice's position
1118	*/
1119	pipe_ctx->plane_res.scl_data.recout = shift_rec(
1120	rec_in: &overlapping_area,
1121	x: -odm_slice.x, y: -odm_slice.y);
1122	adjust_recout_for_visual_confirm(
1123	recout: &pipe_ctx->plane_res.scl_data.recout,
1124	pipe_ctx);
1125	} else {
1126	/* if there is no overlap, zero recout */
1127	memset(&pipe_ctx->plane_res.scl_data.recout, 0,
1128	sizeof(struct rect));
1129	}
1130
1131	}
1132
1133	static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
1134	{
1135	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1136	const struct dc_stream_state *stream = pipe_ctx->stream;
1137	struct rect surf_src = plane_state->src_rect;
1138	const int in_w = stream->src.width;
1139	const int in_h = stream->src.height;
1140	const int out_w = stream->dst.width;
1141	const int out_h = stream->dst.height;
1142
1143	/*Swap surf_src height and width since scaling ratios are in recout rotation*/
1144	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
1145	pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
1146	swap(surf_src.height, surf_src.width);
1147
1148	pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
1149	numerator: surf_src.width,
1150	denominator: plane_state->dst_rect.width);
1151	pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
1152	numerator: surf_src.height,
1153	denominator: plane_state->dst_rect.height);
1154
1155	if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1156	pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
1157	else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1158	pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
1159
1160	pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
1161	dividend: pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, divisor: out_h);
1162	pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
1163	dividend: pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, divisor: out_w);
1164
1165	pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
1166	pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
1167
1168	if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
1169	|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
1170	pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
1171	pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
1172	}
1173	pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
1174	arg: pipe_ctx->plane_res.scl_data.ratios.horz, frac_bits: 19);
1175	pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
1176	arg: pipe_ctx->plane_res.scl_data.ratios.vert, frac_bits: 19);
1177	pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
1178	arg: pipe_ctx->plane_res.scl_data.ratios.horz_c, frac_bits: 19);
1179	pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
1180	arg: pipe_ctx->plane_res.scl_data.ratios.vert_c, frac_bits: 19);
1181	}
1182
1183
1184	/*
1185	* We completely calculate vp offset, size and inits here based entirely on scaling
1186	* ratios and recout for pixel perfect pipe combine.
1187	*/
1188	static void calculate_init_and_vp(
1189	bool flip_scan_dir,
1190	int recout_offset_within_recout_full,
1191	int recout_size,
1192	int src_size,
1193	int taps,
1194	struct fixed31_32 ratio,
1195	struct fixed31_32 *init,
1196	int *vp_offset,
1197	int *vp_size)
1198	{
1199	struct fixed31_32 temp;
1200	int int_part;
1201
1202	/*
1203	* First of the taps starts sampling pixel number <init_int_part> corresponding to recout
1204	* pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
1205	* All following calculations are based on this logic.
1206	*
1207	* Init calculated according to formula:
1208	* init = (scaling_ratio + number_of_taps + 1) / 2
1209	* init_bot = init + scaling_ratio
1210	* to get pixel perfect combine add the fraction from calculating vp offset
1211	*/
1212	temp = dc_fixpt_mul_int(arg1: ratio, arg2: recout_offset_within_recout_full);
1213	*vp_offset = dc_fixpt_floor(arg: temp);
1214	temp.value &= 0xffffffff;
1215	*init = dc_fixpt_truncate(arg: dc_fixpt_add(arg1: dc_fixpt_div_int(
1216	arg1: dc_fixpt_add_int(arg1: ratio, arg2: taps + 1), arg2: 2), arg2: temp), frac_bits: 19);
1217	/*
1218	* If viewport has non 0 offset and there are more taps than covered by init then
1219	* we should decrease the offset and increase init so we are never sampling
1220	* outside of viewport.
1221	*/
1222	int_part = dc_fixpt_floor(arg: *init);
1223	if (int_part < taps) {
1224	int_part = taps - int_part;
1225	if (int_part > *vp_offset)
1226	int_part = *vp_offset;
1227	*vp_offset -= int_part;
1228	*init = dc_fixpt_add_int(arg1: *init, arg2: int_part);
1229	}
1230	/*
1231	* If taps are sampling outside of viewport at end of recout and there are more pixels
1232	* available in the surface we should increase the viewport size, regardless set vp to
1233	* only what is used.
1234	*/
1235	temp = dc_fixpt_add(arg1: *init, arg2: dc_fixpt_mul_int(arg1: ratio, arg2: recout_size - 1));
1236	*vp_size = dc_fixpt_floor(arg: temp);
1237	if (*vp_size + *vp_offset > src_size)
1238	*vp_size = src_size - *vp_offset;
1239
1240	/* We did all the math assuming we are scanning same direction as display does,
1241	* however mirror/rotation changes how vp scans vs how it is offset. If scan direction
1242	* is flipped we simply need to calculate offset from the other side of plane.
1243	* Note that outside of viewport all scaling hardware works in recout space.
1244	*/
1245	if (flip_scan_dir)
1246	*vp_offset = src_size - *vp_offset - *vp_size;
1247	}
1248
1249	static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
1250	{
1251	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1252	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
1253	struct rect src = plane_state->src_rect;
1254	struct rect recout_dst_in_active_timing;
1255	struct rect recout_clip_in_active_timing;
1256	struct rect recout_clip_in_recout_dst;
1257	struct rect overlap_in_active_timing;
1258	struct rect odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);
1259	int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
1260	|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1261	bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
1262
1263	recout_clip_in_active_timing = shift_rec(
1264	rec_in: &data->recout, x: odm_slice.x, y: odm_slice.y);
1265	recout_dst_in_active_timing = calculate_plane_rec_in_timing_active(
1266	pipe_ctx, rec_in: &plane_state->dst_rect);
1267	overlap_in_active_timing = intersect_rec(r0: &recout_clip_in_active_timing,
1268	r1: &recout_dst_in_active_timing);
1269	if (overlap_in_active_timing.width > 0 &&
1270	overlap_in_active_timing.height > 0)
1271	recout_clip_in_recout_dst = shift_rec(rec_in: &overlap_in_active_timing,
1272	x: -recout_dst_in_active_timing.x,
1273	y: -recout_dst_in_active_timing.y);
1274	else
1275	memset(&recout_clip_in_recout_dst, 0, sizeof(struct rect));
1276
1277	/*
1278	* Work in recout rotation since that requires less transformations
1279	*/
1280	get_vp_scan_direction(
1281	rotation: plane_state->rotation,
1282	horizontal_mirror: plane_state->horizontal_mirror,
1283	orthogonal_rotation: &orthogonal_rotation,
1284	flip_vert_scan_dir: &flip_vert_scan_dir,
1285	flip_horz_scan_dir: &flip_horz_scan_dir);
1286
1287	if (orthogonal_rotation) {
1288	swap(src.width, src.height);
1289	swap(flip_vert_scan_dir, flip_horz_scan_dir);
1290	}
1291
1292	calculate_init_and_vp(
1293	flip_scan_dir: flip_horz_scan_dir,
1294	recout_offset_within_recout_full: recout_clip_in_recout_dst.x,
1295	recout_size: data->recout.width,
1296	src_size: src.width,
1297	taps: data->taps.h_taps,
1298	ratio: data->ratios.horz,
1299	init: &data->inits.h,
1300	vp_offset: &data->viewport.x,
1301	vp_size: &data->viewport.width);
1302	calculate_init_and_vp(
1303	flip_scan_dir: flip_horz_scan_dir,
1304	recout_offset_within_recout_full: recout_clip_in_recout_dst.x,
1305	recout_size: data->recout.width,
1306	src_size: src.width / vpc_div,
1307	taps: data->taps.h_taps_c,
1308	ratio: data->ratios.horz_c,
1309	init: &data->inits.h_c,
1310	vp_offset: &data->viewport_c.x,
1311	vp_size: &data->viewport_c.width);
1312	calculate_init_and_vp(
1313	flip_scan_dir: flip_vert_scan_dir,
1314	recout_offset_within_recout_full: recout_clip_in_recout_dst.y,
1315	recout_size: data->recout.height,
1316	src_size: src.height,
1317	taps: data->taps.v_taps,
1318	ratio: data->ratios.vert,
1319	init: &data->inits.v,
1320	vp_offset: &data->viewport.y,
1321	vp_size: &data->viewport.height);
1322	calculate_init_and_vp(
1323	flip_scan_dir: flip_vert_scan_dir,
1324	recout_offset_within_recout_full: recout_clip_in_recout_dst.y,
1325	recout_size: data->recout.height,
1326	src_size: src.height / vpc_div,
1327	taps: data->taps.v_taps_c,
1328	ratio: data->ratios.vert_c,
1329	init: &data->inits.v_c,
1330	vp_offset: &data->viewport_c.y,
1331	vp_size: &data->viewport_c.height);
1332	if (orthogonal_rotation) {
1333	swap(data->viewport.x, data->viewport.y);
1334	swap(data->viewport.width, data->viewport.height);
1335	swap(data->viewport_c.x, data->viewport_c.y);
1336	swap(data->viewport_c.width, data->viewport_c.height);
1337	}
1338	data->viewport.x += src.x;
1339	data->viewport.y += src.y;
1340	ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1341	data->viewport_c.x += src.x / vpc_div;
1342	data->viewport_c.y += src.y / vpc_div;
1343	}
1344
1345	static bool is_subvp_high_refresh_candidate(struct dc_stream_state *stream)
1346	{
1347	uint32_t refresh_rate;
1348	struct dc *dc = stream->ctx->dc;
1349
1350	refresh_rate = (stream->timing.pix_clk_100hz * (uint64_t)100 +
1351	stream->timing.v_total * stream->timing.h_total - (uint64_t)1);
1352	refresh_rate = div_u64(dividend: refresh_rate, divisor: stream->timing.v_total);
1353	refresh_rate = div_u64(dividend: refresh_rate, divisor: stream->timing.h_total);
1354
1355	/* If there's any stream that fits the SubVP high refresh criteria,
1356	* we must return true. This is because cursor updates are asynchronous
1357	* with full updates, so we could transition into a SubVP config and
1358	* remain in HW cursor mode if there's no cursor update which will
1359	* then cause corruption.
1360	*/
1361	if ((refresh_rate >= 120 && refresh_rate <= 175 &&
1362	stream->timing.v_addressable >= 1080 &&
1363	stream->timing.v_addressable <= 2160) &&
1364	(dc->current_state->stream_count > 1 ||
1365	(dc->current_state->stream_count == 1 && !stream->allow_freesync)))
1366	return true;
1367
1368	return false;
1369	}
1370
1371	static enum controller_dp_test_pattern convert_dp_to_controller_test_pattern(
1372	enum dp_test_pattern test_pattern)
1373	{
1374	enum controller_dp_test_pattern controller_test_pattern;
1375
1376	switch (test_pattern) {
1377	case DP_TEST_PATTERN_COLOR_SQUARES:
1378	controller_test_pattern =
1379	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1380	break;
1381	case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
1382	controller_test_pattern =
1383	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
1384	break;
1385	case DP_TEST_PATTERN_VERTICAL_BARS:
1386	controller_test_pattern =
1387	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
1388	break;
1389	case DP_TEST_PATTERN_HORIZONTAL_BARS:
1390	controller_test_pattern =
1391	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
1392	break;
1393	case DP_TEST_PATTERN_COLOR_RAMP:
1394	controller_test_pattern =
1395	CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
1396	break;
1397	default:
1398	controller_test_pattern =
1399	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1400	break;
1401	}
1402
1403	return controller_test_pattern;
1404	}
1405
1406	static enum controller_dp_color_space convert_dp_to_controller_color_space(
1407	enum dp_test_pattern_color_space color_space)
1408	{
1409	enum controller_dp_color_space controller_color_space;
1410
1411	switch (color_space) {
1412	case DP_TEST_PATTERN_COLOR_SPACE_RGB:
1413	controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1414	break;
1415	case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
1416	controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
1417	break;
1418	case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
1419	controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
1420	break;
1421	case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
1422	default:
1423	controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1424	break;
1425	}
1426
1427	return controller_color_space;
1428	}
1429
1430	void resource_build_test_pattern_params(struct resource_context *res_ctx,
1431	struct pipe_ctx *otg_master)
1432	{
1433	int odm_slice_width, last_odm_slice_width, offset = 0;
1434	struct pipe_ctx *opp_heads[MAX_PIPES];
1435	struct test_pattern_params *params;
1436	int odm_cnt = 1;
1437	enum controller_dp_test_pattern controller_test_pattern;
1438	enum controller_dp_color_space controller_color_space;
1439	enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth;
1440	int h_active = otg_master->stream->timing.h_addressable +
1441	otg_master->stream->timing.h_border_left +
1442	otg_master->stream->timing.h_border_right;
1443	int v_active = otg_master->stream->timing.v_addressable +
1444	otg_master->stream->timing.v_border_bottom +
1445	otg_master->stream->timing.v_border_top;
1446	int i;
1447
1448	controller_test_pattern = convert_dp_to_controller_test_pattern(
1449	test_pattern: otg_master->stream->test_pattern.type);
1450	controller_color_space = convert_dp_to_controller_color_space(
1451	color_space: otg_master->stream->test_pattern.color_space);
1452
1453	odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);
1454
1455	odm_slice_width = h_active / odm_cnt;
1456	last_odm_slice_width = h_active - odm_slice_width * (odm_cnt - 1);
1457
1458	for (i = 0; i < odm_cnt; i++) {
1459	params = &opp_heads[i]->stream_res.test_pattern_params;
1460	params->test_pattern = controller_test_pattern;
1461	params->color_space = controller_color_space;
1462	params->color_depth = color_depth;
1463	params->height = v_active;
1464	params->offset = offset;
1465
1466	if (i < odm_cnt - 1)
1467	params->width = odm_slice_width;
1468	else
1469	params->width = last_odm_slice_width;
1470
1471	offset += odm_slice_width;
1472	}
1473	}
1474
1475	bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1476	{
1477	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1478	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1479	const struct rect odm_slice_rec = calculate_odm_slice_in_timing_active(pipe_ctx);
1480	bool res = false;
1481	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1482
1483	/* Invalid input */
1484	if (!plane_state->dst_rect.width ||
1485	!plane_state->dst_rect.height ||
1486	!plane_state->src_rect.width ||
1487	!plane_state->src_rect.height) {
1488	ASSERT(0);
1489	return false;
1490	}
1491
1492	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1493	surface_pixel_format: pipe_ctx->plane_state->format);
1494
1495	/* Timing borders are part of vactive that we are also supposed to skip in addition
1496	* to any stream dst offset. Since dm logic assumes dst is in addressable
1497	* space we need to add the left and top borders to dst offsets temporarily.
1498	* TODO: fix in DM, stream dst is supposed to be in vactive
1499	*/
1500	pipe_ctx->stream->dst.x += timing->h_border_left;
1501	pipe_ctx->stream->dst.y += timing->v_border_top;
1502
1503	/* Calculate H and V active size */
1504	pipe_ctx->plane_res.scl_data.h_active = odm_slice_rec.width;
1505	pipe_ctx->plane_res.scl_data.v_active = odm_slice_rec.height;
1506
1507	/* depends on h_active */
1508	calculate_recout(pipe_ctx);
1509	/* depends on pixel format */
1510	calculate_scaling_ratios(pipe_ctx);
1511	/* depends on scaling ratios and recout, does not calculate offset yet */
1512	calculate_viewport_size(pipe_ctx);
1513
1514	/*
1515	* LB calculations depend on vp size, h/v_active and scaling ratios
1516	* Setting line buffer pixel depth to 24bpp yields banding
1517	* on certain displays, such as the Sharp 4k. 36bpp is needed
1518	* to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1519	* SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1520	* precision on DCN display engines, but apparently not for DCE, as
1521	* far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
1522	* problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1523	* neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
1524	* passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
1525	*/
1526	if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1527	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1528	else
1529	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1530
1531	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1532
1533	if (pipe_ctx->plane_res.xfm != NULL)
1534	res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1535	pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1536
1537	if (pipe_ctx->plane_res.dpp != NULL)
1538	res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1539	pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1540
1541
1542	if (!res) {
1543	/* Try 24 bpp linebuffer */
1544	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1545
1546	if (pipe_ctx->plane_res.xfm != NULL)
1547	res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1548	pipe_ctx->plane_res.xfm,
1549	&pipe_ctx->plane_res.scl_data,
1550	&plane_state->scaling_quality);
1551
1552	if (pipe_ctx->plane_res.dpp != NULL)
1553	res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1554	pipe_ctx->plane_res.dpp,
1555	&pipe_ctx->plane_res.scl_data,
1556	&plane_state->scaling_quality);
1557	}
1558
1559	/*
1560	* Depends on recout, scaling ratios, h_active and taps
1561	* May need to re-check lb size after this in some obscure scenario
1562	*/
1563	if (res)
1564	calculate_inits_and_viewports(pipe_ctx);
1565
1566	/*
1567	* Handle side by side and top bottom 3d recout offsets after vp calculation
1568	* since 3d is special and needs to calculate vp as if there is no recout offset
1569	* This may break with rotation, good thing we aren't mixing hw rotation and 3d
1570	*/
1571	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1572	ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1573	(pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1574	pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1575	if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1576	pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1577	else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1578	pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1579	}
1580
1581	/* Clamp minimum viewport size */
1582	if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
1583	pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
1584	if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1585	pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
1586
1587
1588	DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1589	"src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1590	__func__,
1591	pipe_ctx->pipe_idx,
1592	pipe_ctx->plane_res.scl_data.viewport.height,
1593	pipe_ctx->plane_res.scl_data.viewport.width,
1594	pipe_ctx->plane_res.scl_data.viewport.x,
1595	pipe_ctx->plane_res.scl_data.viewport.y,
1596	pipe_ctx->plane_res.scl_data.recout.height,
1597	pipe_ctx->plane_res.scl_data.recout.width,
1598	pipe_ctx->plane_res.scl_data.recout.x,
1599	pipe_ctx->plane_res.scl_data.recout.y,
1600	pipe_ctx->plane_res.scl_data.h_active,
1601	pipe_ctx->plane_res.scl_data.v_active,
1602	plane_state->src_rect.height,
1603	plane_state->src_rect.width,
1604	plane_state->src_rect.x,
1605	plane_state->src_rect.y,
1606	plane_state->dst_rect.height,
1607	plane_state->dst_rect.width,
1608	plane_state->dst_rect.x,
1609	plane_state->dst_rect.y,
1610	plane_state->clip_rect.height,
1611	plane_state->clip_rect.width,
1612	plane_state->clip_rect.x,
1613	plane_state->clip_rect.y);
1614
1615	pipe_ctx->stream->dst.x -= timing->h_border_left;
1616	pipe_ctx->stream->dst.y -= timing->v_border_top;
1617
1618	return res;
1619	}
1620
1621
1622	enum dc_status resource_build_scaling_params_for_context(
1623	const struct dc *dc,
1624	struct dc_state *context)
1625	{
1626	int i;
1627
1628	for (i = 0; i < MAX_PIPES; i++) {
1629	if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1630	context->res_ctx.pipe_ctx[i].stream != NULL)
1631	if (!resource_build_scaling_params(pipe_ctx: &context->res_ctx.pipe_ctx[i]))
1632	return DC_FAIL_SCALING;
1633	}
1634
1635	return DC_OK;
1636	}
1637
1638	struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
1639	struct resource_context *res_ctx,
1640	const struct resource_pool *pool,
1641	const struct pipe_ctx *primary_pipe)
1642	{
1643	int i;
1644	struct pipe_ctx *secondary_pipe = NULL;
1645
1646	/*
1647	* We add a preferred pipe mapping to avoid the chance that
1648	* MPCCs already in use will need to be reassigned to other trees.
1649	* For example, if we went with the strict, assign backwards logic:
1650	*
1651	* (State 1)
1652	* Display A on, no surface, top pipe = 0
1653	* Display B on, no surface, top pipe = 1
1654	*
1655	* (State 2)
1656	* Display A on, no surface, top pipe = 0
1657	* Display B on, surface enable, top pipe = 1, bottom pipe = 5
1658	*
1659	* (State 3)
1660	* Display A on, surface enable, top pipe = 0, bottom pipe = 5
1661	* Display B on, surface enable, top pipe = 1, bottom pipe = 4
1662	*
1663	* The state 2->3 transition requires remapping MPCC 5 from display B
1664	* to display A.
1665	*
1666	* However, with the preferred pipe logic, state 2 would look like:
1667	*
1668	* (State 2)
1669	* Display A on, no surface, top pipe = 0
1670	* Display B on, surface enable, top pipe = 1, bottom pipe = 4
1671	*
1672	* This would then cause 2->3 to not require remapping any MPCCs.
1673	*/
1674	if (primary_pipe) {
1675	int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1676	if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1677	secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1678	secondary_pipe->pipe_idx = preferred_pipe_idx;
1679	}
1680	}
1681
1682	/*
1683	* search backwards for the second pipe to keep pipe
1684	* assignment more consistent
1685	*/
1686	if (!secondary_pipe)
1687	for (i = pool->pipe_count - 1; i >= 0; i--) {
1688	if (res_ctx->pipe_ctx[i].stream == NULL) {
1689	secondary_pipe = &res_ctx->pipe_ctx[i];
1690	secondary_pipe->pipe_idx = i;
1691	break;
1692	}
1693	}
1694
1695	return secondary_pipe;
1696	}
1697
1698	int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
1699	const struct resource_context *cur_res_ctx,
1700	struct resource_context *new_res_ctx,
1701	const struct pipe_ctx *cur_otg_master)
1702	{
1703	const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;
1704	struct pipe_ctx *new_pipe;
1705	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1706
1707	while (cur_sec_opp_head) {
1708	new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];
1709	if (resource_is_pipe_type(pipe_ctx: new_pipe, type: FREE_PIPE)) {
1710	free_pipe_idx = cur_sec_opp_head->pipe_idx;
1711	break;
1712	}
1713	cur_sec_opp_head = cur_sec_opp_head->next_odm_pipe;
1714	}
1715
1716	return free_pipe_idx;
1717	}
1718
1719	int resource_find_free_pipe_used_in_cur_mpc_blending_tree(
1720	const struct resource_context *cur_res_ctx,
1721	struct resource_context *new_res_ctx,
1722	const struct pipe_ctx *cur_opp_head)
1723	{
1724	const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;
1725	struct pipe_ctx *new_pipe;
1726	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1727
1728	while (cur_sec_dpp) {
1729	/* find a free pipe used in current opp blend tree,
1730	* this is to avoid MPO pipe switching to different opp blending
1731	* tree
1732	*/
1733	new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx];
1734	if (resource_is_pipe_type(pipe_ctx: new_pipe, type: FREE_PIPE)) {
1735	free_pipe_idx = cur_sec_dpp->pipe_idx;
1736	break;
1737	}
1738	cur_sec_dpp = cur_sec_dpp->bottom_pipe;
1739	}
1740
1741	return free_pipe_idx;
1742	}
1743
1744	int recource_find_free_pipe_not_used_in_cur_res_ctx(
1745	const struct resource_context *cur_res_ctx,
1746	struct resource_context *new_res_ctx,
1747	const struct resource_pool *pool)
1748	{
1749	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1750	const struct pipe_ctx *new_pipe, *cur_pipe;
1751	int i;
1752
1753	for (i = 0; i < pool->pipe_count; i++) {
1754	cur_pipe = &cur_res_ctx->pipe_ctx[i];
1755	new_pipe = &new_res_ctx->pipe_ctx[i];
1756
1757	if (resource_is_pipe_type(pipe_ctx: cur_pipe, type: FREE_PIPE) &&
1758	resource_is_pipe_type(pipe_ctx: new_pipe, type: FREE_PIPE)) {
1759	free_pipe_idx = i;
1760	break;
1761	}
1762	}
1763
1764	return free_pipe_idx;
1765	}
1766
1767	int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
1768	const struct resource_context *cur_res_ctx,
1769	struct resource_context *new_res_ctx,
1770	const struct resource_pool *pool)
1771	{
1772	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1773	const struct pipe_ctx *new_pipe, *cur_pipe;
1774	int i;
1775
1776	for (i = 0; i < pool->pipe_count; i++) {
1777	cur_pipe = &cur_res_ctx->pipe_ctx[i];
1778	new_pipe = &new_res_ctx->pipe_ctx[i];
1779
1780	if (resource_is_pipe_type(pipe_ctx: cur_pipe, type: DPP_PIPE) &&
1781	!resource_is_pipe_type(pipe_ctx: cur_pipe, type: OPP_HEAD) &&
1782	resource_get_mpc_slice_index(dpp_pipe: cur_pipe) > 0 &&
1783	resource_is_pipe_type(pipe_ctx: new_pipe, type: FREE_PIPE)) {
1784	free_pipe_idx = i;
1785	break;
1786	}
1787	}
1788
1789	return free_pipe_idx;
1790	}
1791
1792	int resource_find_any_free_pipe(struct resource_context *new_res_ctx,
1793	const struct resource_pool *pool)
1794	{
1795	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1796	const struct pipe_ctx *new_pipe;
1797	int i;
1798
1799	for (i = 0; i < pool->pipe_count; i++) {
1800	new_pipe = &new_res_ctx->pipe_ctx[i];
1801
1802	if (resource_is_pipe_type(pipe_ctx: new_pipe, type: FREE_PIPE)) {
1803	free_pipe_idx = i;
1804	break;
1805	}
1806	}
1807
1808	return free_pipe_idx;
1809	}
1810
1811	bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
1812	{
1813	#ifdef DBG
1814	if (pipe_ctx->stream == NULL) {
1815	/* a free pipe with dangling states */
1816	ASSERT(!pipe_ctx->plane_state);
1817	ASSERT(!pipe_ctx->prev_odm_pipe);
1818	ASSERT(!pipe_ctx->next_odm_pipe);
1819	ASSERT(!pipe_ctx->top_pipe);
1820	ASSERT(!pipe_ctx->bottom_pipe);
1821	} else if (pipe_ctx->top_pipe) {
1822	/* a secondary DPP pipe must be signed to a plane */
1823	ASSERT(pipe_ctx->plane_state)
1824	}
1825	/* Add more checks here to prevent corrupted pipe ctx. It is very hard
1826	* to debug this issue afterwards because we can't pinpoint the code
1827	* location causing inconsistent pipe context states.
1828	*/
1829	#endif
1830	switch (type) {
1831	case OTG_MASTER:
1832	return !pipe_ctx->prev_odm_pipe &&
1833	!pipe_ctx->top_pipe &&
1834	pipe_ctx->stream;
1835	case OPP_HEAD:
1836	return !pipe_ctx->top_pipe && pipe_ctx->stream;
1837	case DPP_PIPE:
1838	return pipe_ctx->plane_state && pipe_ctx->stream;
1839	case FREE_PIPE:
1840	return !pipe_ctx->plane_state && !pipe_ctx->stream;
1841	default:
1842	return false;
1843	}
1844	}
1845
1846	struct pipe_ctx *resource_get_otg_master_for_stream(
1847	struct resource_context *res_ctx,
1848	const struct dc_stream_state *stream)
1849	{
1850	int i;
1851
1852	for (i = 0; i < MAX_PIPES; i++) {
1853	if (res_ctx->pipe_ctx[i].stream == stream &&
1854	resource_is_pipe_type(pipe_ctx: &res_ctx->pipe_ctx[i], type: OTG_MASTER))
1855	return &res_ctx->pipe_ctx[i];
1856	}
1857	return NULL;
1858	}
1859
1860	int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,
1861	struct resource_context *res_ctx,
1862	struct pipe_ctx *opp_heads[MAX_PIPES])
1863	{
1864	struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];
1865	int i = 0;
1866
1867	if (!resource_is_pipe_type(pipe_ctx: otg_master, type: OTG_MASTER)) {
1868	ASSERT(0);
1869	return 0;
1870	}
1871	while (opp_head) {
1872	ASSERT(i < MAX_PIPES);
1873	opp_heads[i++] = opp_head;
1874	opp_head = opp_head->next_odm_pipe;
1875	}
1876	return i;
1877	}
1878
1879	int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,
1880	struct resource_context *res_ctx,
1881	struct pipe_ctx *dpp_pipes[MAX_PIPES])
1882	{
1883	struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];
1884	int i = 0;
1885
1886	if (!resource_is_pipe_type(pipe_ctx: opp_head, type: OPP_HEAD)) {
1887	ASSERT(0);
1888	return 0;
1889	}
1890	while (pipe && resource_is_pipe_type(pipe_ctx: pipe, type: DPP_PIPE)) {
1891	ASSERT(i < MAX_PIPES);
1892	dpp_pipes[i++] = pipe;
1893	pipe = pipe->bottom_pipe;
1894	}
1895	return i;
1896	}
1897
1898	int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,
1899	struct resource_context *res_ctx,
1900	struct pipe_ctx *dpp_pipes[MAX_PIPES])
1901	{
1902	int i = 0, j;
1903	struct pipe_ctx *pipe;
1904
1905	for (j = 0; j < MAX_PIPES; j++) {
1906	pipe = &res_ctx->pipe_ctx[j];
1907	if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {
1908	if (resource_is_pipe_type(pipe_ctx: pipe, type: OPP_HEAD) ||
1909	pipe->top_pipe->plane_state != plane)
1910	break;
1911	}
1912	}
1913
1914	if (j < MAX_PIPES) {
1915	if (pipe->next_odm_pipe)
1916	while (pipe) {
1917	dpp_pipes[i++] = pipe;
1918	pipe = pipe->next_odm_pipe;
1919	}
1920	else
1921	while (pipe && pipe->plane_state == plane) {
1922	dpp_pipes[i++] = pipe;
1923	pipe = pipe->bottom_pipe;
1924	}
1925	}
1926	return i;
1927	}
1928
1929	struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)
1930	{
1931	struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);
1932
1933	while (otg_master->prev_odm_pipe)
1934	otg_master = otg_master->prev_odm_pipe;
1935	return otg_master;
1936	}
1937
1938	struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)
1939	{
1940	struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx;
1941
1942	ASSERT(!resource_is_pipe_type(opp_head, FREE_PIPE));
1943	while (opp_head->top_pipe)
1944	opp_head = opp_head->top_pipe;
1945	return opp_head;
1946	}
1947
1948	struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe)
1949	{
1950	struct pipe_ctx *pri_dpp_pipe = (struct pipe_ctx *) dpp_pipe;
1951
1952	ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
1953	while (pri_dpp_pipe->prev_odm_pipe)
1954	pri_dpp_pipe = pri_dpp_pipe->prev_odm_pipe;
1955	while (pri_dpp_pipe->top_pipe &&
1956	pri_dpp_pipe->top_pipe->plane_state == pri_dpp_pipe->plane_state)
1957	pri_dpp_pipe = pri_dpp_pipe->top_pipe;
1958	return pri_dpp_pipe;
1959	}
1960
1961
1962	int resource_get_mpc_slice_index(const struct pipe_ctx *pipe_ctx)
1963	{
1964	struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
1965	int index = 0;
1966
1967	while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
1968	index++;
1969	split_pipe = split_pipe->top_pipe;
1970	}
1971
1972	return index;
1973	}
1974
1975	int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)
1976	{
1977	int mpc_split_count = 1;
1978	const struct pipe_ctx *other_pipe = pipe->bottom_pipe;
1979
1980	while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
1981	mpc_split_count++;
1982	other_pipe = other_pipe->bottom_pipe;
1983	}
1984	other_pipe = pipe->top_pipe;
1985	while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
1986	mpc_split_count++;
1987	other_pipe = other_pipe->top_pipe;
1988	}
1989
1990	return mpc_split_count;
1991	}
1992
1993	int resource_get_odm_slice_count(const struct pipe_ctx *pipe)
1994	{
1995	int odm_split_count = 1;
1996
1997	pipe = resource_get_otg_master(pipe_ctx: pipe);
1998
1999	while (pipe->next_odm_pipe) {
2000	odm_split_count++;
2001	pipe = pipe->next_odm_pipe;
2002	}
2003	return odm_split_count;
2004	}
2005
2006	int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)
2007	{
2008	int index = 0;
2009
2010	pipe_ctx = resource_get_opp_head(pipe_ctx);
2011	if (!pipe_ctx)
2012	return 0;
2013
2014	while (pipe_ctx->prev_odm_pipe) {
2015	index++;
2016	pipe_ctx = pipe_ctx->prev_odm_pipe;
2017	}
2018
2019	return index;
2020	}
2021
2022	bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
2023	const struct dc_state *state_b)
2024	{
2025	int i;
2026	const struct pipe_ctx *pipe_a, *pipe_b;
2027
2028	if (state_a->stream_count != state_b->stream_count)
2029	return true;
2030
2031	for (i = 0; i < MAX_PIPES; i++) {
2032	pipe_a = &state_a->res_ctx.pipe_ctx[i];
2033	pipe_b = &state_b->res_ctx.pipe_ctx[i];
2034
2035	if (pipe_a->stream && !pipe_b->stream)
2036	return true;
2037	else if (!pipe_a->stream && pipe_b->stream)
2038	return true;
2039
2040	if (pipe_a->plane_state && !pipe_b->plane_state)
2041	return true;
2042	else if (!pipe_a->plane_state && pipe_b->plane_state)
2043	return true;
2044
2045	if (pipe_a->bottom_pipe && pipe_b->bottom_pipe) {
2046	if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx)
2047	return true;
2048	if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) &&
2049	(pipe_b->bottom_pipe->plane_state != pipe_b->plane_state))
2050	return true;
2051	else if ((pipe_a->bottom_pipe->plane_state != pipe_a->plane_state) &&
2052	(pipe_b->bottom_pipe->plane_state == pipe_b->plane_state))
2053	return true;
2054	} else if (pipe_a->bottom_pipe || pipe_b->bottom_pipe) {
2055	return true;
2056	}
2057
2058	if (pipe_a->next_odm_pipe && pipe_b->next_odm_pipe) {
2059	if (pipe_a->next_odm_pipe->pipe_idx != pipe_b->next_odm_pipe->pipe_idx)
2060	return true;
2061	} else if (pipe_a->next_odm_pipe || pipe_b->next_odm_pipe) {
2062	return true;
2063	}
2064	}
2065	return false;
2066	}
2067
2068	bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,
2069	const struct pipe_ctx *otg_master_b)
2070	{
2071	const struct pipe_ctx *opp_head_a = otg_master_a;
2072	const struct pipe_ctx *opp_head_b = otg_master_b;
2073
2074	if (!resource_is_pipe_type(pipe_ctx: otg_master_a, type: OTG_MASTER) ||
2075	!resource_is_pipe_type(pipe_ctx: otg_master_b, type: OTG_MASTER))
2076	return true;
2077
2078	while (opp_head_a && opp_head_b) {
2079	if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp)
2080	return true;
2081	if ((opp_head_a->next_odm_pipe && !opp_head_b->next_odm_pipe) ||
2082	(!opp_head_a->next_odm_pipe && opp_head_b->next_odm_pipe))
2083	return true;
2084	opp_head_a = opp_head_a->next_odm_pipe;
2085	opp_head_b = opp_head_b->next_odm_pipe;
2086	}
2087
2088	return false;
2089	}
2090
2091	/*
2092	* Sample log:
2093	* pipe topology update
2094	* ________________________
2095	* | plane0 slice0 stream0|
2096	* |DPP0----OPP0----OTG0----| <--- case 0 (OTG master pipe with plane)
2097	* | plane1 | | |
2098	* |DPP1----| | | <--- case 5 (DPP pipe not in last slice)
2099	* | plane0 slice1 | |
2100	* |DPP2----OPP2----| | <--- case 2 (OPP head pipe with plane)
2101	* | plane1 | |
2102	* |DPP3----| | <--- case 4 (DPP pipe in last slice)
2103	* | slice0 stream1|
2104	* |DPG4----OPP4----OTG4----| <--- case 1 (OTG master pipe without plane)
2105	* | slice1 | |
2106	* |DPG5----OPP5----| | <--- case 3 (OPP head pipe without plane)
2107	* |________________________|
2108	*/
2109
2110	static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,
2111	int stream_idx, int slice_idx, int plane_idx, int slice_count,
2112	bool is_primary)
2113	{
2114	DC_LOGGER_INIT(dc->ctx->logger);
2115
2116	if (slice_idx == 0 && plane_idx == 0 && is_primary) {
2117	/* case 0 (OTG master pipe with plane) */
2118	DC_LOG_DC(" | plane%d slice%d stream%d|",
2119	plane_idx, slice_idx, stream_idx);
2120	DC_LOG_DC(" |DPP%d----OPP%d----OTG%d----|",
2121	pipe->plane_res.dpp->inst,
2122	pipe->stream_res.opp->inst,
2123	pipe->stream_res.tg->inst);
2124	} else if (slice_idx == 0 && plane_idx == -1) {
2125	/* case 1 (OTG master pipe without plane) */
2126	DC_LOG_DC(" | slice%d stream%d|",
2127	slice_idx, stream_idx);
2128	DC_LOG_DC(" |DPG%d----OPP%d----OTG%d----|",
2129	pipe->stream_res.opp->inst,
2130	pipe->stream_res.opp->inst,
2131	pipe->stream_res.tg->inst);
2132	} else if (slice_idx != 0 && plane_idx == 0 && is_primary) {
2133	/* case 2 (OPP head pipe with plane) */
2134	DC_LOG_DC(" | plane%d slice%d | |",
2135	plane_idx, slice_idx);
2136	DC_LOG_DC(" |DPP%d----OPP%d----| |",
2137	pipe->plane_res.dpp->inst,
2138	pipe->stream_res.opp->inst);
2139	} else if (slice_idx != 0 && plane_idx == -1) {
2140	/* case 3 (OPP head pipe without plane) */
2141	DC_LOG_DC(" | slice%d | |", slice_idx);
2142	DC_LOG_DC(" |DPG%d----OPP%d----| |",
2143	pipe->plane_res.dpp->inst,
2144	pipe->stream_res.opp->inst);
2145	} else if (slice_idx == slice_count - 1) {
2146	/* case 4 (DPP pipe in last slice) */
2147	DC_LOG_DC(" | plane%d | |", plane_idx);
2148	DC_LOG_DC(" |DPP%d----| |",
2149	pipe->plane_res.dpp->inst);
2150	} else {
2151	/* case 5 (DPP pipe not in last slice) */
2152	DC_LOG_DC(" | plane%d | | |", plane_idx);
2153	DC_LOG_DC(" |DPP%d----| | |",
2154	pipe->plane_res.dpp->inst);
2155	}
2156	}
2157
2158	void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
2159	{
2160	struct pipe_ctx *otg_master;
2161	struct pipe_ctx *opp_heads[MAX_PIPES];
2162	struct pipe_ctx *dpp_pipes[MAX_PIPES];
2163
2164	int stream_idx, slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
2165	bool is_primary;
2166	DC_LOGGER_INIT(dc->ctx->logger);
2167
2168	DC_LOG_DC(" pipe topology update");
2169	DC_LOG_DC(" ________________________");
2170	for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
2171	otg_master = resource_get_otg_master_for_stream(
2172	res_ctx: &state->res_ctx, stream: state->streams[stream_idx]);
2173	slice_count = resource_get_opp_heads_for_otg_master(otg_master,
2174	res_ctx: &state->res_ctx, opp_heads);
2175	for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
2176	plane_idx = -1;
2177	if (opp_heads[slice_idx]->plane_state) {
2178	dpp_count = resource_get_dpp_pipes_for_opp_head(
2179	opp_head: opp_heads[slice_idx],
2180	res_ctx: &state->res_ctx,
2181	dpp_pipes);
2182	for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
2183	is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
2184	dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
2185	if (is_primary)
2186	plane_idx++;
2187	resource_log_pipe(dc, pipe: dpp_pipes[dpp_idx],
2188	stream_idx, slice_idx,
2189	plane_idx, slice_count,
2190	is_primary);
2191	}
2192	} else {
2193	resource_log_pipe(dc, pipe: opp_heads[slice_idx],
2194	stream_idx, slice_idx, plane_idx,
2195	slice_count, is_primary: true);
2196	}
2197
2198	}
2199	}
2200	DC_LOG_DC(" |________________________|\n");
2201	}
2202
2203	static struct pipe_ctx *get_tail_pipe(
2204	struct pipe_ctx *head_pipe)
2205	{
2206	struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe;
2207
2208	while (tail_pipe) {
2209	head_pipe = tail_pipe;
2210	tail_pipe = tail_pipe->bottom_pipe;
2211	}
2212
2213	return head_pipe;
2214	}
2215
2216	static struct pipe_ctx *get_last_opp_head(
2217	struct pipe_ctx *opp_head)
2218	{
2219	ASSERT(resource_is_pipe_type(opp_head, OPP_HEAD));
2220	while (opp_head->next_odm_pipe)
2221	opp_head = opp_head->next_odm_pipe;
2222	return opp_head;
2223	}
2224
2225	static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(
2226	struct pipe_ctx *dpp_pipe)
2227	{
2228	ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
2229	while (dpp_pipe->bottom_pipe &&
2230	dpp_pipe->plane_state == dpp_pipe->bottom_pipe->plane_state)
2231	dpp_pipe = dpp_pipe->bottom_pipe;
2232	return dpp_pipe;
2233	}
2234
2235	static bool update_pipe_params_after_odm_slice_count_change(
2236	const struct dc_stream_state *stream,
2237	struct dc_state *context,
2238	const struct resource_pool *pool)
2239	{
2240	int i;
2241	struct pipe_ctx *pipe;
2242	bool result = true;
2243
2244	for (i = 0; i < pool->pipe_count && result; i++) {
2245	pipe = &context->res_ctx.pipe_ctx[i];
2246	if (pipe->stream == stream && pipe->plane_state)
2247	result = resource_build_scaling_params(pipe_ctx: pipe);
2248	}
2249	return result;
2250	}
2251
2252	static bool update_pipe_params_after_mpc_slice_count_change(
2253	const struct dc_plane_state *plane,
2254	struct dc_state *context,
2255	const struct resource_pool *pool)
2256	{
2257	int i;
2258	struct pipe_ctx *pipe;
2259	bool result = true;
2260
2261	for (i = 0; i < pool->pipe_count && result; i++) {
2262	pipe = &context->res_ctx.pipe_ctx[i];
2263	if (pipe->plane_state == plane)
2264	result = resource_build_scaling_params(pipe_ctx: pipe);
2265	}
2266	return result;
2267	}
2268
2269	static int acquire_first_split_pipe(
2270	struct resource_context *res_ctx,
2271	const struct resource_pool *pool,
2272	struct dc_stream_state *stream)
2273	{
2274	int i;
2275
2276	for (i = 0; i < pool->pipe_count; i++) {
2277	struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
2278
2279	if (split_pipe->top_pipe &&
2280	split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
2281	split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
2282	if (split_pipe->bottom_pipe)
2283	split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
2284
2285	if (split_pipe->top_pipe->plane_state)
2286	resource_build_scaling_params(pipe_ctx: split_pipe->top_pipe);
2287
2288	memset(split_pipe, 0, sizeof(*split_pipe));
2289	split_pipe->stream_res.tg = pool->timing_generators[i];
2290	split_pipe->plane_res.hubp = pool->hubps[i];
2291	split_pipe->plane_res.ipp = pool->ipps[i];
2292	split_pipe->plane_res.dpp = pool->dpps[i];
2293	split_pipe->stream_res.opp = pool->opps[i];
2294	split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
2295	split_pipe->pipe_idx = i;
2296
2297	split_pipe->stream = stream;
2298	return i;
2299	}
2300	}
2301	return FREE_PIPE_INDEX_NOT_FOUND;
2302	}
2303
2304	static void update_stream_engine_usage(
2305	struct resource_context *res_ctx,
2306	const struct resource_pool *pool,
2307	struct stream_encoder *stream_enc,
2308	bool acquired)
2309	{
2310	int i;
2311
2312	for (i = 0; i < pool->stream_enc_count; i++) {
2313	if (pool->stream_enc[i] == stream_enc)
2314	res_ctx->is_stream_enc_acquired[i] = acquired;
2315	}
2316	}
2317
2318	static void update_hpo_dp_stream_engine_usage(
2319	struct resource_context *res_ctx,
2320	const struct resource_pool *pool,
2321	struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
2322	bool acquired)
2323	{
2324	int i;
2325
2326	for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
2327	if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
2328	res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
2329	}
2330	}
2331
2332	static inline int find_acquired_hpo_dp_link_enc_for_link(
2333	const struct resource_context *res_ctx,
2334	const struct dc_link *link)
2335	{
2336	int i;
2337
2338	for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
2339	if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
2340	res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
2341	return i;
2342
2343	return -1;
2344	}
2345
2346	static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
2347	const struct resource_pool *pool)
2348	{
2349	int i;
2350
2351	for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
2352	if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
2353	break;
2354
2355	return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
2356	i < pool->hpo_dp_link_enc_count) ? i : -1;
2357	}
2358
2359	static inline void acquire_hpo_dp_link_enc(
2360	struct resource_context *res_ctx,
2361	unsigned int link_index,
2362	int enc_index)
2363	{
2364	res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
2365	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
2366	}
2367
2368	static inline void retain_hpo_dp_link_enc(
2369	struct resource_context *res_ctx,
2370	int enc_index)
2371	{
2372	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
2373	}
2374
2375	static inline void release_hpo_dp_link_enc(
2376	struct resource_context *res_ctx,
2377	int enc_index)
2378	{
2379	ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
2380	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
2381	}
2382
2383	static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
2384	const struct resource_pool *pool,
2385	struct pipe_ctx *pipe_ctx,
2386	struct dc_stream_state *stream)
2387	{
2388	int enc_index;
2389
2390	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link: stream->link);
2391
2392	if (enc_index >= 0) {
2393	retain_hpo_dp_link_enc(res_ctx, enc_index);
2394	} else {
2395	enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
2396	if (enc_index >= 0)
2397	acquire_hpo_dp_link_enc(res_ctx, link_index: stream->link->link_index, enc_index);
2398	}
2399
2400	if (enc_index >= 0)
2401	pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
2402
2403	return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
2404	}
2405
2406	static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
2407	struct pipe_ctx *pipe_ctx,
2408	struct dc_stream_state *stream)
2409	{
2410	int enc_index;
2411
2412	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link: stream->link);
2413
2414	if (enc_index >= 0) {
2415	release_hpo_dp_link_enc(res_ctx, enc_index);
2416	pipe_ctx->link_res.hpo_dp_link_enc = NULL;
2417	}
2418	}
2419
2420	enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,
2421	const struct resource_pool *pool,
2422	struct dc_stream_state *stream)
2423	{
2424	struct dc *dc = stream->ctx->dc;
2425
2426	return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
2427	}
2428
2429	void resource_remove_otg_master_for_stream_output(struct dc_state *context,
2430	const struct resource_pool *pool,
2431	struct dc_stream_state *stream)
2432	{
2433	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
2434	res_ctx: &context->res_ctx, stream);
2435
2436	ASSERT(resource_get_odm_slice_count(otg_master) == 1);
2437	ASSERT(otg_master->plane_state == NULL);
2438	ASSERT(otg_master->stream_res.stream_enc);
2439	update_stream_engine_usage(
2440	res_ctx: &context->res_ctx,
2441	pool,
2442	stream_enc: otg_master->stream_res.stream_enc,
2443	acquired: false);
2444
2445	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master)) {
2446	update_hpo_dp_stream_engine_usage(
2447	res_ctx: &context->res_ctx, pool,
2448	hpo_dp_stream_enc: otg_master->stream_res.hpo_dp_stream_enc,
2449	acquired: false);
2450	remove_hpo_dp_link_enc_from_ctx(
2451	res_ctx: &context->res_ctx, pipe_ctx: otg_master, stream);
2452	}
2453	if (otg_master->stream_res.audio)
2454	update_audio_usage(
2455	res_ctx: &context->res_ctx,
2456	pool,
2457	audio: otg_master->stream_res.audio,
2458	acquired: false);
2459
2460	resource_unreference_clock_source(res_ctx: &context->res_ctx,
2461	pool,
2462	clock_source: otg_master->clock_source);
2463
2464	if (pool->funcs->remove_stream_from_ctx)
2465	pool->funcs->remove_stream_from_ctx(
2466	stream->ctx->dc, context, stream);
2467	memset(otg_master, 0, sizeof(*otg_master));
2468	}
2469
2470	/* For each OPP head of an OTG master, add top plane at plane index 0.
2471	*
2472	* In the following example, the stream has 2 ODM slices without a top plane.
2473	* By adding a plane 0 to OPP heads, we are configuring our hardware to render
2474	* plane 0 by using each OPP head's DPP.
2475	*
2476	* Inter-pipe Relation (Before Adding Plane)
2477	* __________________________________________________
2478	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2479	* | | | slice 0 | |
2480	* | 0 | |blank ----ODM----------- |
2481	* | | | slice 1 | | |
2482	* | 1 | |blank ---- | |
2483	* |________|_______________|___________|_____________|
2484	*
2485	* Inter-pipe Relation (After Adding Plane)
2486	* __________________________________________________
2487	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2488	* | | plane 0 | slice 0 | |
2489	* | 0 | -------------------------ODM----------- |
2490	* | | plane 0 | slice 1 | | |
2491	* | 1 | ------------------------- | |
2492	* |________|_______________|___________|_____________|
2493	*/
2494	static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
2495	struct dc_plane_state *plane_state,
2496	struct dc_state *context)
2497	{
2498	struct pipe_ctx *opp_head_pipe = otg_master_pipe;
2499
2500	while (opp_head_pipe) {
2501	if (opp_head_pipe->plane_state) {
2502	ASSERT(0);
2503	return false;
2504	}
2505	opp_head_pipe->plane_state = plane_state;
2506	opp_head_pipe = opp_head_pipe->next_odm_pipe;
2507	}
2508
2509	return true;
2510	}
2511
2512	/* For each OPP head of an OTG master, acquire a secondary DPP pipe and add
2513	* the plane. So the plane is added to all ODM slices associated with the OTG
2514	* master pipe in the bottom layer.
2515	*
2516	* In the following example, the stream has 2 ODM slices and a top plane 0.
2517	* By acquiring secondary DPP pipes and adding a plane 1, we are configuring our
2518	* hardware to render the plane 1 by acquiring a new pipe for each ODM slice and
2519	* render plane 1 using new pipes' DPP in the Z axis below plane 0.
2520	*
2521	* Inter-pipe Relation (Before Adding Plane)
2522	* __________________________________________________
2523	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2524	* | | plane 0 | slice 0 | |
2525	* | 0 | -------------------------ODM----------- |
2526	* | | plane 0 | slice 1 | | |
2527	* | 1 | ------------------------- | |
2528	* |________|_______________|___________|_____________|
2529	*
2530	* Inter-pipe Relation (After Acquiring and Adding Plane)
2531	* __________________________________________________
2532	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2533	* | | plane 0 | slice 0 | |
2534	* | 0 | -------------MPC---------ODM----------- |
2535	* | | plane 1 | | | | |
2536	* | 2 | ------------- | | | |
2537	* | | plane 0 | slice 1 | | |
2538	* | 1 | -------------MPC--------- | |
2539	* | | plane 1 | | | |
2540	* | 3 | ------------- | | |
2541	* |________|_______________|___________|_____________|
2542	*/
2543	static bool acquire_secondary_dpp_pipes_and_add_plane(
2544	struct pipe_ctx *otg_master_pipe,
2545	struct dc_plane_state *plane_state,
2546	struct dc_state *new_ctx,
2547	struct dc_state *cur_ctx,
2548	struct resource_pool *pool)
2549	{
2550	struct pipe_ctx *opp_head_pipe, *sec_pipe, *tail_pipe;
2551
2552	if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
2553	ASSERT(0);
2554	return false;
2555	}
2556
2557	opp_head_pipe = otg_master_pipe;
2558	while (opp_head_pipe) {
2559	sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
2560	cur_ctx,
2561	new_ctx,
2562	pool,
2563	opp_head_pipe);
2564	if (!sec_pipe) {
2565	/* try tearing down MPCC combine */
2566	int pipe_idx = acquire_first_split_pipe(
2567	res_ctx: &new_ctx->res_ctx, pool,
2568	stream: otg_master_pipe->stream);
2569
2570	if (pipe_idx >= 0)
2571	sec_pipe = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
2572	}
2573
2574	if (!sec_pipe)
2575	return false;
2576
2577	sec_pipe->plane_state = plane_state;
2578
2579	/* establish pipe relationship */
2580	tail_pipe = get_tail_pipe(head_pipe: opp_head_pipe);
2581	tail_pipe->bottom_pipe = sec_pipe;
2582	sec_pipe->top_pipe = tail_pipe;
2583	sec_pipe->bottom_pipe = NULL;
2584	if (tail_pipe->prev_odm_pipe) {
2585	ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe);
2586	sec_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
2587	tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = sec_pipe;
2588	} else {
2589	sec_pipe->prev_odm_pipe = NULL;
2590	}
2591
2592	opp_head_pipe = opp_head_pipe->next_odm_pipe;
2593	}
2594	return true;
2595	}
2596
2597	bool resource_append_dpp_pipes_for_plane_composition(
2598	struct dc_state *new_ctx,
2599	struct dc_state *cur_ctx,
2600	struct resource_pool *pool,
2601	struct pipe_ctx *otg_master_pipe,
2602	struct dc_plane_state *plane_state)
2603	{
2604	if (otg_master_pipe->plane_state == NULL)
2605	return add_plane_to_opp_head_pipes(otg_master_pipe,
2606	plane_state, context: new_ctx);
2607	else
2608	return acquire_secondary_dpp_pipes_and_add_plane(
2609	otg_master_pipe, plane_state, new_ctx,
2610	cur_ctx, pool);
2611	}
2612
2613	void resource_remove_dpp_pipes_for_plane_composition(
2614	struct dc_state *context,
2615	const struct resource_pool *pool,
2616	const struct dc_plane_state *plane_state)
2617	{
2618	int i;
2619	for (i = pool->pipe_count - 1; i >= 0; i--) {
2620	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2621
2622	if (pipe_ctx->plane_state == plane_state) {
2623	if (pipe_ctx->top_pipe)
2624	pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
2625
2626	/* Second condition is to avoid setting NULL to top pipe
2627	* of tail pipe making it look like head pipe in subsequent
2628	* deletes
2629	*/
2630	if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
2631	pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
2632
2633	/*
2634	* For head pipe detach surfaces from pipe for tail
2635	* pipe just zero it out
2636	*/
2637	if (!pipe_ctx->top_pipe)
2638	pipe_ctx->plane_state = NULL;
2639	else
2640	memset(pipe_ctx, 0, sizeof(*pipe_ctx));
2641	}
2642	}
2643	}
2644
2645	/*
2646	* Increase ODM slice count by 1 by acquiring pipes and adding a new ODM slice
2647	* at the last index.
2648	* return - true if a new ODM slice is added and required pipes are acquired.
2649	* false if new_ctx is no longer a valid state after new ODM slice is added.
2650	*
2651	* This is achieved by duplicating MPC blending tree from previous ODM slice.
2652	* In the following example, we have a single MPC tree and 1 ODM slice 0. We
2653	* want to add a new odm slice by duplicating the MPC blending tree and add
2654	* ODM slice 1.
2655	*
2656	* Inter-pipe Relation (Before Acquiring and Adding ODM Slice)
2657	* __________________________________________________
2658	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2659	* | | plane 0 | slice 0 | |
2660	* | 0 | -------------MPC---------ODM----------- |
2661	* | | plane 1 | | | |
2662	* | 1 | ------------- | | |
2663	* |________|_______________|___________|_____________|
2664	*
2665	* Inter-pipe Relation (After Acquiring and Adding ODM Slice)
2666	* __________________________________________________
2667	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2668	* | | plane 0 | slice 0 | |
2669	* | 0 | -------------MPC---------ODM----------- |
2670	* | | plane 1 | | | | |
2671	* | 1 | ------------- | | | |
2672	* | | plane 0 | slice 1 | | |
2673	* | 2 | -------------MPC--------- | |
2674	* | | plane 1 | | | |
2675	* | 3 | ------------- | | |
2676	* |________|_______________|___________|_____________|
2677	*/
2678	static bool acquire_pipes_and_add_odm_slice(
2679	struct pipe_ctx *otg_master_pipe,
2680	struct dc_state *new_ctx,
2681	const struct dc_state *cur_ctx,
2682	const struct resource_pool *pool)
2683	{
2684	struct pipe_ctx *last_opp_head = get_last_opp_head(opp_head: otg_master_pipe);
2685	struct pipe_ctx *new_opp_head;
2686	struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,
2687	*new_top_dpp_pipe, *new_bottom_dpp_pipe;
2688
2689	if (!pool->funcs->acquire_free_pipe_as_secondary_opp_head) {
2690	ASSERT(0);
2691	return false;
2692	}
2693	new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(
2694	cur_ctx, new_ctx, pool,
2695	otg_master_pipe);
2696	if (!new_opp_head)
2697	return false;
2698
2699	last_opp_head->next_odm_pipe = new_opp_head;
2700	new_opp_head->prev_odm_pipe = last_opp_head;
2701	new_opp_head->next_odm_pipe = NULL;
2702	new_opp_head->plane_state = last_opp_head->plane_state;
2703	last_top_dpp_pipe = last_opp_head;
2704	new_top_dpp_pipe = new_opp_head;
2705
2706	while (last_top_dpp_pipe->bottom_pipe) {
2707	last_bottom_dpp_pipe = last_top_dpp_pipe->bottom_pipe;
2708	new_bottom_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
2709	cur_ctx, new_ctx, pool,
2710	new_opp_head);
2711	if (!new_bottom_dpp_pipe)
2712	return false;
2713
2714	new_bottom_dpp_pipe->plane_state = last_bottom_dpp_pipe->plane_state;
2715	new_top_dpp_pipe->bottom_pipe = new_bottom_dpp_pipe;
2716	new_bottom_dpp_pipe->top_pipe = new_top_dpp_pipe;
2717	last_bottom_dpp_pipe->next_odm_pipe = new_bottom_dpp_pipe;
2718	new_bottom_dpp_pipe->prev_odm_pipe = last_bottom_dpp_pipe;
2719	new_bottom_dpp_pipe->next_odm_pipe = NULL;
2720	last_top_dpp_pipe = last_bottom_dpp_pipe;
2721	}
2722
2723	return true;
2724	}
2725
2726	/*
2727	* Decrease ODM slice count by 1 by releasing pipes and removing the ODM slice
2728	* at the last index.
2729	* return - true if the last ODM slice is removed and related pipes are
2730	* released. false if there is no removable ODM slice.
2731	*
2732	* In the following example, we have 2 MPC trees and ODM slice 0 and slice 1.
2733	* We want to remove the last ODM i.e slice 1. We are releasing secondary DPP
2734	* pipe 3 and OPP head pipe 2.
2735	*
2736	* Inter-pipe Relation (Before Releasing and Removing ODM Slice)
2737	* __________________________________________________
2738	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2739	* | | plane 0 | slice 0 | |
2740	* | 0 | -------------MPC---------ODM----------- |
2741	* | | plane 1 | | | | |
2742	* | 1 | ------------- | | | |
2743	* | | plane 0 | slice 1 | | |
2744	* | 2 | -------------MPC--------- | |
2745	* | | plane 1 | | | |
2746	* | 3 | ------------- | | |
2747	* |________|_______________|___________|_____________|
2748	*
2749	* Inter-pipe Relation (After Releasing and Removing ODM Slice)
2750	* __________________________________________________
2751	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2752	* | | plane 0 | slice 0 | |
2753	* | 0 | -------------MPC---------ODM----------- |
2754	* | | plane 1 | | | |
2755	* | 1 | ------------- | | |
2756	* |________|_______________|___________|_____________|
2757	*/
2758	static bool release_pipes_and_remove_odm_slice(
2759	struct pipe_ctx *otg_master_pipe,
2760	struct dc_state *context,
2761	const struct resource_pool *pool)
2762	{
2763	struct pipe_ctx *last_opp_head = get_last_opp_head(opp_head: otg_master_pipe);
2764	struct pipe_ctx *tail_pipe = get_tail_pipe(head_pipe: last_opp_head);
2765
2766	if (!pool->funcs->release_pipe) {
2767	ASSERT(0);
2768	return false;
2769	}
2770
2771	if (resource_is_pipe_type(pipe_ctx: last_opp_head, type: OTG_MASTER))
2772	return false;
2773
2774	while (tail_pipe->top_pipe) {
2775	tail_pipe->prev_odm_pipe->next_odm_pipe = NULL;
2776	tail_pipe = tail_pipe->top_pipe;
2777	pool->funcs->release_pipe(context, tail_pipe->bottom_pipe, pool);
2778	tail_pipe->bottom_pipe = NULL;
2779	}
2780	last_opp_head->prev_odm_pipe->next_odm_pipe = NULL;
2781	pool->funcs->release_pipe(context, last_opp_head, pool);
2782
2783	return true;
2784	}
2785
2786	/*
2787	* Increase MPC slice count by 1 by acquiring a new DPP pipe and add it as the
2788	* last MPC slice of the plane associated with dpp_pipe.
2789	*
2790	* return - true if a new MPC slice is added and required pipes are acquired.
2791	* false if new_ctx is no longer a valid state after new MPC slice is added.
2792	*
2793	* In the following example, we add a new MPC slice for plane 0 into the
2794	* new_ctx. To do so we pass pipe 0 as dpp_pipe. The function acquires a new DPP
2795	* pipe 2 for plane 0 as the bottom most pipe for plane 0.
2796	*
2797	* Inter-pipe Relation (Before Acquiring and Adding MPC Slice)
2798	* __________________________________________________
2799	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2800	* | | plane 0 | | |
2801	* | 0 | -------------MPC----------------------- |
2802	* | | plane 1 | | | |
2803	* | 1 | ------------- | | |
2804	* |________|_______________|___________|_____________|
2805	*
2806	* Inter-pipe Relation (After Acquiring and Adding MPC Slice)
2807	* __________________________________________________
2808	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2809	* | | plane 0 | | |
2810	* | 0 | -------------MPC----------------------- |
2811	* | | plane 0 | | | |
2812	* | 2 | ------------- | | |
2813	* | | plane 1 | | | |
2814	* | 1 | ------------- | | |
2815	* |________|_______________|___________|_____________|
2816	*/
2817	static bool acquire_dpp_pipe_and_add_mpc_slice(
2818	struct pipe_ctx *dpp_pipe,
2819	struct dc_state *new_ctx,
2820	const struct dc_state *cur_ctx,
2821	const struct resource_pool *pool)
2822	{
2823	struct pipe_ctx *last_dpp_pipe =
2824	get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
2825	struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx: dpp_pipe);
2826	struct pipe_ctx *new_dpp_pipe;
2827
2828	if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
2829	ASSERT(0);
2830	return false;
2831	}
2832	new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
2833	cur_ctx, new_ctx, pool, opp_head);
2834	if (!new_dpp_pipe || resource_get_odm_slice_count(pipe: dpp_pipe) > 1)
2835	return false;
2836
2837	new_dpp_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
2838	if (new_dpp_pipe->bottom_pipe)
2839	new_dpp_pipe->bottom_pipe->top_pipe = new_dpp_pipe;
2840	new_dpp_pipe->top_pipe = last_dpp_pipe;
2841	last_dpp_pipe->bottom_pipe = new_dpp_pipe;
2842	new_dpp_pipe->plane_state = last_dpp_pipe->plane_state;
2843
2844	return true;
2845	}
2846
2847	/*
2848	* Reduce MPC slice count by 1 by releasing the bottom DPP pipe in MPCC combine
2849	* with dpp_pipe and removing last MPC slice of the plane associated with
2850	* dpp_pipe.
2851	*
2852	* return - true if the last MPC slice of the plane associated with dpp_pipe is
2853	* removed and last DPP pipe in MPCC combine with dpp_pipe is released.
2854	* false if there is no removable MPC slice.
2855	*
2856	* In the following example, we remove an MPC slice for plane 0 from the
2857	* context. To do so we pass pipe 0 as dpp_pipe. The function releases pipe 1 as
2858	* it is the last pipe for plane 0.
2859	*
2860	* Inter-pipe Relation (Before Releasing and Removing MPC Slice)
2861	* __________________________________________________
2862	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2863	* | | plane 0 | | |
2864	* | 0 | -------------MPC----------------------- |
2865	* | | plane 0 | | | |
2866	* | 1 | ------------- | | |
2867	* | | plane 1 | | | |
2868	* | 2 | ------------- | | |
2869	* |________|_______________|___________|_____________|
2870	*
2871	* Inter-pipe Relation (After Releasing and Removing MPC Slice)
2872	* __________________________________________________
2873	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2874	* | | plane 0 | | |
2875	* | 0 | -------------MPC----------------------- |
2876	* | | plane 1 | | | |
2877	* | 2 | ------------- | | |
2878	* |________|_______________|___________|_____________|
2879	*/
2880	static bool release_dpp_pipe_and_remove_mpc_slice(
2881	struct pipe_ctx *dpp_pipe,
2882	struct dc_state *context,
2883	const struct resource_pool *pool)
2884	{
2885	struct pipe_ctx *last_dpp_pipe =
2886	get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
2887
2888	if (!pool->funcs->release_pipe) {
2889	ASSERT(0);
2890	return false;
2891	}
2892
2893	if (resource_is_pipe_type(pipe_ctx: last_dpp_pipe, type: OPP_HEAD) ||
2894	resource_get_odm_slice_count(pipe: dpp_pipe) > 1)
2895	return false;
2896
2897	last_dpp_pipe->top_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
2898	if (last_dpp_pipe->bottom_pipe)
2899	last_dpp_pipe->bottom_pipe->top_pipe = last_dpp_pipe->top_pipe;
2900	pool->funcs->release_pipe(context, last_dpp_pipe, pool);
2901
2902	return true;
2903	}
2904
2905	bool resource_update_pipes_for_stream_with_slice_count(
2906	struct dc_state *new_ctx,
2907	const struct dc_state *cur_ctx,
2908	const struct resource_pool *pool,
2909	const struct dc_stream_state *stream,
2910	int new_slice_count)
2911	{
2912	int i;
2913	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
2914	res_ctx: &new_ctx->res_ctx, stream);
2915	int cur_slice_count = resource_get_odm_slice_count(pipe: otg_master);
2916	bool result = true;
2917
2918	if (new_slice_count == cur_slice_count)
2919	return result;
2920
2921	if (new_slice_count > cur_slice_count)
2922	for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
2923	result = acquire_pipes_and_add_odm_slice(
2924	otg_master_pipe: otg_master, new_ctx, cur_ctx, pool);
2925	else
2926	for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
2927	result = release_pipes_and_remove_odm_slice(
2928	otg_master_pipe: otg_master, context: new_ctx, pool);
2929	if (result)
2930	result = update_pipe_params_after_odm_slice_count_change(
2931	stream: otg_master->stream, context: new_ctx, pool);
2932	return result;
2933	}
2934
2935	bool resource_update_pipes_for_plane_with_slice_count(
2936	struct dc_state *new_ctx,
2937	const struct dc_state *cur_ctx,
2938	const struct resource_pool *pool,
2939	const struct dc_plane_state *plane,
2940	int new_slice_count)
2941	{
2942	int i;
2943	int dpp_pipe_count;
2944	int cur_slice_count;
2945	struct pipe_ctx *dpp_pipes[MAX_PIPES];
2946	bool result = true;
2947
2948	dpp_pipe_count = resource_get_dpp_pipes_for_plane(plane,
2949	res_ctx: &new_ctx->res_ctx, dpp_pipes);
2950	ASSERT(dpp_pipe_count > 0);
2951	cur_slice_count = resource_get_mpc_slice_count(pipe: dpp_pipes[0]);
2952
2953	if (new_slice_count == cur_slice_count)
2954	return result;
2955
2956	if (new_slice_count > cur_slice_count)
2957	for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
2958	result = acquire_dpp_pipe_and_add_mpc_slice(
2959	dpp_pipe: dpp_pipes[0], new_ctx, cur_ctx, pool);
2960	else
2961	for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
2962	result = release_dpp_pipe_and_remove_mpc_slice(
2963	dpp_pipe: dpp_pipes[0], context: new_ctx, pool);
2964	if (result)
2965	result = update_pipe_params_after_mpc_slice_count_change(
2966	plane: dpp_pipes[0]->plane_state, context: new_ctx, pool);
2967	return result;
2968	}
2969
2970	bool dc_add_plane_to_context(
2971	const struct dc *dc,
2972	struct dc_stream_state *stream,
2973	struct dc_plane_state *plane_state,
2974	struct dc_state *context)
2975	{
2976	struct resource_pool *pool = dc->res_pool;
2977	struct pipe_ctx *otg_master_pipe;
2978	struct dc_stream_status *stream_status = NULL;
2979	bool added = false;
2980
2981	stream_status = dc_stream_get_status_from_state(state: context, stream);
2982	if (stream_status == NULL) {
2983	dm_error("Existing stream not found; failed to attach surface!\n");
2984	goto out;
2985	} else if (stream_status->plane_count == MAX_SURFACE_NUM) {
2986	dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
2987	plane_state, MAX_SURFACE_NUM);
2988	goto out;
2989	}
2990
2991	otg_master_pipe = resource_get_otg_master_for_stream(
2992	res_ctx: &context->res_ctx, stream);
2993	added = resource_append_dpp_pipes_for_plane_composition(new_ctx: context,
2994	cur_ctx: dc->current_state, pool, otg_master_pipe, plane_state);
2995
2996	if (added) {
2997	stream_status->plane_states[stream_status->plane_count] =
2998	plane_state;
2999	stream_status->plane_count++;
3000	dc_plane_state_retain(plane_state);
3001	}
3002
3003	out:
3004	return added;
3005	}
3006
3007	bool dc_remove_plane_from_context(
3008	const struct dc *dc,
3009	struct dc_stream_state *stream,
3010	struct dc_plane_state *plane_state,
3011	struct dc_state *context)
3012	{
3013	int i;
3014	struct dc_stream_status *stream_status = NULL;
3015	struct resource_pool *pool = dc->res_pool;
3016
3017	if (!plane_state)
3018	return true;
3019
3020	for (i = 0; i < context->stream_count; i++)
3021	if (context->streams[i] == stream) {
3022	stream_status = &context->stream_status[i];
3023	break;
3024	}
3025
3026	if (stream_status == NULL) {
3027	dm_error("Existing stream not found; failed to remove plane.\n");
3028	return false;
3029	}
3030
3031	resource_remove_dpp_pipes_for_plane_composition(
3032	context, pool, plane_state);
3033
3034	for (i = 0; i < stream_status->plane_count; i++) {
3035	if (stream_status->plane_states[i] == plane_state) {
3036	dc_plane_state_release(plane_state: stream_status->plane_states[i]);
3037	break;
3038	}
3039	}
3040
3041	if (i == stream_status->plane_count) {
3042	dm_error("Existing plane_state not found; failed to detach it!\n");
3043	return false;
3044	}
3045
3046	stream_status->plane_count--;
3047
3048	/* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
3049	for (; i < stream_status->plane_count; i++)
3050	stream_status->plane_states[i] = stream_status->plane_states[i + 1];
3051
3052	stream_status->plane_states[stream_status->plane_count] = NULL;
3053
3054	if (stream_status->plane_count == 0 && dc->config.enable_windowed_mpo_odm)
3055	/* ODM combine could prevent us from supporting more planes
3056	* we will reset ODM slice count back to 1 when all planes have
3057	* been removed to maximize the amount of planes supported when
3058	* new planes are added.
3059	*/
3060	resource_update_pipes_for_stream_with_slice_count(
3061	new_ctx: context, cur_ctx: dc->current_state, pool: dc->res_pool, stream, new_slice_count: 1);
3062
3063	return true;
3064	}
3065
3066	/**
3067	* dc_rem_all_planes_for_stream - Remove planes attached to the target stream.
3068	*
3069	* @dc: Current dc state.
3070	* @stream: Target stream, which we want to remove the attached plans.
3071	* @context: New context.
3072	*
3073	* Return:
3074	* Return true if DC was able to remove all planes from the target
3075	* stream, otherwise, return false.
3076	*/
3077	bool dc_rem_all_planes_for_stream(
3078	const struct dc *dc,
3079	struct dc_stream_state *stream,
3080	struct dc_state *context)
3081	{
3082	int i, old_plane_count;
3083	struct dc_stream_status *stream_status = NULL;
3084	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
3085
3086	for (i = 0; i < context->stream_count; i++)
3087	if (context->streams[i] == stream) {
3088	stream_status = &context->stream_status[i];
3089	break;
3090	}
3091
3092	if (stream_status == NULL) {
3093	dm_error("Existing stream %p not found!\n", stream);
3094	return false;
3095	}
3096
3097	old_plane_count = stream_status->plane_count;
3098
3099	for (i = 0; i < old_plane_count; i++)
3100	del_planes[i] = stream_status->plane_states[i];
3101
3102	for (i = 0; i < old_plane_count; i++)
3103	if (!dc_remove_plane_from_context(dc, stream, plane_state: del_planes[i], context))
3104	return false;
3105
3106	return true;
3107	}
3108
3109	static bool add_all_planes_for_stream(
3110	const struct dc *dc,
3111	struct dc_stream_state *stream,
3112	const struct dc_validation_set set[],
3113	int set_count,
3114	struct dc_state *context)
3115	{
3116	int i, j;
3117
3118	for (i = 0; i < set_count; i++)
3119	if (set[i].stream == stream)
3120	break;
3121
3122	if (i == set_count) {
3123	dm_error("Stream %p not found in set!\n", stream);
3124	return false;
3125	}
3126
3127	for (j = 0; j < set[i].plane_count; j++)
3128	if (!dc_add_plane_to_context(dc, stream, plane_state: set[i].plane_states[j], context))
3129	return false;
3130
3131	return true;
3132	}
3133
3134	bool dc_add_all_planes_for_stream(
3135	const struct dc *dc,
3136	struct dc_stream_state *stream,
3137	struct dc_plane_state * const *plane_states,
3138	int plane_count,
3139	struct dc_state *context)
3140	{
3141	struct dc_validation_set set;
3142	int i;
3143
3144	set.stream = stream;
3145	set.plane_count = plane_count;
3146
3147	for (i = 0; i < plane_count; i++)
3148	set.plane_states[i] = plane_states[i];
3149
3150	return add_all_planes_for_stream(dc, stream, set: &set, set_count: 1, context);
3151	}
3152
3153	bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
3154	struct dc_stream_state *new_stream)
3155	{
3156	if (cur_stream == NULL)
3157	return true;
3158
3159	/* If output color space is changed, need to reprogram info frames */
3160	if (cur_stream->output_color_space != new_stream->output_color_space)
3161	return true;
3162
3163	return memcmp(
3164	p: &cur_stream->timing,
3165	q: &new_stream->timing,
3166	size: sizeof(struct dc_crtc_timing)) != 0;
3167	}
3168
3169	static bool are_stream_backends_same(
3170	struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
3171	{
3172	if (stream_a == stream_b)
3173	return true;
3174
3175	if (stream_a == NULL || stream_b == NULL)
3176	return false;
3177
3178	if (dc_is_timing_changed(cur_stream: stream_a, new_stream: stream_b))
3179	return false;
3180
3181	if (stream_a->signal != stream_b->signal)
3182	return false;
3183
3184	if (stream_a->dpms_off != stream_b->dpms_off)
3185	return false;
3186
3187	return true;
3188	}
3189
3190	/*
3191	* dc_is_stream_unchanged() - Compare two stream states for equivalence.
3192	*
3193	* Checks if there a difference between the two states
3194	* that would require a mode change.
3195	*
3196	* Does not compare cursor position or attributes.
3197	*/
3198	bool dc_is_stream_unchanged(
3199	struct dc_stream_state *old_stream, struct dc_stream_state *stream)
3200	{
3201
3202	if (!are_stream_backends_same(stream_a: old_stream, stream_b: stream))
3203	return false;
3204
3205	if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
3206	return false;
3207
3208	/*compare audio info*/
3209	if (memcmp(p: &old_stream->audio_info, q: &stream->audio_info, size: sizeof(stream->audio_info)) != 0)
3210	return false;
3211
3212	return true;
3213	}
3214
3215	/*
3216	* dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
3217	*/
3218	bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
3219	struct dc_stream_state *stream)
3220	{
3221	if (old_stream == stream)
3222	return true;
3223
3224	if (old_stream == NULL || stream == NULL)
3225	return false;
3226
3227	if (memcmp(p: &old_stream->src,
3228	q: &stream->src,
3229	size: sizeof(struct rect)) != 0)
3230	return false;
3231
3232	if (memcmp(p: &old_stream->dst,
3233	q: &stream->dst,
3234	size: sizeof(struct rect)) != 0)
3235	return false;
3236
3237	return true;
3238	}
3239
3240	/* TODO: release audio object */
3241	void update_audio_usage(
3242	struct resource_context *res_ctx,
3243	const struct resource_pool *pool,
3244	struct audio *audio,
3245	bool acquired)
3246	{
3247	int i;
3248	for (i = 0; i < pool->audio_count; i++) {
3249	if (pool->audios[i] == audio)
3250	res_ctx->is_audio_acquired[i] = acquired;
3251	}
3252	}
3253
3254	static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
3255	struct resource_context *res_ctx,
3256	const struct resource_pool *pool,
3257	struct dc_stream_state *stream)
3258	{
3259	int i;
3260
3261	for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
3262	if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] &&
3263	pool->hpo_dp_stream_enc[i]) {
3264
3265	return pool->hpo_dp_stream_enc[i];
3266	}
3267	}
3268
3269	return NULL;
3270	}
3271
3272	static struct audio *find_first_free_audio(
3273	struct resource_context *res_ctx,
3274	const struct resource_pool *pool,
3275	enum engine_id id,
3276	enum dce_version dc_version)
3277	{
3278	int i, available_audio_count;
3279
3280	available_audio_count = pool->audio_count;
3281
3282	for (i = 0; i < available_audio_count; i++) {
3283	if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
3284	/*we have enough audio endpoint, find the matching inst*/
3285	if (id != i)
3286	continue;
3287	return pool->audios[i];
3288	}
3289	}
3290
3291	/* use engine id to find free audio */
3292	if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
3293	return pool->audios[id];
3294	}
3295	/*not found the matching one, first come first serve*/
3296	for (i = 0; i < available_audio_count; i++) {
3297	if (res_ctx->is_audio_acquired[i] == false) {
3298	return pool->audios[i];
3299	}
3300	}
3301	return NULL;
3302	}
3303
3304	/*
3305	* dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
3306	*/
3307	enum dc_status dc_add_stream_to_ctx(
3308	struct dc *dc,
3309	struct dc_state *new_ctx,
3310	struct dc_stream_state *stream)
3311	{
3312	enum dc_status res;
3313	DC_LOGGER_INIT(dc->ctx->logger);
3314
3315	if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
3316	DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
3317	return DC_ERROR_UNEXPECTED;
3318	}
3319
3320	new_ctx->streams[new_ctx->stream_count] = stream;
3321	dc_stream_retain(dc_stream: stream);
3322	new_ctx->stream_count++;
3323
3324	res = resource_add_otg_master_for_stream_output(
3325	new_ctx, pool: dc->res_pool, stream);
3326	if (res != DC_OK)
3327	DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
3328
3329	return res;
3330	}
3331
3332	/*
3333	* dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
3334	*/
3335	enum dc_status dc_remove_stream_from_ctx(
3336	struct dc *dc,
3337	struct dc_state *new_ctx,
3338	struct dc_stream_state *stream)
3339	{
3340	int i;
3341	struct dc_context *dc_ctx = dc->ctx;
3342	struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(
3343	res_ctx: &new_ctx->res_ctx, stream);
3344
3345	if (!del_pipe) {
3346	DC_ERROR("Pipe not found for stream %p !\n", stream);
3347	return DC_ERROR_UNEXPECTED;
3348	}
3349
3350	resource_update_pipes_for_stream_with_slice_count(new_ctx,
3351	cur_ctx: dc->current_state, pool: dc->res_pool, stream, new_slice_count: 1);
3352	resource_remove_otg_master_for_stream_output(
3353	context: new_ctx, pool: dc->res_pool, stream);
3354
3355	for (i = 0; i < new_ctx->stream_count; i++)
3356	if (new_ctx->streams[i] == stream)
3357	break;
3358
3359	if (new_ctx->streams[i] != stream) {
3360	DC_ERROR("Context doesn't have stream %p !\n", stream);
3361	return DC_ERROR_UNEXPECTED;
3362	}
3363
3364	dc_stream_release(dc_stream: new_ctx->streams[i]);
3365	new_ctx->stream_count--;
3366
3367	/* Trim back arrays */
3368	for (; i < new_ctx->stream_count; i++) {
3369	new_ctx->streams[i] = new_ctx->streams[i + 1];
3370	new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
3371	}
3372
3373	new_ctx->streams[new_ctx->stream_count] = NULL;
3374	memset(
3375	&new_ctx->stream_status[new_ctx->stream_count],
3376	0,
3377	sizeof(new_ctx->stream_status[0]));
3378
3379	return DC_OK;
3380	}
3381
3382	static struct dc_stream_state *find_pll_sharable_stream(
3383	struct dc_stream_state *stream_needs_pll,
3384	struct dc_state *context)
3385	{
3386	int i;
3387
3388	for (i = 0; i < context->stream_count; i++) {
3389	struct dc_stream_state *stream_has_pll = context->streams[i];
3390
3391	/* We are looking for non dp, non virtual stream */
3392	if (resource_are_streams_timing_synchronizable(
3393	stream1: stream_needs_pll, stream2: stream_has_pll)
3394	&& !dc_is_dp_signal(signal: stream_has_pll->signal)
3395	&& stream_has_pll->link->connector_signal
3396	!= SIGNAL_TYPE_VIRTUAL)
3397	return stream_has_pll;
3398
3399	}
3400
3401	return NULL;
3402	}
3403
3404	static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
3405	{
3406	uint32_t pix_clk = timing->pix_clk_100hz;
3407	uint32_t normalized_pix_clk = pix_clk;
3408
3409	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3410	pix_clk /= 2;
3411	if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
3412	switch (timing->display_color_depth) {
3413	case COLOR_DEPTH_666:
3414	case COLOR_DEPTH_888:
3415	normalized_pix_clk = pix_clk;
3416	break;
3417	case COLOR_DEPTH_101010:
3418	normalized_pix_clk = (pix_clk * 30) / 24;
3419	break;
3420	case COLOR_DEPTH_121212:
3421	normalized_pix_clk = (pix_clk * 36) / 24;
3422	break;
3423	case COLOR_DEPTH_161616:
3424	normalized_pix_clk = (pix_clk * 48) / 24;
3425	break;
3426	default:
3427	ASSERT(0);
3428	break;
3429	}
3430	}
3431	return normalized_pix_clk;
3432	}
3433
3434	static void calculate_phy_pix_clks(struct dc_stream_state *stream)
3435	{
3436	/* update actual pixel clock on all streams */
3437	if (dc_is_hdmi_signal(signal: stream->signal))
3438	stream->phy_pix_clk = get_norm_pix_clk(
3439	timing: &stream->timing) / 10;
3440	else
3441	stream->phy_pix_clk =
3442	stream->timing.pix_clk_100hz / 10;
3443
3444	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
3445	stream->phy_pix_clk *= 2;
3446	}
3447
3448	static int acquire_resource_from_hw_enabled_state(
3449	struct resource_context *res_ctx,
3450	const struct resource_pool *pool,
3451	struct dc_stream_state *stream)
3452	{
3453	struct dc_link *link = stream->link;
3454	unsigned int i, inst, tg_inst = 0;
3455	uint32_t numPipes = 1;
3456	uint32_t id_src[4] = {0};
3457
3458	/* Check for enabled DIG to identify enabled display */
3459	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
3460	return -1;
3461
3462	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
3463
3464	if (inst == ENGINE_ID_UNKNOWN)
3465	return -1;
3466
3467	for (i = 0; i < pool->stream_enc_count; i++) {
3468	if (pool->stream_enc[i]->id == inst) {
3469	tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
3470	pool->stream_enc[i]);
3471	break;
3472	}
3473	}
3474
3475	// tg_inst not found
3476	if (i == pool->stream_enc_count)
3477	return -1;
3478
3479	if (tg_inst >= pool->timing_generator_count)
3480	return -1;
3481
3482	if (!res_ctx->pipe_ctx[tg_inst].stream) {
3483	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
3484
3485	pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3486	id_src[0] = tg_inst;
3487
3488	if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
3489	pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
3490	&numPipes, &id_src[0], &id_src[1]);
3491
3492	if (id_src[0] == 0xf && id_src[1] == 0xf) {
3493	id_src[0] = tg_inst;
3494	numPipes = 1;
3495	}
3496
3497	for (i = 0; i < numPipes; i++) {
3498	//Check if src id invalid
3499	if (id_src[i] == 0xf)
3500	return -1;
3501
3502	pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];
3503
3504	pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3505	pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
3506	pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
3507	pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
3508	pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
3509	pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
3510	pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
3511
3512	if (pool->dpps[id_src[i]]) {
3513	pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
3514
3515	if (pool->mpc->funcs->read_mpcc_state) {
3516	struct mpcc_state s = {0};
3517
3518	pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
3519
3520	if (s.dpp_id < MAX_MPCC)
3521	pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
3522	s.dpp_id;
3523
3524	if (s.bot_mpcc_id < MAX_MPCC)
3525	pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
3526	&pool->mpc->mpcc_array[s.bot_mpcc_id];
3527
3528	if (s.opp_id < MAX_OPP)
3529	pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
3530	}
3531	}
3532	pipe_ctx->pipe_idx = id_src[i];
3533
3534	if (id_src[i] >= pool->timing_generator_count) {
3535	id_src[i] = pool->timing_generator_count - 1;
3536
3537	pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
3538	pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
3539	}
3540
3541	pipe_ctx->stream = stream;
3542	}
3543
3544	if (numPipes == 2) {
3545	stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
3546	res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
3547	res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
3548	res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
3549	res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
3550	} else
3551	stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
3552
3553	return id_src[0];
3554	}
3555
3556	return -1;
3557	}
3558
3559	static void mark_seamless_boot_stream(
3560	const struct dc *dc,
3561	struct dc_stream_state *stream)
3562	{
3563	struct dc_bios *dcb = dc->ctx->dc_bios;
3564
3565	if (dc->config.allow_seamless_boot_optimization &&
3566	!dcb->funcs->is_accelerated_mode(dcb)) {
3567	if (dc_validate_boot_timing(dc, sink: stream->sink, crtc_timing: &stream->timing))
3568	stream->apply_seamless_boot_optimization = true;
3569	}
3570	}
3571
3572	/*
3573	* Acquire a pipe as OTG master and assign to the stream in new dc context.
3574	* return - true if OTG master pipe is acquired and new dc context is updated.
3575	* false if it fails to acquire an OTG master pipe for this stream.
3576	*
3577	* In the example below, we acquired pipe 0 as OTG master pipe for the stream.
3578	* After the function its Inter-pipe Relation is represented by the diagram
3579	* below.
3580	*
3581	* Inter-pipe Relation
3582	* __________________________________________________
3583	* |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3584	* | | | | |
3585	* | 0 | |blank ------------------ |
3586	* |________|_______________|___________|_____________|
3587	*/
3588	static bool acquire_otg_master_pipe_for_stream(
3589	struct dc_state *new_ctx,
3590	const struct resource_pool *pool,
3591	struct dc_stream_state *stream)
3592	{
3593	/* TODO: Move this function to DCN specific resource file and acquire
3594	* DSC resource here. The reason is that the function should have the
3595	* same level of responsibility as when we acquire secondary OPP head.
3596	* We acquire DSC when we acquire secondary OPP head, so we should
3597	* acquire DSC when we acquire OTG master.
3598	*/
3599	int pipe_idx;
3600	struct pipe_ctx *pipe_ctx = NULL;
3601
3602	pipe_idx = resource_find_any_free_pipe(new_res_ctx: &new_ctx->res_ctx, pool);
3603	if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
3604	pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
3605	memset(pipe_ctx, 0, sizeof(*pipe_ctx));
3606	pipe_ctx->pipe_idx = pipe_idx;
3607	pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
3608	pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
3609	pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
3610	pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];
3611	pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];
3612	pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
3613	pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
3614	if (pool->dpps[pipe_idx])
3615	pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
3616
3617	if (pipe_idx >= pool->timing_generator_count) {
3618	int tg_inst = pool->timing_generator_count - 1;
3619
3620	pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3621	pipe_ctx->stream_res.opp = pool->opps[tg_inst];
3622	}
3623
3624	pipe_ctx->stream = stream;
3625	} else {
3626	pipe_idx = acquire_first_split_pipe(res_ctx: &new_ctx->res_ctx, pool, stream);
3627	}
3628
3629	return pipe_idx != FREE_PIPE_INDEX_NOT_FOUND;
3630	}
3631
3632	enum dc_status resource_map_pool_resources(
3633	const struct dc *dc,
3634	struct dc_state *context,
3635	struct dc_stream_state *stream)
3636	{
3637	const struct resource_pool *pool = dc->res_pool;
3638	int i;
3639	struct dc_context *dc_ctx = dc->ctx;
3640	struct pipe_ctx *pipe_ctx = NULL;
3641	int pipe_idx = -1;
3642	bool acquired = false;
3643
3644	calculate_phy_pix_clks(stream);
3645
3646	mark_seamless_boot_stream(dc, stream);
3647
3648	if (stream->apply_seamless_boot_optimization) {
3649	pipe_idx = acquire_resource_from_hw_enabled_state(
3650	res_ctx: &context->res_ctx,
3651	pool,
3652	stream);
3653	if (pipe_idx < 0)
3654	/* hw resource was assigned to other stream */
3655	stream->apply_seamless_boot_optimization = false;
3656	else
3657	acquired = true;
3658	}
3659
3660	if (!acquired)
3661	/* acquire new resources */
3662	acquired = acquire_otg_master_pipe_for_stream(
3663	new_ctx: context, pool, stream);
3664
3665	pipe_ctx = resource_get_otg_master_for_stream(res_ctx: &context->res_ctx, stream);
3666
3667	if (!pipe_ctx || pipe_ctx->stream_res.tg == NULL)
3668	return DC_NO_CONTROLLER_RESOURCE;
3669
3670	pipe_ctx->stream_res.stream_enc =
3671	dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
3672	&context->res_ctx, pool, stream);
3673
3674	if (!pipe_ctx->stream_res.stream_enc)
3675	return DC_NO_STREAM_ENC_RESOURCE;
3676
3677	update_stream_engine_usage(
3678	res_ctx: &context->res_ctx, pool,
3679	stream_enc: pipe_ctx->stream_res.stream_enc,
3680	acquired: true);
3681
3682	/* Allocate DP HPO Stream Encoder based on signal, hw capabilities
3683	* and link settings
3684	*/
3685	if (dc_is_dp_signal(signal: stream->signal)) {
3686	if (!dc->link_srv->dp_decide_link_settings(stream, &pipe_ctx->link_config.dp_link_settings))
3687	return DC_FAIL_DP_LINK_BANDWIDTH;
3688	if (dc->link_srv->dp_get_encoding_format(
3689	&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
3690	pipe_ctx->stream_res.hpo_dp_stream_enc =
3691	find_first_free_match_hpo_dp_stream_enc_for_link(
3692	res_ctx: &context->res_ctx, pool, stream);
3693
3694	if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
3695	return DC_NO_STREAM_ENC_RESOURCE;
3696
3697	update_hpo_dp_stream_engine_usage(
3698	res_ctx: &context->res_ctx, pool,
3699	hpo_dp_stream_enc: pipe_ctx->stream_res.hpo_dp_stream_enc,
3700	acquired: true);
3701	if (!add_hpo_dp_link_enc_to_ctx(res_ctx: &context->res_ctx, pool, pipe_ctx, stream))
3702	return DC_NO_LINK_ENC_RESOURCE;
3703	}
3704	}
3705
3706	/* TODO: Add check if ASIC support and EDID audio */
3707	if (!stream->converter_disable_audio &&
3708	dc_is_audio_capable_signal(signal: pipe_ctx->stream->signal) &&
3709	stream->audio_info.mode_count && stream->audio_info.flags.all) {
3710	pipe_ctx->stream_res.audio = find_first_free_audio(
3711	res_ctx: &context->res_ctx, pool, id: pipe_ctx->stream_res.stream_enc->id, dc_version: dc_ctx->dce_version);
3712
3713	/*
3714	* Audio assigned in order first come first get.
3715	* There are asics which has number of audio
3716	* resources less then number of pipes
3717	*/
3718	if (pipe_ctx->stream_res.audio)
3719	update_audio_usage(res_ctx: &context->res_ctx, pool,
3720	audio: pipe_ctx->stream_res.audio, acquired: true);
3721	}
3722
3723	/* Add ABM to the resource if on EDP */
3724	if (pipe_ctx->stream && dc_is_embedded_signal(signal: pipe_ctx->stream->signal)) {
3725	if (pool->abm)
3726	pipe_ctx->stream_res.abm = pool->abm;
3727	else
3728	pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
3729	}
3730
3731	for (i = 0; i < context->stream_count; i++)
3732	if (context->streams[i] == stream) {
3733	context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3734	context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3735	context->stream_status[i].audio_inst =
3736	pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
3737
3738	return DC_OK;
3739	}
3740
3741	DC_ERROR("Stream %p not found in new ctx!\n", stream);
3742	return DC_ERROR_UNEXPECTED;
3743	}
3744
3745	/**
3746	* dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
3747	*
3748	* @dc: copy out of dc->current_state
3749	* @dst_ctx: copy into this
3750	*
3751	* This function makes a shallow copy of the current DC state and increments
3752	* refcounts on existing streams and planes.
3753	*/
3754	void dc_resource_state_copy_construct_current(
3755	const struct dc *dc,
3756	struct dc_state *dst_ctx)
3757	{
3758	dc_resource_state_copy_construct(src_ctx: dc->current_state, dst_ctx);
3759	}
3760
3761
3762	void dc_resource_state_construct(
3763	const struct dc *dc,
3764	struct dc_state *dst_ctx)
3765	{
3766	dst_ctx->clk_mgr = dc->clk_mgr;
3767
3768	/* Initialise DIG link encoder resource tracking variables. */
3769	link_enc_cfg_init(dc, state: dst_ctx);
3770	}
3771
3772
3773	bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
3774	{
3775	if (dc->res_pool == NULL)
3776	return false;
3777
3778	return dc->res_pool->res_cap->num_dsc > 0;
3779	}
3780
3781	static bool planes_changed_for_existing_stream(struct dc_state *context,
3782	struct dc_stream_state *stream,
3783	const struct dc_validation_set set[],
3784	int set_count)
3785	{
3786	int i, j;
3787	struct dc_stream_status *stream_status = NULL;
3788
3789	for (i = 0; i < context->stream_count; i++) {
3790	if (context->streams[i] == stream) {
3791	stream_status = &context->stream_status[i];
3792	break;
3793	}
3794	}
3795
3796	if (!stream_status)
3797	ASSERT(0);
3798
3799	for (i = 0; i < set_count; i++)
3800	if (set[i].stream == stream)
3801	break;
3802
3803	if (i == set_count)
3804	ASSERT(0);
3805
3806	if (set[i].plane_count != stream_status->plane_count)
3807	return true;
3808
3809	for (j = 0; j < set[i].plane_count; j++)
3810	if (set[i].plane_states[j] != stream_status->plane_states[j])
3811	return true;
3812
3813	return false;
3814	}
3815
3816	/**
3817	* dc_validate_with_context - Validate and update the potential new stream in the context object
3818	*
3819	* @dc: Used to get the current state status
3820	* @set: An array of dc_validation_set with all the current streams reference
3821	* @set_count: Total of streams
3822	* @context: New context
3823	* @fast_validate: Enable or disable fast validation
3824	*
3825	* This function updates the potential new stream in the context object. It
3826	* creates multiple lists for the add, remove, and unchanged streams. In
3827	* particular, if the unchanged streams have a plane that changed, it is
3828	* necessary to remove all planes from the unchanged streams. In summary, this
3829	* function is responsible for validating the new context.
3830	*
3831	* Return:
3832	* In case of success, return DC_OK (1), otherwise, return a DC error.
3833	*/
3834	enum dc_status dc_validate_with_context(struct dc *dc,
3835	const struct dc_validation_set set[],
3836	int set_count,
3837	struct dc_state *context,
3838	bool fast_validate)
3839	{
3840	struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };
3841	struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };
3842	struct dc_stream_state *add_streams[MAX_PIPES] = { 0 };
3843	int old_stream_count = context->stream_count;
3844	enum dc_status res = DC_ERROR_UNEXPECTED;
3845	int unchanged_streams_count = 0;
3846	int del_streams_count = 0;
3847	int add_streams_count = 0;
3848	bool found = false;
3849	int i, j, k;
3850
3851	DC_LOGGER_INIT(dc->ctx->logger);
3852
3853	/* First build a list of streams to be remove from current context */
3854	for (i = 0; i < old_stream_count; i++) {
3855	struct dc_stream_state *stream = context->streams[i];
3856
3857	for (j = 0; j < set_count; j++) {
3858	if (stream == set[j].stream) {
3859	found = true;
3860	break;
3861	}
3862	}
3863
3864	if (!found)
3865	del_streams[del_streams_count++] = stream;
3866
3867	found = false;
3868	}
3869
3870	/* Second, build a list of new streams */
3871	for (i = 0; i < set_count; i++) {
3872	struct dc_stream_state *stream = set[i].stream;
3873
3874	for (j = 0; j < old_stream_count; j++) {
3875	if (stream == context->streams[j]) {
3876	found = true;
3877	break;
3878	}
3879	}
3880
3881	if (!found)
3882	add_streams[add_streams_count++] = stream;
3883
3884	found = false;
3885	}
3886
3887	/* Build a list of unchanged streams which is necessary for handling
3888	* planes change such as added, removed, and updated.
3889	*/
3890	for (i = 0; i < set_count; i++) {
3891	/* Check if stream is part of the delete list */
3892	for (j = 0; j < del_streams_count; j++) {
3893	if (set[i].stream == del_streams[j]) {
3894	found = true;
3895	break;
3896	}
3897	}
3898
3899	if (!found) {
3900	/* Check if stream is part of the add list */
3901	for (j = 0; j < add_streams_count; j++) {
3902	if (set[i].stream == add_streams[j]) {
3903	found = true;
3904	break;
3905	}
3906	}
3907	}
3908
3909	if (!found)
3910	unchanged_streams[unchanged_streams_count++] = set[i].stream;
3911
3912	found = false;
3913	}
3914
3915	/* Remove all planes for unchanged streams if planes changed */
3916	for (i = 0; i < unchanged_streams_count; i++) {
3917	if (planes_changed_for_existing_stream(context,
3918	stream: unchanged_streams[i],
3919	set,
3920	set_count)) {
3921	if (!dc_rem_all_planes_for_stream(dc,
3922	stream: unchanged_streams[i],
3923	context)) {
3924	res = DC_FAIL_DETACH_SURFACES;
3925	goto fail;
3926	}
3927	}
3928	}
3929
3930	/* Remove all planes for removed streams and then remove the streams */
3931	for (i = 0; i < del_streams_count; i++) {
3932	/* Need to cpy the dwb data from the old stream in order to efc to work */
3933	if (del_streams[i]->num_wb_info > 0) {
3934	for (j = 0; j < add_streams_count; j++) {
3935	if (del_streams[i]->sink == add_streams[j]->sink) {
3936	add_streams[j]->num_wb_info = del_streams[i]->num_wb_info;
3937	for (k = 0; k < del_streams[i]->num_wb_info; k++)
3938	add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k];
3939	}
3940	}
3941	}
3942
3943	if (!dc_rem_all_planes_for_stream(dc, stream: del_streams[i], context)) {
3944	res = DC_FAIL_DETACH_SURFACES;
3945	goto fail;
3946	}
3947
3948	res = dc_remove_stream_from_ctx(dc, new_ctx: context, stream: del_streams[i]);
3949	if (res != DC_OK)
3950	goto fail;
3951	}
3952
3953	/* Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx
3954	* matches. This may change in the future if seamless_boot_stream can be
3955	* multiple.
3956	*/
3957	for (i = 0; i < add_streams_count; i++) {
3958	mark_seamless_boot_stream(dc, stream: add_streams[i]);
3959	if (add_streams[i]->apply_seamless_boot_optimization && i != 0) {
3960	struct dc_stream_state *temp = add_streams[0];
3961
3962	add_streams[0] = add_streams[i];
3963	add_streams[i] = temp;
3964	break;
3965	}
3966	}
3967
3968	/* Add new streams and then add all planes for the new stream */
3969	for (i = 0; i < add_streams_count; i++) {
3970	calculate_phy_pix_clks(stream: add_streams[i]);
3971	res = dc_add_stream_to_ctx(dc, new_ctx: context, stream: add_streams[i]);
3972	if (res != DC_OK)
3973	goto fail;
3974
3975	if (!add_all_planes_for_stream(dc, stream: add_streams[i], set, set_count, context)) {
3976	res = DC_FAIL_ATTACH_SURFACES;
3977	goto fail;
3978	}
3979	}
3980
3981	/* Add all planes for unchanged streams if planes changed */
3982	for (i = 0; i < unchanged_streams_count; i++) {
3983	if (planes_changed_for_existing_stream(context,
3984	stream: unchanged_streams[i],
3985	set,
3986	set_count)) {
3987	if (!add_all_planes_for_stream(dc, stream: unchanged_streams[i], set, set_count, context)) {
3988	res = DC_FAIL_ATTACH_SURFACES;
3989	goto fail;
3990	}
3991	}
3992	}
3993
3994	res = dc_validate_global_state(dc, new_ctx: context, fast_validate);
3995
3996	fail:
3997	if (res != DC_OK)
3998	DC_LOG_WARNING("%s:resource validation failed, dc_status:%d\n",
3999	__func__,
4000	res);
4001
4002	return res;
4003	}
4004
4005	/**
4006	* dc_validate_global_state() - Determine if hardware can support a given state
4007	*
4008	* @dc: dc struct for this driver
4009	* @new_ctx: state to be validated
4010	* @fast_validate: set to true if only yes/no to support matters
4011	*
4012	* Checks hardware resource availability and bandwidth requirement.
4013	*
4014	* Return:
4015	* DC_OK if the result can be programmed. Otherwise, an error code.
4016	*/
4017	enum dc_status dc_validate_global_state(
4018	struct dc *dc,
4019	struct dc_state *new_ctx,
4020	bool fast_validate)
4021	{
4022	enum dc_status result = DC_ERROR_UNEXPECTED;
4023	int i, j;
4024
4025	if (!new_ctx)
4026	return DC_ERROR_UNEXPECTED;
4027
4028	if (dc->res_pool->funcs->validate_global) {
4029	result = dc->res_pool->funcs->validate_global(dc, new_ctx);
4030	if (result != DC_OK)
4031	return result;
4032	}
4033
4034	for (i = 0; i < new_ctx->stream_count; i++) {
4035	struct dc_stream_state *stream = new_ctx->streams[i];
4036
4037	for (j = 0; j < dc->res_pool->pipe_count; j++) {
4038	struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
4039
4040	if (pipe_ctx->stream != stream)
4041	continue;
4042
4043	if (dc->res_pool->funcs->patch_unknown_plane_state &&
4044	pipe_ctx->plane_state &&
4045	pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
4046	result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
4047	if (result != DC_OK)
4048	return result;
4049	}
4050
4051	/* Switch to dp clock source only if there is
4052	* no non dp stream that shares the same timing
4053	* with the dp stream.
4054	*/
4055	if (dc_is_dp_signal(signal: pipe_ctx->stream->signal) &&
4056	!find_pll_sharable_stream(stream_needs_pll: stream, context: new_ctx)) {
4057
4058	resource_unreference_clock_source(
4059	res_ctx: &new_ctx->res_ctx,
4060	pool: dc->res_pool,
4061	clock_source: pipe_ctx->clock_source);
4062
4063	pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
4064	resource_reference_clock_source(
4065	res_ctx: &new_ctx->res_ctx,
4066	pool: dc->res_pool,
4067	clock_source: pipe_ctx->clock_source);
4068	}
4069	}
4070	}
4071
4072	result = resource_build_scaling_params_for_context(dc, context: new_ctx);
4073
4074	if (result == DC_OK)
4075	if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
4076	result = DC_FAIL_BANDWIDTH_VALIDATE;
4077
4078	/*
4079	* Only update link encoder to stream assignment after bandwidth validation passed.
4080	* TODO: Split out assignment and validation.
4081	*/
4082	if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
4083	dc->res_pool->funcs->link_encs_assign(
4084	dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
4085
4086	return result;
4087	}
4088
4089	static void patch_gamut_packet_checksum(
4090	struct dc_info_packet *gamut_packet)
4091	{
4092	/* For gamut we recalc checksum */
4093	if (gamut_packet->valid) {
4094	uint8_t chk_sum = 0;
4095	uint8_t *ptr;
4096	uint8_t i;
4097
4098	/*start of the Gamut data. */
4099	ptr = &gamut_packet->sb[3];
4100
4101	for (i = 0; i <= gamut_packet->sb[1]; i++)
4102	chk_sum += ptr[i];
4103
4104	gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
4105	}
4106	}
4107
4108	static void set_avi_info_frame(
4109	struct dc_info_packet *info_packet,
4110	struct pipe_ctx *pipe_ctx)
4111	{
4112	struct dc_stream_state *stream = pipe_ctx->stream;
4113	enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4114	uint32_t pixel_encoding = 0;
4115	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
4116	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
4117	uint8_t *check_sum = NULL;
4118	uint8_t byte_index = 0;
4119	union hdmi_info_packet hdmi_info;
4120	unsigned int vic = pipe_ctx->stream->timing.vic;
4121	unsigned int rid = pipe_ctx->stream->timing.rid;
4122	unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
4123	enum dc_timing_3d_format format;
4124
4125	memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
4126
4127	color_space = pipe_ctx->stream->output_color_space;
4128	if (color_space == COLOR_SPACE_UNKNOWN)
4129	color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
4130	COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4131
4132	/* Initialize header */
4133	hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4134	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
4135	* not be used in HDMI 2.0 (Section 10.1) */
4136	hdmi_info.bits.header.version = 2;
4137	hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4138
4139	/*
4140	* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
4141	* according to HDMI 2.0 spec (Section 10.1)
4142	*/
4143
4144	switch (stream->timing.pixel_encoding) {
4145	case PIXEL_ENCODING_YCBCR422:
4146	pixel_encoding = 1;
4147	break;
4148
4149	case PIXEL_ENCODING_YCBCR444:
4150	pixel_encoding = 2;
4151	break;
4152	case PIXEL_ENCODING_YCBCR420:
4153	pixel_encoding = 3;
4154	break;
4155
4156	case PIXEL_ENCODING_RGB:
4157	default:
4158	pixel_encoding = 0;
4159	}
4160
4161	/* Y0_Y1_Y2 : The pixel encoding */
4162	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
4163	hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4164
4165	/* A0 = 1 Active Format Information valid */
4166	hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4167
4168	/* B0, B1 = 3; Bar info data is valid */
4169	hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4170
4171	hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4172
4173	/* S0, S1 : Underscan / Overscan */
4174	/* TODO: un-hardcode scan type */
4175	scan_type = SCANNING_TYPE_UNDERSCAN;
4176	hdmi_info.bits.S0_S1 = scan_type;
4177
4178	/* C0, C1 : Colorimetry */
4179	switch (color_space) {
4180	case COLOR_SPACE_YCBCR709:
4181	case COLOR_SPACE_YCBCR709_LIMITED:
4182	hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
4183	break;
4184	case COLOR_SPACE_YCBCR601:
4185	case COLOR_SPACE_YCBCR601_LIMITED:
4186	hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
4187	break;
4188	case COLOR_SPACE_2020_RGB_FULLRANGE:
4189	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
4190	case COLOR_SPACE_2020_YCBCR:
4191	hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
4192	hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
4193	break;
4194	case COLOR_SPACE_ADOBERGB:
4195	hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
4196	hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
4197	break;
4198	case COLOR_SPACE_SRGB:
4199	default:
4200	hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
4201	break;
4202	}
4203
4204	if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR &&
4205	stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
4206	hdmi_info.bits.EC0_EC2 = 0;
4207	hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
4208	}
4209
4210	/* TODO: un-hardcode aspect ratio */
4211	aspect = stream->timing.aspect_ratio;
4212
4213	switch (aspect) {
4214	case ASPECT_RATIO_4_3:
4215	case ASPECT_RATIO_16_9:
4216	hdmi_info.bits.M0_M1 = aspect;
4217	break;
4218
4219	case ASPECT_RATIO_NO_DATA:
4220	case ASPECT_RATIO_64_27:
4221	case ASPECT_RATIO_256_135:
4222	default:
4223	hdmi_info.bits.M0_M1 = 0;
4224	}
4225
4226	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
4227	hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4228
4229	switch (stream->content_type) {
4230	case DISPLAY_CONTENT_TYPE_NO_DATA:
4231	hdmi_info.bits.CN0_CN1 = 0;
4232	hdmi_info.bits.ITC = 1;
4233	break;
4234	case DISPLAY_CONTENT_TYPE_GRAPHICS:
4235	hdmi_info.bits.CN0_CN1 = 0;
4236	hdmi_info.bits.ITC = 1;
4237	break;
4238	case DISPLAY_CONTENT_TYPE_PHOTO:
4239	hdmi_info.bits.CN0_CN1 = 1;
4240	hdmi_info.bits.ITC = 1;
4241	break;
4242	case DISPLAY_CONTENT_TYPE_CINEMA:
4243	hdmi_info.bits.CN0_CN1 = 2;
4244	hdmi_info.bits.ITC = 1;
4245	break;
4246	case DISPLAY_CONTENT_TYPE_GAME:
4247	hdmi_info.bits.CN0_CN1 = 3;
4248	hdmi_info.bits.ITC = 1;
4249	break;
4250	}
4251
4252	if (stream->qs_bit == 1) {
4253	if (color_space == COLOR_SPACE_SRGB ||
4254	color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
4255	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
4256	else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
4257	color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
4258	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
4259	else
4260	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
4261	} else
4262	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
4263
4264	/* TODO : We should handle YCC quantization */
4265	/* but we do not have matrix calculation */
4266	hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4267
4268	///VIC
4269	if (pipe_ctx->stream->timing.hdmi_vic != 0)
4270	vic = 0;
4271	format = stream->timing.timing_3d_format;
4272	/*todo, add 3DStereo support*/
4273	if (format != TIMING_3D_FORMAT_NONE) {
4274	// Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4275	switch (pipe_ctx->stream->timing.hdmi_vic) {
4276	case 1:
4277	vic = 95;
4278	break;
4279	case 2:
4280	vic = 94;
4281	break;
4282	case 3:
4283	vic = 93;
4284	break;
4285	case 4:
4286	vic = 98;
4287	break;
4288	default:
4289	break;
4290	}
4291	}
4292	/* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
4293	hdmi_info.bits.VIC0_VIC7 = vic;
4294	if (vic >= 128)
4295	hdmi_info.bits.header.version = 3;
4296	/* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
4297	* the Source shall use 20 AVI InfoFrame Version 4
4298	*/
4299	if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
4300	hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
4301	hdmi_info.bits.header.version = 4;
4302	hdmi_info.bits.header.length = 14;
4303	}
4304
4305	if (rid != 0 && fr_ind != 0) {
4306	hdmi_info.bits.header.version = 5;
4307	hdmi_info.bits.header.length = 15;
4308
4309	hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
4310	hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
4311	hdmi_info.bits.RID0_RID5 = rid;
4312	}
4313
4314	/* pixel repetition
4315	* PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
4316	* repetition start from 1 */
4317	hdmi_info.bits.PR0_PR3 = 0;
4318
4319	/* Bar Info
4320	* barTop: Line Number of End of Top Bar.
4321	* barBottom: Line Number of Start of Bottom Bar.
4322	* barLeft: Pixel Number of End of Left Bar.
4323	* barRight: Pixel Number of Start of Right Bar. */
4324	hdmi_info.bits.bar_top = stream->timing.v_border_top;
4325	hdmi_info.bits.bar_bottom = (stream->timing.v_total
4326	- stream->timing.v_border_bottom + 1);
4327	hdmi_info.bits.bar_left = stream->timing.h_border_left;
4328	hdmi_info.bits.bar_right = (stream->timing.h_total
4329	- stream->timing.h_border_right + 1);
4330
4331	/* Additional Colorimetry Extension
4332	* Used in conduction with C0-C1 and EC0-EC2
4333	* 0 = DCI-P3 RGB (D65)
4334	* 1 = DCI-P3 RGB (theater)
4335	*/
4336	hdmi_info.bits.ACE0_ACE3 = 0;
4337
4338	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
4339	check_sum = &hdmi_info.packet_raw_data.sb[0];
4340
4341	*check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4342
4343	for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
4344	*check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4345
4346	/* one byte complement */
4347	*check_sum = (uint8_t) (0x100 - *check_sum);
4348
4349	/* Store in hw_path_mode */
4350	info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
4351	info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
4352	info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4353
4354	for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
4355	info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4356
4357	info_packet->valid = true;
4358	}
4359
4360	static void set_vendor_info_packet(
4361	struct dc_info_packet *info_packet,
4362	struct dc_stream_state *stream)
4363	{
4364	/* SPD info packet for FreeSync */
4365
4366	/* Check if Freesync is supported. Return if false. If true,
4367	* set the corresponding bit in the info packet
4368	*/
4369	if (!stream->vsp_infopacket.valid)
4370	return;
4371
4372	*info_packet = stream->vsp_infopacket;
4373	}
4374
4375	static void set_spd_info_packet(
4376	struct dc_info_packet *info_packet,
4377	struct dc_stream_state *stream)
4378	{
4379	/* SPD info packet for FreeSync */
4380
4381	/* Check if Freesync is supported. Return if false. If true,
4382	* set the corresponding bit in the info packet
4383	*/
4384	if (!stream->vrr_infopacket.valid)
4385	return;
4386
4387	*info_packet = stream->vrr_infopacket;
4388	}
4389
4390	static void set_hdr_static_info_packet(
4391	struct dc_info_packet *info_packet,
4392	struct dc_stream_state *stream)
4393	{
4394	/* HDR Static Metadata info packet for HDR10 */
4395
4396	if (!stream->hdr_static_metadata.valid ||
4397	stream->use_dynamic_meta)
4398	return;
4399
4400	*info_packet = stream->hdr_static_metadata;
4401	}
4402
4403	static void set_vsc_info_packet(
4404	struct dc_info_packet *info_packet,
4405	struct dc_stream_state *stream)
4406	{
4407	if (!stream->vsc_infopacket.valid)
4408	return;
4409
4410	*info_packet = stream->vsc_infopacket;
4411	}
4412	static void set_hfvs_info_packet(
4413	struct dc_info_packet *info_packet,
4414	struct dc_stream_state *stream)
4415	{
4416	if (!stream->hfvsif_infopacket.valid)
4417	return;
4418
4419	*info_packet = stream->hfvsif_infopacket;
4420	}
4421
4422	static void adaptive_sync_override_dp_info_packets_sdp_line_num(
4423	const struct dc_crtc_timing *timing,
4424	struct enc_sdp_line_num *sdp_line_num,
4425	struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
4426	{
4427	uint32_t asic_blank_start = 0;
4428	uint32_t asic_blank_end = 0;
4429	uint32_t v_update = 0;
4430
4431	const struct dc_crtc_timing *tg = timing;
4432
4433	/* blank_start = frame end - front porch */
4434	asic_blank_start = tg->v_total - tg->v_front_porch;
4435
4436	/* blank_end = blank_start - active */
4437	asic_blank_end = (asic_blank_start - tg->v_border_bottom -
4438	tg->v_addressable - tg->v_border_top);
4439
4440	if (pipe_dlg_param->vstartup_start > asic_blank_end) {
4441	v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end));
4442	sdp_line_num->adaptive_sync_line_num_valid = true;
4443	sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1);
4444	} else {
4445	sdp_line_num->adaptive_sync_line_num_valid = false;
4446	sdp_line_num->adaptive_sync_line_num = 0;
4447	}
4448	}
4449
4450	static void set_adaptive_sync_info_packet(
4451	struct dc_info_packet *info_packet,
4452	const struct dc_stream_state *stream,
4453	struct encoder_info_frame *info_frame,
4454	struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
4455	{
4456	if (!stream->adaptive_sync_infopacket.valid)
4457	return;
4458
4459	adaptive_sync_override_dp_info_packets_sdp_line_num(
4460	timing: &stream->timing,
4461	sdp_line_num: &info_frame->sdp_line_num,
4462	pipe_dlg_param);
4463
4464	*info_packet = stream->adaptive_sync_infopacket;
4465	}
4466
4467	static void set_vtem_info_packet(
4468	struct dc_info_packet *info_packet,
4469	struct dc_stream_state *stream)
4470	{
4471	if (!stream->vtem_infopacket.valid)
4472	return;
4473
4474	*info_packet = stream->vtem_infopacket;
4475	}
4476
4477	void dc_resource_state_destruct(struct dc_state *context)
4478	{
4479	int i, j;
4480
4481	for (i = 0; i < context->stream_count; i++) {
4482	for (j = 0; j < context->stream_status[i].plane_count; j++)
4483	dc_plane_state_release(
4484	plane_state: context->stream_status[i].plane_states[j]);
4485
4486	context->stream_status[i].plane_count = 0;
4487	dc_stream_release(dc_stream: context->streams[i]);
4488	context->streams[i] = NULL;
4489	}
4490	context->stream_count = 0;
4491	context->stream_mask = 0;
4492	memset(&context->res_ctx, 0, sizeof(context->res_ctx));
4493	memset(&context->pp_display_cfg, 0, sizeof(context->pp_display_cfg));
4494	memset(&context->dcn_bw_vars, 0, sizeof(context->dcn_bw_vars));
4495	context->clk_mgr = NULL;
4496	memset(&context->bw_ctx.bw, 0, sizeof(context->bw_ctx.bw));
4497	memset(context->block_sequence, 0, sizeof(context->block_sequence));
4498	context->block_sequence_steps = 0;
4499	memset(context->dc_dmub_cmd, 0, sizeof(context->dc_dmub_cmd));
4500	context->dmub_cmd_count = 0;
4501	memset(&context->perf_params, 0, sizeof(context->perf_params));
4502	memset(&context->scratch, 0, sizeof(context->scratch));
4503	}
4504
4505	void dc_resource_state_copy_construct(
4506	const struct dc_state *src_ctx,
4507	struct dc_state *dst_ctx)
4508	{
4509	int i, j;
4510	struct kref refcount = dst_ctx->refcount;
4511	#ifdef CONFIG_DRM_AMD_DC_FP
4512	struct dml2_context *dml2 = NULL;
4513
4514	// Need to preserve allocated dml2 context
4515	if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2)
4516	dml2 = dst_ctx->bw_ctx.dml2;
4517	#endif
4518
4519	*dst_ctx = *src_ctx;
4520
4521	#ifdef CONFIG_DRM_AMD_DC_FP
4522	// Preserve allocated dml2 context
4523	if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2)
4524	dst_ctx->bw_ctx.dml2 = dml2;
4525	#endif
4526
4527	for (i = 0; i < MAX_PIPES; i++) {
4528	struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
4529
4530	if (cur_pipe->top_pipe)
4531	cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
4532
4533	if (cur_pipe->bottom_pipe)
4534	cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
4535
4536	if (cur_pipe->next_odm_pipe)
4537	cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
4538
4539	if (cur_pipe->prev_odm_pipe)
4540	cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4541	}
4542
4543	for (i = 0; i < dst_ctx->stream_count; i++) {
4544	dc_stream_retain(dc_stream: dst_ctx->streams[i]);
4545	for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
4546	dc_plane_state_retain(
4547	plane_state: dst_ctx->stream_status[i].plane_states[j]);
4548	}
4549
4550	/* context refcount should not be overridden */
4551	dst_ctx->refcount = refcount;
4552
4553	}
4554
4555	struct clock_source *dc_resource_find_first_free_pll(
4556	struct resource_context *res_ctx,
4557	const struct resource_pool *pool)
4558	{
4559	int i;
4560
4561	for (i = 0; i < pool->clk_src_count; ++i) {
4562	if (res_ctx->clock_source_ref_count[i] == 0)
4563	return pool->clock_sources[i];
4564	}
4565
4566	return NULL;
4567	}
4568
4569	void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
4570	{
4571	enum signal_type signal = SIGNAL_TYPE_NONE;
4572	struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4573
4574	/* default all packets to invalid */
4575	info->avi.valid = false;
4576	info->gamut.valid = false;
4577	info->vendor.valid = false;
4578	info->spd.valid = false;
4579	info->hdrsmd.valid = false;
4580	info->vsc.valid = false;
4581	info->hfvsif.valid = false;
4582	info->vtem.valid = false;
4583	info->adaptive_sync.valid = false;
4584	signal = pipe_ctx->stream->signal;
4585
4586	/* HDMi and DP have different info packets*/
4587	if (dc_is_hdmi_signal(signal)) {
4588	set_avi_info_frame(info_packet: &info->avi, pipe_ctx);
4589
4590	set_vendor_info_packet(info_packet: &info->vendor, stream: pipe_ctx->stream);
4591	set_hfvs_info_packet(info_packet: &info->hfvsif, stream: pipe_ctx->stream);
4592	set_vtem_info_packet(info_packet: &info->vtem, stream: pipe_ctx->stream);
4593
4594	set_spd_info_packet(info_packet: &info->spd, stream: pipe_ctx->stream);
4595
4596	set_hdr_static_info_packet(info_packet: &info->hdrsmd, stream: pipe_ctx->stream);
4597
4598	} else if (dc_is_dp_signal(signal)) {
4599	set_vsc_info_packet(info_packet: &info->vsc, stream: pipe_ctx->stream);
4600
4601	set_spd_info_packet(info_packet: &info->spd, stream: pipe_ctx->stream);
4602
4603	set_hdr_static_info_packet(info_packet: &info->hdrsmd, stream: pipe_ctx->stream);
4604	set_adaptive_sync_info_packet(info_packet: &info->adaptive_sync,
4605	stream: pipe_ctx->stream,
4606	info_frame: info,
4607	pipe_dlg_param: &pipe_ctx->pipe_dlg_param);
4608	}
4609
4610	patch_gamut_packet_checksum(gamut_packet: &info->gamut);
4611	}
4612
4613	enum dc_status resource_map_clock_resources(
4614	const struct dc *dc,
4615	struct dc_state *context,
4616	struct dc_stream_state *stream)
4617	{
4618	/* acquire new resources */
4619	const struct resource_pool *pool = dc->res_pool;
4620	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
4621	res_ctx: &context->res_ctx, stream);
4622
4623	if (!pipe_ctx)
4624	return DC_ERROR_UNEXPECTED;
4625
4626	if (dc_is_dp_signal(signal: pipe_ctx->stream->signal)
4627	|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
4628	pipe_ctx->clock_source = pool->dp_clock_source;
4629	else {
4630	pipe_ctx->clock_source = NULL;
4631
4632	if (!dc->config.disable_disp_pll_sharing)
4633	pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
4634	res_ctx: &context->res_ctx,
4635	pipe_ctx);
4636
4637	if (pipe_ctx->clock_source == NULL)
4638	pipe_ctx->clock_source =
4639	dc_resource_find_first_free_pll(
4640	res_ctx: &context->res_ctx,
4641	pool);
4642	}
4643
4644	if (pipe_ctx->clock_source == NULL)
4645	return DC_NO_CLOCK_SOURCE_RESOURCE;
4646
4647	resource_reference_clock_source(
4648	res_ctx: &context->res_ctx, pool,
4649	clock_source: pipe_ctx->clock_source);
4650
4651	return DC_OK;
4652	}
4653
4654	/*
4655	* Note: We need to disable output if clock sources change,
4656	* since bios does optimization and doesn't apply if changing
4657	* PHY when not already disabled.
4658	*/
4659	bool pipe_need_reprogram(
4660	struct pipe_ctx *pipe_ctx_old,
4661	struct pipe_ctx *pipe_ctx)
4662	{
4663	if (!pipe_ctx_old->stream)
4664	return false;
4665
4666	if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
4667	return true;
4668
4669	if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
4670	return true;
4671
4672	if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4673	return true;
4674
4675	if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
4676	&& pipe_ctx_old->stream != pipe_ctx->stream)
4677	return true;
4678
4679	if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4680	return true;
4681
4682	if (dc_is_timing_changed(cur_stream: pipe_ctx_old->stream, new_stream: pipe_ctx->stream))
4683	return true;
4684
4685	if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
4686	return true;
4687
4688	if (false == pipe_ctx_old->stream->link->link_state_valid &&
4689	false == pipe_ctx_old->stream->dpms_off)
4690	return true;
4691
4692	if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
4693	return true;
4694
4695	if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
4696	return true;
4697	if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
4698	return true;
4699
4700	/* DIG link encoder resource assignment for stream changed. */
4701	if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
4702	bool need_reprogram = false;
4703	struct dc *dc = pipe_ctx_old->stream->ctx->dc;
4704	struct link_encoder *link_enc_prev =
4705	link_enc_cfg_get_link_enc_used_by_stream_current(dc, stream: pipe_ctx_old->stream);
4706
4707	if (link_enc_prev != pipe_ctx->stream->link_enc)
4708	need_reprogram = true;
4709
4710	return need_reprogram;
4711	}
4712
4713	return false;
4714	}
4715
4716	void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
4717	struct bit_depth_reduction_params *fmt_bit_depth)
4718	{
4719	enum dc_dither_option option = stream->dither_option;
4720	enum dc_pixel_encoding pixel_encoding =
4721	stream->timing.pixel_encoding;
4722
4723	memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
4724
4725	if (option == DITHER_OPTION_DEFAULT) {
4726	switch (stream->timing.display_color_depth) {
4727	case COLOR_DEPTH_666:
4728	option = DITHER_OPTION_SPATIAL6;
4729	break;
4730	case COLOR_DEPTH_888:
4731	option = DITHER_OPTION_SPATIAL8;
4732	break;
4733	case COLOR_DEPTH_101010:
4734	option = DITHER_OPTION_SPATIAL10;
4735	break;
4736	default:
4737	option = DITHER_OPTION_DISABLE;
4738	}
4739	}
4740
4741	if (option == DITHER_OPTION_DISABLE)
4742	return;
4743
4744	if (option == DITHER_OPTION_TRUN6) {
4745	fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4746	fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
4747	} else if (option == DITHER_OPTION_TRUN8 ||
4748	option == DITHER_OPTION_TRUN8_SPATIAL6 ||
4749	option == DITHER_OPTION_TRUN8_FM6) {
4750	fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4751	fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
4752	} else if (option == DITHER_OPTION_TRUN10 ||
4753	option == DITHER_OPTION_TRUN10_SPATIAL6 ||
4754	option == DITHER_OPTION_TRUN10_SPATIAL8 ||
4755	option == DITHER_OPTION_TRUN10_FM8 ||
4756	option == DITHER_OPTION_TRUN10_FM6 ||
4757	option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4758	fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4759	fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
4760	}
4761
4762	/* special case - Formatter can only reduce by 4 bits at most.
4763	* When reducing from 12 to 6 bits,
4764	* HW recommends we use trunc with round mode
4765	* (if we did nothing, trunc to 10 bits would be used)
4766	* note that any 12->10 bit reduction is ignored prior to DCE8,
4767	* as the input was 10 bits.
4768	*/
4769	if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
4770	option == DITHER_OPTION_SPATIAL6 ||
4771	option == DITHER_OPTION_FM6) {
4772	fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4773	fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
4774	fmt_bit_depth->flags.TRUNCATE_MODE = 1;
4775	}
4776
4777	/* spatial dither
4778	* note that spatial modes 1-3 are never used
4779	*/
4780	if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
4781	option == DITHER_OPTION_SPATIAL6 ||
4782	option == DITHER_OPTION_TRUN10_SPATIAL6 ||
4783	option == DITHER_OPTION_TRUN8_SPATIAL6) {
4784	fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4785	fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
4786	fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4787	fmt_bit_depth->flags.RGB_RANDOM =
4788	(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4789	} else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
4790	option == DITHER_OPTION_SPATIAL8 ||
4791	option == DITHER_OPTION_SPATIAL8_FM6 ||
4792	option == DITHER_OPTION_TRUN10_SPATIAL8 ||
4793	option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4794	fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4795	fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
4796	fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4797	fmt_bit_depth->flags.RGB_RANDOM =
4798	(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4799	} else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
4800	option == DITHER_OPTION_SPATIAL10 ||
4801	option == DITHER_OPTION_SPATIAL10_FM8 ||
4802	option == DITHER_OPTION_SPATIAL10_FM6) {
4803	fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4804	fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
4805	fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4806	fmt_bit_depth->flags.RGB_RANDOM =
4807	(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4808	}
4809
4810	if (option == DITHER_OPTION_SPATIAL6 ||
4811	option == DITHER_OPTION_SPATIAL8 ||
4812	option == DITHER_OPTION_SPATIAL10) {
4813	fmt_bit_depth->flags.FRAME_RANDOM = 0;
4814	} else {
4815	fmt_bit_depth->flags.FRAME_RANDOM = 1;
4816	}
4817
4818	//////////////////////
4819	//// temporal dither
4820	//////////////////////
4821	if (option == DITHER_OPTION_FM6 ||
4822	option == DITHER_OPTION_SPATIAL8_FM6 ||
4823	option == DITHER_OPTION_SPATIAL10_FM6 ||
4824	option == DITHER_OPTION_TRUN10_FM6 ||
4825	option == DITHER_OPTION_TRUN8_FM6 ||
4826	option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4827	fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4828	fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
4829	} else if (option == DITHER_OPTION_FM8 ||
4830	option == DITHER_OPTION_SPATIAL10_FM8 ||
4831	option == DITHER_OPTION_TRUN10_FM8) {
4832	fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4833	fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
4834	} else if (option == DITHER_OPTION_FM10) {
4835	fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4836	fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
4837	}
4838
4839	fmt_bit_depth->pixel_encoding = pixel_encoding;
4840	}
4841
4842	enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
4843	{
4844	struct dc_link *link = stream->link;
4845	struct timing_generator *tg = dc->res_pool->timing_generators[0];
4846	enum dc_status res = DC_OK;
4847
4848	calculate_phy_pix_clks(stream);
4849
4850	if (!tg->funcs->validate_timing(tg, &stream->timing))
4851	res = DC_FAIL_CONTROLLER_VALIDATE;
4852
4853	if (res == DC_OK) {
4854	if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
4855	!link->link_enc->funcs->validate_output_with_stream(
4856	link->link_enc, stream))
4857	res = DC_FAIL_ENC_VALIDATE;
4858	}
4859
4860	/* TODO: validate audio ASIC caps, encoder */
4861
4862	if (res == DC_OK)
4863	res = dc->link_srv->validate_mode_timing(stream,
4864	link,
4865	&stream->timing);
4866
4867	return res;
4868	}
4869
4870	enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
4871	{
4872	enum dc_status res = DC_OK;
4873
4874	/* check if surface has invalid dimensions */
4875	if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
4876	plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
4877	return DC_FAIL_SURFACE_VALIDATE;
4878
4879	/* TODO For now validates pixel format only */
4880	if (dc->res_pool->funcs->validate_plane)
4881	return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
4882
4883	return res;
4884	}
4885
4886	unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
4887	{
4888	switch (format) {
4889	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
4890	return 8;
4891	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4892	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
4893	return 12;
4894	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
4895	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
4896	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
4897	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
4898	return 16;
4899	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
4900	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4901	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
4902	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
4903	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
4904	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
4905	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
4906	return 32;
4907	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
4908	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
4909	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
4910	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
4911	return 64;
4912	default:
4913	ASSERT_CRITICAL(false);
4914	return -1;
4915	}
4916	}
4917	static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
4918	{
4919	if (modes) {
4920	if (modes->sample_rates.rate.RATE_192)
4921	return 192000;
4922	if (modes->sample_rates.rate.RATE_176_4)
4923	return 176400;
4924	if (modes->sample_rates.rate.RATE_96)
4925	return 96000;
4926	if (modes->sample_rates.rate.RATE_88_2)
4927	return 88200;
4928	if (modes->sample_rates.rate.RATE_48)
4929	return 48000;
4930	if (modes->sample_rates.rate.RATE_44_1)
4931	return 44100;
4932	if (modes->sample_rates.rate.RATE_32)
4933	return 32000;
4934	}
4935	/*original logic when no audio info*/
4936	return 441000;
4937	}
4938
4939	void get_audio_check(struct audio_info *aud_modes,
4940	struct audio_check *audio_chk)
4941	{
4942	unsigned int i;
4943	unsigned int max_sample_rate = 0;
4944
4945	if (aud_modes) {
4946	audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
4947
4948	audio_chk->max_audiosample_rate = 0;
4949	for (i = 0; i < aud_modes->mode_count; i++) {
4950	max_sample_rate = get_max_audio_sample_rate(modes: &aud_modes->modes[i]);
4951	if (audio_chk->max_audiosample_rate < max_sample_rate)
4952	audio_chk->max_audiosample_rate = max_sample_rate;
4953	/*dts takes the same as type 2: AP = 0.25*/
4954	}
4955	/*check which one take more bandwidth*/
4956	if (audio_chk->max_audiosample_rate > 192000)
4957	audio_chk->audio_packet_type = 0x9;/*AP =1*/
4958	audio_chk->acat = 0;/*not support*/
4959	}
4960	}
4961
4962	static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc(
4963	const struct resource_context *res_ctx,
4964	const struct resource_pool *const pool,
4965	const struct dc_link *link)
4966	{
4967	struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
4968	int enc_index;
4969
4970	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
4971
4972	if (enc_index < 0)
4973	enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
4974
4975	if (enc_index >= 0)
4976	hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
4977
4978	return hpo_dp_link_enc;
4979	}
4980
4981	bool get_temp_dp_link_res(struct dc_link *link,
4982	struct link_resource *link_res,
4983	struct dc_link_settings *link_settings)
4984	{
4985	const struct dc *dc = link->dc;
4986	const struct resource_context *res_ctx = &dc->current_state->res_ctx;
4987
4988	memset(link_res, 0, sizeof(*link_res));
4989
4990	if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
4991	link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx,
4992	pool: dc->res_pool, link);
4993	if (!link_res->hpo_dp_link_enc)
4994	return false;
4995	}
4996	return true;
4997	}
4998
4999	void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
5000	struct dc_state *context)
5001	{
5002	int i, j;
5003	struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
5004
5005	/* If pipe backend is reset, need to reset pipe syncd status */
5006	for (i = 0; i < dc->res_pool->pipe_count; i++) {
5007	pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];
5008	pipe_ctx = &context->res_ctx.pipe_ctx[i];
5009
5010	if (!resource_is_pipe_type(pipe_ctx: pipe_ctx_old, type: OTG_MASTER))
5011	continue;
5012
5013	if (!pipe_ctx->stream ||
5014	pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
5015
5016	/* Reset all the syncd pipes from the disabled pipe */
5017	for (j = 0; j < dc->res_pool->pipe_count; j++) {
5018	pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
5019	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
5020	!IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
5021	SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
5022	}
5023	}
5024	}
5025	}
5026
5027	void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
5028	struct dc_state *context,
5029	uint8_t disabled_master_pipe_idx)
5030	{
5031	int i;
5032	struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
5033
5034	pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
5035	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
5036	!IS_PIPE_SYNCD_VALID(pipe_ctx))
5037	SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
5038
5039	/* for the pipe disabled, check if any slave pipe exists and assert */
5040	for (i = 0; i < dc->res_pool->pipe_count; i++) {
5041	pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
5042
5043	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
5044	IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) {
5045	struct pipe_ctx *first_pipe = pipe_ctx_check;
5046
5047	while (first_pipe->prev_odm_pipe)
5048	first_pipe = first_pipe->prev_odm_pipe;
5049	/* When ODM combine is enabled, this case is expected. If the disabled pipe
5050	* is part of the ODM tree, then we should not print an error.
5051	* */
5052	if (first_pipe->pipe_idx == disabled_master_pipe_idx)
5053	continue;
5054
5055	DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
5056	i, disabled_master_pipe_idx);
5057	}
5058	}
5059	}
5060
5061	void reset_sync_context_for_pipe(const struct dc *dc,
5062	struct dc_state *context,
5063	uint8_t pipe_idx)
5064	{
5065	int i;
5066	struct pipe_ctx *pipe_ctx_reset;
5067
5068	/* reset the otg sync context for the pipe and its slave pipes if any */
5069	for (i = 0; i < dc->res_pool->pipe_count; i++) {
5070	pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];
5071
5072	if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) &&
5073	IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx))
5074	SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i);
5075	}
5076	}
5077
5078	uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
5079	{
5080	/* TODO - get transmitter to phy idx mapping from DMUB */
5081	uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
5082
5083	if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
5084	dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
5085	switch (transmitter) {
5086	case TRANSMITTER_UNIPHY_A:
5087	phy_idx = 0;
5088	break;
5089	case TRANSMITTER_UNIPHY_B:
5090	phy_idx = 1;
5091	break;
5092	case TRANSMITTER_UNIPHY_C:
5093	phy_idx = 5;
5094	break;
5095	case TRANSMITTER_UNIPHY_D:
5096	phy_idx = 6;
5097	break;
5098	case TRANSMITTER_UNIPHY_E:
5099	phy_idx = 4;
5100	break;
5101	default:
5102	phy_idx = 0;
5103	break;
5104	}
5105	}
5106
5107	return phy_idx;
5108	}
5109
5110	const struct link_hwss *get_link_hwss(const struct dc_link *link,
5111	const struct link_resource *link_res)
5112	{
5113	/* Link_hwss is only accessible by getter function instead of accessing
5114	* by pointers in dc with the intent to protect against breaking polymorphism.
5115	*/
5116	if (can_use_hpo_dp_link_hwss(link, link_res))
5117	/* TODO: some assumes that if decided link settings is 128b/132b
5118	* channel coding format hpo_dp_link_enc should be used.
5119	* Others believe that if hpo_dp_link_enc is available in link
5120	* resource then hpo_dp_link_enc must be used. This bound between
5121	* hpo_dp_link_enc != NULL and decided link settings is loosely coupled
5122	* with a premise that both hpo_dp_link_enc pointer and decided link
5123	* settings are determined based on single policy function like
5124	* "decide_link_settings" from upper layer. This "convention"
5125	* cannot be maintained and enforced at current level.
5126	* Therefore a refactor is due so we can enforce a strong bound
5127	* between those two parameters at this level.
5128	*
5129	* To put it simple, we want to make enforcement at low level so that
5130	* we will not return link hwss if caller plans to do 8b/10b
5131	* with an hpo encoder. Or we can return a very dummy one that doesn't
5132	* do work for all functions
5133	*/
5134	return (requires_fixed_vs_pe_retimer_hpo_link_hwss(link) ?
5135	get_hpo_fixed_vs_pe_retimer_dp_link_hwss() : get_hpo_dp_link_hwss());
5136	else if (can_use_dpia_link_hwss(link, link_res))
5137	return get_dpia_link_hwss();
5138	else if (can_use_dio_link_hwss(link, link_res))
5139	return (requires_fixed_vs_pe_retimer_dio_link_hwss(link)) ?
5140	get_dio_fixed_vs_pe_retimer_link_hwss() : get_dio_link_hwss();
5141	else
5142	return get_virtual_link_hwss();
5143	}
5144
5145	bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
5146	{
5147	bool divisible = false;
5148	uint16_t h_blank_start = 0;
5149	uint16_t h_blank_end = 0;
5150
5151	if (stream) {
5152	h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;
5153	h_blank_end = h_blank_start - stream->timing.h_addressable;
5154
5155	/* HTOTAL, Hblank start/end, and Hsync start/end all must be
5156	* divisible by 2 in order for the horizontal timing params
5157	* to be considered divisible by 2. Hsync start is always 0.
5158	*/
5159	divisible = (stream->timing.h_total % 2 == 0) &&
5160	(h_blank_start % 2 == 0) &&
5161	(h_blank_end % 2 == 0) &&
5162	(stream->timing.h_sync_width % 2 == 0);
5163	}
5164	return divisible;
5165	}
5166
5167	/* This interface is deprecated for new DCNs. It is replaced by the following
5168	* new interfaces. These two interfaces encapsulate pipe selection priority
5169	* with DCN specific minimum hardware transition optimization algorithm. With
5170	* the new interfaces caller no longer needs to know the implementation detail
5171	* of a pipe topology.
5172	*
5173	* resource_update_pipes_with_odm_slice_count
5174	* resource_update_pipes_with_mpc_slice_count
5175	*
5176	*/
5177	bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
5178	const struct dc *dc,
5179	struct dc_state *state,
5180	struct pipe_ctx *pri_pipe,
5181	struct pipe_ctx *sec_pipe,
5182	bool odm)
5183	{
5184	int pipe_idx = sec_pipe->pipe_idx;
5185	struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;
5186	const struct resource_pool *pool = dc->res_pool;
5187
5188	sec_top = sec_pipe->top_pipe;
5189	sec_bottom = sec_pipe->bottom_pipe;
5190	sec_next = sec_pipe->next_odm_pipe;
5191	sec_prev = sec_pipe->prev_odm_pipe;
5192
5193	*sec_pipe = *pri_pipe;
5194
5195	sec_pipe->top_pipe = sec_top;
5196	sec_pipe->bottom_pipe = sec_bottom;
5197	sec_pipe->next_odm_pipe = sec_next;
5198	sec_pipe->prev_odm_pipe = sec_prev;
5199
5200	sec_pipe->pipe_idx = pipe_idx;
5201	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
5202	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
5203	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
5204	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
5205	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
5206	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
5207	sec_pipe->stream_res.dsc = NULL;
5208	if (odm) {
5209	if (!sec_pipe->top_pipe)
5210	sec_pipe->stream_res.opp = pool->opps[pipe_idx];
5211	else
5212	sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
5213	if (sec_pipe->stream->timing.flags.DSC == 1) {
5214	#if defined(CONFIG_DRM_AMD_DC_FP)
5215	dcn20_acquire_dsc(dc, res_ctx: &state->res_ctx, dsc: &sec_pipe->stream_res.dsc, pipe_idx);
5216	#endif
5217	ASSERT(sec_pipe->stream_res.dsc);
5218	if (sec_pipe->stream_res.dsc == NULL)
5219	return false;
5220	}
5221	#if defined(CONFIG_DRM_AMD_DC_FP)
5222	dcn20_build_mapped_resource(dc, context: state, stream: sec_pipe->stream);
5223	#endif
5224	}
5225
5226	return true;
5227	}
5228
5229	enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
5230	struct dc_state *context,
5231	struct pipe_ctx *pipe_ctx)
5232	{
5233	if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
5234	if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {
5235	pipe_ctx->stream_res.hpo_dp_stream_enc =
5236	find_first_free_match_hpo_dp_stream_enc_for_link(
5237	res_ctx: &context->res_ctx, pool: dc->res_pool, stream: pipe_ctx->stream);
5238
5239	if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
5240	return DC_NO_STREAM_ENC_RESOURCE;
5241
5242	update_hpo_dp_stream_engine_usage(
5243	res_ctx: &context->res_ctx, pool: dc->res_pool,
5244	hpo_dp_stream_enc: pipe_ctx->stream_res.hpo_dp_stream_enc,
5245	acquired: true);
5246	}
5247
5248	if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {
5249	if (!add_hpo_dp_link_enc_to_ctx(res_ctx: &context->res_ctx, pool: dc->res_pool, pipe_ctx, stream: pipe_ctx->stream))
5250	return DC_NO_LINK_ENC_RESOURCE;
5251	}
5252	} else {
5253	if (pipe_ctx->stream_res.hpo_dp_stream_enc) {
5254	update_hpo_dp_stream_engine_usage(
5255	res_ctx: &context->res_ctx, pool: dc->res_pool,
5256	hpo_dp_stream_enc: pipe_ctx->stream_res.hpo_dp_stream_enc,
5257	acquired: false);
5258	pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;
5259	}
5260	if (pipe_ctx->link_res.hpo_dp_link_enc)
5261	remove_hpo_dp_link_enc_from_ctx(res_ctx: &context->res_ctx, pipe_ctx, stream: pipe_ctx->stream);
5262	}
5263
5264	return DC_OK;
5265	}
5266
5267	bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream)
5268	{
5269	if (!dc->debug.disable_subvp_high_refresh && is_subvp_high_refresh_candidate(stream))
5270	return true;
5271	if (dc->current_state->stream_count == 1 && stream->timing.v_addressable >= 2880 &&
5272	((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
5273	return true;
5274	else if (dc->current_state->stream_count > 1 && stream->timing.v_addressable >= 2160 &&
5275	((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
5276	return true;
5277
5278	return false;
5279	}
5280