1 | //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the X86 implementation of the TargetInstrInfo class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H |
14 | #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H |
15 | |
16 | #include "MCTargetDesc/X86BaseInfo.h" |
17 | #include "X86InstrFMA3Info.h" |
18 | #include "X86RegisterInfo.h" |
19 | #include "llvm/CodeGen/ISDOpcodes.h" |
20 | #include "llvm/CodeGen/TargetInstrInfo.h" |
21 | #include <vector> |
22 | |
23 | #define |
24 | #include "X86GenInstrInfo.inc" |
25 | |
26 | namespace llvm { |
27 | class X86Subtarget; |
28 | |
29 | // X86 MachineCombiner patterns |
30 | enum X86MachineCombinerPattern : unsigned { |
31 | // X86 VNNI |
32 | DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START, |
33 | }; |
34 | |
35 | namespace X86 { |
36 | |
37 | enum { |
38 | // For instr that was compressed from EVEX to LEGACY. |
39 | AC_EVEX_2_LEGACY = MachineInstr::TAsmComments, |
40 | // For instr that was compressed from EVEX to VEX. |
41 | AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1, |
42 | // For instr that was compressed from EVEX to EVEX. |
43 | AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1 |
44 | }; |
45 | |
46 | /// Return a pair of condition code for the given predicate and whether |
47 | /// the instruction operands should be swaped to match the condition code. |
48 | std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate); |
49 | |
50 | /// Return a cmov opcode for the given register size in bytes, and operand type. |
51 | unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false, |
52 | bool HasNDD = false); |
53 | |
54 | /// Return the source operand # for condition code by \p MCID. If the |
55 | /// instruction doesn't have a condition code, return -1. |
56 | int getCondSrcNoFromDesc(const MCInstrDesc &MCID); |
57 | |
58 | /// Return the condition code of the instruction. If the instruction doesn't |
59 | /// have a condition code, return X86::COND_INVALID. |
60 | CondCode getCondFromMI(const MachineInstr &MI); |
61 | |
62 | // Turn JCC instruction into condition code. |
63 | CondCode getCondFromBranch(const MachineInstr &MI); |
64 | |
65 | // Turn SETCC instruction into condition code. |
66 | CondCode getCondFromSETCC(const MachineInstr &MI); |
67 | |
68 | // Turn CMOV instruction into condition code. |
69 | CondCode getCondFromCMov(const MachineInstr &MI); |
70 | |
71 | // Turn CFCMOV instruction into condition code. |
72 | CondCode getCondFromCFCMov(const MachineInstr &MI); |
73 | |
74 | /// GetOppositeBranchCondition - Return the inverse of the specified cond, |
75 | /// e.g. turning COND_E to COND_NE. |
76 | CondCode GetOppositeBranchCondition(CondCode CC); |
77 | |
78 | /// Get the VPCMP immediate for the given condition. |
79 | unsigned getVPCMPImmForCond(ISD::CondCode CC); |
80 | |
81 | /// Get the VPCMP immediate if the opcodes are swapped. |
82 | unsigned getSwappedVPCMPImm(unsigned Imm); |
83 | |
84 | /// Get the VPCOM immediate if the opcodes are swapped. |
85 | unsigned getSwappedVPCOMImm(unsigned Imm); |
86 | |
87 | /// Get the VCMP immediate if the opcodes are swapped. |
88 | unsigned getSwappedVCMPImm(unsigned Imm); |
89 | |
90 | /// Get the width of the vector register operand. |
91 | unsigned getVectorRegisterWidth(const MCOperandInfo &Info); |
92 | |
93 | /// Check if the instruction is X87 instruction. |
94 | bool isX87Instruction(MachineInstr &MI); |
95 | |
96 | /// Return the index of the instruction's first address operand, if it has a |
97 | /// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(), |
98 | /// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as |
99 | /// real instructions (e.g., JMP64m). |
100 | int getFirstAddrOperandIdx(const MachineInstr &MI); |
101 | |
102 | /// Find any constant pool entry associated with a specific instruction operand. |
103 | const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo); |
104 | |
105 | } // namespace X86 |
106 | |
107 | /// isGlobalStubReference - Return true if the specified TargetFlag operand is |
108 | /// a reference to a stub for a global, not the global itself. |
109 | inline static bool isGlobalStubReference(unsigned char TargetFlag) { |
110 | switch (TargetFlag) { |
111 | case X86II::MO_DLLIMPORT: // dllimport stub. |
112 | case X86II::MO_GOTPCREL: // rip-relative GOT reference. |
113 | case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference. |
114 | case X86II::MO_GOT: // normal GOT reference. |
115 | case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. |
116 | case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. |
117 | case X86II::MO_COFFSTUB: // COFF .refptr stub. |
118 | return true; |
119 | default: |
120 | return false; |
121 | } |
122 | } |
123 | |
124 | /// isGlobalRelativeToPICBase - Return true if the specified global value |
125 | /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this |
126 | /// is true, the addressing mode has the PIC base register added in (e.g. EBX). |
127 | inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { |
128 | switch (TargetFlag) { |
129 | case X86II::MO_GOTOFF: // isPICStyleGOT: local global. |
130 | case X86II::MO_GOT: // isPICStyleGOT: other global. |
131 | case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. |
132 | case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. |
133 | case X86II::MO_TLVP: // ??? Pretty sure.. |
134 | return true; |
135 | default: |
136 | return false; |
137 | } |
138 | } |
139 | |
140 | inline static bool isScale(const MachineOperand &MO) { |
141 | return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || |
142 | MO.getImm() == 4 || MO.getImm() == 8); |
143 | } |
144 | |
145 | inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { |
146 | if (MI.getOperand(i: Op).isFI()) |
147 | return true; |
148 | return Op + X86::AddrSegmentReg <= MI.getNumOperands() && |
149 | MI.getOperand(i: Op + X86::AddrBaseReg).isReg() && |
150 | isScale(MO: MI.getOperand(i: Op + X86::AddrScaleAmt)) && |
151 | MI.getOperand(i: Op + X86::AddrIndexReg).isReg() && |
152 | (MI.getOperand(i: Op + X86::AddrDisp).isImm() || |
153 | MI.getOperand(i: Op + X86::AddrDisp).isGlobal() || |
154 | MI.getOperand(i: Op + X86::AddrDisp).isCPI() || |
155 | MI.getOperand(i: Op + X86::AddrDisp).isJTI()); |
156 | } |
157 | |
158 | inline static bool isMem(const MachineInstr &MI, unsigned Op) { |
159 | if (MI.getOperand(i: Op).isFI()) |
160 | return true; |
161 | return Op + X86::AddrNumOperands <= MI.getNumOperands() && |
162 | MI.getOperand(i: Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op); |
163 | } |
164 | |
165 | class X86InstrInfo final : public X86GenInstrInfo { |
166 | X86Subtarget &Subtarget; |
167 | const X86RegisterInfo RI; |
168 | |
169 | virtual void anchor(); |
170 | |
171 | bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
172 | MachineBasicBlock *&FBB, |
173 | SmallVectorImpl<MachineOperand> &Cond, |
174 | SmallVectorImpl<MachineInstr *> &CondBranches, |
175 | bool AllowModify) const; |
176 | |
177 | bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg, |
178 | int64_t ImmVal, MachineRegisterInfo *MRI, |
179 | bool MakeChange) const; |
180 | |
181 | public: |
182 | explicit X86InstrInfo(X86Subtarget &STI); |
183 | |
184 | /// Given a machine instruction descriptor, returns the register |
185 | /// class constraint for OpNum, or NULL. Returned register class |
186 | /// may be different from the definition in the TD file, e.g. |
187 | /// GR*RegClass (definition in TD file) |
188 | /// -> |
189 | /// GR*_NOREX2RegClass (Returned register class) |
190 | const TargetRegisterClass * |
191 | getRegClass(const MCInstrDesc &MCID, unsigned OpNum, |
192 | const TargetRegisterInfo *TRI, |
193 | const MachineFunction &MF) const override; |
194 | |
195 | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
196 | /// such, whenever a client has an instance of instruction info, it should |
197 | /// always be able to get register info as well (through this method). |
198 | /// |
199 | const X86RegisterInfo &getRegisterInfo() const { return RI; } |
200 | |
201 | /// Returns the stack pointer adjustment that happens inside the frame |
202 | /// setup..destroy sequence (e.g. by pushes, or inside the callee). |
203 | int64_t getFrameAdjustment(const MachineInstr &I) const { |
204 | assert(isFrameInstr(I)); |
205 | if (isFrameSetup(I)) |
206 | return I.getOperand(i: 2).getImm(); |
207 | return I.getOperand(i: 1).getImm(); |
208 | } |
209 | |
210 | /// Sets the stack pointer adjustment made inside the frame made up by this |
211 | /// instruction. |
212 | void setFrameAdjustment(MachineInstr &I, int64_t V) const { |
213 | assert(isFrameInstr(I)); |
214 | if (isFrameSetup(I)) |
215 | I.getOperand(i: 2).setImm(V); |
216 | else |
217 | I.getOperand(i: 1).setImm(V); |
218 | } |
219 | |
220 | /// getSPAdjust - This returns the stack pointer adjustment made by |
221 | /// this instruction. For x86, we need to handle more complex call |
222 | /// sequences involving PUSHes. |
223 | int getSPAdjust(const MachineInstr &MI) const override; |
224 | |
225 | /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" |
226 | /// extension instruction. That is, it's like a copy where it's legal for the |
227 | /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns |
228 | /// true, then it's expected the pre-extension value is available as a subreg |
229 | /// of the result register. This also returns the sub-register index in |
230 | /// SubIdx. |
231 | bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, |
232 | Register &DstReg, unsigned &SubIdx) const override; |
233 | |
234 | /// Returns true if the instruction has no behavior (specified or otherwise) |
235 | /// that is based on the value of any of its register operands |
236 | /// |
237 | /// Instructions are considered data invariant even if they set EFLAGS. |
238 | /// |
239 | /// A classical example of something that is inherently not data invariant is |
240 | /// an indirect jump -- the destination is loaded into icache based on the |
241 | /// bits set in the jump destination register. |
242 | /// |
243 | /// FIXME: This should become part of our instruction tables. |
244 | static bool isDataInvariant(MachineInstr &MI); |
245 | |
246 | /// Returns true if the instruction has no behavior (specified or otherwise) |
247 | /// that is based on the value loaded from memory or the value of any |
248 | /// non-address register operands. |
249 | /// |
250 | /// For example, if the latency of the instruction is dependent on the |
251 | /// particular bits set in any of the registers *or* any of the bits loaded |
252 | /// from memory. |
253 | /// |
254 | /// Instructions are considered data invariant even if they set EFLAGS. |
255 | /// |
256 | /// A classical example of something that is inherently not data invariant is |
257 | /// an indirect jump -- the destination is loaded into icache based on the |
258 | /// bits set in the jump destination register. |
259 | /// |
260 | /// FIXME: This should become part of our instruction tables. |
261 | static bool isDataInvariantLoad(MachineInstr &MI); |
262 | |
263 | Register isLoadFromStackSlot(const MachineInstr &MI, |
264 | int &FrameIndex) const override; |
265 | Register isLoadFromStackSlot(const MachineInstr &MI, |
266 | int &FrameIndex, |
267 | unsigned &MemBytes) const override; |
268 | /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination |
269 | /// stack locations as well. This uses a heuristic so it isn't |
270 | /// reliable for correctness. |
271 | Register isLoadFromStackSlotPostFE(const MachineInstr &MI, |
272 | int &FrameIndex) const override; |
273 | |
274 | Register isStoreToStackSlot(const MachineInstr &MI, |
275 | int &FrameIndex) const override; |
276 | Register isStoreToStackSlot(const MachineInstr &MI, |
277 | int &FrameIndex, |
278 | unsigned &MemBytes) const override; |
279 | /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination |
280 | /// stack locations as well. This uses a heuristic so it isn't |
281 | /// reliable for correctness. |
282 | Register isStoreToStackSlotPostFE(const MachineInstr &MI, |
283 | int &FrameIndex) const override; |
284 | |
285 | bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; |
286 | void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, |
287 | Register DestReg, unsigned SubIdx, |
288 | const MachineInstr &Orig, |
289 | const TargetRegisterInfo &TRI) const override; |
290 | |
291 | /// Given an operand within a MachineInstr, insert preceding code to put it |
292 | /// into the right format for a particular kind of LEA instruction. This may |
293 | /// involve using an appropriate super-register instead (with an implicit use |
294 | /// of the original) or creating a new virtual register and inserting COPY |
295 | /// instructions to get the data into the right class. |
296 | /// |
297 | /// Reference parameters are set to indicate how caller should add this |
298 | /// operand to the LEA instruction. |
299 | bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, |
300 | unsigned LEAOpcode, bool AllowSP, Register &NewSrc, |
301 | bool &isKill, MachineOperand &ImplicitOp, |
302 | LiveVariables *LV, LiveIntervals *LIS) const; |
303 | |
304 | /// convertToThreeAddress - This method must be implemented by targets that |
305 | /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target |
306 | /// may be able to convert a two-address instruction into a true |
307 | /// three-address instruction on demand. This allows the X86 target (for |
308 | /// example) to convert ADD and SHL instructions into LEA instructions if they |
309 | /// would require register copies due to two-addressness. |
310 | /// |
311 | /// This method returns a null pointer if the transformation cannot be |
312 | /// performed, otherwise it returns the new instruction. |
313 | /// |
314 | MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, |
315 | LiveIntervals *LIS) const override; |
316 | |
317 | /// Returns true iff the routine could find two commutable operands in the |
318 | /// given machine instruction. |
319 | /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their |
320 | /// input values can be re-defined in this method only if the input values |
321 | /// are not pre-defined, which is designated by the special value |
322 | /// 'CommuteAnyOperandIndex' assigned to it. |
323 | /// If both of indices are pre-defined and refer to some operands, then the |
324 | /// method simply returns true if the corresponding operands are commutable |
325 | /// and returns false otherwise. |
326 | /// |
327 | /// For example, calling this method this way: |
328 | /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; |
329 | /// findCommutedOpIndices(MI, Op1, Op2); |
330 | /// can be interpreted as a query asking to find an operand that would be |
331 | /// commutable with the operand#1. |
332 | bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, |
333 | unsigned &SrcOpIdx2) const override; |
334 | |
335 | /// Returns true if we have preference on the operands order in MI, the |
336 | /// commute decision is returned in Commute. |
337 | bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override; |
338 | |
339 | /// Returns an adjusted FMA opcode that must be used in FMA instruction that |
340 | /// performs the same computations as the given \p MI but which has the |
341 | /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted. |
342 | /// It may return 0 if it is unsafe to commute the operands. |
343 | /// Note that a machine instruction (instead of its opcode) is passed as the |
344 | /// first parameter to make it possible to analyze the instruction's uses and |
345 | /// commute the first operand of FMA even when it seems unsafe when you look |
346 | /// at the opcode. For example, it is Ok to commute the first operand of |
347 | /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used. |
348 | /// |
349 | /// The returned FMA opcode may differ from the opcode in the given \p MI. |
350 | /// For example, commuting the operands #1 and #3 in the following FMA |
351 | /// FMA213 #1, #2, #3 |
352 | /// results into instruction with adjusted opcode: |
353 | /// FMA231 #3, #2, #1 |
354 | unsigned |
355 | getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, |
356 | unsigned SrcOpIdx2, |
357 | const X86InstrFMA3Group &FMA3Group) const; |
358 | |
359 | // Branch analysis. |
360 | bool isUnconditionalTailCall(const MachineInstr &MI) const override; |
361 | bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, |
362 | const MachineInstr &TailCall) const override; |
363 | void replaceBranchWithTailCall(MachineBasicBlock &MBB, |
364 | SmallVectorImpl<MachineOperand> &Cond, |
365 | const MachineInstr &TailCall) const override; |
366 | |
367 | bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
368 | MachineBasicBlock *&FBB, |
369 | SmallVectorImpl<MachineOperand> &Cond, |
370 | bool AllowModify) const override; |
371 | |
372 | int getJumpTableIndex(const MachineInstr &MI) const override; |
373 | |
374 | std::optional<ExtAddrMode> |
375 | getAddrModeFromMemoryOp(const MachineInstr &MemI, |
376 | const TargetRegisterInfo *TRI) const override; |
377 | |
378 | bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, |
379 | int64_t &ImmVal) const override; |
380 | |
381 | bool preservesZeroValueInReg(const MachineInstr *MI, |
382 | const Register NullValueReg, |
383 | const TargetRegisterInfo *TRI) const override; |
384 | |
385 | bool getMemOperandsWithOffsetWidth( |
386 | const MachineInstr &LdSt, |
387 | SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, |
388 | bool &OffsetIsScalable, LocationSize &Width, |
389 | const TargetRegisterInfo *TRI) const override; |
390 | bool analyzeBranchPredicate(MachineBasicBlock &MBB, |
391 | TargetInstrInfo::MachineBranchPredicate &MBP, |
392 | bool AllowModify = false) const override; |
393 | |
394 | unsigned removeBranch(MachineBasicBlock &MBB, |
395 | int *BytesRemoved = nullptr) const override; |
396 | unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
397 | MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, |
398 | const DebugLoc &DL, |
399 | int *BytesAdded = nullptr) const override; |
400 | bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, |
401 | Register, Register, Register, int &, int &, |
402 | int &) const override; |
403 | void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, |
404 | const DebugLoc &DL, Register DstReg, |
405 | ArrayRef<MachineOperand> Cond, Register TrueReg, |
406 | Register FalseReg) const override; |
407 | void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, |
408 | const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, |
409 | bool KillSrc) const override; |
410 | void storeRegToStackSlot(MachineBasicBlock &MBB, |
411 | MachineBasicBlock::iterator MI, Register SrcReg, |
412 | bool isKill, int FrameIndex, |
413 | const TargetRegisterClass *RC, |
414 | const TargetRegisterInfo *TRI, |
415 | Register VReg) const override; |
416 | |
417 | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
418 | MachineBasicBlock::iterator MI, Register DestReg, |
419 | int FrameIndex, const TargetRegisterClass *RC, |
420 | const TargetRegisterInfo *TRI, |
421 | Register VReg) const override; |
422 | |
423 | void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, |
424 | unsigned Opc, Register Reg, int FrameIdx, |
425 | bool isKill = false) const; |
426 | |
427 | bool expandPostRAPseudo(MachineInstr &MI) const override; |
428 | |
429 | /// Check whether the target can fold a load that feeds a subreg operand |
430 | /// (or a subreg operand that feeds a store). |
431 | bool isSubregFoldable() const override { return true; } |
432 | |
433 | /// Fold a load or store of the specified stack slot into the specified |
434 | /// machine instruction for the specified operand(s). If folding happens, it |
435 | /// is likely that the referenced instruction has been changed. |
436 | /// |
437 | /// \returns true on success. |
438 | MachineInstr * |
439 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, |
440 | ArrayRef<unsigned> Ops, |
441 | MachineBasicBlock::iterator InsertPt, int FrameIndex, |
442 | LiveIntervals *LIS = nullptr, |
443 | VirtRegMap *VRM = nullptr) const override; |
444 | |
445 | /// Same as the previous version except it allows folding of any load and |
446 | /// store from / to any address, not just from a specific stack slot. |
447 | MachineInstr *foldMemoryOperandImpl( |
448 | MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, |
449 | MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, |
450 | LiveIntervals *LIS = nullptr) const override; |
451 | |
452 | bool |
453 | unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, |
454 | bool UnfoldLoad, bool UnfoldStore, |
455 | SmallVectorImpl<MachineInstr *> &NewMIs) const override; |
456 | |
457 | bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, |
458 | SmallVectorImpl<SDNode *> &NewNodes) const override; |
459 | |
460 | unsigned |
461 | getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, |
462 | unsigned *LoadRegIndex = nullptr) const override; |
463 | |
464 | bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, |
465 | int64_t &Offset2) const override; |
466 | |
467 | /// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to |
468 | /// make it capable of identifying ENDBR intructions and prevent it from being |
469 | /// re-scheduled. |
470 | bool isSchedulingBoundary(const MachineInstr &MI, |
471 | const MachineBasicBlock *MBB, |
472 | const MachineFunction &MF) const override; |
473 | |
474 | /// This is a used by the pre-regalloc scheduler to determine (in conjunction |
475 | /// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On |
476 | /// some targets if two loads are loading from addresses in the same cache |
477 | /// line, it's better if they are scheduled together. This function takes two |
478 | /// integers that represent the load offsets from the common base address. It |
479 | /// returns true if it decides it's desirable to schedule the two loads |
480 | /// together. "NumLoads" is the number of loads that have already been |
481 | /// scheduled after Load1. |
482 | bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, |
483 | int64_t Offset2, |
484 | unsigned NumLoads) const override; |
485 | |
486 | void insertNoop(MachineBasicBlock &MBB, |
487 | MachineBasicBlock::iterator MI) const override; |
488 | |
489 | MCInst getNop() const override; |
490 | |
491 | bool |
492 | reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; |
493 | |
494 | bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; |
495 | |
496 | /// True if MI has a condition code def, e.g. EFLAGS, that is |
497 | /// not marked dead. |
498 | bool hasLiveCondCodeDef(MachineInstr &MI) const; |
499 | |
500 | /// getGlobalBaseReg - Return a virtual register initialized with the |
501 | /// the global base register value. Output instructions required to |
502 | /// initialize the register in the function entry block, if necessary. |
503 | /// |
504 | unsigned getGlobalBaseReg(MachineFunction *MF) const; |
505 | |
506 | std::pair<uint16_t, uint16_t> |
507 | getExecutionDomain(const MachineInstr &MI) const override; |
508 | |
509 | uint16_t getExecutionDomainCustom(const MachineInstr &MI) const; |
510 | |
511 | void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; |
512 | |
513 | bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const; |
514 | |
515 | unsigned |
516 | getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, |
517 | const TargetRegisterInfo *TRI) const override; |
518 | unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, |
519 | const TargetRegisterInfo *TRI) const override; |
520 | void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, |
521 | const TargetRegisterInfo *TRI) const override; |
522 | |
523 | MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, |
524 | unsigned OpNum, |
525 | ArrayRef<MachineOperand> MOs, |
526 | MachineBasicBlock::iterator InsertPt, |
527 | unsigned Size, Align Alignment, |
528 | bool AllowCommute) const; |
529 | |
530 | bool isHighLatencyDef(int opc) const override; |
531 | |
532 | bool hasHighOperandLatency(const TargetSchedModel &SchedModel, |
533 | const MachineRegisterInfo *MRI, |
534 | const MachineInstr &DefMI, unsigned DefIdx, |
535 | const MachineInstr &UseMI, |
536 | unsigned UseIdx) const override; |
537 | |
538 | bool useMachineCombiner() const override { return true; } |
539 | |
540 | bool isAssociativeAndCommutative(const MachineInstr &Inst, |
541 | bool Invert) const override; |
542 | |
543 | bool hasReassociableOperands(const MachineInstr &Inst, |
544 | const MachineBasicBlock *MBB) const override; |
545 | |
546 | void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, |
547 | MachineInstr &NewMI1, |
548 | MachineInstr &NewMI2) const override; |
549 | |
550 | bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, |
551 | Register &SrcReg2, int64_t &CmpMask, |
552 | int64_t &CmpValue) const override; |
553 | |
554 | /// Check if there exists an earlier instruction that operates on the same |
555 | /// source operands and sets eflags in the same way as CMP and remove CMP if |
556 | /// possible. |
557 | bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, |
558 | Register SrcReg2, int64_t CmpMask, int64_t CmpValue, |
559 | const MachineRegisterInfo *MRI) const override; |
560 | |
561 | MachineInstr *optimizeLoadInstr(MachineInstr &MI, |
562 | const MachineRegisterInfo *MRI, |
563 | Register &FoldAsLoadDefReg, |
564 | MachineInstr *&DefMI) const override; |
565 | |
566 | bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, |
567 | MachineRegisterInfo *MRI) const override; |
568 | |
569 | std::pair<unsigned, unsigned> |
570 | decomposeMachineOperandsTargetFlags(unsigned TF) const override; |
571 | |
572 | ArrayRef<std::pair<unsigned, const char *>> |
573 | getSerializableDirectMachineOperandTargetFlags() const override; |
574 | |
575 | std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo( |
576 | std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; |
577 | |
578 | bool isFunctionSafeToOutlineFrom(MachineFunction &MF, |
579 | bool OutlineFromLinkOnceODRs) const override; |
580 | |
581 | outliner::InstrType |
582 | getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; |
583 | |
584 | void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, |
585 | const outliner::OutlinedFunction &OF) const override; |
586 | |
587 | MachineBasicBlock::iterator |
588 | insertOutlinedCall(Module &M, MachineBasicBlock &MBB, |
589 | MachineBasicBlock::iterator &It, MachineFunction &MF, |
590 | outliner::Candidate &C) const override; |
591 | |
592 | void buildClearRegister(Register Reg, MachineBasicBlock &MBB, |
593 | MachineBasicBlock::iterator Iter, DebugLoc &DL, |
594 | bool AllowSideEffects = true) const override; |
595 | |
596 | bool verifyInstruction(const MachineInstr &MI, |
597 | StringRef &ErrInfo) const override; |
598 | #define GET_INSTRINFO_HELPER_DECLS |
599 | #include "X86GenInstrInfo.inc" |
600 | |
601 | static bool hasLockPrefix(const MachineInstr &MI) { |
602 | return MI.getDesc().TSFlags & X86II::LOCK; |
603 | } |
604 | |
605 | std::optional<ParamLoadedValue> |
606 | describeLoadedValue(const MachineInstr &MI, Register Reg) const override; |
607 | |
608 | protected: |
609 | MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, |
610 | unsigned CommuteOpIdx1, |
611 | unsigned CommuteOpIdx2) const override; |
612 | |
613 | std::optional<DestSourcePair> |
614 | isCopyInstrImpl(const MachineInstr &MI) const override; |
615 | |
616 | bool getMachineCombinerPatterns(MachineInstr &Root, |
617 | SmallVectorImpl<unsigned> &Patterns, |
618 | bool DoRegPressureReduce) const override; |
619 | |
620 | /// When getMachineCombinerPatterns() finds potential patterns, |
621 | /// this function generates the instructions that could replace the |
622 | /// original code sequence. |
623 | void genAlternativeCodeSequence( |
624 | MachineInstr &Root, unsigned Pattern, |
625 | SmallVectorImpl<MachineInstr *> &InsInstrs, |
626 | SmallVectorImpl<MachineInstr *> &DelInstrs, |
627 | DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; |
628 | |
629 | /// When calculate the latency of the root instruction, accumulate the |
630 | /// latency of the sequence to the root latency. |
631 | /// \param Root - Instruction that could be combined with one of its operands |
632 | /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd |
633 | /// is not in the critical path, so the root latency only include vpmaddwd. |
634 | bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override { |
635 | return false; |
636 | } |
637 | |
638 | void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops, |
639 | int FI) const override; |
640 | |
641 | private: |
642 | /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions. |
643 | /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit |
644 | /// super-register and then truncating back down to a 8/16-bit sub-register. |
645 | MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI, |
646 | LiveVariables *LV, |
647 | LiveIntervals *LIS, |
648 | bool Is8BitOp) const; |
649 | |
650 | /// Handles memory folding for special case instructions, for instance those |
651 | /// requiring custom manipulation of the address. |
652 | MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI, |
653 | unsigned OpNum, |
654 | ArrayRef<MachineOperand> MOs, |
655 | MachineBasicBlock::iterator InsertPt, |
656 | unsigned Size, Align Alignment) const; |
657 | |
658 | MachineInstr *foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI, |
659 | unsigned OpNum, |
660 | ArrayRef<MachineOperand> MOs, |
661 | MachineBasicBlock::iterator InsertPt, |
662 | unsigned BitsSize, bool AllowCommute) const; |
663 | |
664 | /// isFrameOperand - Return true and the FrameIndex if the specified |
665 | /// operand and follow operands form a reference to the stack frame. |
666 | bool isFrameOperand(const MachineInstr &MI, unsigned int Op, |
667 | int &FrameIndex) const; |
668 | |
669 | /// Returns true iff the routine could find two commutable operands in the |
670 | /// given machine instruction with 3 vector inputs. |
671 | /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their |
672 | /// input values can be re-defined in this method only if the input values |
673 | /// are not pre-defined, which is designated by the special value |
674 | /// 'CommuteAnyOperandIndex' assigned to it. |
675 | /// If both of indices are pre-defined and refer to some operands, then the |
676 | /// method simply returns true if the corresponding operands are commutable |
677 | /// and returns false otherwise. |
678 | /// |
679 | /// For example, calling this method this way: |
680 | /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; |
681 | /// findThreeSrcCommutedOpIndices(MI, Op1, Op2); |
682 | /// can be interpreted as a query asking to find an operand that would be |
683 | /// commutable with the operand#1. |
684 | /// |
685 | /// If IsIntrinsic is set, operand 1 will be ignored for commuting. |
686 | bool findThreeSrcCommutedOpIndices(const MachineInstr &MI, |
687 | unsigned &SrcOpIdx1, |
688 | unsigned &SrcOpIdx2, |
689 | bool IsIntrinsic = false) const; |
690 | |
691 | /// Returns true when instruction \p FlagI produces the same flags as \p OI. |
692 | /// The caller should pass in the results of calling analyzeCompare on \p OI: |
693 | /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue. |
694 | /// If the flags match \p OI as if it had the input operands swapped then the |
695 | /// function succeeds and sets \p IsSwapped to true. |
696 | /// |
697 | /// Examples of OI, FlagI pairs returning true: |
698 | /// CMP %1, 42 and CMP %1, 42 |
699 | /// CMP %1, %2 and %3 = SUB %1, %2 |
700 | /// TEST %1, %1 and %2 = SUB %1, 0 |
701 | /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true |
702 | bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg, |
703 | Register SrcReg2, int64_t ImmMask, int64_t ImmValue, |
704 | const MachineInstr &OI, bool *IsSwapped, |
705 | int64_t *ImmDelta) const; |
706 | |
707 | /// Commute operands of \p MI for memory fold. |
708 | /// |
709 | /// \param Idx1 the index of operand to be commuted. |
710 | /// |
711 | /// \returns the index of operand that is commuted with \p Idx1. If the method |
712 | /// fails to commute the operands, it will return \p Idx1. |
713 | unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const; |
714 | }; |
715 | } // namespace llvm |
716 | |
717 | #endif |
718 | |