1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include <linux/firmware.h> |
24 | #include <linux/slab.h> |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> |
27 | |
28 | #include <drm/amdgpu_drm.h> |
29 | |
30 | #include "amdgpu.h" |
31 | #include "amdgpu_atombios.h" |
32 | #include "amdgpu_ih.h" |
33 | #include "amdgpu_uvd.h" |
34 | #include "amdgpu_vce.h" |
35 | #include "amdgpu_ucode.h" |
36 | #include "amdgpu_psp.h" |
37 | #include "atom.h" |
38 | #include "amd_pcie.h" |
39 | |
40 | #include "uvd/uvd_7_0_offset.h" |
41 | #include "gc/gc_9_0_offset.h" |
42 | #include "gc/gc_9_0_sh_mask.h" |
43 | #include "sdma0/sdma0_4_0_offset.h" |
44 | #include "sdma1/sdma1_4_0_offset.h" |
45 | #include "nbio/nbio_7_0_default.h" |
46 | #include "nbio/nbio_7_0_offset.h" |
47 | #include "nbio/nbio_7_0_sh_mask.h" |
48 | #include "nbio/nbio_7_0_smn.h" |
49 | #include "mp/mp_9_0_offset.h" |
50 | |
51 | #include "soc15.h" |
52 | #include "soc15_common.h" |
53 | #include "gfx_v9_0.h" |
54 | #include "gmc_v9_0.h" |
55 | #include "gfxhub_v1_0.h" |
56 | #include "mmhub_v1_0.h" |
57 | #include "df_v1_7.h" |
58 | #include "df_v3_6.h" |
59 | #include "nbio_v6_1.h" |
60 | #include "nbio_v7_0.h" |
61 | #include "nbio_v7_4.h" |
62 | #include "hdp_v4_0.h" |
63 | #include "vega10_ih.h" |
64 | #include "vega20_ih.h" |
65 | #include "navi10_ih.h" |
66 | #include "sdma_v4_0.h" |
67 | #include "uvd_v7_0.h" |
68 | #include "vce_v4_0.h" |
69 | #include "vcn_v1_0.h" |
70 | #include "vcn_v2_0.h" |
71 | #include "jpeg_v2_0.h" |
72 | #include "vcn_v2_5.h" |
73 | #include "jpeg_v2_5.h" |
74 | #include "smuio_v9_0.h" |
75 | #include "smuio_v11_0.h" |
76 | #include "smuio_v13_0.h" |
77 | #include "amdgpu_vkms.h" |
78 | #include "mxgpu_ai.h" |
79 | #include "amdgpu_ras.h" |
80 | #include "amdgpu_xgmi.h" |
81 | #include <uapi/linux/kfd_ioctl.h> |
82 | |
83 | #define mmMP0_MISC_CGTT_CTRL0 0x01b9 |
84 | #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 |
85 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba |
86 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 |
87 | |
88 | static const struct amd_ip_funcs soc15_common_ip_funcs; |
89 | |
90 | /* Vega, Raven, Arcturus */ |
91 | static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = |
92 | { |
93 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, |
94 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, |
95 | }; |
96 | |
97 | static const struct amdgpu_video_codecs vega_video_codecs_encode = |
98 | { |
99 | .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), |
100 | .codec_array = vega_video_codecs_encode_array, |
101 | }; |
102 | |
103 | /* Vega */ |
104 | static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = |
105 | { |
106 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, |
107 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, |
108 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
109 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, |
110 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, |
111 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
112 | }; |
113 | |
114 | static const struct amdgpu_video_codecs vega_video_codecs_decode = |
115 | { |
116 | .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), |
117 | .codec_array = vega_video_codecs_decode_array, |
118 | }; |
119 | |
120 | /* Raven */ |
121 | static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = |
122 | { |
123 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, |
124 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, |
125 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
126 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, |
127 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, |
128 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
129 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, |
130 | }; |
131 | |
132 | static const struct amdgpu_video_codecs rv_video_codecs_decode = |
133 | { |
134 | .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), |
135 | .codec_array = rv_video_codecs_decode_array, |
136 | }; |
137 | |
138 | /* Renoir, Arcturus */ |
139 | static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = |
140 | { |
141 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, |
142 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, |
143 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
144 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, |
145 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, |
146 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
147 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, |
148 | }; |
149 | |
150 | static const struct amdgpu_video_codecs rn_video_codecs_decode = |
151 | { |
152 | .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), |
153 | .codec_array = rn_video_codecs_decode_array, |
154 | }; |
155 | |
156 | static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = { |
157 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
158 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, |
159 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
160 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, |
161 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, |
162 | }; |
163 | |
164 | static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = { |
165 | .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array), |
166 | .codec_array = vcn_4_0_3_video_codecs_decode_array, |
167 | }; |
168 | |
169 | static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = { |
170 | .codec_count = 0, |
171 | .codec_array = NULL, |
172 | }; |
173 | |
174 | static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, |
175 | const struct amdgpu_video_codecs **codecs) |
176 | { |
177 | if (amdgpu_ip_version(adev, ip: VCE_HWIP, inst: 0)) { |
178 | switch (amdgpu_ip_version(adev, ip: VCE_HWIP, inst: 0)) { |
179 | case IP_VERSION(4, 0, 0): |
180 | case IP_VERSION(4, 1, 0): |
181 | if (encode) |
182 | *codecs = &vega_video_codecs_encode; |
183 | else |
184 | *codecs = &vega_video_codecs_decode; |
185 | return 0; |
186 | default: |
187 | return -EINVAL; |
188 | } |
189 | } else { |
190 | switch (amdgpu_ip_version(adev, ip: UVD_HWIP, inst: 0)) { |
191 | case IP_VERSION(1, 0, 0): |
192 | case IP_VERSION(1, 0, 1): |
193 | if (encode) |
194 | *codecs = &vega_video_codecs_encode; |
195 | else |
196 | *codecs = &rv_video_codecs_decode; |
197 | return 0; |
198 | case IP_VERSION(2, 5, 0): |
199 | case IP_VERSION(2, 6, 0): |
200 | case IP_VERSION(2, 2, 0): |
201 | if (encode) |
202 | *codecs = &vega_video_codecs_encode; |
203 | else |
204 | *codecs = &rn_video_codecs_decode; |
205 | return 0; |
206 | case IP_VERSION(4, 0, 3): |
207 | if (encode) |
208 | *codecs = &vcn_4_0_3_video_codecs_encode; |
209 | else |
210 | *codecs = &vcn_4_0_3_video_codecs_decode; |
211 | return 0; |
212 | default: |
213 | return -EINVAL; |
214 | } |
215 | } |
216 | } |
217 | |
218 | static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) |
219 | { |
220 | unsigned long flags, address, data; |
221 | u32 r; |
222 | |
223 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); |
224 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); |
225 | |
226 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); |
227 | WREG32(address, ((reg) & 0x1ff)); |
228 | r = RREG32(data); |
229 | spin_unlock_irqrestore(lock: &adev->uvd_ctx_idx_lock, flags); |
230 | return r; |
231 | } |
232 | |
233 | static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
234 | { |
235 | unsigned long flags, address, data; |
236 | |
237 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); |
238 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); |
239 | |
240 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); |
241 | WREG32(address, ((reg) & 0x1ff)); |
242 | WREG32(data, (v)); |
243 | spin_unlock_irqrestore(lock: &adev->uvd_ctx_idx_lock, flags); |
244 | } |
245 | |
246 | static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) |
247 | { |
248 | unsigned long flags, address, data; |
249 | u32 r; |
250 | |
251 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); |
252 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); |
253 | |
254 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
255 | WREG32(address, (reg)); |
256 | r = RREG32(data); |
257 | spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags); |
258 | return r; |
259 | } |
260 | |
261 | static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
262 | { |
263 | unsigned long flags, address, data; |
264 | |
265 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); |
266 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); |
267 | |
268 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
269 | WREG32(address, (reg)); |
270 | WREG32(data, (v)); |
271 | spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags); |
272 | } |
273 | |
274 | static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) |
275 | { |
276 | unsigned long flags; |
277 | u32 r; |
278 | |
279 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); |
280 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); |
281 | r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); |
282 | spin_unlock_irqrestore(lock: &adev->gc_cac_idx_lock, flags); |
283 | return r; |
284 | } |
285 | |
286 | static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
287 | { |
288 | unsigned long flags; |
289 | |
290 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); |
291 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); |
292 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); |
293 | spin_unlock_irqrestore(lock: &adev->gc_cac_idx_lock, flags); |
294 | } |
295 | |
296 | static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) |
297 | { |
298 | unsigned long flags; |
299 | u32 r; |
300 | |
301 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); |
302 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); |
303 | r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); |
304 | spin_unlock_irqrestore(lock: &adev->se_cac_idx_lock, flags); |
305 | return r; |
306 | } |
307 | |
308 | static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
309 | { |
310 | unsigned long flags; |
311 | |
312 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); |
313 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); |
314 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); |
315 | spin_unlock_irqrestore(lock: &adev->se_cac_idx_lock, flags); |
316 | } |
317 | |
318 | static u32 soc15_get_config_memsize(struct amdgpu_device *adev) |
319 | { |
320 | return adev->nbio.funcs->get_memsize(adev); |
321 | } |
322 | |
323 | static u32 soc15_get_xclk(struct amdgpu_device *adev) |
324 | { |
325 | u32 reference_clock = adev->clock.spll.reference_freq; |
326 | |
327 | if (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0) == IP_VERSION(12, 0, 0) || |
328 | amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0) == IP_VERSION(12, 0, 1) || |
329 | amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0) == IP_VERSION(13, 0, 6)) |
330 | return 10000; |
331 | if (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0) == IP_VERSION(10, 0, 0) || |
332 | amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0) == IP_VERSION(10, 0, 1)) |
333 | return reference_clock / 4; |
334 | |
335 | return reference_clock; |
336 | } |
337 | |
338 | |
339 | void soc15_grbm_select(struct amdgpu_device *adev, |
340 | u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) |
341 | { |
342 | u32 grbm_gfx_cntl = 0; |
343 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); |
344 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); |
345 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); |
346 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); |
347 | |
348 | WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); |
349 | } |
350 | |
351 | static bool soc15_read_disabled_bios(struct amdgpu_device *adev) |
352 | { |
353 | /* todo */ |
354 | return false; |
355 | } |
356 | |
357 | static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { |
358 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, |
359 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, |
360 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, |
361 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, |
362 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, |
363 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, |
364 | { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, |
365 | { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, |
366 | { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, |
367 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, |
368 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, |
369 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, |
370 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, |
371 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, |
372 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, |
373 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, |
374 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, |
375 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, |
376 | { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, |
377 | { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, |
378 | }; |
379 | |
380 | static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, |
381 | u32 sh_num, u32 reg_offset) |
382 | { |
383 | uint32_t val; |
384 | |
385 | mutex_lock(&adev->grbm_idx_mutex); |
386 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
387 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); |
388 | |
389 | val = RREG32(reg_offset); |
390 | |
391 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
392 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
393 | mutex_unlock(lock: &adev->grbm_idx_mutex); |
394 | return val; |
395 | } |
396 | |
397 | static uint32_t soc15_get_register_value(struct amdgpu_device *adev, |
398 | bool indexed, u32 se_num, |
399 | u32 sh_num, u32 reg_offset) |
400 | { |
401 | if (indexed) { |
402 | return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); |
403 | } else { |
404 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) |
405 | return adev->gfx.config.gb_addr_config; |
406 | else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) |
407 | return adev->gfx.config.db_debug2; |
408 | return RREG32(reg_offset); |
409 | } |
410 | } |
411 | |
412 | static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, |
413 | u32 sh_num, u32 reg_offset, u32 *value) |
414 | { |
415 | uint32_t i; |
416 | struct soc15_allowed_register_entry *en; |
417 | |
418 | *value = 0; |
419 | for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { |
420 | en = &soc15_allowed_read_registers[i]; |
421 | if (!adev->reg_offset[en->hwip][en->inst]) |
422 | continue; |
423 | else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] |
424 | + en->reg_offset)) |
425 | continue; |
426 | |
427 | *value = soc15_get_register_value(adev, |
428 | indexed: soc15_allowed_read_registers[i].grbm_indexed, |
429 | se_num, sh_num, reg_offset); |
430 | return 0; |
431 | } |
432 | return -EINVAL; |
433 | } |
434 | |
435 | |
436 | /** |
437 | * soc15_program_register_sequence - program an array of registers. |
438 | * |
439 | * @adev: amdgpu_device pointer |
440 | * @regs: pointer to the register array |
441 | * @array_size: size of the register array |
442 | * |
443 | * Programs an array or registers with and and or masks. |
444 | * This is a helper for setting golden registers. |
445 | */ |
446 | |
447 | void soc15_program_register_sequence(struct amdgpu_device *adev, |
448 | const struct soc15_reg_golden *regs, |
449 | const u32 array_size) |
450 | { |
451 | const struct soc15_reg_golden *entry; |
452 | u32 tmp, reg; |
453 | int i; |
454 | |
455 | for (i = 0; i < array_size; ++i) { |
456 | entry = ®s[i]; |
457 | reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; |
458 | |
459 | if (entry->and_mask == 0xffffffff) { |
460 | tmp = entry->or_mask; |
461 | } else { |
462 | tmp = (entry->hwip == GC_HWIP) ? |
463 | RREG32_SOC15_IP(GC, reg) : RREG32(reg); |
464 | |
465 | tmp &= ~(entry->and_mask); |
466 | tmp |= (entry->or_mask & entry->and_mask); |
467 | } |
468 | |
469 | if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || |
470 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || |
471 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || |
472 | reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) |
473 | WREG32_RLC(reg, tmp); |
474 | else |
475 | (entry->hwip == GC_HWIP) ? |
476 | WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); |
477 | |
478 | } |
479 | |
480 | } |
481 | |
482 | static int soc15_asic_baco_reset(struct amdgpu_device *adev) |
483 | { |
484 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
485 | int ret = 0; |
486 | |
487 | /* avoid NBIF got stuck when do RAS recovery in BACO reset */ |
488 | if (ras && adev->ras_enabled) |
489 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
490 | |
491 | ret = amdgpu_dpm_baco_reset(adev); |
492 | if (ret) |
493 | return ret; |
494 | |
495 | /* re-enable doorbell interrupt after BACO exit */ |
496 | if (ras && adev->ras_enabled) |
497 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
498 | |
499 | return 0; |
500 | } |
501 | |
502 | static enum amd_reset_method |
503 | soc15_asic_reset_method(struct amdgpu_device *adev) |
504 | { |
505 | bool baco_reset = false; |
506 | bool connected_to_cpu = false; |
507 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
508 | |
509 | if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) |
510 | connected_to_cpu = true; |
511 | |
512 | if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || |
513 | amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || |
514 | amdgpu_reset_method == AMD_RESET_METHOD_BACO || |
515 | amdgpu_reset_method == AMD_RESET_METHOD_PCI) { |
516 | /* If connected to cpu, driver only support mode2 */ |
517 | if (connected_to_cpu) |
518 | return AMD_RESET_METHOD_MODE2; |
519 | return amdgpu_reset_method; |
520 | } |
521 | |
522 | if (amdgpu_reset_method != -1) |
523 | dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n" , |
524 | amdgpu_reset_method); |
525 | |
526 | switch (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0)) { |
527 | case IP_VERSION(10, 0, 0): |
528 | case IP_VERSION(10, 0, 1): |
529 | case IP_VERSION(12, 0, 0): |
530 | case IP_VERSION(12, 0, 1): |
531 | return AMD_RESET_METHOD_MODE2; |
532 | case IP_VERSION(9, 0, 0): |
533 | case IP_VERSION(11, 0, 2): |
534 | if (adev->asic_type == CHIP_VEGA20) { |
535 | if (adev->psp.sos.fw_version >= 0x80067) |
536 | baco_reset = amdgpu_dpm_is_baco_supported(adev); |
537 | /* |
538 | * 1. PMFW version > 0x284300: all cases use baco |
539 | * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco |
540 | */ |
541 | if (ras && adev->ras_enabled && |
542 | adev->pm.fw_version <= 0x283400) |
543 | baco_reset = false; |
544 | } else { |
545 | baco_reset = amdgpu_dpm_is_baco_supported(adev); |
546 | } |
547 | break; |
548 | case IP_VERSION(13, 0, 2): |
549 | /* |
550 | * 1.connected to cpu: driver issue mode2 reset |
551 | * 2.discret gpu: driver issue mode1 reset |
552 | */ |
553 | if (connected_to_cpu) |
554 | return AMD_RESET_METHOD_MODE2; |
555 | break; |
556 | case IP_VERSION(13, 0, 6): |
557 | /* Use gpu_recovery param to target a reset method. |
558 | * Enable triggering of GPU reset only if specified |
559 | * by module parameter. |
560 | */ |
561 | if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) |
562 | return AMD_RESET_METHOD_MODE2; |
563 | else if (!(adev->flags & AMD_IS_APU)) |
564 | return AMD_RESET_METHOD_MODE1; |
565 | else |
566 | return AMD_RESET_METHOD_MODE2; |
567 | default: |
568 | break; |
569 | } |
570 | |
571 | if (baco_reset) |
572 | return AMD_RESET_METHOD_BACO; |
573 | else |
574 | return AMD_RESET_METHOD_MODE1; |
575 | } |
576 | |
577 | static int soc15_asic_reset(struct amdgpu_device *adev) |
578 | { |
579 | /* original raven doesn't have full asic reset */ |
580 | if ((adev->apu_flags & AMD_APU_IS_RAVEN) || |
581 | (adev->apu_flags & AMD_APU_IS_RAVEN2)) |
582 | return 0; |
583 | |
584 | switch (soc15_asic_reset_method(adev)) { |
585 | case AMD_RESET_METHOD_PCI: |
586 | dev_info(adev->dev, "PCI reset\n" ); |
587 | return amdgpu_device_pci_reset(adev); |
588 | case AMD_RESET_METHOD_BACO: |
589 | dev_info(adev->dev, "BACO reset\n" ); |
590 | return soc15_asic_baco_reset(adev); |
591 | case AMD_RESET_METHOD_MODE2: |
592 | dev_info(adev->dev, "MODE2 reset\n" ); |
593 | return amdgpu_dpm_mode2_reset(adev); |
594 | default: |
595 | dev_info(adev->dev, "MODE1 reset\n" ); |
596 | return amdgpu_device_mode1_reset(adev); |
597 | } |
598 | } |
599 | |
600 | static bool soc15_supports_baco(struct amdgpu_device *adev) |
601 | { |
602 | switch (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0)) { |
603 | case IP_VERSION(9, 0, 0): |
604 | case IP_VERSION(11, 0, 2): |
605 | if (adev->asic_type == CHIP_VEGA20) { |
606 | if (adev->psp.sos.fw_version >= 0x80067) |
607 | return amdgpu_dpm_is_baco_supported(adev); |
608 | return false; |
609 | } else { |
610 | return amdgpu_dpm_is_baco_supported(adev); |
611 | } |
612 | break; |
613 | default: |
614 | return false; |
615 | } |
616 | } |
617 | |
618 | /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, |
619 | u32 cntl_reg, u32 status_reg) |
620 | { |
621 | return 0; |
622 | }*/ |
623 | |
624 | static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) |
625 | { |
626 | /*int r; |
627 | |
628 | r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); |
629 | if (r) |
630 | return r; |
631 | |
632 | r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); |
633 | */ |
634 | return 0; |
635 | } |
636 | |
637 | static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) |
638 | { |
639 | /* todo */ |
640 | |
641 | return 0; |
642 | } |
643 | |
644 | static void soc15_program_aspm(struct amdgpu_device *adev) |
645 | { |
646 | if (!amdgpu_device_should_use_aspm(adev)) |
647 | return; |
648 | |
649 | if (adev->nbio.funcs->program_aspm) |
650 | adev->nbio.funcs->program_aspm(adev); |
651 | } |
652 | |
653 | const struct amdgpu_ip_block_version vega10_common_ip_block = |
654 | { |
655 | .type = AMD_IP_BLOCK_TYPE_COMMON, |
656 | .major = 2, |
657 | .minor = 0, |
658 | .rev = 0, |
659 | .funcs = &soc15_common_ip_funcs, |
660 | }; |
661 | |
662 | static void soc15_reg_base_init(struct amdgpu_device *adev) |
663 | { |
664 | /* Set IP register base before any HW register access */ |
665 | switch (adev->asic_type) { |
666 | case CHIP_VEGA10: |
667 | case CHIP_VEGA12: |
668 | case CHIP_RAVEN: |
669 | case CHIP_RENOIR: |
670 | vega10_reg_base_init(adev); |
671 | break; |
672 | case CHIP_VEGA20: |
673 | vega20_reg_base_init(adev); |
674 | break; |
675 | case CHIP_ARCTURUS: |
676 | arct_reg_base_init(adev); |
677 | break; |
678 | case CHIP_ALDEBARAN: |
679 | aldebaran_reg_base_init(adev); |
680 | break; |
681 | default: |
682 | DRM_ERROR("Unsupported asic type: %d!\n" , adev->asic_type); |
683 | break; |
684 | } |
685 | } |
686 | |
687 | void soc15_set_virt_ops(struct amdgpu_device *adev) |
688 | { |
689 | adev->virt.ops = &xgpu_ai_virt_ops; |
690 | |
691 | /* init soc15 reg base early enough so we can |
692 | * request request full access for sriov before |
693 | * set_ip_blocks. */ |
694 | soc15_reg_base_init(adev); |
695 | } |
696 | |
697 | static bool soc15_need_full_reset(struct amdgpu_device *adev) |
698 | { |
699 | /* change this when we implement soft reset */ |
700 | return true; |
701 | } |
702 | |
703 | static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
704 | uint64_t *count1) |
705 | { |
706 | uint32_t perfctr = 0; |
707 | uint64_t cnt0_of, cnt1_of; |
708 | int tmp; |
709 | |
710 | /* This reports 0 on APUs, so return to avoid writing/reading registers |
711 | * that may or may not be different from their GPU counterparts |
712 | */ |
713 | if (adev->flags & AMD_IS_APU) |
714 | return; |
715 | |
716 | /* Set the 2 events that we wish to watch, defined above */ |
717 | /* Reg 40 is # received msgs */ |
718 | /* Reg 104 is # of posted requests sent */ |
719 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); |
720 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); |
721 | |
722 | /* Write to enable desired perf counters */ |
723 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); |
724 | /* Zero out and enable the perf counters |
725 | * Write 0x5: |
726 | * Bit 0 = Start all counters(1) |
727 | * Bit 2 = Global counter reset enable(1) |
728 | */ |
729 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); |
730 | |
731 | msleep(msecs: 1000); |
732 | |
733 | /* Load the shadow and disable the perf counters |
734 | * Write 0x2: |
735 | * Bit 0 = Stop counters(0) |
736 | * Bit 1 = Load the shadow counters(1) |
737 | */ |
738 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); |
739 | |
740 | /* Read register values to get any >32bit overflow */ |
741 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); |
742 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); |
743 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); |
744 | |
745 | /* Get the values and add the overflow */ |
746 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); |
747 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); |
748 | } |
749 | |
750 | static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
751 | uint64_t *count1) |
752 | { |
753 | uint32_t perfctr = 0; |
754 | uint64_t cnt0_of, cnt1_of; |
755 | int tmp; |
756 | |
757 | /* This reports 0 on APUs, so return to avoid writing/reading registers |
758 | * that may or may not be different from their GPU counterparts |
759 | */ |
760 | if (adev->flags & AMD_IS_APU) |
761 | return; |
762 | |
763 | /* Set the 2 events that we wish to watch, defined above */ |
764 | /* Reg 40 is # received msgs */ |
765 | /* Reg 108 is # of posted requests sent on VG20 */ |
766 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, |
767 | EVENT0_SEL, 40); |
768 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, |
769 | EVENT1_SEL, 108); |
770 | |
771 | /* Write to enable desired perf counters */ |
772 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); |
773 | /* Zero out and enable the perf counters |
774 | * Write 0x5: |
775 | * Bit 0 = Start all counters(1) |
776 | * Bit 2 = Global counter reset enable(1) |
777 | */ |
778 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); |
779 | |
780 | msleep(msecs: 1000); |
781 | |
782 | /* Load the shadow and disable the perf counters |
783 | * Write 0x2: |
784 | * Bit 0 = Stop counters(0) |
785 | * Bit 1 = Load the shadow counters(1) |
786 | */ |
787 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); |
788 | |
789 | /* Read register values to get any >32bit overflow */ |
790 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); |
791 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); |
792 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); |
793 | |
794 | /* Get the values and add the overflow */ |
795 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); |
796 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); |
797 | } |
798 | |
799 | static bool soc15_need_reset_on_init(struct amdgpu_device *adev) |
800 | { |
801 | u32 sol_reg; |
802 | |
803 | /* CP hangs in IGT reloading test on RN, reset to WA */ |
804 | if (adev->asic_type == CHIP_RENOIR) |
805 | return true; |
806 | |
807 | /* Just return false for soc15 GPUs. Reset does not seem to |
808 | * be necessary. |
809 | */ |
810 | if (!amdgpu_passthrough(adev)) |
811 | return false; |
812 | |
813 | if (adev->flags & AMD_IS_APU) |
814 | return false; |
815 | |
816 | /* Check sOS sign of life register to confirm sys driver and sOS |
817 | * are already been loaded. |
818 | */ |
819 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); |
820 | if (sol_reg) |
821 | return true; |
822 | |
823 | return false; |
824 | } |
825 | |
826 | static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) |
827 | { |
828 | uint64_t nak_r, nak_g; |
829 | |
830 | /* Get the number of NAKs received and generated */ |
831 | nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); |
832 | nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); |
833 | |
834 | /* Add the total number of NAKs, i.e the number of replays */ |
835 | return (nak_r + nak_g); |
836 | } |
837 | |
838 | static void soc15_pre_asic_init(struct amdgpu_device *adev) |
839 | { |
840 | gmc_v9_0_restore_registers(adev); |
841 | } |
842 | |
843 | static const struct amdgpu_asic_funcs soc15_asic_funcs = |
844 | { |
845 | .read_disabled_bios = &soc15_read_disabled_bios, |
846 | .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, |
847 | .read_register = &soc15_read_register, |
848 | .reset = &soc15_asic_reset, |
849 | .reset_method = &soc15_asic_reset_method, |
850 | .get_xclk = &soc15_get_xclk, |
851 | .set_uvd_clocks = &soc15_set_uvd_clocks, |
852 | .set_vce_clocks = &soc15_set_vce_clocks, |
853 | .get_config_memsize = &soc15_get_config_memsize, |
854 | .need_full_reset = &soc15_need_full_reset, |
855 | .init_doorbell_index = &vega10_doorbell_index_init, |
856 | .get_pcie_usage = &soc15_get_pcie_usage, |
857 | .need_reset_on_init = &soc15_need_reset_on_init, |
858 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
859 | .supports_baco = &soc15_supports_baco, |
860 | .pre_asic_init = &soc15_pre_asic_init, |
861 | .query_video_codecs = &soc15_query_video_codecs, |
862 | }; |
863 | |
864 | static const struct amdgpu_asic_funcs vega20_asic_funcs = |
865 | { |
866 | .read_disabled_bios = &soc15_read_disabled_bios, |
867 | .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, |
868 | .read_register = &soc15_read_register, |
869 | .reset = &soc15_asic_reset, |
870 | .reset_method = &soc15_asic_reset_method, |
871 | .get_xclk = &soc15_get_xclk, |
872 | .set_uvd_clocks = &soc15_set_uvd_clocks, |
873 | .set_vce_clocks = &soc15_set_vce_clocks, |
874 | .get_config_memsize = &soc15_get_config_memsize, |
875 | .need_full_reset = &soc15_need_full_reset, |
876 | .init_doorbell_index = &vega20_doorbell_index_init, |
877 | .get_pcie_usage = &vega20_get_pcie_usage, |
878 | .need_reset_on_init = &soc15_need_reset_on_init, |
879 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
880 | .supports_baco = &soc15_supports_baco, |
881 | .pre_asic_init = &soc15_pre_asic_init, |
882 | .query_video_codecs = &soc15_query_video_codecs, |
883 | }; |
884 | |
885 | static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = |
886 | { |
887 | .read_disabled_bios = &soc15_read_disabled_bios, |
888 | .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, |
889 | .read_register = &soc15_read_register, |
890 | .reset = &soc15_asic_reset, |
891 | .reset_method = &soc15_asic_reset_method, |
892 | .get_xclk = &soc15_get_xclk, |
893 | .set_uvd_clocks = &soc15_set_uvd_clocks, |
894 | .set_vce_clocks = &soc15_set_vce_clocks, |
895 | .get_config_memsize = &soc15_get_config_memsize, |
896 | .need_full_reset = &soc15_need_full_reset, |
897 | .init_doorbell_index = &aqua_vanjaram_doorbell_index_init, |
898 | .get_pcie_usage = &amdgpu_nbio_get_pcie_usage, |
899 | .need_reset_on_init = &soc15_need_reset_on_init, |
900 | .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, |
901 | .supports_baco = &soc15_supports_baco, |
902 | .pre_asic_init = &soc15_pre_asic_init, |
903 | .query_video_codecs = &soc15_query_video_codecs, |
904 | .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing, |
905 | }; |
906 | |
907 | static int soc15_common_early_init(void *handle) |
908 | { |
909 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) |
910 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
911 | |
912 | if (!amdgpu_sriov_vf(adev)) { |
913 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; |
914 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; |
915 | } |
916 | adev->smc_rreg = NULL; |
917 | adev->smc_wreg = NULL; |
918 | adev->pcie_rreg = &amdgpu_device_indirect_rreg; |
919 | adev->pcie_wreg = &amdgpu_device_indirect_wreg; |
920 | adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; |
921 | adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; |
922 | adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; |
923 | adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; |
924 | adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; |
925 | adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; |
926 | adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; |
927 | adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; |
928 | adev->didt_rreg = &soc15_didt_rreg; |
929 | adev->didt_wreg = &soc15_didt_wreg; |
930 | adev->gc_cac_rreg = &soc15_gc_cac_rreg; |
931 | adev->gc_cac_wreg = &soc15_gc_cac_wreg; |
932 | adev->se_cac_rreg = &soc15_se_cac_rreg; |
933 | adev->se_cac_wreg = &soc15_se_cac_wreg; |
934 | |
935 | adev->rev_id = amdgpu_device_get_rev_id(adev); |
936 | adev->external_rev_id = 0xFF; |
937 | /* TODO: split the GC and PG flags based on the relevant IP version for which |
938 | * they are relevant. |
939 | */ |
940 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
941 | case IP_VERSION(9, 0, 1): |
942 | adev->asic_funcs = &soc15_asic_funcs; |
943 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
944 | AMD_CG_SUPPORT_GFX_MGLS | |
945 | AMD_CG_SUPPORT_GFX_RLC_LS | |
946 | AMD_CG_SUPPORT_GFX_CP_LS | |
947 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
948 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
949 | AMD_CG_SUPPORT_GFX_CGCG | |
950 | AMD_CG_SUPPORT_GFX_CGLS | |
951 | AMD_CG_SUPPORT_BIF_MGCG | |
952 | AMD_CG_SUPPORT_BIF_LS | |
953 | AMD_CG_SUPPORT_HDP_LS | |
954 | AMD_CG_SUPPORT_DRM_MGCG | |
955 | AMD_CG_SUPPORT_DRM_LS | |
956 | AMD_CG_SUPPORT_ROM_MGCG | |
957 | AMD_CG_SUPPORT_DF_MGCG | |
958 | AMD_CG_SUPPORT_SDMA_MGCG | |
959 | AMD_CG_SUPPORT_SDMA_LS | |
960 | AMD_CG_SUPPORT_MC_MGCG | |
961 | AMD_CG_SUPPORT_MC_LS; |
962 | adev->pg_flags = 0; |
963 | adev->external_rev_id = 0x1; |
964 | break; |
965 | case IP_VERSION(9, 2, 1): |
966 | adev->asic_funcs = &soc15_asic_funcs; |
967 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
968 | AMD_CG_SUPPORT_GFX_MGLS | |
969 | AMD_CG_SUPPORT_GFX_CGCG | |
970 | AMD_CG_SUPPORT_GFX_CGLS | |
971 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
972 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
973 | AMD_CG_SUPPORT_GFX_CP_LS | |
974 | AMD_CG_SUPPORT_MC_LS | |
975 | AMD_CG_SUPPORT_MC_MGCG | |
976 | AMD_CG_SUPPORT_SDMA_MGCG | |
977 | AMD_CG_SUPPORT_SDMA_LS | |
978 | AMD_CG_SUPPORT_BIF_MGCG | |
979 | AMD_CG_SUPPORT_BIF_LS | |
980 | AMD_CG_SUPPORT_HDP_MGCG | |
981 | AMD_CG_SUPPORT_HDP_LS | |
982 | AMD_CG_SUPPORT_ROM_MGCG | |
983 | AMD_CG_SUPPORT_VCE_MGCG | |
984 | AMD_CG_SUPPORT_UVD_MGCG; |
985 | adev->pg_flags = 0; |
986 | adev->external_rev_id = adev->rev_id + 0x14; |
987 | break; |
988 | case IP_VERSION(9, 4, 0): |
989 | adev->asic_funcs = &vega20_asic_funcs; |
990 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
991 | AMD_CG_SUPPORT_GFX_MGLS | |
992 | AMD_CG_SUPPORT_GFX_CGCG | |
993 | AMD_CG_SUPPORT_GFX_CGLS | |
994 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
995 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
996 | AMD_CG_SUPPORT_GFX_CP_LS | |
997 | AMD_CG_SUPPORT_MC_LS | |
998 | AMD_CG_SUPPORT_MC_MGCG | |
999 | AMD_CG_SUPPORT_SDMA_MGCG | |
1000 | AMD_CG_SUPPORT_SDMA_LS | |
1001 | AMD_CG_SUPPORT_BIF_MGCG | |
1002 | AMD_CG_SUPPORT_BIF_LS | |
1003 | AMD_CG_SUPPORT_HDP_MGCG | |
1004 | AMD_CG_SUPPORT_HDP_LS | |
1005 | AMD_CG_SUPPORT_ROM_MGCG | |
1006 | AMD_CG_SUPPORT_VCE_MGCG | |
1007 | AMD_CG_SUPPORT_UVD_MGCG; |
1008 | adev->pg_flags = 0; |
1009 | adev->external_rev_id = adev->rev_id + 0x28; |
1010 | break; |
1011 | case IP_VERSION(9, 1, 0): |
1012 | case IP_VERSION(9, 2, 2): |
1013 | adev->asic_funcs = &soc15_asic_funcs; |
1014 | |
1015 | if (adev->rev_id >= 0x8) |
1016 | adev->apu_flags |= AMD_APU_IS_RAVEN2; |
1017 | |
1018 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1019 | adev->external_rev_id = adev->rev_id + 0x79; |
1020 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
1021 | adev->external_rev_id = adev->rev_id + 0x41; |
1022 | else if (adev->rev_id == 1) |
1023 | adev->external_rev_id = adev->rev_id + 0x20; |
1024 | else |
1025 | adev->external_rev_id = adev->rev_id + 0x01; |
1026 | |
1027 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) { |
1028 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1029 | AMD_CG_SUPPORT_GFX_MGLS | |
1030 | AMD_CG_SUPPORT_GFX_CP_LS | |
1031 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
1032 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
1033 | AMD_CG_SUPPORT_GFX_CGCG | |
1034 | AMD_CG_SUPPORT_GFX_CGLS | |
1035 | AMD_CG_SUPPORT_BIF_LS | |
1036 | AMD_CG_SUPPORT_HDP_LS | |
1037 | AMD_CG_SUPPORT_MC_MGCG | |
1038 | AMD_CG_SUPPORT_MC_LS | |
1039 | AMD_CG_SUPPORT_SDMA_MGCG | |
1040 | AMD_CG_SUPPORT_SDMA_LS | |
1041 | AMD_CG_SUPPORT_VCN_MGCG; |
1042 | |
1043 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
1044 | } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { |
1045 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1046 | AMD_CG_SUPPORT_GFX_MGLS | |
1047 | AMD_CG_SUPPORT_GFX_CP_LS | |
1048 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
1049 | AMD_CG_SUPPORT_GFX_CGCG | |
1050 | AMD_CG_SUPPORT_GFX_CGLS | |
1051 | AMD_CG_SUPPORT_BIF_LS | |
1052 | AMD_CG_SUPPORT_HDP_LS | |
1053 | AMD_CG_SUPPORT_MC_MGCG | |
1054 | AMD_CG_SUPPORT_MC_LS | |
1055 | AMD_CG_SUPPORT_SDMA_MGCG | |
1056 | AMD_CG_SUPPORT_SDMA_LS | |
1057 | AMD_CG_SUPPORT_VCN_MGCG; |
1058 | |
1059 | /* |
1060 | * MMHUB PG needs to be disabled for Picasso for |
1061 | * stability reasons. |
1062 | */ |
1063 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | |
1064 | AMD_PG_SUPPORT_VCN; |
1065 | } else { |
1066 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1067 | AMD_CG_SUPPORT_GFX_MGLS | |
1068 | AMD_CG_SUPPORT_GFX_RLC_LS | |
1069 | AMD_CG_SUPPORT_GFX_CP_LS | |
1070 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
1071 | AMD_CG_SUPPORT_GFX_CGCG | |
1072 | AMD_CG_SUPPORT_GFX_CGLS | |
1073 | AMD_CG_SUPPORT_BIF_MGCG | |
1074 | AMD_CG_SUPPORT_BIF_LS | |
1075 | AMD_CG_SUPPORT_HDP_MGCG | |
1076 | AMD_CG_SUPPORT_HDP_LS | |
1077 | AMD_CG_SUPPORT_DRM_MGCG | |
1078 | AMD_CG_SUPPORT_DRM_LS | |
1079 | AMD_CG_SUPPORT_MC_MGCG | |
1080 | AMD_CG_SUPPORT_MC_LS | |
1081 | AMD_CG_SUPPORT_SDMA_MGCG | |
1082 | AMD_CG_SUPPORT_SDMA_LS | |
1083 | AMD_CG_SUPPORT_VCN_MGCG; |
1084 | |
1085 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
1086 | } |
1087 | break; |
1088 | case IP_VERSION(9, 4, 1): |
1089 | adev->asic_funcs = &vega20_asic_funcs; |
1090 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1091 | AMD_CG_SUPPORT_GFX_MGLS | |
1092 | AMD_CG_SUPPORT_GFX_CGCG | |
1093 | AMD_CG_SUPPORT_GFX_CGLS | |
1094 | AMD_CG_SUPPORT_GFX_CP_LS | |
1095 | AMD_CG_SUPPORT_HDP_MGCG | |
1096 | AMD_CG_SUPPORT_HDP_LS | |
1097 | AMD_CG_SUPPORT_SDMA_MGCG | |
1098 | AMD_CG_SUPPORT_SDMA_LS | |
1099 | AMD_CG_SUPPORT_MC_MGCG | |
1100 | AMD_CG_SUPPORT_MC_LS | |
1101 | AMD_CG_SUPPORT_IH_CG | |
1102 | AMD_CG_SUPPORT_VCN_MGCG | |
1103 | AMD_CG_SUPPORT_JPEG_MGCG; |
1104 | adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; |
1105 | adev->external_rev_id = adev->rev_id + 0x32; |
1106 | break; |
1107 | case IP_VERSION(9, 3, 0): |
1108 | adev->asic_funcs = &soc15_asic_funcs; |
1109 | |
1110 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
1111 | adev->external_rev_id = adev->rev_id + 0x91; |
1112 | else |
1113 | adev->external_rev_id = adev->rev_id + 0xa1; |
1114 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1115 | AMD_CG_SUPPORT_GFX_MGLS | |
1116 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
1117 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
1118 | AMD_CG_SUPPORT_GFX_CGCG | |
1119 | AMD_CG_SUPPORT_GFX_CGLS | |
1120 | AMD_CG_SUPPORT_GFX_CP_LS | |
1121 | AMD_CG_SUPPORT_MC_MGCG | |
1122 | AMD_CG_SUPPORT_MC_LS | |
1123 | AMD_CG_SUPPORT_SDMA_MGCG | |
1124 | AMD_CG_SUPPORT_SDMA_LS | |
1125 | AMD_CG_SUPPORT_BIF_LS | |
1126 | AMD_CG_SUPPORT_HDP_LS | |
1127 | AMD_CG_SUPPORT_VCN_MGCG | |
1128 | AMD_CG_SUPPORT_JPEG_MGCG | |
1129 | AMD_CG_SUPPORT_IH_CG | |
1130 | AMD_CG_SUPPORT_ATHUB_LS | |
1131 | AMD_CG_SUPPORT_ATHUB_MGCG | |
1132 | AMD_CG_SUPPORT_DF_MGCG; |
1133 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | |
1134 | AMD_PG_SUPPORT_VCN | |
1135 | AMD_PG_SUPPORT_JPEG | |
1136 | AMD_PG_SUPPORT_VCN_DPG; |
1137 | break; |
1138 | case IP_VERSION(9, 4, 2): |
1139 | adev->asic_funcs = &vega20_asic_funcs; |
1140 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1141 | AMD_CG_SUPPORT_GFX_MGLS | |
1142 | AMD_CG_SUPPORT_GFX_CP_LS | |
1143 | AMD_CG_SUPPORT_HDP_LS | |
1144 | AMD_CG_SUPPORT_SDMA_MGCG | |
1145 | AMD_CG_SUPPORT_SDMA_LS | |
1146 | AMD_CG_SUPPORT_IH_CG | |
1147 | AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; |
1148 | adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; |
1149 | adev->external_rev_id = adev->rev_id + 0x3c; |
1150 | break; |
1151 | case IP_VERSION(9, 4, 3): |
1152 | adev->asic_funcs = &aqua_vanjaram_asic_funcs; |
1153 | adev->cg_flags = |
1154 | AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | |
1155 | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | |
1156 | AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG | |
1157 | AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | |
1158 | AMD_CG_SUPPORT_IH_CG; |
1159 | adev->pg_flags = |
1160 | AMD_PG_SUPPORT_VCN | |
1161 | AMD_PG_SUPPORT_VCN_DPG | |
1162 | AMD_PG_SUPPORT_JPEG; |
1163 | adev->external_rev_id = adev->rev_id + 0x46; |
1164 | break; |
1165 | default: |
1166 | /* FIXME: not supported yet */ |
1167 | return -EINVAL; |
1168 | } |
1169 | |
1170 | if (amdgpu_sriov_vf(adev)) { |
1171 | amdgpu_virt_init_setting(adev); |
1172 | xgpu_ai_mailbox_set_irq_funcs(adev); |
1173 | } |
1174 | |
1175 | return 0; |
1176 | } |
1177 | |
1178 | static int soc15_common_late_init(void *handle) |
1179 | { |
1180 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1181 | |
1182 | if (amdgpu_sriov_vf(adev)) |
1183 | xgpu_ai_mailbox_get_irq(adev); |
1184 | |
1185 | /* Enable selfring doorbell aperture late because doorbell BAR |
1186 | * aperture will change if resize BAR successfully in gmc sw_init. |
1187 | */ |
1188 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); |
1189 | |
1190 | return 0; |
1191 | } |
1192 | |
1193 | static int soc15_common_sw_init(void *handle) |
1194 | { |
1195 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1196 | |
1197 | if (amdgpu_sriov_vf(adev)) |
1198 | xgpu_ai_mailbox_add_irq_id(adev); |
1199 | |
1200 | if (adev->df.funcs && |
1201 | adev->df.funcs->sw_init) |
1202 | adev->df.funcs->sw_init(adev); |
1203 | |
1204 | return 0; |
1205 | } |
1206 | |
1207 | static int soc15_common_sw_fini(void *handle) |
1208 | { |
1209 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1210 | |
1211 | if (adev->df.funcs && |
1212 | adev->df.funcs->sw_fini) |
1213 | adev->df.funcs->sw_fini(adev); |
1214 | return 0; |
1215 | } |
1216 | |
1217 | static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) |
1218 | { |
1219 | int i; |
1220 | |
1221 | /* sdma doorbell range is programed by hypervisor */ |
1222 | if (!amdgpu_sriov_vf(adev)) { |
1223 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1224 | adev->nbio.funcs->sdma_doorbell_range(adev, i, |
1225 | true, adev->doorbell_index.sdma_engine[i] << 1, |
1226 | adev->doorbell_index.sdma_doorbell_range); |
1227 | } |
1228 | } |
1229 | } |
1230 | |
1231 | static int soc15_common_hw_init(void *handle) |
1232 | { |
1233 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1234 | |
1235 | /* enable aspm */ |
1236 | soc15_program_aspm(adev); |
1237 | /* setup nbio registers */ |
1238 | adev->nbio.funcs->init_registers(adev); |
1239 | /* remap HDP registers to a hole in mmio space, |
1240 | * for the purpose of expose those registers |
1241 | * to process space |
1242 | */ |
1243 | if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) |
1244 | adev->nbio.funcs->remap_hdp_registers(adev); |
1245 | |
1246 | /* enable the doorbell aperture */ |
1247 | adev->nbio.funcs->enable_doorbell_aperture(adev, true); |
1248 | |
1249 | /* HW doorbell routing policy: doorbell writing not |
1250 | * in SDMA/IH/MM/ACV range will be routed to CP. So |
1251 | * we need to init SDMA doorbell range prior |
1252 | * to CP ip block init and ring test. IH already |
1253 | * happens before CP. |
1254 | */ |
1255 | soc15_sdma_doorbell_range_init(adev); |
1256 | |
1257 | return 0; |
1258 | } |
1259 | |
1260 | static int soc15_common_hw_fini(void *handle) |
1261 | { |
1262 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1263 | |
1264 | /* Disable the doorbell aperture and selfring doorbell aperture |
1265 | * separately in hw_fini because soc15_enable_doorbell_aperture |
1266 | * has been removed and there is no need to delay disabling |
1267 | * selfring doorbell. |
1268 | */ |
1269 | adev->nbio.funcs->enable_doorbell_aperture(adev, false); |
1270 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); |
1271 | |
1272 | if (amdgpu_sriov_vf(adev)) |
1273 | xgpu_ai_mailbox_put_irq(adev); |
1274 | |
1275 | if (adev->nbio.ras_if && |
1276 | amdgpu_ras_is_supported(adev, block: adev->nbio.ras_if->block)) { |
1277 | if (adev->nbio.ras && |
1278 | adev->nbio.ras->init_ras_controller_interrupt) |
1279 | amdgpu_irq_put(adev, src: &adev->nbio.ras_controller_irq, type: 0); |
1280 | if (adev->nbio.ras && |
1281 | adev->nbio.ras->init_ras_err_event_athub_interrupt) |
1282 | amdgpu_irq_put(adev, src: &adev->nbio.ras_err_event_athub_irq, type: 0); |
1283 | } |
1284 | |
1285 | return 0; |
1286 | } |
1287 | |
1288 | static int soc15_common_suspend(void *handle) |
1289 | { |
1290 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1291 | |
1292 | return soc15_common_hw_fini(handle: adev); |
1293 | } |
1294 | |
1295 | static int soc15_common_resume(void *handle) |
1296 | { |
1297 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1298 | |
1299 | return soc15_common_hw_init(handle: adev); |
1300 | } |
1301 | |
1302 | static bool soc15_common_is_idle(void *handle) |
1303 | { |
1304 | return true; |
1305 | } |
1306 | |
1307 | static int soc15_common_wait_for_idle(void *handle) |
1308 | { |
1309 | return 0; |
1310 | } |
1311 | |
1312 | static int soc15_common_soft_reset(void *handle) |
1313 | { |
1314 | return 0; |
1315 | } |
1316 | |
1317 | static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) |
1318 | { |
1319 | uint32_t def, data; |
1320 | |
1321 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); |
1322 | |
1323 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) |
1324 | data &= ~(0x01000000 | |
1325 | 0x02000000 | |
1326 | 0x04000000 | |
1327 | 0x08000000 | |
1328 | 0x10000000 | |
1329 | 0x20000000 | |
1330 | 0x40000000 | |
1331 | 0x80000000); |
1332 | else |
1333 | data |= (0x01000000 | |
1334 | 0x02000000 | |
1335 | 0x04000000 | |
1336 | 0x08000000 | |
1337 | 0x10000000 | |
1338 | 0x20000000 | |
1339 | 0x40000000 | |
1340 | 0x80000000); |
1341 | |
1342 | if (def != data) |
1343 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); |
1344 | } |
1345 | |
1346 | static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) |
1347 | { |
1348 | uint32_t def, data; |
1349 | |
1350 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); |
1351 | |
1352 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) |
1353 | data |= 1; |
1354 | else |
1355 | data &= ~1; |
1356 | |
1357 | if (def != data) |
1358 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); |
1359 | } |
1360 | |
1361 | static int soc15_common_set_clockgating_state(void *handle, |
1362 | enum amd_clockgating_state state) |
1363 | { |
1364 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1365 | |
1366 | if (amdgpu_sriov_vf(adev)) |
1367 | return 0; |
1368 | |
1369 | switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) { |
1370 | case IP_VERSION(6, 1, 0): |
1371 | case IP_VERSION(6, 2, 0): |
1372 | case IP_VERSION(7, 4, 0): |
1373 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
1374 | state == AMD_CG_STATE_GATE); |
1375 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
1376 | state == AMD_CG_STATE_GATE); |
1377 | adev->hdp.funcs->update_clock_gating(adev, |
1378 | state == AMD_CG_STATE_GATE); |
1379 | soc15_update_drm_clock_gating(adev, |
1380 | enable: state == AMD_CG_STATE_GATE); |
1381 | soc15_update_drm_light_sleep(adev, |
1382 | enable: state == AMD_CG_STATE_GATE); |
1383 | adev->smuio.funcs->update_rom_clock_gating(adev, |
1384 | state == AMD_CG_STATE_GATE); |
1385 | adev->df.funcs->update_medium_grain_clock_gating(adev, |
1386 | state == AMD_CG_STATE_GATE); |
1387 | break; |
1388 | case IP_VERSION(7, 0, 0): |
1389 | case IP_VERSION(7, 0, 1): |
1390 | case IP_VERSION(2, 5, 0): |
1391 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
1392 | state == AMD_CG_STATE_GATE); |
1393 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
1394 | state == AMD_CG_STATE_GATE); |
1395 | adev->hdp.funcs->update_clock_gating(adev, |
1396 | state == AMD_CG_STATE_GATE); |
1397 | soc15_update_drm_clock_gating(adev, |
1398 | enable: state == AMD_CG_STATE_GATE); |
1399 | soc15_update_drm_light_sleep(adev, |
1400 | enable: state == AMD_CG_STATE_GATE); |
1401 | break; |
1402 | case IP_VERSION(7, 4, 1): |
1403 | case IP_VERSION(7, 4, 4): |
1404 | adev->hdp.funcs->update_clock_gating(adev, |
1405 | state == AMD_CG_STATE_GATE); |
1406 | break; |
1407 | default: |
1408 | break; |
1409 | } |
1410 | return 0; |
1411 | } |
1412 | |
1413 | static void soc15_common_get_clockgating_state(void *handle, u64 *flags) |
1414 | { |
1415 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1416 | int data; |
1417 | |
1418 | if (amdgpu_sriov_vf(adev)) |
1419 | *flags = 0; |
1420 | |
1421 | adev->nbio.funcs->get_clockgating_state(adev, flags); |
1422 | |
1423 | adev->hdp.funcs->get_clock_gating_state(adev, flags); |
1424 | |
1425 | if (amdgpu_ip_version(adev, ip: MP0_HWIP, inst: 0) != IP_VERSION(13, 0, 2)) { |
1426 | /* AMD_CG_SUPPORT_DRM_MGCG */ |
1427 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); |
1428 | if (!(data & 0x01000000)) |
1429 | *flags |= AMD_CG_SUPPORT_DRM_MGCG; |
1430 | |
1431 | /* AMD_CG_SUPPORT_DRM_LS */ |
1432 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); |
1433 | if (data & 0x1) |
1434 | *flags |= AMD_CG_SUPPORT_DRM_LS; |
1435 | } |
1436 | |
1437 | /* AMD_CG_SUPPORT_ROM_MGCG */ |
1438 | adev->smuio.funcs->get_clock_gating_state(adev, flags); |
1439 | |
1440 | adev->df.funcs->get_clockgating_state(adev, flags); |
1441 | } |
1442 | |
1443 | static int soc15_common_set_powergating_state(void *handle, |
1444 | enum amd_powergating_state state) |
1445 | { |
1446 | /* todo */ |
1447 | return 0; |
1448 | } |
1449 | |
1450 | static const struct amd_ip_funcs soc15_common_ip_funcs = { |
1451 | .name = "soc15_common" , |
1452 | .early_init = soc15_common_early_init, |
1453 | .late_init = soc15_common_late_init, |
1454 | .sw_init = soc15_common_sw_init, |
1455 | .sw_fini = soc15_common_sw_fini, |
1456 | .hw_init = soc15_common_hw_init, |
1457 | .hw_fini = soc15_common_hw_fini, |
1458 | .suspend = soc15_common_suspend, |
1459 | .resume = soc15_common_resume, |
1460 | .is_idle = soc15_common_is_idle, |
1461 | .wait_for_idle = soc15_common_wait_for_idle, |
1462 | .soft_reset = soc15_common_soft_reset, |
1463 | .set_clockgating_state = soc15_common_set_clockgating_state, |
1464 | .set_powergating_state = soc15_common_set_powergating_state, |
1465 | .get_clockgating_state= soc15_common_get_clockgating_state, |
1466 | }; |
1467 | |