1 | //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file implements the XCoreTargetLowering class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #include "XCoreISelLowering.h" |
14 | #include "XCore.h" |
15 | #include "XCoreMachineFunctionInfo.h" |
16 | #include "XCoreSubtarget.h" |
17 | #include "XCoreTargetMachine.h" |
18 | #include "XCoreTargetObjectFile.h" |
19 | #include "llvm/CodeGen/CallingConvLower.h" |
20 | #include "llvm/CodeGen/MachineFrameInfo.h" |
21 | #include "llvm/CodeGen/MachineFunction.h" |
22 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
23 | #include "llvm/CodeGen/MachineJumpTableInfo.h" |
24 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
25 | #include "llvm/CodeGen/ValueTypes.h" |
26 | #include "llvm/IR/CallingConv.h" |
27 | #include "llvm/IR/Constants.h" |
28 | #include "llvm/IR/DerivedTypes.h" |
29 | #include "llvm/IR/Function.h" |
30 | #include "llvm/IR/GlobalAlias.h" |
31 | #include "llvm/IR/GlobalVariable.h" |
32 | #include "llvm/IR/Intrinsics.h" |
33 | #include "llvm/IR/IntrinsicsXCore.h" |
34 | #include "llvm/Support/Debug.h" |
35 | #include "llvm/Support/ErrorHandling.h" |
36 | #include "llvm/Support/KnownBits.h" |
37 | #include "llvm/Support/raw_ostream.h" |
38 | #include <algorithm> |
39 | |
40 | using namespace llvm; |
41 | |
42 | #define DEBUG_TYPE "xcore-lower" |
43 | |
44 | const char *XCoreTargetLowering:: |
45 | getTargetNodeName(unsigned Opcode) const |
46 | { |
47 | switch ((XCoreISD::NodeType)Opcode) |
48 | { |
49 | case XCoreISD::FIRST_NUMBER : break; |
50 | case XCoreISD::BL : return "XCoreISD::BL" ; |
51 | case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; |
52 | case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; |
53 | case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; |
54 | case XCoreISD::LDWSP : return "XCoreISD::LDWSP" ; |
55 | case XCoreISD::STWSP : return "XCoreISD::STWSP" ; |
56 | case XCoreISD::RETSP : return "XCoreISD::RETSP" ; |
57 | case XCoreISD::LADD : return "XCoreISD::LADD" ; |
58 | case XCoreISD::LSUB : return "XCoreISD::LSUB" ; |
59 | case XCoreISD::LMUL : return "XCoreISD::LMUL" ; |
60 | case XCoreISD::MACCU : return "XCoreISD::MACCU" ; |
61 | case XCoreISD::MACCS : return "XCoreISD::MACCS" ; |
62 | case XCoreISD::CRC8 : return "XCoreISD::CRC8" ; |
63 | case XCoreISD::BR_JT : return "XCoreISD::BR_JT" ; |
64 | case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32" ; |
65 | case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET" ; |
66 | case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN" ; |
67 | } |
68 | return nullptr; |
69 | } |
70 | |
71 | XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM, |
72 | const XCoreSubtarget &Subtarget) |
73 | : TargetLowering(TM), TM(TM), Subtarget(Subtarget) { |
74 | |
75 | // Set up the register classes. |
76 | addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); |
77 | |
78 | // Compute derived properties from the register classes |
79 | computeRegisterProperties(TRI: Subtarget.getRegisterInfo()); |
80 | |
81 | setStackPointerRegisterToSaveRestore(XCore::SP); |
82 | |
83 | setSchedulingPreference(Sched::Source); |
84 | |
85 | // Use i32 for setcc operations results (slt, sgt, ...). |
86 | setBooleanContents(ZeroOrOneBooleanContent); |
87 | setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? |
88 | |
89 | // XCore does not have the NodeTypes below. |
90 | setOperationAction(ISD::BR_CC, MVT::i32, Expand); |
91 | setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); |
92 | |
93 | // 64bit |
94 | setOperationAction(ISD::ADD, MVT::i64, Custom); |
95 | setOperationAction(ISD::SUB, MVT::i64, Custom); |
96 | setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); |
97 | setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); |
98 | setOperationAction(ISD::MULHS, MVT::i32, Expand); |
99 | setOperationAction(ISD::MULHU, MVT::i32, Expand); |
100 | setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); |
101 | setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); |
102 | setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); |
103 | |
104 | // Bit Manipulation |
105 | setOperationAction(ISD::CTPOP, MVT::i32, Expand); |
106 | setOperationAction(ISD::ROTL , MVT::i32, Expand); |
107 | setOperationAction(ISD::ROTR , MVT::i32, Expand); |
108 | setOperationAction(ISD::BITREVERSE , MVT::i32, Legal); |
109 | |
110 | setOperationAction(ISD::TRAP, MVT::Other, Legal); |
111 | |
112 | // Jump tables. |
113 | setOperationAction(ISD::BR_JT, MVT::Other, Custom); |
114 | |
115 | setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); |
116 | setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); |
117 | |
118 | // Conversion of i64 -> double produces constantpool nodes |
119 | setOperationAction(ISD::ConstantPool, MVT::i32, Custom); |
120 | |
121 | // Loads |
122 | for (MVT VT : MVT::integer_valuetypes()) { |
123 | setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); |
124 | setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); |
125 | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); |
126 | |
127 | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); |
128 | setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); |
129 | } |
130 | |
131 | // Custom expand misaligned loads / stores. |
132 | setOperationAction(ISD::LOAD, MVT::i32, Custom); |
133 | setOperationAction(ISD::STORE, MVT::i32, Custom); |
134 | |
135 | // Varargs |
136 | setOperationAction(ISD::VAEND, MVT::Other, Expand); |
137 | setOperationAction(ISD::VACOPY, MVT::Other, Expand); |
138 | setOperationAction(ISD::VAARG, MVT::Other, Custom); |
139 | setOperationAction(ISD::VASTART, MVT::Other, Custom); |
140 | |
141 | // Dynamic stack |
142 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
143 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
144 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); |
145 | |
146 | // Exception handling |
147 | setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); |
148 | setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); |
149 | |
150 | setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); |
151 | |
152 | // TRAMPOLINE is custom lowered. |
153 | setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); |
154 | setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); |
155 | |
156 | // We want to custom lower some of our intrinsics. |
157 | setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); |
158 | |
159 | MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4; |
160 | MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize |
161 | = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2; |
162 | |
163 | // We have target-specific dag combine patterns for the following nodes: |
164 | setTargetDAGCombine( |
165 | {ISD::STORE, ISD::ADD, ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN}); |
166 | |
167 | setMinFunctionAlignment(Align(2)); |
168 | setPrefFunctionAlignment(Align(4)); |
169 | |
170 | // This target doesn't implement native atomics. |
171 | setMaxAtomicSizeInBitsSupported(0); |
172 | } |
173 | |
174 | bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { |
175 | if (Val.getOpcode() != ISD::LOAD) |
176 | return false; |
177 | |
178 | EVT VT1 = Val.getValueType(); |
179 | if (!VT1.isSimple() || !VT1.isInteger() || |
180 | !VT2.isSimple() || !VT2.isInteger()) |
181 | return false; |
182 | |
183 | switch (VT1.getSimpleVT().SimpleTy) { |
184 | default: break; |
185 | case MVT::i8: |
186 | return true; |
187 | } |
188 | |
189 | return false; |
190 | } |
191 | |
192 | SDValue XCoreTargetLowering:: |
193 | LowerOperation(SDValue Op, SelectionDAG &DAG) const { |
194 | switch (Op.getOpcode()) |
195 | { |
196 | case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); |
197 | case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); |
198 | case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); |
199 | case ISD::ConstantPool: return LowerConstantPool(Op, DAG); |
200 | case ISD::BR_JT: return LowerBR_JT(Op, DAG); |
201 | case ISD::LOAD: return LowerLOAD(Op, DAG); |
202 | case ISD::STORE: return LowerSTORE(Op, DAG); |
203 | case ISD::VAARG: return LowerVAARG(Op, DAG); |
204 | case ISD::VASTART: return LowerVASTART(Op, DAG); |
205 | case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG); |
206 | case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG); |
207 | // FIXME: Remove these when LegalizeDAGTypes lands. |
208 | case ISD::ADD: |
209 | case ISD::SUB: return ExpandADDSUB(Op: Op.getNode(), DAG); |
210 | case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); |
211 | case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); |
212 | case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); |
213 | case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); |
214 | case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); |
215 | case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); |
216 | case ISD::ATOMIC_FENCE: |
217 | return LowerATOMIC_FENCE(Op, DAG); |
218 | default: |
219 | llvm_unreachable("unimplemented operand" ); |
220 | } |
221 | } |
222 | |
223 | /// ReplaceNodeResults - Replace the results of node with an illegal result |
224 | /// type with new values built out of custom code. |
225 | void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, |
226 | SmallVectorImpl<SDValue>&Results, |
227 | SelectionDAG &DAG) const { |
228 | switch (N->getOpcode()) { |
229 | default: |
230 | llvm_unreachable("Don't know how to custom expand this!" ); |
231 | case ISD::ADD: |
232 | case ISD::SUB: |
233 | Results.push_back(Elt: ExpandADDSUB(Op: N, DAG)); |
234 | return; |
235 | } |
236 | } |
237 | |
238 | //===----------------------------------------------------------------------===// |
239 | // Misc Lower Operation implementation |
240 | //===----------------------------------------------------------------------===// |
241 | |
242 | SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA, |
243 | const GlobalValue *GV, |
244 | SelectionDAG &DAG) const { |
245 | // FIXME there is no actual debug info here |
246 | SDLoc dl(GA); |
247 | |
248 | if (GV->getValueType()->isFunctionTy()) |
249 | return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); |
250 | |
251 | const auto *GVar = dyn_cast<GlobalVariable>(Val: GV); |
252 | if ((GV->hasSection() && GV->getSection().starts_with(".cp." )) || |
253 | (GVar && GVar->isConstant() && GV->hasLocalLinkage())) |
254 | return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); |
255 | |
256 | return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); |
257 | } |
258 | |
259 | static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) { |
260 | if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small) |
261 | return true; |
262 | |
263 | Type *ObjType = GV->getValueType(); |
264 | if (!ObjType->isSized()) |
265 | return false; |
266 | |
267 | auto &DL = GV->getParent()->getDataLayout(); |
268 | unsigned ObjSize = DL.getTypeAllocSize(Ty: ObjType); |
269 | return ObjSize < CodeModelLargeSize && ObjSize != 0; |
270 | } |
271 | |
272 | SDValue XCoreTargetLowering:: |
273 | LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const |
274 | { |
275 | const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Val&: Op); |
276 | const GlobalValue *GV = GN->getGlobal(); |
277 | SDLoc DL(GN); |
278 | int64_t Offset = GN->getOffset(); |
279 | if (IsSmallObject(GV, XTL: *this)) { |
280 | // We can only fold positive offsets that are a multiple of the word size. |
281 | int64_t FoldedOffset = std::max(a: Offset & ~3, b: (int64_t)0); |
282 | SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset); |
283 | GA = getGlobalAddressWrapper(GA, GV, DAG); |
284 | // Handle the rest of the offset. |
285 | if (Offset != FoldedOffset) { |
286 | SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL, MVT::i32); |
287 | GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); |
288 | } |
289 | return GA; |
290 | } else { |
291 | // Ideally we would not fold in offset with an index <= 11. |
292 | Type *Ty = Type::getInt32Ty(C&: *DAG.getContext()); |
293 | Constant *Idx = ConstantInt::get(Ty, V: Offset); |
294 | Constant *GAI = ConstantExpr::getGetElementPtr( |
295 | Ty: Type::getInt8Ty(C&: *DAG.getContext()), C: const_cast<GlobalValue *>(GV), Idx); |
296 | SDValue CP = DAG.getConstantPool(GAI, MVT::i32); |
297 | return DAG.getLoad(VT: getPointerTy(DL: DAG.getDataLayout()), dl: DL, |
298 | Chain: DAG.getEntryNode(), Ptr: CP, PtrInfo: MachinePointerInfo()); |
299 | } |
300 | } |
301 | |
302 | SDValue XCoreTargetLowering:: |
303 | LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const |
304 | { |
305 | SDLoc DL(Op); |
306 | auto PtrVT = getPointerTy(DL: DAG.getDataLayout()); |
307 | const BlockAddress *BA = cast<BlockAddressSDNode>(Val&: Op)->getBlockAddress(); |
308 | SDValue Result = DAG.getTargetBlockAddress(BA, VT: PtrVT); |
309 | |
310 | return DAG.getNode(Opcode: XCoreISD::PCRelativeWrapper, DL, VT: PtrVT, Operand: Result); |
311 | } |
312 | |
313 | SDValue XCoreTargetLowering:: |
314 | LowerConstantPool(SDValue Op, SelectionDAG &DAG) const |
315 | { |
316 | ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Val&: Op); |
317 | // FIXME there isn't really debug info here |
318 | SDLoc dl(CP); |
319 | EVT PtrVT = Op.getValueType(); |
320 | SDValue Res; |
321 | if (CP->isMachineConstantPoolEntry()) { |
322 | Res = DAG.getTargetConstantPool(C: CP->getMachineCPVal(), VT: PtrVT, |
323 | Align: CP->getAlign(), Offset: CP->getOffset()); |
324 | } else { |
325 | Res = DAG.getTargetConstantPool(C: CP->getConstVal(), VT: PtrVT, Align: CP->getAlign(), |
326 | Offset: CP->getOffset()); |
327 | } |
328 | return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); |
329 | } |
330 | |
331 | unsigned XCoreTargetLowering::getJumpTableEncoding() const { |
332 | return MachineJumpTableInfo::EK_Inline; |
333 | } |
334 | |
335 | SDValue XCoreTargetLowering:: |
336 | LowerBR_JT(SDValue Op, SelectionDAG &DAG) const |
337 | { |
338 | SDValue Chain = Op.getOperand(i: 0); |
339 | SDValue Table = Op.getOperand(i: 1); |
340 | SDValue Index = Op.getOperand(i: 2); |
341 | SDLoc dl(Op); |
342 | JumpTableSDNode *JT = cast<JumpTableSDNode>(Val&: Table); |
343 | unsigned JTI = JT->getIndex(); |
344 | MachineFunction &MF = DAG.getMachineFunction(); |
345 | const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); |
346 | SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); |
347 | |
348 | unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size(); |
349 | if (NumEntries <= 32) { |
350 | return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); |
351 | } |
352 | assert((NumEntries >> 31) == 0); |
353 | SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, |
354 | DAG.getConstant(1, dl, MVT::i32)); |
355 | return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, |
356 | ScaledIndex); |
357 | } |
358 | |
359 | SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset( |
360 | const SDLoc &DL, SDValue Chain, SDValue Base, int64_t Offset, |
361 | SelectionDAG &DAG) const { |
362 | auto PtrVT = getPointerTy(DL: DAG.getDataLayout()); |
363 | if ((Offset & 0x3) == 0) { |
364 | return DAG.getLoad(VT: PtrVT, dl: DL, Chain, Ptr: Base, PtrInfo: MachinePointerInfo()); |
365 | } |
366 | // Lower to pair of consecutive word aligned loads plus some bit shifting. |
367 | int32_t HighOffset = alignTo(Value: Offset, Align: 4); |
368 | int32_t LowOffset = HighOffset - 4; |
369 | SDValue LowAddr, HighAddr; |
370 | if (GlobalAddressSDNode *GASD = |
371 | dyn_cast<GlobalAddressSDNode>(Val: Base.getNode())) { |
372 | LowAddr = DAG.getGlobalAddress(GV: GASD->getGlobal(), DL, VT: Base.getValueType(), |
373 | offset: LowOffset); |
374 | HighAddr = DAG.getGlobalAddress(GV: GASD->getGlobal(), DL, VT: Base.getValueType(), |
375 | offset: HighOffset); |
376 | } else { |
377 | LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, |
378 | DAG.getConstant(LowOffset, DL, MVT::i32)); |
379 | HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, |
380 | DAG.getConstant(HighOffset, DL, MVT::i32)); |
381 | } |
382 | SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32); |
383 | SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32); |
384 | |
385 | SDValue Low = DAG.getLoad(VT: PtrVT, dl: DL, Chain, Ptr: LowAddr, PtrInfo: MachinePointerInfo()); |
386 | SDValue High = DAG.getLoad(VT: PtrVT, dl: DL, Chain, Ptr: HighAddr, PtrInfo: MachinePointerInfo()); |
387 | SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); |
388 | SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); |
389 | SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); |
390 | Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), |
391 | High.getValue(1)); |
392 | SDValue Ops[] = { Result, Chain }; |
393 | return DAG.getMergeValues(Ops, dl: DL); |
394 | } |
395 | |
396 | static bool isWordAligned(SDValue Value, SelectionDAG &DAG) |
397 | { |
398 | KnownBits Known = DAG.computeKnownBits(Op: Value); |
399 | return Known.countMinTrailingZeros() >= 2; |
400 | } |
401 | |
402 | SDValue XCoreTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { |
403 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
404 | LLVMContext &Context = *DAG.getContext(); |
405 | LoadSDNode *LD = cast<LoadSDNode>(Val&: Op); |
406 | assert(LD->getExtensionType() == ISD::NON_EXTLOAD && |
407 | "Unexpected extension type" ); |
408 | assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT" ); |
409 | |
410 | if (allowsMemoryAccessForAlignment(Context, DL: DAG.getDataLayout(), |
411 | VT: LD->getMemoryVT(), MMO: *LD->getMemOperand())) |
412 | return SDValue(); |
413 | |
414 | SDValue Chain = LD->getChain(); |
415 | SDValue BasePtr = LD->getBasePtr(); |
416 | SDLoc DL(Op); |
417 | |
418 | if (!LD->isVolatile()) { |
419 | const GlobalValue *GV; |
420 | int64_t Offset = 0; |
421 | if (DAG.isBaseWithConstantOffset(Op: BasePtr) && |
422 | isWordAligned(Value: BasePtr->getOperand(Num: 0), DAG)) { |
423 | SDValue NewBasePtr = BasePtr->getOperand(Num: 0); |
424 | Offset = cast<ConstantSDNode>(Val: BasePtr->getOperand(Num: 1))->getSExtValue(); |
425 | return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, Base: NewBasePtr, |
426 | Offset, DAG); |
427 | } |
428 | if (TLI.isGAPlusOffset(N: BasePtr.getNode(), GA&: GV, Offset) && |
429 | GV->getPointerAlignment(DL: DAG.getDataLayout()) >= 4) { |
430 | SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL, |
431 | VT: BasePtr->getValueType(ResNo: 0)); |
432 | return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, Base: NewBasePtr, |
433 | Offset, DAG); |
434 | } |
435 | } |
436 | |
437 | if (LD->getAlign() == Align(2)) { |
438 | SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr, |
439 | LD->getPointerInfo(), MVT::i16, Align(2), |
440 | LD->getMemOperand()->getFlags()); |
441 | SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, |
442 | DAG.getConstant(2, DL, MVT::i32)); |
443 | SDValue High = |
444 | DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr, |
445 | LD->getPointerInfo().getWithOffset(2), MVT::i16, |
446 | Align(2), LD->getMemOperand()->getFlags()); |
447 | SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, |
448 | DAG.getConstant(16, DL, MVT::i32)); |
449 | SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); |
450 | Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), |
451 | High.getValue(1)); |
452 | SDValue Ops[] = { Result, Chain }; |
453 | return DAG.getMergeValues(Ops, dl: DL); |
454 | } |
455 | |
456 | // Lower to a call to __misaligned_load(BasePtr). |
457 | Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(C&: Context); |
458 | TargetLowering::ArgListTy Args; |
459 | TargetLowering::ArgListEntry Entry; |
460 | |
461 | Entry.Ty = IntPtrTy; |
462 | Entry.Node = BasePtr; |
463 | Args.push_back(x: Entry); |
464 | |
465 | TargetLowering::CallLoweringInfo CLI(DAG); |
466 | CLI.setDebugLoc(DL).setChain(Chain).setLibCallee( |
467 | CC: CallingConv::C, ResultType: IntPtrTy, |
468 | Target: DAG.getExternalSymbol(Sym: "__misaligned_load" , |
469 | VT: getPointerTy(DL: DAG.getDataLayout())), |
470 | ArgsList: std::move(Args)); |
471 | |
472 | std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); |
473 | SDValue Ops[] = { CallResult.first, CallResult.second }; |
474 | return DAG.getMergeValues(Ops, dl: DL); |
475 | } |
476 | |
477 | SDValue XCoreTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { |
478 | LLVMContext &Context = *DAG.getContext(); |
479 | StoreSDNode *ST = cast<StoreSDNode>(Val&: Op); |
480 | assert(!ST->isTruncatingStore() && "Unexpected store type" ); |
481 | assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT" ); |
482 | |
483 | if (allowsMemoryAccessForAlignment(Context, DL: DAG.getDataLayout(), |
484 | VT: ST->getMemoryVT(), MMO: *ST->getMemOperand())) |
485 | return SDValue(); |
486 | |
487 | SDValue Chain = ST->getChain(); |
488 | SDValue BasePtr = ST->getBasePtr(); |
489 | SDValue Value = ST->getValue(); |
490 | SDLoc dl(Op); |
491 | |
492 | if (ST->getAlign() == Align(2)) { |
493 | SDValue Low = Value; |
494 | SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, |
495 | DAG.getConstant(16, dl, MVT::i32)); |
496 | SDValue StoreLow = |
497 | DAG.getTruncStore(Chain, dl, Low, BasePtr, ST->getPointerInfo(), |
498 | MVT::i16, Align(2), ST->getMemOperand()->getFlags()); |
499 | SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, |
500 | DAG.getConstant(2, dl, MVT::i32)); |
501 | SDValue StoreHigh = DAG.getTruncStore( |
502 | Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2), |
503 | MVT::i16, Align(2), ST->getMemOperand()->getFlags()); |
504 | return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); |
505 | } |
506 | |
507 | // Lower to a call to __misaligned_store(BasePtr, Value). |
508 | Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(C&: Context); |
509 | TargetLowering::ArgListTy Args; |
510 | TargetLowering::ArgListEntry Entry; |
511 | |
512 | Entry.Ty = IntPtrTy; |
513 | Entry.Node = BasePtr; |
514 | Args.push_back(x: Entry); |
515 | |
516 | Entry.Node = Value; |
517 | Args.push_back(x: Entry); |
518 | |
519 | TargetLowering::CallLoweringInfo CLI(DAG); |
520 | CLI.setDebugLoc(dl).setChain(Chain).setCallee( |
521 | CC: CallingConv::C, ResultType: Type::getVoidTy(C&: Context), |
522 | Target: DAG.getExternalSymbol(Sym: "__misaligned_store" , |
523 | VT: getPointerTy(DL: DAG.getDataLayout())), |
524 | ArgsList: std::move(Args)); |
525 | |
526 | std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); |
527 | return CallResult.second; |
528 | } |
529 | |
530 | SDValue XCoreTargetLowering:: |
531 | LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const |
532 | { |
533 | assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI && |
534 | "Unexpected operand to lower!" ); |
535 | SDLoc dl(Op); |
536 | SDValue LHS = Op.getOperand(i: 0); |
537 | SDValue RHS = Op.getOperand(i: 1); |
538 | SDValue Zero = DAG.getConstant(0, dl, MVT::i32); |
539 | SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, |
540 | DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, |
541 | LHS, RHS); |
542 | SDValue Lo(Hi.getNode(), 1); |
543 | SDValue Ops[] = { Lo, Hi }; |
544 | return DAG.getMergeValues(Ops, dl); |
545 | } |
546 | |
547 | SDValue XCoreTargetLowering:: |
548 | LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const |
549 | { |
550 | assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI && |
551 | "Unexpected operand to lower!" ); |
552 | SDLoc dl(Op); |
553 | SDValue LHS = Op.getOperand(i: 0); |
554 | SDValue RHS = Op.getOperand(i: 1); |
555 | SDValue Zero = DAG.getConstant(0, dl, MVT::i32); |
556 | SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, |
557 | DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, |
558 | Zero, Zero); |
559 | SDValue Lo(Hi.getNode(), 1); |
560 | SDValue Ops[] = { Lo, Hi }; |
561 | return DAG.getMergeValues(Ops, dl); |
562 | } |
563 | |
564 | /// isADDADDMUL - Return whether Op is in a form that is equivalent to |
565 | /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then |
566 | /// each intermediate result in the calculation must also have a single use. |
567 | /// If the Op is in the correct form the constituent parts are written to Mul0, |
568 | /// Mul1, Addend0 and Addend1. |
569 | static bool |
570 | isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, |
571 | SDValue &Addend1, bool requireIntermediatesHaveOneUse) |
572 | { |
573 | if (Op.getOpcode() != ISD::ADD) |
574 | return false; |
575 | SDValue N0 = Op.getOperand(i: 0); |
576 | SDValue N1 = Op.getOperand(i: 1); |
577 | SDValue AddOp; |
578 | SDValue OtherOp; |
579 | if (N0.getOpcode() == ISD::ADD) { |
580 | AddOp = N0; |
581 | OtherOp = N1; |
582 | } else if (N1.getOpcode() == ISD::ADD) { |
583 | AddOp = N1; |
584 | OtherOp = N0; |
585 | } else { |
586 | return false; |
587 | } |
588 | if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse()) |
589 | return false; |
590 | if (OtherOp.getOpcode() == ISD::MUL) { |
591 | // add(add(a,b),mul(x,y)) |
592 | if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse()) |
593 | return false; |
594 | Mul0 = OtherOp.getOperand(i: 0); |
595 | Mul1 = OtherOp.getOperand(i: 1); |
596 | Addend0 = AddOp.getOperand(i: 0); |
597 | Addend1 = AddOp.getOperand(i: 1); |
598 | return true; |
599 | } |
600 | if (AddOp.getOperand(i: 0).getOpcode() == ISD::MUL) { |
601 | // add(add(mul(x,y),a),b) |
602 | if (requireIntermediatesHaveOneUse && !AddOp.getOperand(i: 0).hasOneUse()) |
603 | return false; |
604 | Mul0 = AddOp.getOperand(i: 0).getOperand(i: 0); |
605 | Mul1 = AddOp.getOperand(i: 0).getOperand(i: 1); |
606 | Addend0 = AddOp.getOperand(i: 1); |
607 | Addend1 = OtherOp; |
608 | return true; |
609 | } |
610 | if (AddOp.getOperand(i: 1).getOpcode() == ISD::MUL) { |
611 | // add(add(a,mul(x,y)),b) |
612 | if (requireIntermediatesHaveOneUse && !AddOp.getOperand(i: 1).hasOneUse()) |
613 | return false; |
614 | Mul0 = AddOp.getOperand(i: 1).getOperand(i: 0); |
615 | Mul1 = AddOp.getOperand(i: 1).getOperand(i: 1); |
616 | Addend0 = AddOp.getOperand(i: 0); |
617 | Addend1 = OtherOp; |
618 | return true; |
619 | } |
620 | return false; |
621 | } |
622 | |
623 | SDValue XCoreTargetLowering:: |
624 | TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const |
625 | { |
626 | SDValue Mul; |
627 | SDValue Other; |
628 | if (N->getOperand(Num: 0).getOpcode() == ISD::MUL) { |
629 | Mul = N->getOperand(Num: 0); |
630 | Other = N->getOperand(Num: 1); |
631 | } else if (N->getOperand(Num: 1).getOpcode() == ISD::MUL) { |
632 | Mul = N->getOperand(Num: 1); |
633 | Other = N->getOperand(Num: 0); |
634 | } else { |
635 | return SDValue(); |
636 | } |
637 | SDLoc dl(N); |
638 | SDValue LL, RL, AddendL, AddendH; |
639 | LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
640 | Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32)); |
641 | RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
642 | Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32)); |
643 | AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
644 | Other, DAG.getConstant(0, dl, MVT::i32)); |
645 | AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
646 | Other, DAG.getConstant(1, dl, MVT::i32)); |
647 | APInt HighMask = APInt::getHighBitsSet(numBits: 64, hiBitsSet: 32); |
648 | unsigned LHSSB = DAG.ComputeNumSignBits(Op: Mul.getOperand(i: 0)); |
649 | unsigned RHSSB = DAG.ComputeNumSignBits(Op: Mul.getOperand(i: 1)); |
650 | if (DAG.MaskedValueIsZero(Op: Mul.getOperand(i: 0), Mask: HighMask) && |
651 | DAG.MaskedValueIsZero(Op: Mul.getOperand(i: 1), Mask: HighMask)) { |
652 | // The inputs are both zero-extended. |
653 | SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, |
654 | DAG.getVTList(MVT::i32, MVT::i32), AddendH, |
655 | AddendL, LL, RL); |
656 | SDValue Lo(Hi.getNode(), 1); |
657 | return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); |
658 | } |
659 | if (LHSSB > 32 && RHSSB > 32) { |
660 | // The inputs are both sign-extended. |
661 | SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, |
662 | DAG.getVTList(MVT::i32, MVT::i32), AddendH, |
663 | AddendL, LL, RL); |
664 | SDValue Lo(Hi.getNode(), 1); |
665 | return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); |
666 | } |
667 | SDValue LH, RH; |
668 | LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
669 | Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32)); |
670 | RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
671 | Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32)); |
672 | SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, |
673 | DAG.getVTList(MVT::i32, MVT::i32), AddendH, |
674 | AddendL, LL, RL); |
675 | SDValue Lo(Hi.getNode(), 1); |
676 | RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); |
677 | LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); |
678 | Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); |
679 | Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); |
680 | return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); |
681 | } |
682 | |
683 | SDValue XCoreTargetLowering:: |
684 | ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const |
685 | { |
686 | assert(N->getValueType(0) == MVT::i64 && |
687 | (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && |
688 | "Unknown operand to lower!" ); |
689 | |
690 | if (N->getOpcode() == ISD::ADD) |
691 | if (SDValue Result = TryExpandADDWithMul(N, DAG)) |
692 | return Result; |
693 | |
694 | SDLoc dl(N); |
695 | |
696 | // Extract components |
697 | SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
698 | N->getOperand(0), |
699 | DAG.getConstant(0, dl, MVT::i32)); |
700 | SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
701 | N->getOperand(0), |
702 | DAG.getConstant(1, dl, MVT::i32)); |
703 | SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
704 | N->getOperand(1), |
705 | DAG.getConstant(0, dl, MVT::i32)); |
706 | SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
707 | N->getOperand(1), |
708 | DAG.getConstant(1, dl, MVT::i32)); |
709 | |
710 | // Expand |
711 | unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : |
712 | XCoreISD::LSUB; |
713 | SDValue Zero = DAG.getConstant(0, dl, MVT::i32); |
714 | SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), |
715 | LHSL, RHSL, Zero); |
716 | SDValue Carry(Lo.getNode(), 1); |
717 | |
718 | SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), |
719 | LHSH, RHSH, Carry); |
720 | SDValue Ignored(Hi.getNode(), 1); |
721 | // Merge the pieces |
722 | return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); |
723 | } |
724 | |
725 | SDValue XCoreTargetLowering:: |
726 | LowerVAARG(SDValue Op, SelectionDAG &DAG) const |
727 | { |
728 | // Whist llvm does not support aggregate varargs we can ignore |
729 | // the possibility of the ValueType being an implicit byVal vararg. |
730 | SDNode *Node = Op.getNode(); |
731 | EVT VT = Node->getValueType(ResNo: 0); // not an aggregate |
732 | SDValue InChain = Node->getOperand(Num: 0); |
733 | SDValue VAListPtr = Node->getOperand(Num: 1); |
734 | EVT PtrVT = VAListPtr.getValueType(); |
735 | const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue(); |
736 | SDLoc dl(Node); |
737 | SDValue VAList = |
738 | DAG.getLoad(VT: PtrVT, dl, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV)); |
739 | // Increment the pointer, VAList, to the next vararg |
740 | SDValue nextPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: PtrVT, N1: VAList, |
741 | N2: DAG.getIntPtrConstant(Val: VT.getSizeInBits() / 8, |
742 | DL: dl)); |
743 | // Store the incremented VAList to the legalized pointer |
744 | InChain = DAG.getStore(Chain: VAList.getValue(R: 1), dl, Val: nextPtr, Ptr: VAListPtr, |
745 | PtrInfo: MachinePointerInfo(SV)); |
746 | // Load the actual argument out of the pointer VAList |
747 | return DAG.getLoad(VT, dl, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo()); |
748 | } |
749 | |
750 | SDValue XCoreTargetLowering:: |
751 | LowerVASTART(SDValue Op, SelectionDAG &DAG) const |
752 | { |
753 | SDLoc dl(Op); |
754 | // vastart stores the address of the VarArgsFrameIndex slot into the |
755 | // memory location argument |
756 | MachineFunction &MF = DAG.getMachineFunction(); |
757 | XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); |
758 | SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); |
759 | return DAG.getStore(Chain: Op.getOperand(i: 0), dl, Val: Addr, Ptr: Op.getOperand(i: 1), |
760 | PtrInfo: MachinePointerInfo()); |
761 | } |
762 | |
763 | SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, |
764 | SelectionDAG &DAG) const { |
765 | // This nodes represent llvm.frameaddress on the DAG. |
766 | // It takes one operand, the index of the frame address to return. |
767 | // An index of zero corresponds to the current function's frame address. |
768 | // An index of one to the parent's frame address, and so on. |
769 | // Depths > 0 not supported yet! |
770 | if (Op.getConstantOperandVal(i: 0) > 0) |
771 | return SDValue(); |
772 | |
773 | MachineFunction &MF = DAG.getMachineFunction(); |
774 | const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); |
775 | return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), |
776 | RegInfo->getFrameRegister(MF), MVT::i32); |
777 | } |
778 | |
779 | SDValue XCoreTargetLowering:: |
780 | LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { |
781 | // This nodes represent llvm.returnaddress on the DAG. |
782 | // It takes one operand, the index of the return address to return. |
783 | // An index of zero corresponds to the current function's return address. |
784 | // An index of one to the parent's return address, and so on. |
785 | // Depths > 0 not supported yet! |
786 | if (Op.getConstantOperandVal(i: 0) > 0) |
787 | return SDValue(); |
788 | |
789 | MachineFunction &MF = DAG.getMachineFunction(); |
790 | XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); |
791 | int FI = XFI->createLRSpillSlot(MF); |
792 | SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); |
793 | return DAG.getLoad(VT: getPointerTy(DL: DAG.getDataLayout()), dl: SDLoc(Op), |
794 | Chain: DAG.getEntryNode(), Ptr: FIN, |
795 | PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)); |
796 | } |
797 | |
798 | SDValue XCoreTargetLowering:: |
799 | LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const { |
800 | // This node represents offset from frame pointer to first on-stack argument. |
801 | // This is needed for correct stack adjustment during unwind. |
802 | // However, we don't know the offset until after the frame has be finalised. |
803 | // This is done during the XCoreFTAOElim pass. |
804 | return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32); |
805 | } |
806 | |
807 | SDValue XCoreTargetLowering:: |
808 | LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { |
809 | // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) |
810 | // This node represents 'eh_return' gcc dwarf builtin, which is used to |
811 | // return from exception. The general meaning is: adjust stack by OFFSET and |
812 | // pass execution to HANDLER. |
813 | MachineFunction &MF = DAG.getMachineFunction(); |
814 | SDValue Chain = Op.getOperand(i: 0); |
815 | SDValue Offset = Op.getOperand(i: 1); |
816 | SDValue Handler = Op.getOperand(i: 2); |
817 | SDLoc dl(Op); |
818 | |
819 | // Absolute SP = (FP + FrameToArgs) + Offset |
820 | const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); |
821 | SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl, |
822 | RegInfo->getFrameRegister(MF), MVT::i32); |
823 | SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl, |
824 | MVT::i32); |
825 | Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs); |
826 | Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset); |
827 | |
828 | // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister |
829 | // which leaves 2 caller saved registers, R2 & R3 for us to use. |
830 | unsigned StackReg = XCore::R2; |
831 | unsigned HandlerReg = XCore::R3; |
832 | |
833 | SDValue OutChains[] = { |
834 | DAG.getCopyToReg(Chain, dl, Reg: StackReg, N: Stack), |
835 | DAG.getCopyToReg(Chain, dl, Reg: HandlerReg, N: Handler) |
836 | }; |
837 | |
838 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); |
839 | |
840 | return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain, |
841 | DAG.getRegister(StackReg, MVT::i32), |
842 | DAG.getRegister(HandlerReg, MVT::i32)); |
843 | |
844 | } |
845 | |
846 | SDValue XCoreTargetLowering:: |
847 | LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { |
848 | return Op.getOperand(i: 0); |
849 | } |
850 | |
851 | SDValue XCoreTargetLowering:: |
852 | LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { |
853 | SDValue Chain = Op.getOperand(i: 0); |
854 | SDValue Trmp = Op.getOperand(i: 1); // trampoline |
855 | SDValue FPtr = Op.getOperand(i: 2); // nested function |
856 | SDValue Nest = Op.getOperand(i: 3); // 'nest' parameter value |
857 | |
858 | const Value *TrmpAddr = cast<SrcValueSDNode>(Val: Op.getOperand(i: 4))->getValue(); |
859 | |
860 | // .align 4 |
861 | // LDAPF_u10 r11, nest |
862 | // LDW_2rus r11, r11[0] |
863 | // STWSP_ru6 r11, sp[0] |
864 | // LDAPF_u10 r11, fptr |
865 | // LDW_2rus r11, r11[0] |
866 | // BAU_1r r11 |
867 | // nest: |
868 | // .word nest |
869 | // fptr: |
870 | // .word fptr |
871 | SDValue OutChains[5]; |
872 | |
873 | SDValue Addr = Trmp; |
874 | |
875 | SDLoc dl(Op); |
876 | OutChains[0] = |
877 | DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr, |
878 | MachinePointerInfo(TrmpAddr)); |
879 | |
880 | Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, |
881 | DAG.getConstant(4, dl, MVT::i32)); |
882 | OutChains[1] = |
883 | DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr, |
884 | MachinePointerInfo(TrmpAddr, 4)); |
885 | |
886 | Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, |
887 | DAG.getConstant(8, dl, MVT::i32)); |
888 | OutChains[2] = |
889 | DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr, |
890 | MachinePointerInfo(TrmpAddr, 8)); |
891 | |
892 | Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, |
893 | DAG.getConstant(12, dl, MVT::i32)); |
894 | OutChains[3] = |
895 | DAG.getStore(Chain, dl, Val: Nest, Ptr: Addr, PtrInfo: MachinePointerInfo(TrmpAddr, 12)); |
896 | |
897 | Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, |
898 | DAG.getConstant(16, dl, MVT::i32)); |
899 | OutChains[4] = |
900 | DAG.getStore(Chain, dl, Val: FPtr, Ptr: Addr, PtrInfo: MachinePointerInfo(TrmpAddr, 16)); |
901 | |
902 | return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); |
903 | } |
904 | |
905 | SDValue XCoreTargetLowering:: |
906 | LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { |
907 | SDLoc DL(Op); |
908 | unsigned IntNo = Op.getConstantOperandVal(i: 0); |
909 | switch (IntNo) { |
910 | case Intrinsic::xcore_crc8: |
911 | EVT VT = Op.getValueType(); |
912 | SDValue Data = |
913 | DAG.getNode(Opcode: XCoreISD::CRC8, DL, VTList: DAG.getVTList(VT1: VT, VT2: VT), |
914 | N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2) , N3: Op.getOperand(i: 3)); |
915 | SDValue Crc(Data.getNode(), 1); |
916 | SDValue Results[] = { Crc, Data }; |
917 | return DAG.getMergeValues(Ops: Results, dl: DL); |
918 | } |
919 | return SDValue(); |
920 | } |
921 | |
922 | SDValue XCoreTargetLowering:: |
923 | LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { |
924 | SDLoc DL(Op); |
925 | return DAG.getNode(ISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0)); |
926 | } |
927 | |
928 | //===----------------------------------------------------------------------===// |
929 | // Calling Convention Implementation |
930 | //===----------------------------------------------------------------------===// |
931 | |
932 | #include "XCoreGenCallingConv.inc" |
933 | |
934 | //===----------------------------------------------------------------------===// |
935 | // Call Calling Convention Implementation |
936 | //===----------------------------------------------------------------------===// |
937 | |
938 | /// XCore call implementation |
939 | SDValue |
940 | XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, |
941 | SmallVectorImpl<SDValue> &InVals) const { |
942 | SelectionDAG &DAG = CLI.DAG; |
943 | SDLoc &dl = CLI.DL; |
944 | SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; |
945 | SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; |
946 | SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; |
947 | SDValue Chain = CLI.Chain; |
948 | SDValue Callee = CLI.Callee; |
949 | bool &isTailCall = CLI.IsTailCall; |
950 | CallingConv::ID CallConv = CLI.CallConv; |
951 | bool isVarArg = CLI.IsVarArg; |
952 | |
953 | // XCore target does not yet support tail call optimization. |
954 | isTailCall = false; |
955 | |
956 | // For now, only CallingConv::C implemented |
957 | switch (CallConv) |
958 | { |
959 | default: |
960 | report_fatal_error(reason: "Unsupported calling convention" ); |
961 | case CallingConv::Fast: |
962 | case CallingConv::C: |
963 | return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, |
964 | Outs, OutVals, Ins, dl, DAG, InVals); |
965 | } |
966 | } |
967 | |
968 | /// LowerCallResult - Lower the result values of a call into the |
969 | /// appropriate copies out of appropriate physical registers / memory locations. |
970 | static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, |
971 | const SmallVectorImpl<CCValAssign> &RVLocs, |
972 | const SDLoc &dl, SelectionDAG &DAG, |
973 | SmallVectorImpl<SDValue> &InVals) { |
974 | SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs; |
975 | // Copy results out of physical registers. |
976 | for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { |
977 | const CCValAssign &VA = RVLocs[i]; |
978 | if (VA.isRegLoc()) { |
979 | Chain = DAG.getCopyFromReg(Chain, dl, Reg: VA.getLocReg(), VT: VA.getValVT(), |
980 | Glue: InGlue).getValue(R: 1); |
981 | InGlue = Chain.getValue(R: 2); |
982 | InVals.push_back(Elt: Chain.getValue(R: 0)); |
983 | } else { |
984 | assert(VA.isMemLoc()); |
985 | ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(), |
986 | InVals.size())); |
987 | // Reserve space for this result. |
988 | InVals.push_back(Elt: SDValue()); |
989 | } |
990 | } |
991 | |
992 | // Copy results out of memory. |
993 | SmallVector<SDValue, 4> MemOpChains; |
994 | for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) { |
995 | int offset = ResultMemLocs[i].first; |
996 | unsigned index = ResultMemLocs[i].second; |
997 | SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); |
998 | SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) }; |
999 | SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops); |
1000 | InVals[index] = load; |
1001 | MemOpChains.push_back(Elt: load.getValue(R: 1)); |
1002 | } |
1003 | |
1004 | // Transform all loads nodes into one single node because |
1005 | // all load nodes are independent of each other. |
1006 | if (!MemOpChains.empty()) |
1007 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); |
1008 | |
1009 | return Chain; |
1010 | } |
1011 | |
1012 | /// LowerCCCCallTo - functions arguments are copied from virtual |
1013 | /// regs to (physical regs)/(stack frame), CALLSEQ_START and |
1014 | /// CALLSEQ_END are emitted. |
1015 | /// TODO: isTailCall, sret. |
1016 | SDValue XCoreTargetLowering::LowerCCCCallTo( |
1017 | SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, |
1018 | bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, |
1019 | const SmallVectorImpl<SDValue> &OutVals, |
1020 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, |
1021 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { |
1022 | |
1023 | // Analyze operands of the call, assigning locations to each operand. |
1024 | SmallVector<CCValAssign, 16> ArgLocs; |
1025 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, |
1026 | *DAG.getContext()); |
1027 | |
1028 | // The ABI dictates there should be one stack slot available to the callee |
1029 | // on function entry (for saving lr). |
1030 | CCInfo.AllocateStack(Size: 4, Alignment: Align(4)); |
1031 | |
1032 | CCInfo.AnalyzeCallOperands(Outs, CC_XCore); |
1033 | |
1034 | SmallVector<CCValAssign, 16> RVLocs; |
1035 | // Analyze return values to determine the number of bytes of stack required. |
1036 | CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, |
1037 | *DAG.getContext()); |
1038 | RetCCInfo.AllocateStack(Size: CCInfo.getStackSize(), Alignment: Align(4)); |
1039 | RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore); |
1040 | |
1041 | // Get a count of how many bytes are to be pushed on the stack. |
1042 | unsigned NumBytes = RetCCInfo.getStackSize(); |
1043 | |
1044 | Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytes, OutSize: 0, DL: dl); |
1045 | |
1046 | SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; |
1047 | SmallVector<SDValue, 12> MemOpChains; |
1048 | |
1049 | // Walk the register/memloc assignments, inserting copies/loads. |
1050 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { |
1051 | CCValAssign &VA = ArgLocs[i]; |
1052 | SDValue Arg = OutVals[i]; |
1053 | |
1054 | // Promote the value if needed. |
1055 | switch (VA.getLocInfo()) { |
1056 | default: llvm_unreachable("Unknown loc info!" ); |
1057 | case CCValAssign::Full: break; |
1058 | case CCValAssign::SExt: |
1059 | Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg); |
1060 | break; |
1061 | case CCValAssign::ZExt: |
1062 | Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg); |
1063 | break; |
1064 | case CCValAssign::AExt: |
1065 | Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg); |
1066 | break; |
1067 | } |
1068 | |
1069 | // Arguments that can be passed on register must be kept at |
1070 | // RegsToPass vector |
1071 | if (VA.isRegLoc()) { |
1072 | RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg)); |
1073 | } else { |
1074 | assert(VA.isMemLoc()); |
1075 | |
1076 | int Offset = VA.getLocMemOffset(); |
1077 | |
1078 | MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, |
1079 | Chain, Arg, |
1080 | DAG.getConstant(Offset/4, dl, |
1081 | MVT::i32))); |
1082 | } |
1083 | } |
1084 | |
1085 | // Transform all store nodes into one single node because |
1086 | // all store nodes are independent of each other. |
1087 | if (!MemOpChains.empty()) |
1088 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); |
1089 | |
1090 | // Build a sequence of copy-to-reg nodes chained together with token |
1091 | // chain and flag operands which copy the outgoing args into registers. |
1092 | // The InGlue in necessary since all emitted instructions must be |
1093 | // stuck together. |
1094 | SDValue InGlue; |
1095 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { |
1096 | Chain = DAG.getCopyToReg(Chain, dl, Reg: RegsToPass[i].first, |
1097 | N: RegsToPass[i].second, Glue: InGlue); |
1098 | InGlue = Chain.getValue(R: 1); |
1099 | } |
1100 | |
1101 | // If the callee is a GlobalAddress node (quite common, every direct call is) |
1102 | // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. |
1103 | // Likewise ExternalSymbol -> TargetExternalSymbol. |
1104 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) |
1105 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); |
1106 | else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) |
1107 | Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); |
1108 | |
1109 | // XCoreBranchLink = #chain, #target_address, #opt_in_flags... |
1110 | // = Chain, Callee, Reg#1, Reg#2, ... |
1111 | // |
1112 | // Returns a chain & a flag for retval copy to use. |
1113 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
1114 | SmallVector<SDValue, 8> Ops; |
1115 | Ops.push_back(Elt: Chain); |
1116 | Ops.push_back(Elt: Callee); |
1117 | |
1118 | // Add argument registers to the end of the list so that they are |
1119 | // known live into the call. |
1120 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) |
1121 | Ops.push_back(Elt: DAG.getRegister(Reg: RegsToPass[i].first, |
1122 | VT: RegsToPass[i].second.getValueType())); |
1123 | |
1124 | if (InGlue.getNode()) |
1125 | Ops.push_back(Elt: InGlue); |
1126 | |
1127 | Chain = DAG.getNode(Opcode: XCoreISD::BL, DL: dl, VTList: NodeTys, Ops); |
1128 | InGlue = Chain.getValue(R: 1); |
1129 | |
1130 | // Create the CALLSEQ_END node. |
1131 | Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytes, Size2: 0, Glue: InGlue, DL: dl); |
1132 | InGlue = Chain.getValue(R: 1); |
1133 | |
1134 | // Handle result values, copying them out of physregs into vregs that we |
1135 | // return. |
1136 | return LowerCallResult(Chain, InGlue, RVLocs, dl, DAG, InVals); |
1137 | } |
1138 | |
1139 | //===----------------------------------------------------------------------===// |
1140 | // Formal Arguments Calling Convention Implementation |
1141 | //===----------------------------------------------------------------------===// |
1142 | |
1143 | namespace { |
1144 | struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; }; |
1145 | } |
1146 | |
1147 | /// XCore formal arguments implementation |
1148 | SDValue XCoreTargetLowering::LowerFormalArguments( |
1149 | SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
1150 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, |
1151 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { |
1152 | switch (CallConv) |
1153 | { |
1154 | default: |
1155 | report_fatal_error(reason: "Unsupported calling convention" ); |
1156 | case CallingConv::C: |
1157 | case CallingConv::Fast: |
1158 | return LowerCCCArguments(Chain, CallConv, isVarArg, |
1159 | Ins, dl, DAG, InVals); |
1160 | } |
1161 | } |
1162 | |
1163 | /// LowerCCCArguments - transform physical registers into |
1164 | /// virtual registers and generate load operations for |
1165 | /// arguments places on the stack. |
1166 | /// TODO: sret |
1167 | SDValue XCoreTargetLowering::LowerCCCArguments( |
1168 | SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
1169 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, |
1170 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { |
1171 | MachineFunction &MF = DAG.getMachineFunction(); |
1172 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
1173 | MachineRegisterInfo &RegInfo = MF.getRegInfo(); |
1174 | XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); |
1175 | |
1176 | // Assign locations to all of the incoming arguments. |
1177 | SmallVector<CCValAssign, 16> ArgLocs; |
1178 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, |
1179 | *DAG.getContext()); |
1180 | |
1181 | CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); |
1182 | |
1183 | unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize(); |
1184 | |
1185 | unsigned LRSaveSize = StackSlotSize; |
1186 | |
1187 | if (!isVarArg) |
1188 | XFI->setReturnStackOffset(CCInfo.getStackSize() + LRSaveSize); |
1189 | |
1190 | // All getCopyFromReg ops must precede any getMemcpys to prevent the |
1191 | // scheduler clobbering a register before it has been copied. |
1192 | // The stages are: |
1193 | // 1. CopyFromReg (and load) arg & vararg registers. |
1194 | // 2. Chain CopyFromReg nodes into a TokenFactor. |
1195 | // 3. Memcpy 'byVal' args & push final InVals. |
1196 | // 4. Chain mem ops nodes into a TokenFactor. |
1197 | SmallVector<SDValue, 4> CFRegNode; |
1198 | SmallVector<ArgDataPair, 4> ArgData; |
1199 | SmallVector<SDValue, 4> MemOps; |
1200 | |
1201 | // 1a. CopyFromReg (and load) arg registers. |
1202 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { |
1203 | |
1204 | CCValAssign &VA = ArgLocs[i]; |
1205 | SDValue ArgIn; |
1206 | |
1207 | if (VA.isRegLoc()) { |
1208 | // Arguments passed in registers |
1209 | EVT RegVT = VA.getLocVT(); |
1210 | switch (RegVT.getSimpleVT().SimpleTy) { |
1211 | default: |
1212 | { |
1213 | #ifndef NDEBUG |
1214 | errs() << "LowerFormalArguments Unhandled argument type: " |
1215 | << RegVT << "\n" ; |
1216 | #endif |
1217 | llvm_unreachable(nullptr); |
1218 | } |
1219 | case MVT::i32: |
1220 | Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); |
1221 | RegInfo.addLiveIn(Reg: VA.getLocReg(), vreg: VReg); |
1222 | ArgIn = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: RegVT); |
1223 | CFRegNode.push_back(Elt: ArgIn.getValue(R: ArgIn->getNumValues() - 1)); |
1224 | } |
1225 | } else { |
1226 | // Only arguments passed on the stack should make it here. |
1227 | assert(VA.isMemLoc()); |
1228 | // Load the argument to a virtual register |
1229 | unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; |
1230 | if (ObjSize > StackSlotSize) { |
1231 | errs() << "LowerFormalArguments Unhandled argument type: " |
1232 | << VA.getLocVT() << "\n" ; |
1233 | } |
1234 | // Create the frame index object for this incoming parameter... |
1235 | int FI = MFI.CreateFixedObject(Size: ObjSize, |
1236 | SPOffset: LRSaveSize + VA.getLocMemOffset(), |
1237 | IsImmutable: true); |
1238 | |
1239 | // Create the SelectionDAG nodes corresponding to a load |
1240 | //from this parameter |
1241 | SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); |
1242 | ArgIn = DAG.getLoad(VT: VA.getLocVT(), dl, Chain, Ptr: FIN, |
1243 | PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)); |
1244 | } |
1245 | const ArgDataPair ADP = { .SDV: ArgIn, .Flags: Ins[i].Flags }; |
1246 | ArgData.push_back(Elt: ADP); |
1247 | } |
1248 | |
1249 | // 1b. CopyFromReg vararg registers. |
1250 | if (isVarArg) { |
1251 | // Argument registers |
1252 | static const MCPhysReg ArgRegs[] = { |
1253 | XCore::R0, XCore::R1, XCore::R2, XCore::R3 |
1254 | }; |
1255 | XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); |
1256 | unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); |
1257 | if (FirstVAReg < std::size(ArgRegs)) { |
1258 | int offset = 0; |
1259 | // Save remaining registers, storing higher register numbers at a higher |
1260 | // address |
1261 | for (int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { |
1262 | // Create a stack slot |
1263 | int FI = MFI.CreateFixedObject(Size: 4, SPOffset: offset, IsImmutable: true); |
1264 | if (i == (int)FirstVAReg) { |
1265 | XFI->setVarArgsFrameIndex(FI); |
1266 | } |
1267 | offset -= StackSlotSize; |
1268 | SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); |
1269 | // Move argument from phys reg -> virt reg |
1270 | Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); |
1271 | RegInfo.addLiveIn(Reg: ArgRegs[i], vreg: VReg); |
1272 | SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); |
1273 | CFRegNode.push_back(Elt: Val.getValue(R: Val->getNumValues() - 1)); |
1274 | // Move argument from virt reg -> stack |
1275 | SDValue Store = |
1276 | DAG.getStore(Chain: Val.getValue(R: 1), dl, Val, Ptr: FIN, PtrInfo: MachinePointerInfo()); |
1277 | MemOps.push_back(Elt: Store); |
1278 | } |
1279 | } else { |
1280 | // This will point to the next argument passed via stack. |
1281 | XFI->setVarArgsFrameIndex( |
1282 | MFI.CreateFixedObject(Size: 4, SPOffset: LRSaveSize + CCInfo.getStackSize(), IsImmutable: true)); |
1283 | } |
1284 | } |
1285 | |
1286 | // 2. chain CopyFromReg nodes into a TokenFactor. |
1287 | if (!CFRegNode.empty()) |
1288 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode); |
1289 | |
1290 | // 3. Memcpy 'byVal' args & push final InVals. |
1291 | // Aggregates passed "byVal" need to be copied by the callee. |
1292 | // The callee will use a pointer to this copy, rather than the original |
1293 | // pointer. |
1294 | for (const ArgDataPair &ArgDI : ArgData) { |
1295 | if (ArgDI.Flags.isByVal() && ArgDI.Flags.getByValSize()) { |
1296 | unsigned Size = ArgDI.Flags.getByValSize(); |
1297 | Align Alignment = |
1298 | std::max(a: Align(StackSlotSize), b: ArgDI.Flags.getNonZeroByValAlign()); |
1299 | // Create a new object on the stack and copy the pointee into it. |
1300 | int FI = MFI.CreateStackObject(Size, Alignment, isSpillSlot: false); |
1301 | SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); |
1302 | InVals.push_back(Elt: FIN); |
1303 | MemOps.push_back(DAG.getMemcpy( |
1304 | Chain, dl, FIN, ArgDI.SDV, DAG.getConstant(Size, dl, MVT::i32), |
1305 | Alignment, false, false, false, MachinePointerInfo(), |
1306 | MachinePointerInfo())); |
1307 | } else { |
1308 | InVals.push_back(Elt: ArgDI.SDV); |
1309 | } |
1310 | } |
1311 | |
1312 | // 4, chain mem ops nodes into a TokenFactor. |
1313 | if (!MemOps.empty()) { |
1314 | MemOps.push_back(Elt: Chain); |
1315 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); |
1316 | } |
1317 | |
1318 | return Chain; |
1319 | } |
1320 | |
1321 | //===----------------------------------------------------------------------===// |
1322 | // Return Value Calling Convention Implementation |
1323 | //===----------------------------------------------------------------------===// |
1324 | |
1325 | bool XCoreTargetLowering:: |
1326 | CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, |
1327 | bool isVarArg, |
1328 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
1329 | LLVMContext &Context) const { |
1330 | SmallVector<CCValAssign, 16> RVLocs; |
1331 | CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); |
1332 | if (!CCInfo.CheckReturn(Outs, RetCC_XCore)) |
1333 | return false; |
1334 | if (CCInfo.getStackSize() != 0 && isVarArg) |
1335 | return false; |
1336 | return true; |
1337 | } |
1338 | |
1339 | SDValue |
1340 | XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, |
1341 | bool isVarArg, |
1342 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
1343 | const SmallVectorImpl<SDValue> &OutVals, |
1344 | const SDLoc &dl, SelectionDAG &DAG) const { |
1345 | |
1346 | XCoreFunctionInfo *XFI = |
1347 | DAG.getMachineFunction().getInfo<XCoreFunctionInfo>(); |
1348 | MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); |
1349 | |
1350 | // CCValAssign - represent the assignment of |
1351 | // the return value to a location |
1352 | SmallVector<CCValAssign, 16> RVLocs; |
1353 | |
1354 | // CCState - Info about the registers and stack slot. |
1355 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, |
1356 | *DAG.getContext()); |
1357 | |
1358 | // Analyze return values. |
1359 | if (!isVarArg) |
1360 | CCInfo.AllocateStack(Size: XFI->getReturnStackOffset(), Alignment: Align(4)); |
1361 | |
1362 | CCInfo.AnalyzeReturn(Outs, RetCC_XCore); |
1363 | |
1364 | SDValue Glue; |
1365 | SmallVector<SDValue, 4> RetOps(1, Chain); |
1366 | |
1367 | // Return on XCore is always a "retsp 0" |
1368 | RetOps.push_back(DAG.getConstant(0, dl, MVT::i32)); |
1369 | |
1370 | SmallVector<SDValue, 4> MemOpChains; |
1371 | // Handle return values that must be copied to memory. |
1372 | for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { |
1373 | CCValAssign &VA = RVLocs[i]; |
1374 | if (VA.isRegLoc()) |
1375 | continue; |
1376 | assert(VA.isMemLoc()); |
1377 | if (isVarArg) { |
1378 | report_fatal_error(reason: "Can't return value from vararg function in memory" ); |
1379 | } |
1380 | |
1381 | int Offset = VA.getLocMemOffset(); |
1382 | unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; |
1383 | // Create the frame index object for the memory location. |
1384 | int FI = MFI.CreateFixedObject(Size: ObjSize, SPOffset: Offset, IsImmutable: false); |
1385 | |
1386 | // Create a SelectionDAG node corresponding to a store |
1387 | // to this memory location. |
1388 | SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); |
1389 | MemOpChains.push_back(Elt: DAG.getStore( |
1390 | Chain, dl, Val: OutVals[i], Ptr: FIN, |
1391 | PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI))); |
1392 | } |
1393 | |
1394 | // Transform all store nodes into one single node because |
1395 | // all stores are independent of each other. |
1396 | if (!MemOpChains.empty()) |
1397 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); |
1398 | |
1399 | // Now handle return values copied to registers. |
1400 | for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { |
1401 | CCValAssign &VA = RVLocs[i]; |
1402 | if (!VA.isRegLoc()) |
1403 | continue; |
1404 | // Copy the result values into the output registers. |
1405 | Chain = DAG.getCopyToReg(Chain, dl, Reg: VA.getLocReg(), N: OutVals[i], Glue); |
1406 | |
1407 | // guarantee that all emitted copies are |
1408 | // stuck together, avoiding something bad |
1409 | Glue = Chain.getValue(R: 1); |
1410 | RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT())); |
1411 | } |
1412 | |
1413 | RetOps[0] = Chain; // Update chain. |
1414 | |
1415 | // Add the glue if we have it. |
1416 | if (Glue.getNode()) |
1417 | RetOps.push_back(Elt: Glue); |
1418 | |
1419 | return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps); |
1420 | } |
1421 | |
1422 | //===----------------------------------------------------------------------===// |
1423 | // Other Lowering Code |
1424 | //===----------------------------------------------------------------------===// |
1425 | |
1426 | MachineBasicBlock * |
1427 | XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, |
1428 | MachineBasicBlock *BB) const { |
1429 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1430 | DebugLoc dl = MI.getDebugLoc(); |
1431 | assert((MI.getOpcode() == XCore::SELECT_CC) && |
1432 | "Unexpected instr type to insert" ); |
1433 | |
1434 | // To "insert" a SELECT_CC instruction, we actually have to insert the diamond |
1435 | // control-flow pattern. The incoming instruction knows the destination vreg |
1436 | // to set, the condition code register to branch on, the true/false values to |
1437 | // select between, and a branch opcode to use. |
1438 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
1439 | MachineFunction::iterator It = ++BB->getIterator(); |
1440 | |
1441 | // thisMBB: |
1442 | // ... |
1443 | // TrueVal = ... |
1444 | // cmpTY ccX, r1, r2 |
1445 | // bCC copy1MBB |
1446 | // fallthrough --> copy0MBB |
1447 | MachineBasicBlock *thisMBB = BB; |
1448 | MachineFunction *F = BB->getParent(); |
1449 | MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(BB: LLVM_BB); |
1450 | MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB); |
1451 | F->insert(MBBI: It, MBB: copy0MBB); |
1452 | F->insert(MBBI: It, MBB: sinkMBB); |
1453 | |
1454 | // Transfer the remainder of BB and its successor edges to sinkMBB. |
1455 | sinkMBB->splice(Where: sinkMBB->begin(), Other: BB, |
1456 | From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end()); |
1457 | sinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB); |
1458 | |
1459 | // Next, add the true and fallthrough blocks as its successors. |
1460 | BB->addSuccessor(Succ: copy0MBB); |
1461 | BB->addSuccessor(Succ: sinkMBB); |
1462 | |
1463 | BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) |
1464 | .addReg(MI.getOperand(1).getReg()) |
1465 | .addMBB(sinkMBB); |
1466 | |
1467 | // copy0MBB: |
1468 | // %FalseValue = ... |
1469 | // # fallthrough to sinkMBB |
1470 | BB = copy0MBB; |
1471 | |
1472 | // Update machine-CFG edges |
1473 | BB->addSuccessor(Succ: sinkMBB); |
1474 | |
1475 | // sinkMBB: |
1476 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] |
1477 | // ... |
1478 | BB = sinkMBB; |
1479 | BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg()) |
1480 | .addReg(MI.getOperand(3).getReg()) |
1481 | .addMBB(copy0MBB) |
1482 | .addReg(MI.getOperand(2).getReg()) |
1483 | .addMBB(thisMBB); |
1484 | |
1485 | MI.eraseFromParent(); // The pseudo instruction is gone now. |
1486 | return BB; |
1487 | } |
1488 | |
1489 | //===----------------------------------------------------------------------===// |
1490 | // Target Optimization Hooks |
1491 | //===----------------------------------------------------------------------===// |
1492 | |
1493 | SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, |
1494 | DAGCombinerInfo &DCI) const { |
1495 | SelectionDAG &DAG = DCI.DAG; |
1496 | SDLoc dl(N); |
1497 | switch (N->getOpcode()) { |
1498 | default: break; |
1499 | case ISD::INTRINSIC_VOID: |
1500 | switch (N->getConstantOperandVal(Num: 1)) { |
1501 | case Intrinsic::xcore_outt: |
1502 | case Intrinsic::xcore_outct: |
1503 | case Intrinsic::xcore_chkct: { |
1504 | SDValue OutVal = N->getOperand(Num: 3); |
1505 | // These instructions ignore the high bits. |
1506 | if (OutVal.hasOneUse()) { |
1507 | unsigned BitWidth = OutVal.getValueSizeInBits(); |
1508 | APInt DemandedMask = APInt::getLowBitsSet(numBits: BitWidth, loBitsSet: 8); |
1509 | KnownBits Known; |
1510 | TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), |
1511 | !DCI.isBeforeLegalizeOps()); |
1512 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
1513 | if (TLI.ShrinkDemandedConstant(Op: OutVal, DemandedBits: DemandedMask, TLO) || |
1514 | TLI.SimplifyDemandedBits(Op: OutVal, DemandedBits: DemandedMask, Known, TLO)) |
1515 | DCI.CommitTargetLoweringOpt(TLO); |
1516 | } |
1517 | break; |
1518 | } |
1519 | case Intrinsic::xcore_setpt: { |
1520 | SDValue Time = N->getOperand(Num: 3); |
1521 | // This instruction ignores the high bits. |
1522 | if (Time.hasOneUse()) { |
1523 | unsigned BitWidth = Time.getValueSizeInBits(); |
1524 | APInt DemandedMask = APInt::getLowBitsSet(numBits: BitWidth, loBitsSet: 16); |
1525 | KnownBits Known; |
1526 | TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), |
1527 | !DCI.isBeforeLegalizeOps()); |
1528 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
1529 | if (TLI.ShrinkDemandedConstant(Op: Time, DemandedBits: DemandedMask, TLO) || |
1530 | TLI.SimplifyDemandedBits(Op: Time, DemandedBits: DemandedMask, Known, TLO)) |
1531 | DCI.CommitTargetLoweringOpt(TLO); |
1532 | } |
1533 | break; |
1534 | } |
1535 | } |
1536 | break; |
1537 | case XCoreISD::LADD: { |
1538 | SDValue N0 = N->getOperand(Num: 0); |
1539 | SDValue N1 = N->getOperand(Num: 1); |
1540 | SDValue N2 = N->getOperand(Num: 2); |
1541 | ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(Val&: N0); |
1542 | ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Val&: N1); |
1543 | EVT VT = N0.getValueType(); |
1544 | |
1545 | // canonicalize constant to RHS |
1546 | if (N0C && !N1C) |
1547 | return DAG.getNode(Opcode: XCoreISD::LADD, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), N1, N2: N0, N3: N2); |
1548 | |
1549 | // fold (ladd 0, 0, x) -> 0, x & 1 |
1550 | if (N0C && N0C->isZero() && N1C && N1C->isZero()) { |
1551 | SDValue Carry = DAG.getConstant(Val: 0, DL: dl, VT); |
1552 | SDValue Result = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: N2, |
1553 | N2: DAG.getConstant(Val: 1, DL: dl, VT)); |
1554 | SDValue Ops[] = { Result, Carry }; |
1555 | return DAG.getMergeValues(Ops, dl); |
1556 | } |
1557 | |
1558 | // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the |
1559 | // low bit set |
1560 | if (N1C && N1C->isZero() && N->hasNUsesOfValue(NUses: 0, Value: 1)) { |
1561 | APInt Mask = APInt::getHighBitsSet(numBits: VT.getSizeInBits(), |
1562 | hiBitsSet: VT.getSizeInBits() - 1); |
1563 | KnownBits Known = DAG.computeKnownBits(Op: N2); |
1564 | if ((Known.Zero & Mask) == Mask) { |
1565 | SDValue Carry = DAG.getConstant(Val: 0, DL: dl, VT); |
1566 | SDValue Result = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: N0, N2); |
1567 | SDValue Ops[] = { Result, Carry }; |
1568 | return DAG.getMergeValues(Ops, dl); |
1569 | } |
1570 | } |
1571 | } |
1572 | break; |
1573 | case XCoreISD::LSUB: { |
1574 | SDValue N0 = N->getOperand(Num: 0); |
1575 | SDValue N1 = N->getOperand(Num: 1); |
1576 | SDValue N2 = N->getOperand(Num: 2); |
1577 | ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(Val&: N0); |
1578 | ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Val&: N1); |
1579 | EVT VT = N0.getValueType(); |
1580 | |
1581 | // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set |
1582 | if (N0C && N0C->isZero() && N1C && N1C->isZero()) { |
1583 | APInt Mask = APInt::getHighBitsSet(numBits: VT.getSizeInBits(), |
1584 | hiBitsSet: VT.getSizeInBits() - 1); |
1585 | KnownBits Known = DAG.computeKnownBits(Op: N2); |
1586 | if ((Known.Zero & Mask) == Mask) { |
1587 | SDValue Borrow = N2; |
1588 | SDValue Result = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, |
1589 | N1: DAG.getConstant(Val: 0, DL: dl, VT), N2); |
1590 | SDValue Ops[] = { Result, Borrow }; |
1591 | return DAG.getMergeValues(Ops, dl); |
1592 | } |
1593 | } |
1594 | |
1595 | // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the |
1596 | // low bit set |
1597 | if (N1C && N1C->isZero() && N->hasNUsesOfValue(NUses: 0, Value: 1)) { |
1598 | APInt Mask = APInt::getHighBitsSet(numBits: VT.getSizeInBits(), |
1599 | hiBitsSet: VT.getSizeInBits() - 1); |
1600 | KnownBits Known = DAG.computeKnownBits(Op: N2); |
1601 | if ((Known.Zero & Mask) == Mask) { |
1602 | SDValue Borrow = DAG.getConstant(Val: 0, DL: dl, VT); |
1603 | SDValue Result = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: N0, N2); |
1604 | SDValue Ops[] = { Result, Borrow }; |
1605 | return DAG.getMergeValues(Ops, dl); |
1606 | } |
1607 | } |
1608 | } |
1609 | break; |
1610 | case XCoreISD::LMUL: { |
1611 | SDValue N0 = N->getOperand(Num: 0); |
1612 | SDValue N1 = N->getOperand(Num: 1); |
1613 | SDValue N2 = N->getOperand(Num: 2); |
1614 | SDValue N3 = N->getOperand(Num: 3); |
1615 | ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(Val&: N0); |
1616 | ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Val&: N1); |
1617 | EVT VT = N0.getValueType(); |
1618 | // Canonicalize multiplicative constant to RHS. If both multiplicative |
1619 | // operands are constant canonicalize smallest to RHS. |
1620 | if ((N0C && !N1C) || |
1621 | (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue())) |
1622 | return DAG.getNode(Opcode: XCoreISD::LMUL, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), |
1623 | N1, N2: N0, N3: N2, N4: N3); |
1624 | |
1625 | // lmul(x, 0, a, b) |
1626 | if (N1C && N1C->isZero()) { |
1627 | // If the high result is unused fold to add(a, b) |
1628 | if (N->hasNUsesOfValue(NUses: 0, Value: 0)) { |
1629 | SDValue Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: N2, N2: N3); |
1630 | SDValue Ops[] = { Lo, Lo }; |
1631 | return DAG.getMergeValues(Ops, dl); |
1632 | } |
1633 | // Otherwise fold to ladd(a, b, 0) |
1634 | SDValue Result = |
1635 | DAG.getNode(Opcode: XCoreISD::LADD, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), N1: N2, N2: N3, N3: N1); |
1636 | SDValue Carry(Result.getNode(), 1); |
1637 | SDValue Ops[] = { Carry, Result }; |
1638 | return DAG.getMergeValues(Ops, dl); |
1639 | } |
1640 | } |
1641 | break; |
1642 | case ISD::ADD: { |
1643 | // Fold 32 bit expressions such as add(add(mul(x,y),a),b) -> |
1644 | // lmul(x, y, a, b). The high result of lmul will be ignored. |
1645 | // This is only profitable if the intermediate results are unused |
1646 | // elsewhere. |
1647 | SDValue Mul0, Mul1, Addend0, Addend1; |
1648 | if (N->getValueType(0) == MVT::i32 && |
1649 | isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { |
1650 | SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, |
1651 | DAG.getVTList(MVT::i32, MVT::i32), Mul0, |
1652 | Mul1, Addend0, Addend1); |
1653 | SDValue Result(Ignored.getNode(), 1); |
1654 | return Result; |
1655 | } |
1656 | APInt HighMask = APInt::getHighBitsSet(numBits: 64, hiBitsSet: 32); |
1657 | // Fold 64 bit expression such as add(add(mul(x,y),a),b) -> |
1658 | // lmul(x, y, a, b) if all operands are zero-extended. We do this |
1659 | // before type legalization as it is messy to match the operands after |
1660 | // that. |
1661 | if (N->getValueType(0) == MVT::i64 && |
1662 | isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && |
1663 | DAG.MaskedValueIsZero(Mul0, HighMask) && |
1664 | DAG.MaskedValueIsZero(Mul1, HighMask) && |
1665 | DAG.MaskedValueIsZero(Addend0, HighMask) && |
1666 | DAG.MaskedValueIsZero(Addend1, HighMask)) { |
1667 | SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
1668 | Mul0, DAG.getConstant(0, dl, MVT::i32)); |
1669 | SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
1670 | Mul1, DAG.getConstant(0, dl, MVT::i32)); |
1671 | SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
1672 | Addend0, DAG.getConstant(0, dl, MVT::i32)); |
1673 | SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, |
1674 | Addend1, DAG.getConstant(0, dl, MVT::i32)); |
1675 | SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, |
1676 | DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, |
1677 | Addend0L, Addend1L); |
1678 | SDValue Lo(Hi.getNode(), 1); |
1679 | return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); |
1680 | } |
1681 | } |
1682 | break; |
1683 | case ISD::STORE: { |
1684 | // Replace unaligned store of unaligned load with memmove. |
1685 | StoreSDNode *ST = cast<StoreSDNode>(Val: N); |
1686 | if (!DCI.isBeforeLegalize() || |
1687 | allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), |
1688 | VT: ST->getMemoryVT(), |
1689 | MMO: *ST->getMemOperand()) || |
1690 | ST->isVolatile() || ST->isIndexed()) { |
1691 | break; |
1692 | } |
1693 | SDValue Chain = ST->getChain(); |
1694 | |
1695 | unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); |
1696 | assert((StoreBits % 8) == 0 && |
1697 | "Store size in bits must be a multiple of 8" ); |
1698 | Align Alignment = ST->getAlign(); |
1699 | |
1700 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: ST->getValue())) { |
1701 | if (LD->hasNUsesOfValue(NUses: 1, Value: 0) && ST->getMemoryVT() == LD->getMemoryVT() && |
1702 | LD->getAlign() == Alignment && |
1703 | !LD->isVolatile() && !LD->isIndexed() && |
1704 | Chain.reachesChainWithoutSideEffects(Dest: SDValue(LD, 1))) { |
1705 | bool isTail = isInTailCallPosition(DAG, Node: ST, Chain); |
1706 | return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(), |
1707 | DAG.getConstant(StoreBits / 8, dl, MVT::i32), |
1708 | Alignment, false, isTail, |
1709 | ST->getPointerInfo(), LD->getPointerInfo()); |
1710 | } |
1711 | } |
1712 | break; |
1713 | } |
1714 | } |
1715 | return SDValue(); |
1716 | } |
1717 | |
1718 | void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, |
1719 | KnownBits &Known, |
1720 | const APInt &DemandedElts, |
1721 | const SelectionDAG &DAG, |
1722 | unsigned Depth) const { |
1723 | Known.resetAll(); |
1724 | switch (Op.getOpcode()) { |
1725 | default: break; |
1726 | case XCoreISD::LADD: |
1727 | case XCoreISD::LSUB: |
1728 | if (Op.getResNo() == 1) { |
1729 | // Top bits of carry / borrow are clear. |
1730 | Known.Zero = APInt::getHighBitsSet(numBits: Known.getBitWidth(), |
1731 | hiBitsSet: Known.getBitWidth() - 1); |
1732 | } |
1733 | break; |
1734 | case ISD::INTRINSIC_W_CHAIN: |
1735 | { |
1736 | unsigned IntNo = Op.getConstantOperandVal(i: 1); |
1737 | switch (IntNo) { |
1738 | case Intrinsic::xcore_getts: |
1739 | // High bits are known to be zero. |
1740 | Known.Zero = |
1741 | APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 16); |
1742 | break; |
1743 | case Intrinsic::xcore_int: |
1744 | case Intrinsic::xcore_inct: |
1745 | // High bits are known to be zero. |
1746 | Known.Zero = |
1747 | APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 8); |
1748 | break; |
1749 | case Intrinsic::xcore_testct: |
1750 | // Result is either 0 or 1. |
1751 | Known.Zero = |
1752 | APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 1); |
1753 | break; |
1754 | case Intrinsic::xcore_testwct: |
1755 | // Result is in the range 0 - 4. |
1756 | Known.Zero = |
1757 | APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 3); |
1758 | break; |
1759 | } |
1760 | } |
1761 | break; |
1762 | } |
1763 | } |
1764 | |
1765 | //===----------------------------------------------------------------------===// |
1766 | // Addressing mode description hooks |
1767 | //===----------------------------------------------------------------------===// |
1768 | |
1769 | static inline bool isImmUs(int64_t val) |
1770 | { |
1771 | return (val >= 0 && val <= 11); |
1772 | } |
1773 | |
1774 | static inline bool isImmUs2(int64_t val) |
1775 | { |
1776 | return (val%2 == 0 && isImmUs(val: val/2)); |
1777 | } |
1778 | |
1779 | static inline bool isImmUs4(int64_t val) |
1780 | { |
1781 | return (val%4 == 0 && isImmUs(val: val/4)); |
1782 | } |
1783 | |
1784 | /// isLegalAddressingMode - Return true if the addressing mode represented |
1785 | /// by AM is legal for this target, for a load/store of the specified type. |
1786 | bool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL, |
1787 | const AddrMode &AM, Type *Ty, |
1788 | unsigned AS, |
1789 | Instruction *I) const { |
1790 | if (Ty->getTypeID() == Type::VoidTyID) |
1791 | return AM.Scale == 0 && isImmUs(val: AM.BaseOffs) && isImmUs4(val: AM.BaseOffs); |
1792 | |
1793 | unsigned Size = DL.getTypeAllocSize(Ty); |
1794 | if (AM.BaseGV) { |
1795 | return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && |
1796 | AM.BaseOffs%4 == 0; |
1797 | } |
1798 | |
1799 | switch (Size) { |
1800 | case 1: |
1801 | // reg + imm |
1802 | if (AM.Scale == 0) { |
1803 | return isImmUs(val: AM.BaseOffs); |
1804 | } |
1805 | // reg + reg |
1806 | return AM.Scale == 1 && AM.BaseOffs == 0; |
1807 | case 2: |
1808 | case 3: |
1809 | // reg + imm |
1810 | if (AM.Scale == 0) { |
1811 | return isImmUs2(val: AM.BaseOffs); |
1812 | } |
1813 | // reg + reg<<1 |
1814 | return AM.Scale == 2 && AM.BaseOffs == 0; |
1815 | default: |
1816 | // reg + imm |
1817 | if (AM.Scale == 0) { |
1818 | return isImmUs4(val: AM.BaseOffs); |
1819 | } |
1820 | // reg + reg<<2 |
1821 | return AM.Scale == 4 && AM.BaseOffs == 0; |
1822 | } |
1823 | } |
1824 | |
1825 | //===----------------------------------------------------------------------===// |
1826 | // XCore Inline Assembly Support |
1827 | //===----------------------------------------------------------------------===// |
1828 | |
1829 | std::pair<unsigned, const TargetRegisterClass *> |
1830 | XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, |
1831 | StringRef Constraint, |
1832 | MVT VT) const { |
1833 | if (Constraint.size() == 1) { |
1834 | switch (Constraint[0]) { |
1835 | default : break; |
1836 | case 'r': |
1837 | return std::make_pair(0U, &XCore::GRRegsRegClass); |
1838 | } |
1839 | } |
1840 | // Use the default implementation in TargetLowering to convert the register |
1841 | // constraint into a member of a register class. |
1842 | return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); |
1843 | } |
1844 | |