1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "pp_debug.h"
24#include <linux/delay.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/slab.h>
28#include <asm/div64.h>
29#if IS_ENABLED(CONFIG_X86_64)
30#include <asm/intel-family.h>
31#endif
32#include <drm/amdgpu_drm.h>
33#include "ppatomctrl.h"
34#include "atombios.h"
35#include "pptable_v1_0.h"
36#include "pppcielanes.h"
37#include "amd_pcie_helpers.h"
38#include "hardwaremanager.h"
39#include "process_pptables_v1_0.h"
40#include "cgs_common.h"
41
42#include "smu7_common.h"
43
44#include "hwmgr.h"
45#include "smu7_hwmgr.h"
46#include "smu_ucode_xfer_vi.h"
47#include "smu7_powertune.h"
48#include "smu7_dyn_defaults.h"
49#include "smu7_thermal.h"
50#include "smu7_clockpowergating.h"
51#include "processpptables.h"
52#include "pp_thermal.h"
53#include "smu7_baco.h"
54#include "smu7_smumgr.h"
55#include "polaris10_smumgr.h"
56
57#include "ivsrcid/ivsrcid_vislands30.h"
58
59#define MC_CG_ARB_FREQ_F0 0x0a
60#define MC_CG_ARB_FREQ_F1 0x0b
61#define MC_CG_ARB_FREQ_F2 0x0c
62#define MC_CG_ARB_FREQ_F3 0x0d
63
64#define MC_CG_SEQ_DRAMCONF_S0 0x05
65#define MC_CG_SEQ_DRAMCONF_S1 0x06
66#define MC_CG_SEQ_YCLK_SUSPEND 0x04
67#define MC_CG_SEQ_YCLK_RESUME 0x0a
68
69#define SMC_CG_IND_START 0xc0030000
70#define SMC_CG_IND_END 0xc0040000
71
72#define MEM_FREQ_LOW_LATENCY 25000
73#define MEM_FREQ_HIGH_LATENCY 80000
74
75#define MEM_LATENCY_HIGH 45
76#define MEM_LATENCY_LOW 35
77#define MEM_LATENCY_ERR 0xFFFF
78
79#define MC_SEQ_MISC0_GDDR5_SHIFT 28
80#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
81#define MC_SEQ_MISC0_GDDR5_VALUE 5
82
83#define PCIE_BUS_CLK 10000
84#define TCLK (PCIE_BUS_CLK / 10)
85
86static struct profile_mode_setting smu7_profiling[7] = {
87 {0, 0, 0, 0, 0, 0, 0, 0},
88 {1, 0, 100, 30, 1, 0, 100, 10},
89 {1, 10, 0, 30, 0, 0, 0, 0},
90 {0, 0, 0, 0, 1, 10, 16, 31},
91 {1, 0, 11, 50, 1, 0, 100, 10},
92 {1, 0, 5, 30, 0, 0, 0, 0},
93 {0, 0, 0, 0, 0, 0, 0, 0},
94};
95
96#define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310)
97
98#define ixPWR_SVI2_PLANE1_LOAD 0xC0200280
99#define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L
100#define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L
101#define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005
102#define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006
103
104#define STRAP_EVV_REVISION_MSB 2211
105#define STRAP_EVV_REVISION_LSB 2208
106
107/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
108enum DPM_EVENT_SRC {
109 DPM_EVENT_SRC_ANALOG = 0,
110 DPM_EVENT_SRC_EXTERNAL = 1,
111 DPM_EVENT_SRC_DIGITAL = 2,
112 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
113 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
114};
115
116#define ixDIDT_SQ_EDC_CTRL 0x0013
117#define ixDIDT_SQ_EDC_THRESHOLD 0x0014
118#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015
119#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016
120#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017
121#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018
122
123#define ixDIDT_TD_EDC_CTRL 0x0053
124#define ixDIDT_TD_EDC_THRESHOLD 0x0054
125#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055
126#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056
127#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057
128#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058
129
130#define ixDIDT_TCP_EDC_CTRL 0x0073
131#define ixDIDT_TCP_EDC_THRESHOLD 0x0074
132#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075
133#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076
134#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077
135#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078
136
137#define ixDIDT_DB_EDC_CTRL 0x0033
138#define ixDIDT_DB_EDC_THRESHOLD 0x0034
139#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035
140#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036
141#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037
142#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038
143
144uint32_t DIDTEDCConfig_P12[] = {
145 ixDIDT_SQ_EDC_STALL_PATTERN_1_2,
146 ixDIDT_SQ_EDC_STALL_PATTERN_3_4,
147 ixDIDT_SQ_EDC_STALL_PATTERN_5_6,
148 ixDIDT_SQ_EDC_STALL_PATTERN_7,
149 ixDIDT_SQ_EDC_THRESHOLD,
150 ixDIDT_SQ_EDC_CTRL,
151 ixDIDT_TD_EDC_STALL_PATTERN_1_2,
152 ixDIDT_TD_EDC_STALL_PATTERN_3_4,
153 ixDIDT_TD_EDC_STALL_PATTERN_5_6,
154 ixDIDT_TD_EDC_STALL_PATTERN_7,
155 ixDIDT_TD_EDC_THRESHOLD,
156 ixDIDT_TD_EDC_CTRL,
157 ixDIDT_TCP_EDC_STALL_PATTERN_1_2,
158 ixDIDT_TCP_EDC_STALL_PATTERN_3_4,
159 ixDIDT_TCP_EDC_STALL_PATTERN_5_6,
160 ixDIDT_TCP_EDC_STALL_PATTERN_7,
161 ixDIDT_TCP_EDC_THRESHOLD,
162 ixDIDT_TCP_EDC_CTRL,
163 ixDIDT_DB_EDC_STALL_PATTERN_1_2,
164 ixDIDT_DB_EDC_STALL_PATTERN_3_4,
165 ixDIDT_DB_EDC_STALL_PATTERN_5_6,
166 ixDIDT_DB_EDC_STALL_PATTERN_7,
167 ixDIDT_DB_EDC_THRESHOLD,
168 ixDIDT_DB_EDC_CTRL,
169 0xFFFFFFFF // End of list
170};
171
172static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
173static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
174 enum pp_clock_type type, uint32_t mask);
175static int smu7_notify_has_display(struct pp_hwmgr *hwmgr);
176
177static struct smu7_power_state *cast_phw_smu7_power_state(
178 struct pp_hw_power_state *hw_ps)
179{
180 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
181 "Invalid Powerstate Type!",
182 return NULL);
183
184 return (struct smu7_power_state *)hw_ps;
185}
186
187static const struct smu7_power_state *cast_const_phw_smu7_power_state(
188 const struct pp_hw_power_state *hw_ps)
189{
190 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
191 "Invalid Powerstate Type!",
192 return NULL);
193
194 return (const struct smu7_power_state *)hw_ps;
195}
196
197/**
198 * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct
199 *
200 * @hwmgr: the address of the powerplay hardware manager.
201 * Return: always 0
202 */
203static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
204{
205 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
206
207 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
208
209 return 0;
210}
211
212static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
213{
214 uint32_t speedCntl = 0;
215
216 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
217 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
218 ixPCIE_LC_SPEED_CNTL);
219 return((uint16_t)PHM_GET_FIELD(speedCntl,
220 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
221}
222
223static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
224{
225 uint32_t link_width;
226
227 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
228 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
229 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
230
231 PP_ASSERT_WITH_CODE((7 >= link_width),
232 "Invalid PCIe lane width!", return 0);
233
234 return decode_pcie_lane_width(num_lanes: link_width);
235}
236
237/**
238 * smu7_enable_smc_voltage_controller - Enable voltage control
239 *
240 * @hwmgr: the address of the powerplay hardware manager.
241 * Return: always PP_Result_OK
242 */
243static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
244{
245 if (hwmgr->chip_id >= CHIP_POLARIS10 &&
246 hwmgr->chip_id <= CHIP_VEGAM) {
247 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
248 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
249 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
250 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
251 }
252
253 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
254 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL);
255
256 return 0;
257}
258
259/**
260 * smu7_voltage_control - Checks if we want to support voltage control
261 *
262 * @hwmgr: the address of the powerplay hardware manager.
263 */
264static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
265{
266 const struct smu7_hwmgr *data =
267 (const struct smu7_hwmgr *)(hwmgr->backend);
268
269 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
270}
271
272/**
273 * smu7_enable_voltage_control - Enable voltage control
274 *
275 * @hwmgr: the address of the powerplay hardware manager.
276 * Return: always 0
277 */
278static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
279{
280 /* enable voltage control */
281 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
282 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
283
284 return 0;
285}
286
287static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
288 struct phm_clock_voltage_dependency_table *voltage_dependency_table
289 )
290{
291 uint32_t i;
292
293 PP_ASSERT_WITH_CODE((NULL != voltage_table),
294 "Voltage Dependency Table empty.", return -EINVAL;);
295
296 voltage_table->mask_low = 0;
297 voltage_table->phase_delay = 0;
298 voltage_table->count = voltage_dependency_table->count;
299
300 for (i = 0; i < voltage_dependency_table->count; i++) {
301 voltage_table->entries[i].value =
302 voltage_dependency_table->entries[i].v;
303 voltage_table->entries[i].smio_low = 0;
304 }
305
306 return 0;
307}
308
309
310/**
311 * smu7_construct_voltage_tables - Create Voltage Tables.
312 *
313 * @hwmgr: the address of the powerplay hardware manager.
314 * Return: always 0
315 */
316static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
317{
318 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
319 struct phm_ppt_v1_information *table_info =
320 (struct phm_ppt_v1_information *)hwmgr->pptable;
321 int result = 0;
322 uint32_t tmp;
323
324 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
325 result = atomctrl_get_voltage_table_v3(hwmgr,
326 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
327 voltage_table: &(data->mvdd_voltage_table));
328 PP_ASSERT_WITH_CODE((0 == result),
329 "Failed to retrieve MVDD table.",
330 return result);
331 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
332 if (hwmgr->pp_table_version == PP_TABLE_V1)
333 result = phm_get_svi2_mvdd_voltage_table(vol_table: &(data->mvdd_voltage_table),
334 dep_table: table_info->vdd_dep_on_mclk);
335 else if (hwmgr->pp_table_version == PP_TABLE_V0)
336 result = phm_get_svi2_voltage_table_v0(voltage_table: &(data->mvdd_voltage_table),
337 voltage_dependency_table: hwmgr->dyn_state.mvdd_dependency_on_mclk);
338
339 PP_ASSERT_WITH_CODE((0 == result),
340 "Failed to retrieve SVI2 MVDD table from dependency table.",
341 return result;);
342 }
343
344 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
345 result = atomctrl_get_voltage_table_v3(hwmgr,
346 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
347 voltage_table: &(data->vddci_voltage_table));
348 PP_ASSERT_WITH_CODE((0 == result),
349 "Failed to retrieve VDDCI table.",
350 return result);
351 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
352 if (hwmgr->pp_table_version == PP_TABLE_V1)
353 result = phm_get_svi2_vddci_voltage_table(vol_table: &(data->vddci_voltage_table),
354 dep_table: table_info->vdd_dep_on_mclk);
355 else if (hwmgr->pp_table_version == PP_TABLE_V0)
356 result = phm_get_svi2_voltage_table_v0(voltage_table: &(data->vddci_voltage_table),
357 voltage_dependency_table: hwmgr->dyn_state.vddci_dependency_on_mclk);
358 PP_ASSERT_WITH_CODE((0 == result),
359 "Failed to retrieve SVI2 VDDCI table from dependency table.",
360 return result);
361 }
362
363 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
364 /* VDDGFX has only SVI2 voltage control */
365 result = phm_get_svi2_vdd_voltage_table(vol_table: &(data->vddgfx_voltage_table),
366 lookup_table: table_info->vddgfx_lookup_table);
367 PP_ASSERT_WITH_CODE((0 == result),
368 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
369 }
370
371
372 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
373 result = atomctrl_get_voltage_table_v3(hwmgr,
374 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
375 voltage_table: &data->vddc_voltage_table);
376 PP_ASSERT_WITH_CODE((0 == result),
377 "Failed to retrieve VDDC table.", return result;);
378 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
379
380 if (hwmgr->pp_table_version == PP_TABLE_V0)
381 result = phm_get_svi2_voltage_table_v0(voltage_table: &data->vddc_voltage_table,
382 voltage_dependency_table: hwmgr->dyn_state.vddc_dependency_on_mclk);
383 else if (hwmgr->pp_table_version == PP_TABLE_V1)
384 result = phm_get_svi2_vdd_voltage_table(vol_table: &(data->vddc_voltage_table),
385 lookup_table: table_info->vddc_lookup_table);
386
387 PP_ASSERT_WITH_CODE((0 == result),
388 "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
389 }
390
391 tmp = smum_get_mac_definition(hwmgr, value: SMU_MAX_LEVELS_VDDC);
392 PP_ASSERT_WITH_CODE(
393 (data->vddc_voltage_table.count <= tmp),
394 "Too many voltage values for VDDC. Trimming to fit state table.",
395 phm_trim_voltage_table_to_fit_state_table(tmp,
396 &(data->vddc_voltage_table)));
397
398 tmp = smum_get_mac_definition(hwmgr, value: SMU_MAX_LEVELS_VDDGFX);
399 PP_ASSERT_WITH_CODE(
400 (data->vddgfx_voltage_table.count <= tmp),
401 "Too many voltage values for VDDC. Trimming to fit state table.",
402 phm_trim_voltage_table_to_fit_state_table(tmp,
403 &(data->vddgfx_voltage_table)));
404
405 tmp = smum_get_mac_definition(hwmgr, value: SMU_MAX_LEVELS_VDDCI);
406 PP_ASSERT_WITH_CODE(
407 (data->vddci_voltage_table.count <= tmp),
408 "Too many voltage values for VDDCI. Trimming to fit state table.",
409 phm_trim_voltage_table_to_fit_state_table(tmp,
410 &(data->vddci_voltage_table)));
411
412 tmp = smum_get_mac_definition(hwmgr, value: SMU_MAX_LEVELS_MVDD);
413 PP_ASSERT_WITH_CODE(
414 (data->mvdd_voltage_table.count <= tmp),
415 "Too many voltage values for MVDD. Trimming to fit state table.",
416 phm_trim_voltage_table_to_fit_state_table(tmp,
417 &(data->mvdd_voltage_table)));
418
419 return 0;
420}
421
422/**
423 * smu7_program_static_screen_threshold_parameters - Programs static screed detection parameters
424 *
425 * @hwmgr: the address of the powerplay hardware manager.
426 * Return: always 0
427 */
428static int smu7_program_static_screen_threshold_parameters(
429 struct pp_hwmgr *hwmgr)
430{
431 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
432
433 /* Set static screen threshold unit */
434 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
435 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
436 data->static_screen_threshold_unit);
437 /* Set static screen threshold */
438 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
439 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
440 data->static_screen_threshold);
441
442 return 0;
443}
444
445/**
446 * smu7_enable_display_gap - Setup display gap for glitch free memory clock switching.
447 *
448 * @hwmgr: the address of the powerplay hardware manager.
449 * Return: always 0
450 */
451static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
452{
453 uint32_t display_gap =
454 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
455 ixCG_DISPLAY_GAP_CNTL);
456
457 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
458 DISP_GAP, DISPLAY_GAP_IGNORE);
459
460 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
461 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
462
463 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
464 ixCG_DISPLAY_GAP_CNTL, display_gap);
465
466 return 0;
467}
468
469/**
470 * smu7_program_voting_clients - Programs activity state transition voting clients
471 *
472 * @hwmgr: the address of the powerplay hardware manager.
473 * Return: always 0
474 */
475static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
476{
477 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
478 int i;
479
480 /* Clear reset for voting clients before enabling DPM */
481 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
482 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
483 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
484 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
485
486 for (i = 0; i < 8; i++)
487 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
488 ixCG_FREQ_TRAN_VOTING_0 + i * 4,
489 data->voting_rights_clients[i]);
490 return 0;
491}
492
493static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
494{
495 int i;
496
497 /* Reset voting clients before disabling DPM */
498 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
499 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
500 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
501 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
502
503 for (i = 0; i < 8; i++)
504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
505 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
506
507 return 0;
508}
509
510/* Copy one arb setting to another and then switch the active set.
511 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
512 */
513static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
514 uint32_t arb_src, uint32_t arb_dest)
515{
516 uint32_t mc_arb_dram_timing;
517 uint32_t mc_arb_dram_timing2;
518 uint32_t burst_time;
519 uint32_t mc_cg_config;
520
521 switch (arb_src) {
522 case MC_CG_ARB_FREQ_F0:
523 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
524 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
525 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
526 break;
527 case MC_CG_ARB_FREQ_F1:
528 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
529 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
530 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
531 break;
532 default:
533 return -EINVAL;
534 }
535
536 switch (arb_dest) {
537 case MC_CG_ARB_FREQ_F0:
538 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
539 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
540 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
541 break;
542 case MC_CG_ARB_FREQ_F1:
543 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
544 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
545 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
552 mc_cg_config |= 0x0000000F;
553 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
554 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
555
556 return 0;
557}
558
559static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
560{
561 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL);
562}
563
564/**
565 * smu7_initial_switch_from_arbf0_to_f1 - Initial switch from ARB F0->F1
566 *
567 * @hwmgr: the address of the powerplay hardware manager.
568 * Return: always 0
569 * This function is to be called from the SetPowerState table.
570 */
571static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
572{
573 return smu7_copy_and_switch_arb_sets(hwmgr,
574 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
575}
576
577static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
578{
579 uint32_t tmp;
580
581 tmp = (cgs_read_ind_register(hwmgr->device,
582 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
583 0x0000ff00) >> 8;
584
585 if (tmp == MC_CG_ARB_FREQ_F0)
586 return 0;
587
588 return smu7_copy_and_switch_arb_sets(hwmgr,
589 arb_src: tmp, MC_CG_ARB_FREQ_F0);
590}
591
592static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr)
593{
594 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
595 uint16_t pcie_gen = 0;
596
597 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 &&
598 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4)
599 pcie_gen = 3;
600 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 &&
601 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
602 pcie_gen = 2;
603 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 &&
604 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2)
605 pcie_gen = 1;
606 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 &&
607 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1)
608 pcie_gen = 0;
609
610 return pcie_gen;
611}
612
613static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr)
614{
615 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
616 uint16_t pcie_width = 0;
617
618 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
619 pcie_width = 16;
620 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
621 pcie_width = 12;
622 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
623 pcie_width = 8;
624 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
625 pcie_width = 4;
626 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
627 pcie_width = 2;
628 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
629 pcie_width = 1;
630
631 return pcie_width;
632}
633
634static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
635{
636 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
637
638 struct phm_ppt_v1_information *table_info =
639 (struct phm_ppt_v1_information *)(hwmgr->pptable);
640 struct phm_ppt_v1_pcie_table *pcie_table = NULL;
641
642 uint32_t i, max_entry;
643 uint32_t tmp;
644
645 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
646 data->use_pcie_power_saving_levels), "No pcie performance levels!",
647 return -EINVAL);
648
649 if (table_info != NULL)
650 pcie_table = table_info->pcie_table;
651
652 if (data->use_pcie_performance_levels &&
653 !data->use_pcie_power_saving_levels) {
654 data->pcie_gen_power_saving = data->pcie_gen_performance;
655 data->pcie_lane_power_saving = data->pcie_lane_performance;
656 } else if (!data->use_pcie_performance_levels &&
657 data->use_pcie_power_saving_levels) {
658 data->pcie_gen_performance = data->pcie_gen_power_saving;
659 data->pcie_lane_performance = data->pcie_lane_power_saving;
660 }
661 tmp = smum_get_mac_definition(hwmgr, value: SMU_MAX_LEVELS_LINK);
662 phm_reset_single_dpm_table(table: &data->dpm_table.pcie_speed_table,
663 count: tmp,
664 MAX_REGULAR_DPM_NUMBER);
665
666 if (pcie_table != NULL) {
667 /* max_entry is used to make sure we reserve one PCIE level
668 * for boot level (fix for A+A PSPP issue).
669 * If PCIE table from PPTable have ULV entry + 8 entries,
670 * then ignore the last entry.*/
671 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
672 for (i = 1; i < max_entry; i++) {
673 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: i - 1,
674 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
675 ns_pcie_gen: pcie_table->entries[i].gen_speed),
676 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
677 ns_pcie_lanes: pcie_table->entries[i].lane_width));
678 }
679 data->dpm_table.pcie_speed_table.count = max_entry - 1;
680 smum_update_smc_table(hwmgr, type: SMU_BIF_TABLE);
681 } else {
682 /* Hardcode Pcie Table */
683 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: 0,
684 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
685 PP_Min_PCIEGen),
686 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
687 PP_Max_PCIELane));
688 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: 1,
689 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
690 PP_Min_PCIEGen),
691 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
692 PP_Max_PCIELane));
693 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: 2,
694 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
695 PP_Max_PCIEGen),
696 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
697 PP_Max_PCIELane));
698 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: 3,
699 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
700 PP_Max_PCIEGen),
701 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
702 PP_Max_PCIELane));
703 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: 4,
704 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
705 PP_Max_PCIEGen),
706 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
707 PP_Max_PCIELane));
708 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: 5,
709 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
710 PP_Max_PCIEGen),
711 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
712 PP_Max_PCIELane));
713
714 data->dpm_table.pcie_speed_table.count = 6;
715 }
716 /* Populate last level for boot PCIE level, but do not increment count. */
717 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
718 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
719 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table, index: i,
720 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
721 PP_Max_PCIEGen),
722 pcie_lanes: data->vbios_boot_state.pcie_lane_bootup_value);
723 } else {
724 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table,
725 index: data->dpm_table.pcie_speed_table.count,
726 pcie_gen: get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
727 PP_Min_PCIEGen),
728 pcie_lanes: get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
729 PP_Max_PCIELane));
730
731 if (data->pcie_dpm_key_disabled)
732 phm_setup_pcie_table_entry(table: &data->dpm_table.pcie_speed_table,
733 index: data->dpm_table.pcie_speed_table.count,
734 pcie_gen: smu7_override_pcie_speed(hwmgr), pcie_lanes: smu7_override_pcie_width(hwmgr));
735 }
736 return 0;
737}
738
739static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
740{
741 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
742
743 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
744
745 phm_reset_single_dpm_table(
746 table: &data->dpm_table.sclk_table,
747 count: smum_get_mac_definition(hwmgr,
748 value: SMU_MAX_LEVELS_GRAPHICS),
749 MAX_REGULAR_DPM_NUMBER);
750 phm_reset_single_dpm_table(
751 table: &data->dpm_table.mclk_table,
752 count: smum_get_mac_definition(hwmgr,
753 value: SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
754
755 phm_reset_single_dpm_table(
756 table: &data->dpm_table.vddc_table,
757 count: smum_get_mac_definition(hwmgr,
758 value: SMU_MAX_LEVELS_VDDC),
759 MAX_REGULAR_DPM_NUMBER);
760 phm_reset_single_dpm_table(
761 table: &data->dpm_table.vddci_table,
762 count: smum_get_mac_definition(hwmgr,
763 value: SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
764
765 phm_reset_single_dpm_table(
766 table: &data->dpm_table.mvdd_table,
767 count: smum_get_mac_definition(hwmgr,
768 value: SMU_MAX_LEVELS_MVDD),
769 MAX_REGULAR_DPM_NUMBER);
770 return 0;
771}
772/*
773 * This function is to initialize all DPM state tables
774 * for SMU7 based on the dependency table.
775 * Dynamic state patching function will then trim these
776 * state tables to the allowed range based
777 * on the power policy or external client requests,
778 * such as UVD request, etc.
779 */
780
781static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
782{
783 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
784 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
785 hwmgr->dyn_state.vddc_dependency_on_sclk;
786 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
787 hwmgr->dyn_state.vddc_dependency_on_mclk;
788 struct phm_cac_leakage_table *std_voltage_table =
789 hwmgr->dyn_state.cac_leakage_table;
790 uint32_t i;
791
792 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
793 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
794 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
795 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
796
797 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
798 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
799 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
800 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
801
802
803 /* Initialize Sclk DPM table based on allow Sclk values*/
804 data->dpm_table.sclk_table.count = 0;
805
806 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
807 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
808 allowed_vdd_sclk_table->entries[i].clk) {
809 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
810 allowed_vdd_sclk_table->entries[i].clk;
811 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
812 data->dpm_table.sclk_table.count++;
813 }
814 }
815
816 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
817 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
818 /* Initialize Mclk DPM table based on allow Mclk values */
819 data->dpm_table.mclk_table.count = 0;
820 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
821 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
822 allowed_vdd_mclk_table->entries[i].clk) {
823 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
824 allowed_vdd_mclk_table->entries[i].clk;
825 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
826 data->dpm_table.mclk_table.count++;
827 }
828 }
829
830 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
831 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
832 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
833 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
834 /* param1 is for corresponding std voltage */
835 data->dpm_table.vddc_table.dpm_levels[i].enabled = true;
836 }
837
838 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
839 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
840
841 if (NULL != allowed_vdd_mclk_table) {
842 /* Initialize Vddci DPM table based on allow Mclk values */
843 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
844 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
845 data->dpm_table.vddci_table.dpm_levels[i].enabled = true;
846 }
847 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
848 }
849
850 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
851
852 if (NULL != allowed_vdd_mclk_table) {
853 /*
854 * Initialize MVDD DPM table based on allow Mclk
855 * values
856 */
857 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
858 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
859 data->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
860 }
861 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
862 }
863
864 return 0;
865}
866
867static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
868{
869 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
870 struct phm_ppt_v1_information *table_info =
871 (struct phm_ppt_v1_information *)(hwmgr->pptable);
872 uint32_t i;
873
874 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
875 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
876
877 if (table_info == NULL)
878 return -EINVAL;
879
880 dep_sclk_table = table_info->vdd_dep_on_sclk;
881 dep_mclk_table = table_info->vdd_dep_on_mclk;
882
883 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
884 "SCLK dependency table is missing.",
885 return -EINVAL);
886 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
887 "SCLK dependency table count is 0.",
888 return -EINVAL);
889
890 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
891 "MCLK dependency table is missing.",
892 return -EINVAL);
893 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
894 "MCLK dependency table count is 0",
895 return -EINVAL);
896
897 /* Initialize Sclk DPM table based on allow Sclk values */
898 data->dpm_table.sclk_table.count = 0;
899 for (i = 0; i < dep_sclk_table->count; i++) {
900 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
901 dep_sclk_table->entries[i].clk) {
902
903 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
904 dep_sclk_table->entries[i].clk;
905
906 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
907 i == 0;
908 data->dpm_table.sclk_table.count++;
909 }
910 }
911 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
912 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
913 /* Initialize Mclk DPM table based on allow Mclk values */
914 data->dpm_table.mclk_table.count = 0;
915 for (i = 0; i < dep_mclk_table->count; i++) {
916 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
917 [data->dpm_table.mclk_table.count - 1].value !=
918 dep_mclk_table->entries[i].clk) {
919 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
920 dep_mclk_table->entries[i].clk;
921 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
922 i == 0;
923 data->dpm_table.mclk_table.count++;
924 }
925 }
926
927 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
928 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
929 return 0;
930}
931
932static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
933{
934 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
935 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
936 struct phm_ppt_v1_information *table_info =
937 (struct phm_ppt_v1_information *)(hwmgr->pptable);
938 uint32_t i;
939
940 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
941 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
942 struct phm_odn_performance_level *entries;
943
944 if (table_info == NULL)
945 return -EINVAL;
946
947 dep_sclk_table = table_info->vdd_dep_on_sclk;
948 dep_mclk_table = table_info->vdd_dep_on_mclk;
949
950 odn_table->odn_core_clock_dpm_levels.num_of_pl =
951 data->golden_dpm_table.sclk_table.count;
952 entries = odn_table->odn_core_clock_dpm_levels.entries;
953 for (i = 0; i < data->golden_dpm_table.sclk_table.count; i++) {
954 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
955 entries[i].enabled = true;
956 entries[i].vddc = dep_sclk_table->entries[i].vddc;
957 }
958
959 smu_get_voltage_dependency_table_ppt_v1(allowed_dep_table: dep_sclk_table,
960 dep_table: (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
961
962 odn_table->odn_memory_clock_dpm_levels.num_of_pl =
963 data->golden_dpm_table.mclk_table.count;
964 entries = odn_table->odn_memory_clock_dpm_levels.entries;
965 for (i = 0; i < data->golden_dpm_table.mclk_table.count; i++) {
966 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
967 entries[i].enabled = true;
968 entries[i].vddc = dep_mclk_table->entries[i].vddc;
969 }
970
971 smu_get_voltage_dependency_table_ppt_v1(allowed_dep_table: dep_mclk_table,
972 dep_table: (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
973
974 return 0;
975}
976
977static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
978{
979 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
980 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
981 struct phm_ppt_v1_information *table_info =
982 (struct phm_ppt_v1_information *)(hwmgr->pptable);
983 uint32_t min_vddc = 0;
984 uint32_t max_vddc = 0;
985
986 if (!table_info)
987 return;
988
989 dep_sclk_table = table_info->vdd_dep_on_sclk;
990
991 atomctrl_get_voltage_range(hwmgr, max_vddc: &max_vddc, min_vddc: &min_vddc);
992
993 if (min_vddc == 0 || min_vddc > 2000
994 || min_vddc > dep_sclk_table->entries[0].vddc)
995 min_vddc = dep_sclk_table->entries[0].vddc;
996
997 if (max_vddc == 0 || max_vddc > 2000
998 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
999 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
1000
1001 data->odn_dpm_table.min_vddc = min_vddc;
1002 data->odn_dpm_table.max_vddc = max_vddc;
1003}
1004
1005static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
1006{
1007 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1008 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
1009 struct phm_ppt_v1_information *table_info =
1010 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1011 uint32_t i;
1012
1013 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1014 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
1015
1016 if (table_info == NULL)
1017 return;
1018
1019 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1020 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
1021 data->dpm_table.sclk_table.dpm_levels[i].value) {
1022 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
1023 break;
1024 }
1025 }
1026
1027 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1028 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
1029 data->dpm_table.mclk_table.dpm_levels[i].value) {
1030 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
1031 break;
1032 }
1033 }
1034
1035 dep_table = table_info->vdd_dep_on_mclk;
1036 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
1037
1038 for (i = 0; i < dep_table->count; i++) {
1039 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
1040 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
1041 return;
1042 }
1043 }
1044
1045 dep_table = table_info->vdd_dep_on_sclk;
1046 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
1047 for (i = 0; i < dep_table->count; i++) {
1048 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
1049 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
1050 return;
1051 }
1052 }
1053 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1054 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
1055 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
1056 }
1057}
1058
1059static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1060{
1061 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1062
1063 smu7_reset_dpm_tables(hwmgr);
1064
1065 if (hwmgr->pp_table_version == PP_TABLE_V1)
1066 smu7_setup_dpm_tables_v1(hwmgr);
1067 else if (hwmgr->pp_table_version == PP_TABLE_V0)
1068 smu7_setup_dpm_tables_v0(hwmgr);
1069
1070 smu7_setup_default_pcie_table(hwmgr);
1071
1072 /* save a copy of the default DPM table */
1073 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1074 sizeof(struct smu7_dpm_table));
1075
1076 /* initialize ODN table */
1077 if (hwmgr->od_enabled) {
1078 if (data->odn_dpm_table.max_vddc) {
1079 smu7_check_dpm_table_updated(hwmgr);
1080 } else {
1081 smu7_setup_voltage_range_from_vbios(hwmgr);
1082 smu7_odn_initial_default_setting(hwmgr);
1083 }
1084 }
1085 return 0;
1086}
1087
1088static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
1089{
1090
1091 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1092 c: PHM_PlatformCaps_RegulatorHot))
1093 return smum_send_msg_to_smc(hwmgr,
1094 PPSMC_MSG_EnableVRHotGPIOInterrupt,
1095 NULL);
1096
1097 return 0;
1098}
1099
1100static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
1101{
1102 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1103 SCLK_PWRMGT_OFF, 0);
1104 return 0;
1105}
1106
1107static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
1108{
1109 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1110
1111 if (data->ulv_supported)
1112 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL);
1113
1114 return 0;
1115}
1116
1117static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1118{
1119 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1120
1121 if (data->ulv_supported)
1122 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL);
1123
1124 return 0;
1125}
1126
1127static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1128{
1129 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1130 c: PHM_PlatformCaps_SclkDeepSleep)) {
1131 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL))
1132 PP_ASSERT_WITH_CODE(false,
1133 "Attempt to enable Master Deep Sleep switch failed!",
1134 return -EINVAL);
1135 } else {
1136 if (smum_send_msg_to_smc(hwmgr,
1137 PPSMC_MSG_MASTER_DeepSleep_OFF,
1138 NULL)) {
1139 PP_ASSERT_WITH_CODE(false,
1140 "Attempt to disable Master Deep Sleep switch failed!",
1141 return -EINVAL);
1142 }
1143 }
1144
1145 return 0;
1146}
1147
1148static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1149{
1150 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1151 c: PHM_PlatformCaps_SclkDeepSleep)) {
1152 if (smum_send_msg_to_smc(hwmgr,
1153 PPSMC_MSG_MASTER_DeepSleep_OFF,
1154 NULL)) {
1155 PP_ASSERT_WITH_CODE(false,
1156 "Attempt to disable Master Deep Sleep switch failed!",
1157 return -EINVAL);
1158 }
1159 }
1160
1161 return 0;
1162}
1163
1164static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1165{
1166 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1167 uint32_t soft_register_value = 0;
1168 uint32_t handshake_disables_offset = data->soft_regs_start
1169 + smum_get_offsetof(hwmgr,
1170 type: SMU_SoftRegisters, member: HandshakeDisables);
1171
1172 soft_register_value = cgs_read_ind_register(hwmgr->device,
1173 CGS_IND_REG__SMC, handshake_disables_offset);
1174 soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1175 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1176 handshake_disables_offset, soft_register_value);
1177 return 0;
1178}
1179
1180static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1181{
1182 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1183 uint32_t soft_register_value = 0;
1184 uint32_t handshake_disables_offset = data->soft_regs_start
1185 + smum_get_offsetof(hwmgr,
1186 type: SMU_SoftRegisters, member: HandshakeDisables);
1187
1188 soft_register_value = cgs_read_ind_register(hwmgr->device,
1189 CGS_IND_REG__SMC, handshake_disables_offset);
1190 soft_register_value |= smum_get_mac_definition(hwmgr,
1191 value: SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1192 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1193 handshake_disables_offset, soft_register_value);
1194 return 0;
1195}
1196
1197static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1198{
1199 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1200
1201 /* enable SCLK dpm */
1202 if (!data->sclk_dpm_key_disabled) {
1203 if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1204 hwmgr->chip_id <= CHIP_VEGAM)
1205 smu7_disable_sclk_vce_handshake(hwmgr);
1206
1207 PP_ASSERT_WITH_CODE(
1208 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)),
1209 "Failed to enable SCLK DPM during DPM Start Function!",
1210 return -EINVAL);
1211 }
1212
1213 /* enable MCLK dpm */
1214 if (0 == data->mclk_dpm_key_disabled) {
1215 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1216 smu7_disable_handshake_uvd(hwmgr);
1217
1218 PP_ASSERT_WITH_CODE(
1219 (0 == smum_send_msg_to_smc(hwmgr,
1220 PPSMC_MSG_MCLKDPM_Enable,
1221 NULL)),
1222 "Failed to enable MCLK DPM during DPM Start Function!",
1223 return -EINVAL);
1224
1225 if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) ||
1226 (hwmgr->chip_id == CHIP_POLARIS10) ||
1227 (hwmgr->chip_id == CHIP_POLARIS11) ||
1228 (hwmgr->chip_id == CHIP_POLARIS12) ||
1229 (hwmgr->chip_id == CHIP_TONGA) ||
1230 (hwmgr->chip_id == CHIP_TOPAZ))
1231 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1232
1233
1234 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1235 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1236 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1237 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1238 udelay(10);
1239 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1240 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1242 } else {
1243 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1244 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1245 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1246 udelay(10);
1247 if (hwmgr->chip_id == CHIP_VEGAM) {
1248 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1249 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1250 } else {
1251 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1252 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1253 }
1254 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1255 }
1256 }
1257
1258 return 0;
1259}
1260
1261static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1262{
1263 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1264
1265 /*enable general power management */
1266
1267 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1268 GLOBAL_PWRMGT_EN, 1);
1269
1270 /* enable sclk deep sleep */
1271
1272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1273 DYNAMIC_PM_EN, 1);
1274
1275 /* prepare for PCIE DPM */
1276
1277 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1278 data->soft_regs_start +
1279 smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1280 VoltageChangeTimeout), 0x1000);
1281 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1282 SWRST_COMMAND_1, RESETLC, 0x0);
1283
1284 if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1285 cgs_write_register(hwmgr->device, 0x1488,
1286 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1287
1288 if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1289 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1290 return -EINVAL;
1291 }
1292
1293 /* enable PCIE dpm */
1294 if (0 == data->pcie_dpm_key_disabled) {
1295 PP_ASSERT_WITH_CODE(
1296 (0 == smum_send_msg_to_smc(hwmgr,
1297 PPSMC_MSG_PCIeDPM_Enable,
1298 NULL)),
1299 "Failed to enable pcie DPM during DPM Start Function!",
1300 return -EINVAL);
1301 } else {
1302 PP_ASSERT_WITH_CODE(
1303 (0 == smum_send_msg_to_smc(hwmgr,
1304 PPSMC_MSG_PCIeDPM_Disable,
1305 NULL)),
1306 "Failed to disable pcie DPM during DPM Start Function!",
1307 return -EINVAL);
1308 }
1309
1310 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1311 c: PHM_PlatformCaps_Falcon_QuickTransition)) {
1312 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1313 PPSMC_MSG_EnableACDCGPIOInterrupt,
1314 NULL)),
1315 "Failed to enable AC DC GPIO Interrupt!",
1316 );
1317 }
1318
1319 return 0;
1320}
1321
1322static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1323{
1324 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1325
1326 /* disable SCLK dpm */
1327 if (!data->sclk_dpm_key_disabled) {
1328 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1329 "Trying to disable SCLK DPM when DPM is disabled",
1330 return 0);
1331 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL);
1332 }
1333
1334 /* disable MCLK dpm */
1335 if (!data->mclk_dpm_key_disabled) {
1336 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1337 "Trying to disable MCLK DPM when DPM is disabled",
1338 return 0);
1339 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL);
1340 }
1341
1342 return 0;
1343}
1344
1345static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1346{
1347 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1348
1349 /* disable general power management */
1350 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1351 GLOBAL_PWRMGT_EN, 0);
1352 /* disable sclk deep sleep */
1353 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1354 DYNAMIC_PM_EN, 0);
1355
1356 /* disable PCIE dpm */
1357 if (!data->pcie_dpm_key_disabled) {
1358 PP_ASSERT_WITH_CODE(
1359 (smum_send_msg_to_smc(hwmgr,
1360 PPSMC_MSG_PCIeDPM_Disable,
1361 NULL) == 0),
1362 "Failed to disable pcie DPM during DPM Stop Function!",
1363 return -EINVAL);
1364 }
1365
1366 smu7_disable_sclk_mclk_dpm(hwmgr);
1367
1368 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1369 "Trying to disable voltage DPM when DPM is disabled",
1370 return 0);
1371
1372 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL);
1373
1374 return 0;
1375}
1376
1377static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1378{
1379 bool protection;
1380 enum DPM_EVENT_SRC src;
1381
1382 switch (sources) {
1383 default:
1384 pr_err("Unknown throttling event sources.");
1385 fallthrough;
1386 case 0:
1387 protection = false;
1388 /* src is unused */
1389 break;
1390 case (1 << PHM_AutoThrottleSource_Thermal):
1391 protection = true;
1392 src = DPM_EVENT_SRC_DIGITAL;
1393 break;
1394 case (1 << PHM_AutoThrottleSource_External):
1395 protection = true;
1396 src = DPM_EVENT_SRC_EXTERNAL;
1397 break;
1398 case (1 << PHM_AutoThrottleSource_External) |
1399 (1 << PHM_AutoThrottleSource_Thermal):
1400 protection = true;
1401 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1402 break;
1403 }
1404 /* Order matters - don't enable thermal protection for the wrong source. */
1405 if (protection) {
1406 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1407 DPM_EVENT_SRC, src);
1408 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1409 THERMAL_PROTECTION_DIS,
1410 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1411 PHM_PlatformCaps_ThermalController));
1412 } else
1413 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1414 THERMAL_PROTECTION_DIS, 1);
1415}
1416
1417static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1418 PHM_AutoThrottleSource source)
1419{
1420 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1421
1422 if (!(data->active_auto_throttle_sources & (1 << source))) {
1423 data->active_auto_throttle_sources |= 1 << source;
1424 smu7_set_dpm_event_sources(hwmgr, sources: data->active_auto_throttle_sources);
1425 }
1426 return 0;
1427}
1428
1429static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1430{
1431 return smu7_enable_auto_throttle_source(hwmgr, source: PHM_AutoThrottleSource_Thermal);
1432}
1433
1434static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1435 PHM_AutoThrottleSource source)
1436{
1437 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1438
1439 if (data->active_auto_throttle_sources & (1 << source)) {
1440 data->active_auto_throttle_sources &= ~(1 << source);
1441 smu7_set_dpm_event_sources(hwmgr, sources: data->active_auto_throttle_sources);
1442 }
1443 return 0;
1444}
1445
1446static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1447{
1448 return smu7_disable_auto_throttle_source(hwmgr, source: PHM_AutoThrottleSource_Thermal);
1449}
1450
1451static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1452{
1453 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1454 data->pcie_performance_request = true;
1455
1456 return 0;
1457}
1458
1459static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr,
1460 uint32_t *cac_config_regs,
1461 AtomCtrl_EDCLeakgeTable *edc_leakage_table)
1462{
1463 uint32_t data, i = 0;
1464
1465 while (cac_config_regs[i] != 0xFFFFFFFF) {
1466 data = edc_leakage_table->DIDT_REG[i];
1467 cgs_write_ind_register(hwmgr->device,
1468 CGS_IND_REG__DIDT,
1469 cac_config_regs[i],
1470 data);
1471 i++;
1472 }
1473
1474 return 0;
1475}
1476
1477static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr)
1478{
1479 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1480 int ret = 0;
1481
1482 if (!data->disable_edc_leakage_controller &&
1483 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
1484 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
1485 ret = smu7_program_edc_didt_registers(hwmgr,
1486 cac_config_regs: DIDTEDCConfig_P12,
1487 edc_leakage_table: &data->edc_leakage_table);
1488 if (ret)
1489 return ret;
1490
1491 ret = smum_send_msg_to_smc(hwmgr,
1492 msg: (PPSMC_Msg)PPSMC_MSG_EnableEDCController,
1493 NULL);
1494 } else {
1495 ret = smum_send_msg_to_smc(hwmgr,
1496 msg: (PPSMC_Msg)PPSMC_MSG_DisableEDCController,
1497 NULL);
1498 }
1499
1500 return ret;
1501}
1502
1503static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
1504{
1505 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1506 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
1507 int32_t tmp_sclk, count, percentage;
1508
1509 if (golden_dpm_table->mclk_table.count == 1) {
1510 percentage = 70;
1511 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value;
1512 } else {
1513 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
1514 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
1515 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
1516 }
1517
1518 tmp_sclk = hwmgr->pstate_mclk * percentage / 100;
1519
1520 if (hwmgr->pp_table_version == PP_TABLE_V0) {
1521 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk =
1522 hwmgr->dyn_state.vddc_dependency_on_sclk;
1523
1524 for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) {
1525 if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) {
1526 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk;
1527 break;
1528 }
1529 }
1530 if (count < 0)
1531 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk;
1532
1533 hwmgr->pstate_sclk_peak =
1534 vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk;
1535 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
1536 struct phm_ppt_v1_information *table_info =
1537 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1538 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk =
1539 table_info->vdd_dep_on_sclk;
1540
1541 for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) {
1542 if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) {
1543 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk;
1544 break;
1545 }
1546 }
1547 if (count < 0)
1548 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk;
1549
1550 hwmgr->pstate_sclk_peak =
1551 vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk;
1552 }
1553
1554 hwmgr->pstate_mclk_peak =
1555 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
1556
1557 /* make sure the output is in Mhz */
1558 hwmgr->pstate_sclk /= 100;
1559 hwmgr->pstate_mclk /= 100;
1560 hwmgr->pstate_sclk_peak /= 100;
1561 hwmgr->pstate_mclk_peak /= 100;
1562}
1563
1564static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1565{
1566 int tmp_result = 0;
1567 int result = 0;
1568
1569 if (smu7_voltage_control(hwmgr)) {
1570 tmp_result = smu7_enable_voltage_control(hwmgr);
1571 PP_ASSERT_WITH_CODE(tmp_result == 0,
1572 "Failed to enable voltage control!",
1573 result = tmp_result);
1574
1575 tmp_result = smu7_construct_voltage_tables(hwmgr);
1576 PP_ASSERT_WITH_CODE((0 == tmp_result),
1577 "Failed to construct voltage tables!",
1578 result = tmp_result);
1579 }
1580 smum_initialize_mc_reg_table(hwmgr);
1581
1582 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1583 c: PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1584 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1585 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1586
1587 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1588 c: PHM_PlatformCaps_ThermalController))
1589 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1590 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1591
1592 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1593 PP_ASSERT_WITH_CODE((0 == tmp_result),
1594 "Failed to program static screen threshold parameters!",
1595 result = tmp_result);
1596
1597 tmp_result = smu7_enable_display_gap(hwmgr);
1598 PP_ASSERT_WITH_CODE((0 == tmp_result),
1599 "Failed to enable display gap!", result = tmp_result);
1600
1601 tmp_result = smu7_program_voting_clients(hwmgr);
1602 PP_ASSERT_WITH_CODE((0 == tmp_result),
1603 "Failed to program voting clients!", result = tmp_result);
1604
1605 tmp_result = smum_process_firmware_header(hwmgr);
1606 PP_ASSERT_WITH_CODE((0 == tmp_result),
1607 "Failed to process firmware header!", result = tmp_result);
1608
1609 if (hwmgr->chip_id != CHIP_VEGAM) {
1610 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1611 PP_ASSERT_WITH_CODE((0 == tmp_result),
1612 "Failed to initialize switch from ArbF0 to F1!",
1613 result = tmp_result);
1614 }
1615
1616 result = smu7_setup_default_dpm_tables(hwmgr);
1617 PP_ASSERT_WITH_CODE(0 == result,
1618 "Failed to setup default DPM tables!", return result);
1619
1620 tmp_result = smum_init_smc_table(hwmgr);
1621 PP_ASSERT_WITH_CODE((0 == tmp_result),
1622 "Failed to initialize SMC table!", result = tmp_result);
1623
1624 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1625 PP_ASSERT_WITH_CODE((0 == tmp_result),
1626 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1627
1628 if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1629 hwmgr->chip_id <= CHIP_VEGAM) {
1630 tmp_result = smu7_notify_has_display(hwmgr);
1631 PP_ASSERT_WITH_CODE((0 == tmp_result),
1632 "Failed to enable display setting!", result = tmp_result);
1633 } else {
1634 smum_send_msg_to_smc(hwmgr, msg: (PPSMC_Msg)PPSMC_NoDisplay, NULL);
1635 }
1636
1637 if (hwmgr->chip_id >= CHIP_POLARIS10 &&
1638 hwmgr->chip_id <= CHIP_VEGAM) {
1639 tmp_result = smu7_populate_edc_leakage_registers(hwmgr);
1640 PP_ASSERT_WITH_CODE((0 == tmp_result),
1641 "Failed to populate edc leakage registers!", result = tmp_result);
1642 }
1643
1644 tmp_result = smu7_enable_sclk_control(hwmgr);
1645 PP_ASSERT_WITH_CODE((0 == tmp_result),
1646 "Failed to enable SCLK control!", result = tmp_result);
1647
1648 tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1649 PP_ASSERT_WITH_CODE((0 == tmp_result),
1650 "Failed to enable voltage control!", result = tmp_result);
1651
1652 tmp_result = smu7_enable_ulv(hwmgr);
1653 PP_ASSERT_WITH_CODE((0 == tmp_result),
1654 "Failed to enable ULV!", result = tmp_result);
1655
1656 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1657 PP_ASSERT_WITH_CODE((0 == tmp_result),
1658 "Failed to enable deep sleep master switch!", result = tmp_result);
1659
1660 tmp_result = smu7_enable_didt_config(hwmgr);
1661 PP_ASSERT_WITH_CODE((tmp_result == 0),
1662 "Failed to enable deep sleep master switch!", result = tmp_result);
1663
1664 tmp_result = smu7_start_dpm(hwmgr);
1665 PP_ASSERT_WITH_CODE((0 == tmp_result),
1666 "Failed to start DPM!", result = tmp_result);
1667
1668 tmp_result = smu7_enable_smc_cac(hwmgr);
1669 PP_ASSERT_WITH_CODE((0 == tmp_result),
1670 "Failed to enable SMC CAC!", result = tmp_result);
1671
1672 tmp_result = smu7_enable_power_containment(hwmgr);
1673 PP_ASSERT_WITH_CODE((0 == tmp_result),
1674 "Failed to enable power containment!", result = tmp_result);
1675
1676 tmp_result = smu7_power_control_set_level(hwmgr);
1677 PP_ASSERT_WITH_CODE((0 == tmp_result),
1678 "Failed to power control set level!", result = tmp_result);
1679
1680 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1681 PP_ASSERT_WITH_CODE((0 == tmp_result),
1682 "Failed to enable thermal auto throttle!", result = tmp_result);
1683
1684 tmp_result = smu7_pcie_performance_request(hwmgr);
1685 PP_ASSERT_WITH_CODE((0 == tmp_result),
1686 "pcie performance request failed!", result = tmp_result);
1687
1688 smu7_populate_umdpstate_clocks(hwmgr);
1689
1690 return 0;
1691}
1692
1693static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1694{
1695 if (!hwmgr->avfs_supported)
1696 return 0;
1697
1698 if (enable) {
1699 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1700 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1701 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1702 hwmgr, PPSMC_MSG_EnableAvfs, NULL),
1703 "Failed to enable AVFS!",
1704 return -EINVAL);
1705 }
1706 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1707 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1708 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1709 hwmgr, PPSMC_MSG_DisableAvfs, NULL),
1710 "Failed to disable AVFS!",
1711 return -EINVAL);
1712 }
1713
1714 return 0;
1715}
1716
1717static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1718{
1719 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1720
1721 if (!hwmgr->avfs_supported)
1722 return 0;
1723
1724 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1725 smu7_avfs_control(hwmgr, enable: false);
1726 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1727 smu7_avfs_control(hwmgr, enable: false);
1728 smu7_avfs_control(hwmgr, enable: true);
1729 } else {
1730 smu7_avfs_control(hwmgr, enable: true);
1731 }
1732
1733 return 0;
1734}
1735
1736static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1737{
1738 int tmp_result, result = 0;
1739
1740 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1741 c: PHM_PlatformCaps_ThermalController))
1742 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1743 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1744
1745 tmp_result = smu7_disable_power_containment(hwmgr);
1746 PP_ASSERT_WITH_CODE((tmp_result == 0),
1747 "Failed to disable power containment!", result = tmp_result);
1748
1749 tmp_result = smu7_disable_smc_cac(hwmgr);
1750 PP_ASSERT_WITH_CODE((tmp_result == 0),
1751 "Failed to disable SMC CAC!", result = tmp_result);
1752
1753 tmp_result = smu7_disable_didt_config(hwmgr);
1754 PP_ASSERT_WITH_CODE((tmp_result == 0),
1755 "Failed to disable DIDT!", result = tmp_result);
1756
1757 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1758 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1759 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1760 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1761
1762 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1763 PP_ASSERT_WITH_CODE((tmp_result == 0),
1764 "Failed to disable thermal auto throttle!", result = tmp_result);
1765
1766 tmp_result = smu7_avfs_control(hwmgr, enable: false);
1767 PP_ASSERT_WITH_CODE((tmp_result == 0),
1768 "Failed to disable AVFS!", result = tmp_result);
1769
1770 tmp_result = smu7_stop_dpm(hwmgr);
1771 PP_ASSERT_WITH_CODE((tmp_result == 0),
1772 "Failed to stop DPM!", result = tmp_result);
1773
1774 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1775 PP_ASSERT_WITH_CODE((tmp_result == 0),
1776 "Failed to disable deep sleep master switch!", result = tmp_result);
1777
1778 tmp_result = smu7_disable_ulv(hwmgr);
1779 PP_ASSERT_WITH_CODE((tmp_result == 0),
1780 "Failed to disable ULV!", result = tmp_result);
1781
1782 tmp_result = smu7_clear_voting_clients(hwmgr);
1783 PP_ASSERT_WITH_CODE((tmp_result == 0),
1784 "Failed to clear voting clients!", result = tmp_result);
1785
1786 tmp_result = smu7_reset_to_default(hwmgr);
1787 PP_ASSERT_WITH_CODE((tmp_result == 0),
1788 "Failed to reset to default!", result = tmp_result);
1789
1790 tmp_result = smum_stop_smc(hwmgr);
1791 PP_ASSERT_WITH_CODE((tmp_result == 0),
1792 "Failed to stop smc!", result = tmp_result);
1793
1794 tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1795 PP_ASSERT_WITH_CODE((tmp_result == 0),
1796 "Failed to force to switch arbf0!", result = tmp_result);
1797
1798 return result;
1799}
1800
1801static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1802{
1803 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1804 struct phm_ppt_v1_information *table_info =
1805 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1806 struct amdgpu_device *adev = hwmgr->adev;
1807 uint8_t tmp1, tmp2;
1808 uint16_t tmp3 = 0;
1809
1810 data->dll_default_on = false;
1811 data->mclk_dpm0_activity_target = 0xa;
1812 data->vddc_vddgfx_delta = 300;
1813 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1814 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1815 data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1816 data->voting_rights_clients[1] = SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1817 data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1818 data->voting_rights_clients[3] = SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1819 data->voting_rights_clients[4] = SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1820 data->voting_rights_clients[5] = SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1821 data->voting_rights_clients[6] = SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1822 data->voting_rights_clients[7] = SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1823
1824 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1825 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1826 data->pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
1827 /* need to set voltage control types before EVV patching */
1828 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1829 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1830 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1831 data->enable_tdc_limit_feature = true;
1832 data->enable_pkg_pwr_tracking_feature = true;
1833 data->force_pcie_gen = PP_PCIEGenInvalid;
1834 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1835 data->current_profile_setting.bupdate_sclk = 1;
1836 data->current_profile_setting.sclk_up_hyst = 0;
1837 data->current_profile_setting.sclk_down_hyst = 100;
1838 data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1839 data->current_profile_setting.bupdate_mclk = 1;
1840 if (hwmgr->chip_id >= CHIP_POLARIS10) {
1841 if (adev->gmc.vram_width == 256) {
1842 data->current_profile_setting.mclk_up_hyst = 10;
1843 data->current_profile_setting.mclk_down_hyst = 60;
1844 data->current_profile_setting.mclk_activity = 25;
1845 } else if (adev->gmc.vram_width == 128) {
1846 data->current_profile_setting.mclk_up_hyst = 5;
1847 data->current_profile_setting.mclk_down_hyst = 16;
1848 data->current_profile_setting.mclk_activity = 20;
1849 } else if (adev->gmc.vram_width == 64) {
1850 data->current_profile_setting.mclk_up_hyst = 3;
1851 data->current_profile_setting.mclk_down_hyst = 16;
1852 data->current_profile_setting.mclk_activity = 20;
1853 }
1854 } else {
1855 data->current_profile_setting.mclk_up_hyst = 0;
1856 data->current_profile_setting.mclk_down_hyst = 100;
1857 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1858 }
1859 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1860 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1861 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1862
1863 if (hwmgr->chip_id == CHIP_HAWAII) {
1864 data->thermal_temp_setting.temperature_low = 94500;
1865 data->thermal_temp_setting.temperature_high = 95000;
1866 data->thermal_temp_setting.temperature_shutdown = 104000;
1867 } else {
1868 data->thermal_temp_setting.temperature_low = 99500;
1869 data->thermal_temp_setting.temperature_high = 100000;
1870 data->thermal_temp_setting.temperature_shutdown = 104000;
1871 }
1872
1873 data->fast_watermark_threshold = 100;
1874 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1875 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1876 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1877 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1878 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1879 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1880
1881 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1882 c: PHM_PlatformCaps_ControlVDDGFX)) {
1883 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1884 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1885 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1886 }
1887 }
1888
1889 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1890 c: PHM_PlatformCaps_EnableMVDDControl)) {
1891 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1892 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1893 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1894 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1895 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1896 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1897 }
1898
1899 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1900 phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps,
1901 c: PHM_PlatformCaps_ControlVDDGFX);
1902
1903 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
1904 c: PHM_PlatformCaps_ControlVDDCI)) {
1905 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1906 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1907 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1908 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1909 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1910 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1911 }
1912
1913 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1914 phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps,
1915 c: PHM_PlatformCaps_EnableMVDDControl);
1916
1917 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1918 phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps,
1919 c: PHM_PlatformCaps_ControlVDDCI);
1920
1921 data->vddc_phase_shed_control = 1;
1922 if ((hwmgr->chip_id == CHIP_POLARIS12) ||
1923 ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1924 ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
1925 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
1926 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
1927 if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1928 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, svd_gpio_id: &tmp1, svc_gpio_id: &tmp2,
1929 load_line: &tmp3);
1930 tmp3 = (tmp3 >> 5) & 0x3;
1931 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1932 }
1933 } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1934 data->vddc_phase_shed_control = 1;
1935 }
1936
1937 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1938 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1939 phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps,
1940 c: PHM_PlatformCaps_ClockStretcher);
1941
1942 data->pcie_gen_performance.max = PP_PCIEGen1;
1943 data->pcie_gen_performance.min = PP_PCIEGen3;
1944 data->pcie_gen_power_saving.max = PP_PCIEGen1;
1945 data->pcie_gen_power_saving.min = PP_PCIEGen3;
1946 data->pcie_lane_performance.max = 0;
1947 data->pcie_lane_performance.min = 16;
1948 data->pcie_lane_power_saving.max = 0;
1949 data->pcie_lane_power_saving.min = 16;
1950
1951
1952 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1953 phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps,
1954 c: PHM_PlatformCaps_UVDPowerGating);
1955 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1956 phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps,
1957 c: PHM_PlatformCaps_VCEPowerGating);
1958
1959 data->disable_edc_leakage_controller = true;
1960 if (((adev->asic_type == CHIP_POLARIS10) && hwmgr->is_kicker) ||
1961 ((adev->asic_type == CHIP_POLARIS11) && hwmgr->is_kicker) ||
1962 (adev->asic_type == CHIP_POLARIS12) ||
1963 (adev->asic_type == CHIP_VEGAM))
1964 data->disable_edc_leakage_controller = false;
1965
1966 if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) {
1967 phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps,
1968 c: PHM_PlatformCaps_MemorySpreadSpectrumSupport);
1969 phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps,
1970 c: PHM_PlatformCaps_EngineSpreadSpectrumSupport);
1971 }
1972
1973 if ((adev->pdev->device == 0x699F) &&
1974 (adev->pdev->revision == 0xCF)) {
1975 phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps,
1976 c: PHM_PlatformCaps_PowerContainment);
1977 data->enable_tdc_limit_feature = false;
1978 data->enable_pkg_pwr_tracking_feature = false;
1979 data->disable_edc_leakage_controller = true;
1980 phm_cap_unset(caps: hwmgr->platform_descriptor.platformCaps,
1981 c: PHM_PlatformCaps_ClockStretcher);
1982 }
1983}
1984
1985static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
1986{
1987 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1988 struct amdgpu_device *adev = hwmgr->adev;
1989 uint32_t asicrev1, evv_revision, max = 0, min = 0;
1990
1991 atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB, STRAP_EVV_REVISION_MSB,
1992 efuse: &evv_revision);
1993
1994 atomctrl_read_efuse(hwmgr, start_index: 568, end_index: 579, efuse: &asicrev1);
1995
1996 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1997 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) {
1998 min = 1200;
1999 max = 2500;
2000 } else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
2001 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
2002 min = 900;
2003 max = 2100;
2004 } else if (hwmgr->chip_id == CHIP_POLARIS10) {
2005 if (adev->pdev->subsystem_vendor == 0x106B) {
2006 min = 1000;
2007 max = 2300;
2008 } else {
2009 if (evv_revision == 0) {
2010 min = 1000;
2011 max = 2300;
2012 } else if (evv_revision == 1) {
2013 if (asicrev1 == 326) {
2014 min = 1200;
2015 max = 2500;
2016 /* TODO: PATCH RO in VBIOS */
2017 } else {
2018 min = 1200;
2019 max = 2000;
2020 }
2021 } else if (evv_revision == 2) {
2022 min = 1200;
2023 max = 2500;
2024 }
2025 }
2026 } else {
2027 min = 1100;
2028 max = 2100;
2029 }
2030
2031 data->ro_range_minimum = min;
2032 data->ro_range_maximum = max;
2033
2034 /* TODO: PATCH RO in VBIOS here */
2035
2036 return 0;
2037}
2038
2039/**
2040 * smu7_get_evv_voltages - Get Leakage VDDC based on leakage ID.
2041 *
2042 * @hwmgr: the address of the powerplay hardware manager.
2043 * Return: always 0
2044 */
2045static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
2046{
2047 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2048 uint16_t vv_id;
2049 uint16_t vddc = 0;
2050 uint16_t vddgfx = 0;
2051 uint16_t i, j;
2052 uint32_t sclk = 0;
2053 struct phm_ppt_v1_information *table_info =
2054 (struct phm_ppt_v1_information *)hwmgr->pptable;
2055 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
2056
2057 if (hwmgr->chip_id == CHIP_POLARIS10 ||
2058 hwmgr->chip_id == CHIP_POLARIS11 ||
2059 hwmgr->chip_id == CHIP_POLARIS12)
2060 smu7_calculate_ro_range(hwmgr);
2061
2062 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2063 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2064
2065 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2066 if ((hwmgr->pp_table_version == PP_TABLE_V1)
2067 && !phm_get_sclk_for_voltage_evv(hwmgr,
2068 lookup_table: table_info->vddgfx_lookup_table, virtual_voltage_id: vv_id, sclk: &sclk)) {
2069 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
2070 c: PHM_PlatformCaps_ClockStretcher)) {
2071 sclk_table = table_info->vdd_dep_on_sclk;
2072
2073 for (j = 1; j < sclk_table->count; j++) {
2074 if (sclk_table->entries[j].clk == sclk &&
2075 sclk_table->entries[j].cks_enable == 0) {
2076 sclk += 5000;
2077 break;
2078 }
2079 }
2080 }
2081 if (0 == atomctrl_get_voltage_evv_on_sclk
2082 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
2083 virtual_voltage_Id: vv_id, voltage: &vddgfx)) {
2084 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
2085 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
2086
2087 /* the voltage should not be zero nor equal to leakage ID */
2088 if (vddgfx != 0 && vddgfx != vv_id) {
2089 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
2090 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
2091 data->vddcgfx_leakage.count++;
2092 }
2093 } else {
2094 pr_info("Error retrieving EVV voltage value!\n");
2095 }
2096 }
2097 } else {
2098 if ((hwmgr->pp_table_version == PP_TABLE_V0)
2099 || !phm_get_sclk_for_voltage_evv(hwmgr,
2100 lookup_table: table_info->vddc_lookup_table, virtual_voltage_id: vv_id, sclk: &sclk)) {
2101 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
2102 c: PHM_PlatformCaps_ClockStretcher)) {
2103 if (table_info == NULL)
2104 return -EINVAL;
2105 sclk_table = table_info->vdd_dep_on_sclk;
2106
2107 for (j = 1; j < sclk_table->count; j++) {
2108 if (sclk_table->entries[j].clk == sclk &&
2109 sclk_table->entries[j].cks_enable == 0) {
2110 sclk += 5000;
2111 break;
2112 }
2113 }
2114 }
2115
2116 if (phm_get_voltage_evv_on_sclk(hwmgr,
2117 VOLTAGE_TYPE_VDDC,
2118 sclk, id: vv_id, voltage: &vddc) == 0) {
2119 if (vddc >= 2000 || vddc == 0)
2120 return -EINVAL;
2121 } else {
2122 pr_debug("failed to retrieving EVV voltage!\n");
2123 continue;
2124 }
2125
2126 /* the voltage should not be zero nor equal to leakage ID */
2127 if (vddc != 0 && vddc != vv_id) {
2128 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
2129 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2130 data->vddc_leakage.count++;
2131 }
2132 }
2133 }
2134 }
2135
2136 return 0;
2137}
2138
2139/**
2140 * smu7_patch_ppt_v1_with_vdd_leakage - Change virtual leakage voltage to actual value.
2141 *
2142 * @hwmgr: the address of the powerplay hardware manager.
2143 * @voltage: pointer to changing voltage
2144 * @leakage_table: pointer to leakage table
2145 */
2146static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2147 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
2148{
2149 uint32_t index;
2150
2151 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2152 for (index = 0; index < leakage_table->count; index++) {
2153 /* if this voltage matches a leakage voltage ID */
2154 /* patch with actual leakage voltage */
2155 if (leakage_table->leakage_id[index] == *voltage) {
2156 *voltage = leakage_table->actual_voltage[index];
2157 break;
2158 }
2159 }
2160
2161 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2162 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
2163}
2164
2165/**
2166 * smu7_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
2167 *
2168 * @hwmgr: the address of the powerplay hardware manager.
2169 * @lookup_table: pointer to voltage lookup table
2170 * @leakage_table: pointer to leakage table
2171 * Return: always 0
2172 */
2173static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2174 phm_ppt_v1_voltage_lookup_table *lookup_table,
2175 struct smu7_leakage_voltage *leakage_table)
2176{
2177 uint32_t i;
2178
2179 for (i = 0; i < lookup_table->count; i++)
2180 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2181 voltage: &lookup_table->entries[i].us_vdd, leakage_table);
2182
2183 return 0;
2184}
2185
2186static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
2187 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
2188 uint16_t *vddc)
2189{
2190 struct phm_ppt_v1_information *table_info =
2191 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2192 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, voltage: (uint16_t *)vddc, leakage_table);
2193 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2194 table_info->max_clock_voltage_on_dc.vddc;
2195 return 0;
2196}
2197
2198static int smu7_patch_voltage_dependency_tables_with_lookup_table(
2199 struct pp_hwmgr *hwmgr)
2200{
2201 uint8_t entry_id;
2202 uint8_t voltage_id;
2203 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2204 struct phm_ppt_v1_information *table_info =
2205 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2206
2207 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2208 table_info->vdd_dep_on_sclk;
2209 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2210 table_info->vdd_dep_on_mclk;
2211 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2212 table_info->mm_dep_table;
2213
2214 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2215 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2216 voltage_id = sclk_table->entries[entry_id].vddInd;
2217 sclk_table->entries[entry_id].vddgfx =
2218 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
2219 }
2220 } else {
2221 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2222 voltage_id = sclk_table->entries[entry_id].vddInd;
2223 sclk_table->entries[entry_id].vddc =
2224 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2225 }
2226 }
2227
2228 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
2229 voltage_id = mclk_table->entries[entry_id].vddInd;
2230 mclk_table->entries[entry_id].vddc =
2231 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2232 }
2233
2234 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
2235 voltage_id = mm_table->entries[entry_id].vddcInd;
2236 mm_table->entries[entry_id].vddc =
2237 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
2238 }
2239
2240 return 0;
2241
2242}
2243
2244static int phm_add_voltage(struct pp_hwmgr *hwmgr,
2245 phm_ppt_v1_voltage_lookup_table *look_up_table,
2246 phm_ppt_v1_voltage_lookup_record *record)
2247{
2248 uint32_t i;
2249
2250 PP_ASSERT_WITH_CODE((NULL != look_up_table),
2251 "Lookup Table empty.", return -EINVAL);
2252 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
2253 "Lookup Table empty.", return -EINVAL);
2254
2255 i = smum_get_mac_definition(hwmgr, value: SMU_MAX_LEVELS_VDDGFX);
2256 PP_ASSERT_WITH_CODE((i >= look_up_table->count),
2257 "Lookup Table is full.", return -EINVAL);
2258
2259 /* This is to avoid entering duplicate calculated records. */
2260 for (i = 0; i < look_up_table->count; i++) {
2261 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
2262 if (look_up_table->entries[i].us_calculated == 1)
2263 return 0;
2264 break;
2265 }
2266 }
2267
2268 look_up_table->entries[i].us_calculated = 1;
2269 look_up_table->entries[i].us_vdd = record->us_vdd;
2270 look_up_table->entries[i].us_cac_low = record->us_cac_low;
2271 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
2272 look_up_table->entries[i].us_cac_high = record->us_cac_high;
2273 /* Only increment the count when we're appending, not replacing duplicate entry. */
2274 if (i == look_up_table->count)
2275 look_up_table->count++;
2276
2277 return 0;
2278}
2279
2280
2281static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2282{
2283 uint8_t entry_id;
2284 struct phm_ppt_v1_voltage_lookup_record v_record;
2285 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2286 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2287
2288 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
2289 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
2290
2291 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2292 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
2293 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
2294 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
2295 sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
2296 else
2297 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
2298 sclk_table->entries[entry_id].vdd_offset;
2299
2300 sclk_table->entries[entry_id].vddc =
2301 v_record.us_cac_low = v_record.us_cac_mid =
2302 v_record.us_cac_high = v_record.us_vdd;
2303
2304 phm_add_voltage(hwmgr, look_up_table: pptable_info->vddc_lookup_table, record: &v_record);
2305 }
2306
2307 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
2308 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
2309 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
2310 mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
2311 else
2312 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
2313 mclk_table->entries[entry_id].vdd_offset;
2314
2315 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
2316 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
2317 phm_add_voltage(hwmgr, look_up_table: pptable_info->vddgfx_lookup_table, record: &v_record);
2318 }
2319 }
2320 return 0;
2321}
2322
2323static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2324{
2325 uint8_t entry_id;
2326 struct phm_ppt_v1_voltage_lookup_record v_record;
2327 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2328 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2329 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
2330
2331 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2332 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
2333 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
2334 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2335 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
2336 else
2337 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2338 mm_table->entries[entry_id].vddgfx_offset;
2339
2340 /* Add the calculated VDDGFX to the VDDGFX lookup table */
2341 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
2342 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
2343 phm_add_voltage(hwmgr, look_up_table: pptable_info->vddgfx_lookup_table, record: &v_record);
2344 }
2345 }
2346 return 0;
2347}
2348
2349static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
2350 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2351{
2352 uint32_t table_size, i, j;
2353 table_size = lookup_table->count;
2354
2355 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2356 "Lookup table is empty", return -EINVAL);
2357
2358 /* Sorting voltages */
2359 for (i = 0; i < table_size - 1; i++) {
2360 for (j = i + 1; j > 0; j--) {
2361 if (lookup_table->entries[j].us_vdd <
2362 lookup_table->entries[j - 1].us_vdd) {
2363 swap(lookup_table->entries[j - 1],
2364 lookup_table->entries[j]);
2365 }
2366 }
2367 }
2368
2369 return 0;
2370}
2371
2372static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2373{
2374 int result = 0;
2375 int tmp_result;
2376 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2377 struct phm_ppt_v1_information *table_info =
2378 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2379
2380 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2381 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2382 lookup_table: table_info->vddgfx_lookup_table, leakage_table: &(data->vddcgfx_leakage));
2383 if (tmp_result != 0)
2384 result = tmp_result;
2385
2386 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2387 voltage: &table_info->max_clock_voltage_on_dc.vddgfx, leakage_table: &(data->vddcgfx_leakage));
2388 } else {
2389
2390 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2391 lookup_table: table_info->vddc_lookup_table, leakage_table: &(data->vddc_leakage));
2392 if (tmp_result)
2393 result = tmp_result;
2394
2395 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2396 leakage_table: &(data->vddc_leakage), vddc: &table_info->max_clock_voltage_on_dc.vddc);
2397 if (tmp_result)
2398 result = tmp_result;
2399 }
2400
2401 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2402 if (tmp_result)
2403 result = tmp_result;
2404
2405 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2406 if (tmp_result)
2407 result = tmp_result;
2408
2409 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2410 if (tmp_result)
2411 result = tmp_result;
2412
2413 tmp_result = smu7_sort_lookup_table(hwmgr, lookup_table: table_info->vddgfx_lookup_table);
2414 if (tmp_result)
2415 result = tmp_result;
2416
2417 tmp_result = smu7_sort_lookup_table(hwmgr, lookup_table: table_info->vddc_lookup_table);
2418 if (tmp_result)
2419 result = tmp_result;
2420
2421 return result;
2422}
2423
2424static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr)
2425{
2426 struct phm_ppt_v1_information *table_info =
2427 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2428 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2429 table_info->vdd_dep_on_sclk;
2430 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
2431 table_info->vddc_lookup_table;
2432 uint16_t highest_voltage;
2433 uint32_t i;
2434
2435 highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2436
2437 for (i = 0; i < lookup_table->count; i++) {
2438 if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 &&
2439 lookup_table->entries[i].us_vdd > highest_voltage)
2440 highest_voltage = lookup_table->entries[i].us_vdd;
2441 }
2442
2443 return highest_voltage;
2444}
2445
2446static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2447{
2448 struct phm_ppt_v1_information *table_info =
2449 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2450
2451 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2452 table_info->vdd_dep_on_sclk;
2453 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2454 table_info->vdd_dep_on_mclk;
2455
2456 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2457 "VDD dependency on SCLK table is missing.",
2458 return -EINVAL);
2459 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2460 "VDD dependency on SCLK table has to have is missing.",
2461 return -EINVAL);
2462
2463 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2464 "VDD dependency on MCLK table is missing",
2465 return -EINVAL);
2466 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2467 "VDD dependency on MCLK table has to have is missing.",
2468 return -EINVAL);
2469
2470 table_info->max_clock_voltage_on_ac.sclk =
2471 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2472 table_info->max_clock_voltage_on_ac.mclk =
2473 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2474 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
2475 table_info->max_clock_voltage_on_ac.vddc =
2476 smu7_find_highest_vddc(hwmgr);
2477 else
2478 table_info->max_clock_voltage_on_ac.vddc =
2479 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2480 table_info->max_clock_voltage_on_ac.vddci =
2481 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2482
2483 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2484 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2485 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2486 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2487
2488 return 0;
2489}
2490
2491static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2492{
2493 struct phm_ppt_v1_information *table_info =
2494 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2495 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2496 struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2497 uint32_t i;
2498 uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2499 struct amdgpu_device *adev = hwmgr->adev;
2500
2501 if (table_info != NULL) {
2502 dep_mclk_table = table_info->vdd_dep_on_mclk;
2503 lookup_table = table_info->vddc_lookup_table;
2504 } else
2505 return 0;
2506
2507 hw_revision = adev->pdev->revision;
2508 sub_sys_id = adev->pdev->subsystem_device;
2509 sub_vendor_id = adev->pdev->subsystem_vendor;
2510
2511 if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 &&
2512 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2513 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2514 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2515
2516 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
2517 CGS_IND_REG__SMC,
2518 PWR_CKS_CNTL,
2519 CKS_STRETCH_AMOUNT,
2520 0x3);
2521
2522 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2523 return 0;
2524
2525 for (i = 0; i < lookup_table->count; i++) {
2526 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2527 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2528 return 0;
2529 }
2530 }
2531 }
2532 return 0;
2533}
2534
2535static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2536{
2537 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2538 uint32_t temp_reg;
2539 struct phm_ppt_v1_information *table_info =
2540 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2541
2542
2543 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, gpio_pin_assignment: &gpio_pin_assignment)) {
2544 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2545 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2546 case 0:
2547 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2548 break;
2549 case 1:
2550 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2551 break;
2552 case 2:
2553 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2554 break;
2555 case 3:
2556 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2557 break;
2558 case 4:
2559 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2560 break;
2561 default:
2562 break;
2563 }
2564 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2565 }
2566
2567 if (table_info == NULL)
2568 return 0;
2569
2570 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2571 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2572 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2573 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2574
2575 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2576 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2577
2578 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2579
2580 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2581
2582 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2583 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2584
2585 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2586
2587 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2588 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2589
2590 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2591 table_info->cac_dtp_table->usOperatingTempStep = 1;
2592 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2593
2594 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2595 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2596
2597 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2598 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2599
2600 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2601 table_info->cac_dtp_table->usOperatingTempMinLimit;
2602
2603 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2604 table_info->cac_dtp_table->usOperatingTempMaxLimit;
2605
2606 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2607 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2608
2609 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2610 table_info->cac_dtp_table->usOperatingTempStep;
2611
2612 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2613 table_info->cac_dtp_table->usTargetOperatingTemp;
2614 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2615 phm_cap_set(caps: hwmgr->platform_descriptor.platformCaps,
2616 c: PHM_PlatformCaps_ODFuzzyFanControlSupport);
2617 }
2618
2619 return 0;
2620}
2621
2622/**
2623 * smu7_patch_ppt_v0_with_vdd_leakage - Change virtual leakage voltage to actual value.
2624 *
2625 * @hwmgr: the address of the powerplay hardware manager.
2626 * @voltage: pointer to changing voltage
2627 * @leakage_table: pointer to leakage table
2628 */
2629static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2630 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2631{
2632 uint32_t index;
2633
2634 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2635 for (index = 0; index < leakage_table->count; index++) {
2636 /* if this voltage matches a leakage voltage ID */
2637 /* patch with actual leakage voltage */
2638 if (leakage_table->leakage_id[index] == *voltage) {
2639 *voltage = leakage_table->actual_voltage[index];
2640 break;
2641 }
2642 }
2643
2644 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2645 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
2646}
2647
2648
2649static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2650 struct phm_clock_voltage_dependency_table *tab)
2651{
2652 uint16_t i;
2653 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2654
2655 if (tab)
2656 for (i = 0; i < tab->count; i++)
2657 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &tab->entries[i].v,
2658 leakage_table: &data->vddc_leakage);
2659
2660 return 0;
2661}
2662
2663static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2664 struct phm_clock_voltage_dependency_table *tab)
2665{
2666 uint16_t i;
2667 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2668
2669 if (tab)
2670 for (i = 0; i < tab->count; i++)
2671 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &tab->entries[i].v,
2672 leakage_table: &data->vddci_leakage);
2673
2674 return 0;
2675}
2676
2677static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2678 struct phm_vce_clock_voltage_dependency_table *tab)
2679{
2680 uint16_t i;
2681 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2682
2683 if (tab)
2684 for (i = 0; i < tab->count; i++)
2685 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &tab->entries[i].v,
2686 leakage_table: &data->vddc_leakage);
2687
2688 return 0;
2689}
2690
2691
2692static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2693 struct phm_uvd_clock_voltage_dependency_table *tab)
2694{
2695 uint16_t i;
2696 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2697
2698 if (tab)
2699 for (i = 0; i < tab->count; i++)
2700 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &tab->entries[i].v,
2701 leakage_table: &data->vddc_leakage);
2702
2703 return 0;
2704}
2705
2706static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2707 struct phm_phase_shedding_limits_table *tab)
2708{
2709 uint16_t i;
2710 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2711
2712 if (tab)
2713 for (i = 0; i < tab->count; i++)
2714 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &tab->entries[i].Voltage,
2715 leakage_table: &data->vddc_leakage);
2716
2717 return 0;
2718}
2719
2720static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2721 struct phm_samu_clock_voltage_dependency_table *tab)
2722{
2723 uint16_t i;
2724 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2725
2726 if (tab)
2727 for (i = 0; i < tab->count; i++)
2728 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &tab->entries[i].v,
2729 leakage_table: &data->vddc_leakage);
2730
2731 return 0;
2732}
2733
2734static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2735 struct phm_acp_clock_voltage_dependency_table *tab)
2736{
2737 uint16_t i;
2738 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2739
2740 if (tab)
2741 for (i = 0; i < tab->count; i++)
2742 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &tab->entries[i].v,
2743 leakage_table: &data->vddc_leakage);
2744
2745 return 0;
2746}
2747
2748static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2749 struct phm_clock_and_voltage_limits *tab)
2750{
2751 uint32_t vddc, vddci;
2752 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2753
2754 if (tab) {
2755 vddc = tab->vddc;
2756 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &vddc,
2757 leakage_table: &data->vddc_leakage);
2758 tab->vddc = vddc;
2759 vddci = tab->vddci;
2760 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &vddci,
2761 leakage_table: &data->vddci_leakage);
2762 tab->vddci = vddci;
2763 }
2764
2765 return 0;
2766}
2767
2768static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2769{
2770 uint32_t i;
2771 uint32_t vddc;
2772 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2773
2774 if (tab) {
2775 for (i = 0; i < tab->count; i++) {
2776 vddc = (uint32_t)(tab->entries[i].Vddc);
2777 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, voltage: &vddc, leakage_table: &data->vddc_leakage);
2778 tab->entries[i].Vddc = (uint16_t)vddc;
2779 }
2780 }
2781
2782 return 0;
2783}
2784
2785static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2786{
2787 int tmp;
2788
2789 tmp = smu7_patch_vddc(hwmgr, tab: hwmgr->dyn_state.vddc_dependency_on_sclk);
2790 if (tmp)
2791 return -EINVAL;
2792
2793 tmp = smu7_patch_vddc(hwmgr, tab: hwmgr->dyn_state.vddc_dependency_on_mclk);
2794 if (tmp)
2795 return -EINVAL;
2796
2797 tmp = smu7_patch_vddc(hwmgr, tab: hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2798 if (tmp)
2799 return -EINVAL;
2800
2801 tmp = smu7_patch_vddci(hwmgr, tab: hwmgr->dyn_state.vddci_dependency_on_mclk);
2802 if (tmp)
2803 return -EINVAL;
2804
2805 tmp = smu7_patch_vce_vddc(hwmgr, tab: hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2806 if (tmp)
2807 return -EINVAL;
2808
2809 tmp = smu7_patch_uvd_vddc(hwmgr, tab: hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2810 if (tmp)
2811 return -EINVAL;
2812
2813 tmp = smu7_patch_samu_vddc(hwmgr, tab: hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2814 if (tmp)
2815 return -EINVAL;
2816
2817 tmp = smu7_patch_acp_vddc(hwmgr, tab: hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2818 if (tmp)
2819 return -EINVAL;
2820
2821 tmp = smu7_patch_vddc_shed_limit(hwmgr, tab: hwmgr->dyn_state.vddc_phase_shed_limits_table);
2822 if (tmp)
2823 return -EINVAL;
2824
2825 tmp = smu7_patch_limits_vddc(hwmgr, tab: &hwmgr->dyn_state.max_clock_voltage_on_ac);
2826 if (tmp)
2827 return -EINVAL;
2828
2829 tmp = smu7_patch_limits_vddc(hwmgr, tab: &hwmgr->dyn_state.max_clock_voltage_on_dc);
2830 if (tmp)
2831 return -EINVAL;
2832
2833 tmp = smu7_patch_cac_vddc(hwmgr, tab: hwmgr->dyn_state.cac_leakage_table);
2834 if (tmp)
2835 return -EINVAL;
2836
2837 return 0;
2838}
2839
2840
2841static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2842{
2843 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2844
2845 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2846 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2847 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2848
2849 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2850 "VDDC dependency on SCLK table is missing. This table is mandatory",
2851 return -EINVAL);
2852 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2853 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2854 return -EINVAL);
2855
2856 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2857 "VDDC dependency on MCLK table is missing. This table is mandatory",
2858 return -EINVAL);
2859 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2860 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2861 return -EINVAL);
2862
2863 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2864 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2865
2866 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2867 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2868 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2869 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2870 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2871 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2872
2873 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2874 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2875 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2876 }
2877
2878 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2879 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2880
2881 return 0;
2882}
2883
2884static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2885{
2886 kfree(objp: hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2887 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2888 kfree(objp: hwmgr->backend);
2889 hwmgr->backend = NULL;
2890
2891 return 0;
2892}
2893
2894static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2895{
2896 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2897 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2898 int i;
2899
2900 if (atomctrl_get_leakage_id_from_efuse(hwmgr, virtual_voltage_id: &efuse_voltage_id) == 0) {
2901 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2902 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2903 if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, vddc: &vddc, vddci: &vddci,
2904 virtual_voltage_id,
2905 efuse_voltage_id) == 0) {
2906 if (vddc != 0 && vddc != virtual_voltage_id) {
2907 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2908 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2909 data->vddc_leakage.count++;
2910 }
2911 if (vddci != 0 && vddci != virtual_voltage_id) {
2912 data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2913 data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2914 data->vddci_leakage.count++;
2915 }
2916 }
2917 }
2918 }
2919 return 0;
2920}
2921
2922#define LEAKAGE_ID_MSB 463
2923#define LEAKAGE_ID_LSB 454
2924
2925static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr)
2926{
2927 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2928 uint32_t efuse;
2929 uint16_t offset;
2930 int ret = 0;
2931
2932 if (data->disable_edc_leakage_controller)
2933 return 0;
2934
2935 ret = atomctrl_get_edc_hilo_leakage_offset_table(hwmgr,
2936 table: &data->edc_hilo_leakage_offset_from_vbios);
2937 if (ret)
2938 return ret;
2939
2940 if (data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
2941 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
2942 atomctrl_read_efuse(hwmgr, LEAKAGE_ID_LSB, LEAKAGE_ID_MSB, efuse: &efuse);
2943 if (efuse < data->edc_hilo_leakage_offset_from_vbios.usHiLoLeakageThreshold)
2944 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset;
2945 else
2946 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset;
2947
2948 ret = atomctrl_get_edc_leakage_table(hwmgr,
2949 table: &data->edc_leakage_table,
2950 offset);
2951 if (ret)
2952 return ret;
2953 }
2954
2955 return ret;
2956}
2957
2958static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2959{
2960 struct smu7_hwmgr *data;
2961 int result = 0;
2962
2963 data = kzalloc(size: sizeof(struct smu7_hwmgr), GFP_KERNEL);
2964 if (data == NULL)
2965 return -ENOMEM;
2966
2967 hwmgr->backend = data;
2968 smu7_patch_voltage_workaround(hwmgr);
2969 smu7_init_dpm_defaults(hwmgr);
2970
2971 /* Get leakage voltage based on leakage ID. */
2972 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
2973 c: PHM_PlatformCaps_EVV)) {
2974 result = smu7_get_evv_voltages(hwmgr);
2975 if (result) {
2976 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
2977 kfree(objp: hwmgr->backend);
2978 hwmgr->backend = NULL;
2979 return -EINVAL;
2980 }
2981 } else {
2982 smu7_get_elb_voltages(hwmgr);
2983 }
2984
2985 if (hwmgr->pp_table_version == PP_TABLE_V1) {
2986 smu7_complete_dependency_tables(hwmgr);
2987 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2988 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2989 smu7_patch_dependency_tables_with_leakage(hwmgr);
2990 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2991 }
2992
2993 /* Initalize Dynamic State Adjustment Rule Settings */
2994 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2995
2996 if (0 == result) {
2997 struct amdgpu_device *adev = hwmgr->adev;
2998
2999 data->is_tlu_enabled = false;
3000
3001 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3002 SMU7_MAX_HARDWARE_POWERLEVELS;
3003 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3004 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3005
3006 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
3007 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3008 data->pcie_spc_cap = 20;
3009 else
3010 data->pcie_spc_cap = 16;
3011 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
3012
3013 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3014/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3015 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3016 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3017 smu7_thermal_parameter_init(hwmgr);
3018 } else {
3019 /* Ignore return value in here, we are cleaning up a mess. */
3020 smu7_hwmgr_backend_fini(hwmgr);
3021 }
3022
3023 result = smu7_update_edc_leakage_table(hwmgr);
3024 if (result) {
3025 smu7_hwmgr_backend_fini(hwmgr);
3026 return result;
3027 }
3028
3029 return 0;
3030}
3031
3032static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
3033{
3034 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3035 uint32_t level, tmp;
3036
3037 if (!data->pcie_dpm_key_disabled) {
3038 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3039 level = 0;
3040 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3041 while (tmp >>= 1)
3042 level++;
3043
3044 if (level)
3045 smum_send_msg_to_smc_with_parameter(hwmgr,
3046 PPSMC_MSG_PCIeDPM_ForceLevel, parameter: level,
3047 NULL);
3048 }
3049 }
3050
3051 if (!data->sclk_dpm_key_disabled) {
3052 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3053 level = 0;
3054 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3055 while (tmp >>= 1)
3056 level++;
3057
3058 if (level)
3059 smum_send_msg_to_smc_with_parameter(hwmgr,
3060 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3061 parameter: (1 << level),
3062 NULL);
3063 }
3064 }
3065
3066 if (!data->mclk_dpm_key_disabled) {
3067 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3068 level = 0;
3069 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3070 while (tmp >>= 1)
3071 level++;
3072
3073 if (level)
3074 smum_send_msg_to_smc_with_parameter(hwmgr,
3075 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3076 parameter: (1 << level),
3077 NULL);
3078 }
3079 }
3080
3081 return 0;
3082}
3083
3084static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3085{
3086 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3087
3088 if (hwmgr->pp_table_version == PP_TABLE_V1)
3089 phm_apply_dal_min_voltage_request(hwmgr);
3090/* TO DO for v0 iceland and Ci*/
3091
3092 if (!data->sclk_dpm_key_disabled) {
3093 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3094 smum_send_msg_to_smc_with_parameter(hwmgr,
3095 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3096 parameter: data->dpm_level_enable_mask.sclk_dpm_enable_mask,
3097 NULL);
3098 }
3099
3100 if (!data->mclk_dpm_key_disabled) {
3101 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3102 smum_send_msg_to_smc_with_parameter(hwmgr,
3103 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3104 parameter: data->dpm_level_enable_mask.mclk_dpm_enable_mask,
3105 NULL);
3106 }
3107
3108 return 0;
3109}
3110
3111static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3112{
3113 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3114
3115 if (!smum_is_dpm_running(hwmgr))
3116 return -EINVAL;
3117
3118 if (!data->pcie_dpm_key_disabled) {
3119 smum_send_msg_to_smc(hwmgr,
3120 PPSMC_MSG_PCIeDPM_UnForceLevel,
3121 NULL);
3122 }
3123
3124 return smu7_upload_dpm_level_enable_mask(hwmgr);
3125}
3126
3127static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3128{
3129 struct smu7_hwmgr *data =
3130 (struct smu7_hwmgr *)(hwmgr->backend);
3131 uint32_t level;
3132
3133 if (!data->sclk_dpm_key_disabled)
3134 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3135 level = phm_get_lowest_enabled_level(hwmgr,
3136 mask: data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3137 smum_send_msg_to_smc_with_parameter(hwmgr,
3138 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3139 parameter: (1 << level),
3140 NULL);
3141
3142 }
3143
3144 if (!data->mclk_dpm_key_disabled) {
3145 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3146 level = phm_get_lowest_enabled_level(hwmgr,
3147 mask: data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3148 smum_send_msg_to_smc_with_parameter(hwmgr,
3149 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3150 parameter: (1 << level),
3151 NULL);
3152 }
3153 }
3154
3155 if (!data->pcie_dpm_key_disabled) {
3156 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3157 level = phm_get_lowest_enabled_level(hwmgr,
3158 mask: data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3159 smum_send_msg_to_smc_with_parameter(hwmgr,
3160 PPSMC_MSG_PCIeDPM_ForceLevel,
3161 parameter: (level),
3162 NULL);
3163 }
3164 }
3165
3166 return 0;
3167}
3168
3169static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
3170 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
3171{
3172 uint32_t percentage;
3173 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3174 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3175 int32_t tmp_mclk;
3176 int32_t tmp_sclk;
3177 int32_t count;
3178
3179 if (golden_dpm_table->mclk_table.count < 1)
3180 return -EINVAL;
3181
3182 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
3183 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
3184
3185 if (golden_dpm_table->mclk_table.count == 1) {
3186 percentage = 70;
3187 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
3188 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3189 } else {
3190 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
3191 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
3192 }
3193
3194 tmp_sclk = tmp_mclk * percentage / 100;
3195
3196 if (hwmgr->pp_table_version == PP_TABLE_V0) {
3197 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
3198 count >= 0; count--) {
3199 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
3200 *sclk_mask = count;
3201 break;
3202 }
3203 }
3204 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
3205 *sclk_mask = 0;
3206
3207 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3208 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
3209 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3210 struct phm_ppt_v1_information *table_info =
3211 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3212
3213 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
3214 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
3215 *sclk_mask = count;
3216 break;
3217 }
3218 }
3219 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
3220 *sclk_mask = 0;
3221
3222 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3223 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
3224 }
3225
3226 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
3227 *mclk_mask = 0;
3228 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3229 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3230
3231 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
3232
3233 return 0;
3234}
3235
3236static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
3237 enum amd_dpm_forced_level level)
3238{
3239 int ret = 0;
3240 uint32_t sclk_mask = 0;
3241 uint32_t mclk_mask = 0;
3242 uint32_t pcie_mask = 0;
3243
3244 switch (level) {
3245 case AMD_DPM_FORCED_LEVEL_HIGH:
3246 ret = smu7_force_dpm_highest(hwmgr);
3247 break;
3248 case AMD_DPM_FORCED_LEVEL_LOW:
3249 ret = smu7_force_dpm_lowest(hwmgr);
3250 break;
3251 case AMD_DPM_FORCED_LEVEL_AUTO:
3252 ret = smu7_unforce_dpm_levels(hwmgr);
3253 break;
3254 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
3255 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
3256 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
3257 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
3258 ret = smu7_get_profiling_clk(hwmgr, level, sclk_mask: &sclk_mask, mclk_mask: &mclk_mask, pcie_mask: &pcie_mask);
3259 if (ret)
3260 return ret;
3261 smu7_force_clock_level(hwmgr, type: PP_SCLK, mask: 1<<sclk_mask);
3262 smu7_force_clock_level(hwmgr, type: PP_MCLK, mask: 1<<mclk_mask);
3263 smu7_force_clock_level(hwmgr, type: PP_PCIE, mask: 1<<pcie_mask);
3264 break;
3265 case AMD_DPM_FORCED_LEVEL_MANUAL:
3266 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
3267 default:
3268 break;
3269 }
3270
3271 if (!ret) {
3272 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3273 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, speed: 255);
3274 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3275 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
3276 }
3277 return ret;
3278}
3279
3280static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
3281{
3282 return sizeof(struct smu7_power_state);
3283}
3284
3285static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
3286 uint32_t vblank_time_us)
3287{
3288 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3289 uint32_t switch_limit_us;
3290
3291 switch (hwmgr->chip_id) {
3292 case CHIP_POLARIS10:
3293 case CHIP_POLARIS11:
3294 case CHIP_POLARIS12:
3295 if (hwmgr->is_kicker || (hwmgr->chip_id == CHIP_POLARIS12))
3296 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
3297 else
3298 switch_limit_us = data->is_memory_gddr5 ? 200 : 150;
3299 break;
3300 case CHIP_VEGAM:
3301 switch_limit_us = 30;
3302 break;
3303 default:
3304 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
3305 break;
3306 }
3307
3308 if (vblank_time_us < switch_limit_us)
3309 return true;
3310 else
3311 return false;
3312}
3313
3314static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3315 struct pp_power_state *request_ps,
3316 const struct pp_power_state *current_ps)
3317{
3318 struct amdgpu_device *adev = hwmgr->adev;
3319 struct smu7_power_state *smu7_ps =
3320 cast_phw_smu7_power_state(hw_ps: &request_ps->hardware);
3321 uint32_t sclk;
3322 uint32_t mclk;
3323 struct PP_Clocks minimum_clocks = {0};
3324 bool disable_mclk_switching;
3325 bool disable_mclk_switching_for_frame_lock;
3326 bool disable_mclk_switching_for_display;
3327 const struct phm_clock_and_voltage_limits *max_limits;
3328 uint32_t i;
3329 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3330 struct phm_ppt_v1_information *table_info =
3331 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3332 int32_t count;
3333 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3334 uint32_t latency;
3335 bool latency_allowed = false;
3336
3337 data->battery_state = (PP_StateUILabel_Battery ==
3338 request_ps->classification.ui_label);
3339 data->mclk_ignore_signal = false;
3340
3341 max_limits = adev->pm.ac_power ?
3342 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3343 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3344
3345 /* Cap clock DPM tables at DC MAX if it is in DC. */
3346 if (!adev->pm.ac_power) {
3347 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3348 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
3349 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
3350 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
3351 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
3352 }
3353 }
3354
3355 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3356 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3357
3358 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
3359 c: PHM_PlatformCaps_StablePState)) {
3360 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3361 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3362
3363 for (count = table_info->vdd_dep_on_sclk->count - 1;
3364 count >= 0; count--) {
3365 if (stable_pstate_sclk >=
3366 table_info->vdd_dep_on_sclk->entries[count].clk) {
3367 stable_pstate_sclk =
3368 table_info->vdd_dep_on_sclk->entries[count].clk;
3369 break;
3370 }
3371 }
3372
3373 if (count < 0)
3374 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3375
3376 stable_pstate_mclk = max_limits->mclk;
3377
3378 minimum_clocks.engineClock = stable_pstate_sclk;
3379 minimum_clocks.memoryClock = stable_pstate_mclk;
3380 }
3381
3382 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3383 caps: hwmgr->platform_descriptor.platformCaps,
3384 c: PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3385
3386 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) &&
3387 !hwmgr->display_config->multi_monitor_in_sync) ||
3388 (hwmgr->display_config->num_display &&
3389 smu7_vblank_too_short(hwmgr, vblank_time_us: hwmgr->display_config->min_vblank_time));
3390
3391 disable_mclk_switching = disable_mclk_switching_for_frame_lock ||
3392 disable_mclk_switching_for_display;
3393
3394 if (hwmgr->display_config->num_display == 0) {
3395 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
3396 data->mclk_ignore_signal = true;
3397 else
3398 disable_mclk_switching = false;
3399 }
3400
3401 sclk = smu7_ps->performance_levels[0].engine_clock;
3402 mclk = smu7_ps->performance_levels[0].memory_clock;
3403
3404 if (disable_mclk_switching &&
3405 (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
3406 hwmgr->chip_id <= CHIP_VEGAM)))
3407 mclk = smu7_ps->performance_levels
3408 [smu7_ps->performance_level_count - 1].memory_clock;
3409
3410 if (sclk < minimum_clocks.engineClock)
3411 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3412 max_limits->sclk : minimum_clocks.engineClock;
3413
3414 if (mclk < minimum_clocks.memoryClock)
3415 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3416 max_limits->mclk : minimum_clocks.memoryClock;
3417
3418 smu7_ps->performance_levels[0].engine_clock = sclk;
3419 smu7_ps->performance_levels[0].memory_clock = mclk;
3420
3421 smu7_ps->performance_levels[1].engine_clock =
3422 (smu7_ps->performance_levels[1].engine_clock >=
3423 smu7_ps->performance_levels[0].engine_clock) ?
3424 smu7_ps->performance_levels[1].engine_clock :
3425 smu7_ps->performance_levels[0].engine_clock;
3426
3427 if (disable_mclk_switching) {
3428 if (mclk < smu7_ps->performance_levels[1].memory_clock)
3429 mclk = smu7_ps->performance_levels[1].memory_clock;
3430
3431 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) {
3432 if (disable_mclk_switching_for_display) {
3433 /* Find the lowest MCLK frequency that is within
3434 * the tolerable latency defined in DAL
3435 */
3436 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3437 for (i = 0; i < data->mclk_latency_table.count; i++) {
3438 if (data->mclk_latency_table.entries[i].latency <= latency) {
3439 latency_allowed = true;
3440
3441 if ((data->mclk_latency_table.entries[i].frequency >=
3442 smu7_ps->performance_levels[0].memory_clock) &&
3443 (data->mclk_latency_table.entries[i].frequency <=
3444 smu7_ps->performance_levels[1].memory_clock)) {
3445 mclk = data->mclk_latency_table.entries[i].frequency;
3446 break;
3447 }
3448 }
3449 }
3450 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) {
3451 data->mclk_ignore_signal = true;
3452 } else {
3453 data->mclk_ignore_signal = false;
3454 }
3455 }
3456
3457 if (disable_mclk_switching_for_frame_lock)
3458 mclk = smu7_ps->performance_levels[1].memory_clock;
3459 }
3460
3461 smu7_ps->performance_levels[0].memory_clock = mclk;
3462
3463 if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
3464 hwmgr->chip_id <= CHIP_VEGAM))
3465 smu7_ps->performance_levels[1].memory_clock = mclk;
3466 } else {
3467 if (smu7_ps->performance_levels[1].memory_clock <
3468 smu7_ps->performance_levels[0].memory_clock)
3469 smu7_ps->performance_levels[1].memory_clock =
3470 smu7_ps->performance_levels[0].memory_clock;
3471 }
3472
3473 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
3474 c: PHM_PlatformCaps_StablePState)) {
3475 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3476 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3477 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3478 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3479 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3480 }
3481 }
3482 return 0;
3483}
3484
3485
3486static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3487{
3488 struct pp_power_state *ps;
3489 struct smu7_power_state *smu7_ps;
3490
3491 if (hwmgr == NULL)
3492 return -EINVAL;
3493
3494 ps = hwmgr->request_ps;
3495
3496 if (ps == NULL)
3497 return -EINVAL;
3498
3499 smu7_ps = cast_phw_smu7_power_state(hw_ps: &ps->hardware);
3500
3501 if (low)
3502 return smu7_ps->performance_levels[0].memory_clock;
3503 else
3504 return smu7_ps->performance_levels
3505 [smu7_ps->performance_level_count-1].memory_clock;
3506}
3507
3508static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3509{
3510 struct pp_power_state *ps;
3511 struct smu7_power_state *smu7_ps;
3512
3513 if (hwmgr == NULL)
3514 return -EINVAL;
3515
3516 ps = hwmgr->request_ps;
3517
3518 if (ps == NULL)
3519 return -EINVAL;
3520
3521 smu7_ps = cast_phw_smu7_power_state(hw_ps: &ps->hardware);
3522
3523 if (low)
3524 return smu7_ps->performance_levels[0].engine_clock;
3525 else
3526 return smu7_ps->performance_levels
3527 [smu7_ps->performance_level_count-1].engine_clock;
3528}
3529
3530static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3531 struct pp_hw_power_state *hw_ps)
3532{
3533 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3534 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
3535 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3536 uint16_t size;
3537 uint8_t frev, crev;
3538 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3539
3540 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3541 * We assume here that fw_info is unchanged if this call fails.
3542 */
3543 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(dev: hwmgr->adev, table: index,
3544 size: &size, frev: &frev, crev: &crev);
3545 if (!fw_info)
3546 /* During a test, there is no firmware info table. */
3547 return 0;
3548
3549 /* Patch the state. */
3550 data->vbios_boot_state.sclk_bootup_value =
3551 le32_to_cpu(fw_info->ulDefaultEngineClock);
3552 data->vbios_boot_state.mclk_bootup_value =
3553 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3554 data->vbios_boot_state.mvdd_bootup_value =
3555 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3556 data->vbios_boot_state.vddc_bootup_value =
3557 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3558 data->vbios_boot_state.vddci_bootup_value =
3559 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3560 data->vbios_boot_state.pcie_gen_bootup_value =
3561 smu7_get_current_pcie_speed(hwmgr);
3562
3563 data->vbios_boot_state.pcie_lane_bootup_value =
3564 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
3565
3566 /* set boot power state */
3567 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3568 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3569 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3570 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3571
3572 return 0;
3573}
3574
3575static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
3576{
3577 int result;
3578 unsigned long ret = 0;
3579
3580 if (hwmgr->pp_table_version == PP_TABLE_V0) {
3581 result = pp_tables_get_num_of_entries(hwmgr, num_of_entries: &ret);
3582 return result ? 0 : ret;
3583 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3584 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
3585 return result;
3586 }
3587 return 0;
3588}
3589
3590static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3591 void *state, struct pp_power_state *power_state,
3592 void *pp_table, uint32_t classification_flag)
3593{
3594 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3595 struct smu7_power_state *smu7_power_state =
3596 (struct smu7_power_state *)(&(power_state->hardware));
3597 struct smu7_performance_level *performance_level;
3598 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3599 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3600 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3601 PPTable_Generic_SubTable_Header *sclk_dep_table =
3602 (PPTable_Generic_SubTable_Header *)
3603 (((unsigned long)powerplay_table) +
3604 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3605
3606 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3607 (ATOM_Tonga_MCLK_Dependency_Table *)
3608 (((unsigned long)powerplay_table) +
3609 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3610
3611 /* The following fields are not initialized here: id orderedList allStatesList */
3612 power_state->classification.ui_label =
3613 (le16_to_cpu(state_entry->usClassification) &
3614 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3615 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3616 power_state->classification.flags = classification_flag;
3617 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3618
3619 power_state->classification.temporary_state = false;
3620 power_state->classification.to_be_deleted = false;
3621
3622 power_state->validation.disallowOnDC =
3623 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3624 ATOM_Tonga_DISALLOW_ON_DC));
3625
3626 power_state->pcie.lanes = 0;
3627
3628 power_state->display.disableFrameModulation = false;
3629 power_state->display.limitRefreshrate = false;
3630 power_state->display.enableVariBright =
3631 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3632 ATOM_Tonga_ENABLE_VARIBRIGHT));
3633
3634 power_state->validation.supportedPowerLevels = 0;
3635 power_state->uvd_clocks.VCLK = 0;
3636 power_state->uvd_clocks.DCLK = 0;
3637 power_state->temperatures.min = 0;
3638 power_state->temperatures.max = 0;
3639
3640 performance_level = &(smu7_power_state->performance_levels
3641 [smu7_power_state->performance_level_count++]);
3642
3643 PP_ASSERT_WITH_CODE(
3644 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3645 "Performance levels exceeds SMC limit!",
3646 return -EINVAL);
3647
3648 PP_ASSERT_WITH_CODE(
3649 (smu7_power_state->performance_level_count <
3650 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3651 "Performance levels exceeds Driver limit!",
3652 return -EINVAL);
3653
3654 /* Performance levels are arranged from low to high. */
3655 performance_level->memory_clock = mclk_dep_table->entries
3656 [state_entry->ucMemoryClockIndexLow].ulMclk;
3657 if (sclk_dep_table->ucRevId == 0)
3658 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3659 [state_entry->ucEngineClockIndexLow].ulSclk;
3660 else if (sclk_dep_table->ucRevId == 1)
3661 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3662 [state_entry->ucEngineClockIndexLow].ulSclk;
3663 performance_level->pcie_gen = get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
3664 ns_pcie_gen: state_entry->ucPCIEGenLow);
3665 performance_level->pcie_lane = get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
3666 ns_pcie_lanes: state_entry->ucPCIELaneLow);
3667
3668 performance_level = &(smu7_power_state->performance_levels
3669 [smu7_power_state->performance_level_count++]);
3670 performance_level->memory_clock = mclk_dep_table->entries
3671 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3672
3673 if (sclk_dep_table->ucRevId == 0)
3674 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3675 [state_entry->ucEngineClockIndexHigh].ulSclk;
3676 else if (sclk_dep_table->ucRevId == 1)
3677 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3678 [state_entry->ucEngineClockIndexHigh].ulSclk;
3679
3680 performance_level->pcie_gen = get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap,
3681 ns_pcie_gen: state_entry->ucPCIEGenHigh);
3682 performance_level->pcie_lane = get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap,
3683 ns_pcie_lanes: state_entry->ucPCIELaneHigh);
3684
3685 return 0;
3686}
3687
3688static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3689 unsigned long entry_index, struct pp_power_state *state)
3690{
3691 int result;
3692 struct smu7_power_state *ps;
3693 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3694 struct phm_ppt_v1_information *table_info =
3695 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3696 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3697 table_info->vdd_dep_on_mclk;
3698
3699 state->hardware.magic = PHM_VIslands_Magic;
3700
3701 ps = (struct smu7_power_state *)(&state->hardware);
3702
3703 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, power_state: state,
3704 call_back_func: smu7_get_pp_table_entry_callback_func_v1);
3705
3706 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3707 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3708 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3709 */
3710 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3711 if (dep_mclk_table->entries[0].clk !=
3712 data->vbios_boot_state.mclk_bootup_value)
3713 pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3714 "does not match VBIOS boot MCLK level");
3715 if (dep_mclk_table->entries[0].vddci !=
3716 data->vbios_boot_state.vddci_bootup_value)
3717 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3718 "does not match VBIOS boot VDDCI level");
3719 }
3720
3721 /* set DC compatible flag if this state supports DC */
3722 if (!state->validation.disallowOnDC)
3723 ps->dc_compatible = true;
3724
3725 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3726 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3727
3728 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3729 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3730
3731 if (!result) {
3732 uint32_t i;
3733
3734 switch (state->classification.ui_label) {
3735 case PP_StateUILabel_Performance:
3736 data->use_pcie_performance_levels = true;
3737 for (i = 0; i < ps->performance_level_count; i++) {
3738 if (data->pcie_gen_performance.max <
3739 ps->performance_levels[i].pcie_gen)
3740 data->pcie_gen_performance.max =
3741 ps->performance_levels[i].pcie_gen;
3742
3743 if (data->pcie_gen_performance.min >
3744 ps->performance_levels[i].pcie_gen)
3745 data->pcie_gen_performance.min =
3746 ps->performance_levels[i].pcie_gen;
3747
3748 if (data->pcie_lane_performance.max <
3749 ps->performance_levels[i].pcie_lane)
3750 data->pcie_lane_performance.max =
3751 ps->performance_levels[i].pcie_lane;
3752 if (data->pcie_lane_performance.min >
3753 ps->performance_levels[i].pcie_lane)
3754 data->pcie_lane_performance.min =
3755 ps->performance_levels[i].pcie_lane;
3756 }
3757 break;
3758 case PP_StateUILabel_Battery:
3759 data->use_pcie_power_saving_levels = true;
3760
3761 for (i = 0; i < ps->performance_level_count; i++) {
3762 if (data->pcie_gen_power_saving.max <
3763 ps->performance_levels[i].pcie_gen)
3764 data->pcie_gen_power_saving.max =
3765 ps->performance_levels[i].pcie_gen;
3766
3767 if (data->pcie_gen_power_saving.min >
3768 ps->performance_levels[i].pcie_gen)
3769 data->pcie_gen_power_saving.min =
3770 ps->performance_levels[i].pcie_gen;
3771
3772 if (data->pcie_lane_power_saving.max <
3773 ps->performance_levels[i].pcie_lane)
3774 data->pcie_lane_power_saving.max =
3775 ps->performance_levels[i].pcie_lane;
3776
3777 if (data->pcie_lane_power_saving.min >
3778 ps->performance_levels[i].pcie_lane)
3779 data->pcie_lane_power_saving.min =
3780 ps->performance_levels[i].pcie_lane;
3781 }
3782 break;
3783 default:
3784 break;
3785 }
3786 }
3787 return 0;
3788}
3789
3790static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3791 struct pp_hw_power_state *power_state,
3792 unsigned int index, const void *clock_info)
3793{
3794 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3795 struct smu7_power_state *ps = cast_phw_smu7_power_state(hw_ps: power_state);
3796 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3797 struct smu7_performance_level *performance_level;
3798 uint32_t engine_clock, memory_clock;
3799 uint16_t pcie_gen_from_bios;
3800
3801 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3802 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3803
3804 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3805 data->highest_mclk = memory_clock;
3806
3807 PP_ASSERT_WITH_CODE(
3808 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3809 "Performance levels exceeds SMC limit!",
3810 return -EINVAL);
3811
3812 PP_ASSERT_WITH_CODE(
3813 (ps->performance_level_count <
3814 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3815 "Performance levels exceeds Driver limit, Skip!",
3816 return 0);
3817
3818 performance_level = &(ps->performance_levels
3819 [ps->performance_level_count++]);
3820
3821 /* Performance levels are arranged from low to high. */
3822 performance_level->memory_clock = memory_clock;
3823 performance_level->engine_clock = engine_clock;
3824
3825 pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3826
3827 performance_level->pcie_gen = get_pcie_gen_support(pcie_link_speed_cap: data->pcie_gen_cap, ns_pcie_gen: pcie_gen_from_bios);
3828 performance_level->pcie_lane = get_pcie_lane_support(pcie_lane_width_cap: data->pcie_lane_cap, ns_pcie_lanes: visland_clk_info->usPCIELane);
3829
3830 return 0;
3831}
3832
3833static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3834 unsigned long entry_index, struct pp_power_state *state)
3835{
3836 int result;
3837 struct smu7_power_state *ps;
3838 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3839 struct phm_clock_voltage_dependency_table *dep_mclk_table =
3840 hwmgr->dyn_state.vddci_dependency_on_mclk;
3841
3842 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3843
3844 state->hardware.magic = PHM_VIslands_Magic;
3845
3846 ps = (struct smu7_power_state *)(&state->hardware);
3847
3848 result = pp_tables_get_entry(hwmgr, entry_index, ps: state,
3849 func: smu7_get_pp_table_entry_callback_func_v0);
3850
3851 /*
3852 * This is the earliest time we have all the dependency table
3853 * and the VBIOS boot state as
3854 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3855 * state if there is only one VDDCI/MCLK level, check if it's
3856 * the same as VBIOS boot state
3857 */
3858 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3859 if (dep_mclk_table->entries[0].clk !=
3860 data->vbios_boot_state.mclk_bootup_value)
3861 pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3862 "does not match VBIOS boot MCLK level");
3863 if (dep_mclk_table->entries[0].v !=
3864 data->vbios_boot_state.vddci_bootup_value)
3865 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3866 "does not match VBIOS boot VDDCI level");
3867 }
3868
3869 /* set DC compatible flag if this state supports DC */
3870 if (!state->validation.disallowOnDC)
3871 ps->dc_compatible = true;
3872
3873 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3874 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3875
3876 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3877 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3878
3879 if (!result) {
3880 uint32_t i;
3881
3882 switch (state->classification.ui_label) {
3883 case PP_StateUILabel_Performance:
3884 data->use_pcie_performance_levels = true;
3885
3886 for (i = 0; i < ps->performance_level_count; i++) {
3887 if (data->pcie_gen_performance.max <
3888 ps->performance_levels[i].pcie_gen)
3889 data->pcie_gen_performance.max =
3890 ps->performance_levels[i].pcie_gen;
3891
3892 if (data->pcie_gen_performance.min >
3893 ps->performance_levels[i].pcie_gen)
3894 data->pcie_gen_performance.min =
3895 ps->performance_levels[i].pcie_gen;
3896
3897 if (data->pcie_lane_performance.max <
3898 ps->performance_levels[i].pcie_lane)
3899 data->pcie_lane_performance.max =
3900 ps->performance_levels[i].pcie_lane;
3901
3902 if (data->pcie_lane_performance.min >
3903 ps->performance_levels[i].pcie_lane)
3904 data->pcie_lane_performance.min =
3905 ps->performance_levels[i].pcie_lane;
3906 }
3907 break;
3908 case PP_StateUILabel_Battery:
3909 data->use_pcie_power_saving_levels = true;
3910
3911 for (i = 0; i < ps->performance_level_count; i++) {
3912 if (data->pcie_gen_power_saving.max <
3913 ps->performance_levels[i].pcie_gen)
3914 data->pcie_gen_power_saving.max =
3915 ps->performance_levels[i].pcie_gen;
3916
3917 if (data->pcie_gen_power_saving.min >
3918 ps->performance_levels[i].pcie_gen)
3919 data->pcie_gen_power_saving.min =
3920 ps->performance_levels[i].pcie_gen;
3921
3922 if (data->pcie_lane_power_saving.max <
3923 ps->performance_levels[i].pcie_lane)
3924 data->pcie_lane_power_saving.max =
3925 ps->performance_levels[i].pcie_lane;
3926
3927 if (data->pcie_lane_power_saving.min >
3928 ps->performance_levels[i].pcie_lane)
3929 data->pcie_lane_power_saving.min =
3930 ps->performance_levels[i].pcie_lane;
3931 }
3932 break;
3933 default:
3934 break;
3935 }
3936 }
3937 return 0;
3938}
3939
3940static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3941 unsigned long entry_index, struct pp_power_state *state)
3942{
3943 if (hwmgr->pp_table_version == PP_TABLE_V0)
3944 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3945 else if (hwmgr->pp_table_version == PP_TABLE_V1)
3946 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3947
3948 return 0;
3949}
3950
3951static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
3952{
3953 struct amdgpu_device *adev = hwmgr->adev;
3954 int i;
3955 u32 tmp = 0;
3956
3957 if (!query)
3958 return -EINVAL;
3959
3960 /*
3961 * PPSMC_MSG_GetCurrPkgPwr is not supported on:
3962 * - Hawaii
3963 * - Bonaire
3964 * - Fiji
3965 * - Tonga
3966 */
3967 if ((adev->asic_type != CHIP_HAWAII) &&
3968 (adev->asic_type != CHIP_BONAIRE) &&
3969 (adev->asic_type != CHIP_FIJI) &&
3970 (adev->asic_type != CHIP_TONGA)) {
3971 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, parameter: 0, resp: &tmp);
3972 *query = tmp;
3973
3974 if (tmp != 0)
3975 return 0;
3976 }
3977
3978 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL);
3979 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3980 ixSMU_PM_STATUS_95, 0);
3981
3982 for (i = 0; i < 10; i++) {
3983 msleep(msecs: 500);
3984 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL);
3985 tmp = cgs_read_ind_register(hwmgr->device,
3986 CGS_IND_REG__SMC,
3987 ixSMU_PM_STATUS_95);
3988 if (tmp != 0)
3989 break;
3990 }
3991 *query = tmp;
3992
3993 return 0;
3994}
3995
3996static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3997 void *value, int *size)
3998{
3999 uint32_t sclk, mclk, activity_percent;
4000 uint32_t offset, val_vid;
4001 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4002 struct amdgpu_device *adev = hwmgr->adev;
4003
4004 /* size must be at least 4 bytes for all sensors */
4005 if (*size < 4)
4006 return -EINVAL;
4007
4008 switch (idx) {
4009 case AMDGPU_PP_SENSOR_GFX_SCLK:
4010 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, resp: &sclk);
4011 *((uint32_t *)value) = sclk;
4012 *size = 4;
4013 return 0;
4014 case AMDGPU_PP_SENSOR_GFX_MCLK:
4015 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, resp: &mclk);
4016 *((uint32_t *)value) = mclk;
4017 *size = 4;
4018 return 0;
4019 case AMDGPU_PP_SENSOR_GPU_LOAD:
4020 case AMDGPU_PP_SENSOR_MEM_LOAD:
4021 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
4022 type: SMU_SoftRegisters,
4023 member: (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ?
4024 AverageGraphicsActivity :
4025 AverageMemoryActivity);
4026
4027 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4028 activity_percent += 0x80;
4029 activity_percent >>= 8;
4030 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
4031 *size = 4;
4032 return 0;
4033 case AMDGPU_PP_SENSOR_GPU_TEMP:
4034 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
4035 *size = 4;
4036 return 0;
4037 case AMDGPU_PP_SENSOR_UVD_POWER:
4038 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
4039 *size = 4;
4040 return 0;
4041 case AMDGPU_PP_SENSOR_VCE_POWER:
4042 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
4043 *size = 4;
4044 return 0;
4045 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
4046 if ((adev->asic_type != CHIP_HAWAII) &&
4047 (adev->asic_type != CHIP_BONAIRE) &&
4048 (adev->asic_type != CHIP_FIJI) &&
4049 (adev->asic_type != CHIP_TONGA))
4050 return smu7_get_gpu_power(hwmgr, query: (uint32_t *)value);
4051 else
4052 return -EOPNOTSUPP;
4053 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
4054 if ((adev->asic_type != CHIP_HAWAII) &&
4055 (adev->asic_type != CHIP_BONAIRE) &&
4056 (adev->asic_type != CHIP_FIJI) &&
4057 (adev->asic_type != CHIP_TONGA))
4058 return -EOPNOTSUPP;
4059 else
4060 return smu7_get_gpu_power(hwmgr, query: (uint32_t *)value);
4061 case AMDGPU_PP_SENSOR_VDDGFX:
4062 if ((data->vr_config & VRCONF_VDDGFX_MASK) ==
4063 (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT))
4064 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4065 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
4066 else
4067 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4068 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
4069
4070 *((uint32_t *)value) = (uint32_t)convert_to_vddc(vid: val_vid);
4071 return 0;
4072 default:
4073 return -EOPNOTSUPP;
4074 }
4075}
4076
4077static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4078{
4079 const struct phm_set_power_state_input *states =
4080 (const struct phm_set_power_state_input *)input;
4081 const struct smu7_power_state *smu7_ps =
4082 cast_const_phw_smu7_power_state(hw_ps: states->pnew_state);
4083 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4084 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4085 uint32_t sclk = smu7_ps->performance_levels
4086 [smu7_ps->performance_level_count - 1].engine_clock;
4087 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4088 uint32_t mclk = smu7_ps->performance_levels
4089 [smu7_ps->performance_level_count - 1].memory_clock;
4090 struct PP_Clocks min_clocks = {0};
4091 uint32_t i;
4092
4093 for (i = 0; i < sclk_table->count; i++) {
4094 if (sclk == sclk_table->dpm_levels[i].value)
4095 break;
4096 }
4097
4098 if (i >= sclk_table->count) {
4099 if (sclk > sclk_table->dpm_levels[i-1].value) {
4100 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4101 sclk_table->dpm_levels[i-1].value = sclk;
4102 }
4103 } else {
4104 /* TODO: Check SCLK in DAL's minimum clocks
4105 * in case DeepSleep divider update is required.
4106 */
4107 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4108 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
4109 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4110 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4111 }
4112
4113 for (i = 0; i < mclk_table->count; i++) {
4114 if (mclk == mclk_table->dpm_levels[i].value)
4115 break;
4116 }
4117
4118 if (i >= mclk_table->count) {
4119 if (mclk > mclk_table->dpm_levels[i-1].value) {
4120 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4121 mclk_table->dpm_levels[i-1].value = mclk;
4122 }
4123 }
4124
4125 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4126 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4127
4128 return 0;
4129}
4130
4131static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4132 const struct smu7_power_state *smu7_ps)
4133{
4134 uint32_t i;
4135 uint32_t sclk, max_sclk = 0;
4136 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4137 struct smu7_dpm_table *dpm_table = &data->dpm_table;
4138
4139 for (i = 0; i < smu7_ps->performance_level_count; i++) {
4140 sclk = smu7_ps->performance_levels[i].engine_clock;
4141 if (max_sclk < sclk)
4142 max_sclk = sclk;
4143 }
4144
4145 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4146 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4147 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4148 dpm_table->pcie_speed_table.dpm_levels
4149 [dpm_table->pcie_speed_table.count - 1].value :
4150 dpm_table->pcie_speed_table.dpm_levels[i].value);
4151 }
4152
4153 return 0;
4154}
4155
4156static int smu7_request_link_speed_change_before_state_change(
4157 struct pp_hwmgr *hwmgr, const void *input)
4158{
4159 const struct phm_set_power_state_input *states =
4160 (const struct phm_set_power_state_input *)input;
4161 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4162 const struct smu7_power_state *smu7_nps =
4163 cast_const_phw_smu7_power_state(hw_ps: states->pnew_state);
4164 const struct smu7_power_state *polaris10_cps =
4165 cast_const_phw_smu7_power_state(hw_ps: states->pcurrent_state);
4166
4167 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps: smu7_nps);
4168 uint16_t current_link_speed;
4169
4170 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4171 current_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps: polaris10_cps);
4172 else
4173 current_link_speed = data->force_pcie_gen;
4174
4175 data->force_pcie_gen = PP_PCIEGenInvalid;
4176 data->pspp_notify_required = false;
4177
4178 if (target_link_speed > current_link_speed) {
4179 switch (target_link_speed) {
4180#ifdef CONFIG_ACPI
4181 case PP_PCIEGen3:
4182 if (0 == amdgpu_acpi_pcie_performance_request(adev: hwmgr->adev, PCIE_PERF_REQ_GEN3, advertise: false))
4183 break;
4184 data->force_pcie_gen = PP_PCIEGen2;
4185 if (current_link_speed == PP_PCIEGen2)
4186 break;
4187 fallthrough;
4188 case PP_PCIEGen2:
4189 if (0 == amdgpu_acpi_pcie_performance_request(adev: hwmgr->adev, PCIE_PERF_REQ_GEN2, advertise: false))
4190 break;
4191 fallthrough;
4192#endif
4193 default:
4194 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
4195 break;
4196 }
4197 } else {
4198 if (target_link_speed < current_link_speed)
4199 data->pspp_notify_required = true;
4200 }
4201
4202 return 0;
4203}
4204
4205static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4206{
4207 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4208
4209 if (0 == data->need_update_smu7_dpm_table)
4210 return 0;
4211
4212 if ((0 == data->sclk_dpm_key_disabled) &&
4213 (data->need_update_smu7_dpm_table &
4214 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
4215 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4216 "Trying to freeze SCLK DPM when DPM is disabled",
4217 );
4218 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4219 PPSMC_MSG_SCLKDPM_FreezeLevel,
4220 NULL),
4221 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4222 return -EINVAL);
4223 }
4224
4225 if ((0 == data->mclk_dpm_key_disabled) &&
4226 !data->mclk_ignore_signal &&
4227 (data->need_update_smu7_dpm_table &
4228 DPMTABLE_OD_UPDATE_MCLK)) {
4229 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4230 "Trying to freeze MCLK DPM when DPM is disabled",
4231 );
4232 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4233 PPSMC_MSG_MCLKDPM_FreezeLevel,
4234 NULL),
4235 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4236 return -EINVAL);
4237 }
4238
4239 return 0;
4240}
4241
4242static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
4243 struct pp_hwmgr *hwmgr, const void *input)
4244{
4245 int result = 0;
4246 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4247 struct smu7_dpm_table *dpm_table = &data->dpm_table;
4248 uint32_t count;
4249 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4250 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4251 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4252
4253 if (0 == data->need_update_smu7_dpm_table)
4254 return 0;
4255
4256 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4257 for (count = 0; count < dpm_table->sclk_table.count; count++) {
4258 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
4259 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
4260 }
4261 }
4262
4263 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4264 for (count = 0; count < dpm_table->mclk_table.count; count++) {
4265 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
4266 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
4267 }
4268 }
4269
4270 if (data->need_update_smu7_dpm_table &
4271 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4272 result = smum_populate_all_graphic_levels(hwmgr);
4273 PP_ASSERT_WITH_CODE((0 == result),
4274 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4275 return result);
4276 }
4277
4278 if (data->need_update_smu7_dpm_table &
4279 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4280 /*populate MCLK dpm table to SMU7 */
4281 result = smum_populate_all_memory_levels(hwmgr);
4282 PP_ASSERT_WITH_CODE((0 == result),
4283 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4284 return result);
4285 }
4286
4287 return result;
4288}
4289
4290static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4291 struct smu7_single_dpm_table *dpm_table,
4292 uint32_t low_limit, uint32_t high_limit)
4293{
4294 uint32_t i;
4295
4296 /* force the trim if mclk_switching is disabled to prevent flicker */
4297 bool force_trim = (low_limit == high_limit);
4298 for (i = 0; i < dpm_table->count; i++) {
4299 /*skip the trim if od is enabled*/
4300 if ((!hwmgr->od_enabled || force_trim)
4301 && (dpm_table->dpm_levels[i].value < low_limit
4302 || dpm_table->dpm_levels[i].value > high_limit))
4303 dpm_table->dpm_levels[i].enabled = false;
4304 else
4305 dpm_table->dpm_levels[i].enabled = true;
4306 }
4307
4308 return 0;
4309}
4310
4311static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
4312 const struct smu7_power_state *smu7_ps)
4313{
4314 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4315 uint32_t high_limit_count;
4316
4317 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
4318 "power state did not have any performance level",
4319 return -EINVAL);
4320
4321 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
4322
4323 smu7_trim_single_dpm_states(hwmgr,
4324 dpm_table: &(data->dpm_table.sclk_table),
4325 low_limit: smu7_ps->performance_levels[0].engine_clock,
4326 high_limit: smu7_ps->performance_levels[high_limit_count].engine_clock);
4327
4328 smu7_trim_single_dpm_states(hwmgr,
4329 dpm_table: &(data->dpm_table.mclk_table),
4330 low_limit: smu7_ps->performance_levels[0].memory_clock,
4331 high_limit: smu7_ps->performance_levels[high_limit_count].memory_clock);
4332
4333 return 0;
4334}
4335
4336static int smu7_generate_dpm_level_enable_mask(
4337 struct pp_hwmgr *hwmgr, const void *input)
4338{
4339 int result = 0;
4340 const struct phm_set_power_state_input *states =
4341 (const struct phm_set_power_state_input *)input;
4342 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4343 const struct smu7_power_state *smu7_ps =
4344 cast_const_phw_smu7_power_state(hw_ps: states->pnew_state);
4345
4346
4347 result = smu7_trim_dpm_states(hwmgr, smu7_ps);
4348 if (result)
4349 return result;
4350
4351 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4352 phm_get_dpm_level_enable_mask_value(table: &data->dpm_table.sclk_table);
4353 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4354 phm_get_dpm_level_enable_mask_value(table: &data->dpm_table.mclk_table);
4355 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4356 phm_get_dpm_level_enable_mask_value(table: &data->dpm_table.pcie_speed_table);
4357
4358 return 0;
4359}
4360
4361static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4362{
4363 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4364
4365 if (0 == data->need_update_smu7_dpm_table)
4366 return 0;
4367
4368 if ((0 == data->sclk_dpm_key_disabled) &&
4369 (data->need_update_smu7_dpm_table &
4370 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
4371
4372 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4373 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4374 );
4375 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4376 PPSMC_MSG_SCLKDPM_UnfreezeLevel,
4377 NULL),
4378 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4379 return -EINVAL);
4380 }
4381
4382 if ((0 == data->mclk_dpm_key_disabled) &&
4383 !data->mclk_ignore_signal &&
4384 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4385
4386 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
4387 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4388 );
4389 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
4390 PPSMC_MSG_MCLKDPM_UnfreezeLevel,
4391 NULL),
4392 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4393 return -EINVAL);
4394 }
4395
4396 data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
4397
4398 return 0;
4399}
4400
4401static int smu7_notify_link_speed_change_after_state_change(
4402 struct pp_hwmgr *hwmgr, const void *input)
4403{
4404 const struct phm_set_power_state_input *states =
4405 (const struct phm_set_power_state_input *)input;
4406 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4407 const struct smu7_power_state *smu7_ps =
4408 cast_const_phw_smu7_power_state(hw_ps: states->pnew_state);
4409 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
4410 uint8_t request;
4411
4412 if (data->pspp_notify_required) {
4413 if (target_link_speed == PP_PCIEGen3)
4414 request = PCIE_PERF_REQ_GEN3;
4415 else if (target_link_speed == PP_PCIEGen2)
4416 request = PCIE_PERF_REQ_GEN2;
4417 else
4418 request = PCIE_PERF_REQ_GEN1;
4419
4420 if (request == PCIE_PERF_REQ_GEN1 &&
4421 smu7_get_current_pcie_speed(hwmgr) > 0)
4422 return 0;
4423
4424#ifdef CONFIG_ACPI
4425 if (amdgpu_acpi_pcie_performance_request(adev: hwmgr->adev, perf_req: request, advertise: false)) {
4426 if (PP_PCIEGen2 == target_link_speed)
4427 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
4428 else
4429 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
4430 }
4431#endif
4432 }
4433
4434 return 0;
4435}
4436
4437static int smu7_notify_no_display(struct pp_hwmgr *hwmgr)
4438{
4439 return (smum_send_msg_to_smc(hwmgr, msg: (PPSMC_Msg)PPSMC_NoDisplay, NULL) == 0) ? 0 : -EINVAL;
4440}
4441
4442static int smu7_notify_has_display(struct pp_hwmgr *hwmgr)
4443{
4444 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4445
4446 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
4447 if (hwmgr->chip_id == CHIP_VEGAM)
4448 smum_send_msg_to_smc_with_parameter(hwmgr,
4449 msg: (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, parameter: data->frame_time_x2,
4450 NULL);
4451 else
4452 smum_send_msg_to_smc_with_parameter(hwmgr,
4453 msg: (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, parameter: data->frame_time_x2,
4454 NULL);
4455 data->last_sent_vbi_timeout = data->frame_time_x2;
4456 }
4457
4458 return (smum_send_msg_to_smc(hwmgr, msg: (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ? 0 : -EINVAL;
4459}
4460
4461static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
4462{
4463 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4464 int result = 0;
4465
4466 if (data->mclk_ignore_signal)
4467 result = smu7_notify_no_display(hwmgr);
4468 else
4469 result = smu7_notify_has_display(hwmgr);
4470
4471 return result;
4472}
4473
4474static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4475{
4476 int tmp_result, result = 0;
4477 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4478
4479 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4480 PP_ASSERT_WITH_CODE((0 == tmp_result),
4481 "Failed to find DPM states clocks in DPM table!",
4482 result = tmp_result);
4483
4484 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
4485 c: PHM_PlatformCaps_PCIEPerformanceRequest)) {
4486 tmp_result =
4487 smu7_request_link_speed_change_before_state_change(hwmgr, input);
4488 PP_ASSERT_WITH_CODE((0 == tmp_result),
4489 "Failed to request link speed change before state change!",
4490 result = tmp_result);
4491 }
4492
4493 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
4494 PP_ASSERT_WITH_CODE((0 == tmp_result),
4495 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4496
4497 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4498 PP_ASSERT_WITH_CODE((0 == tmp_result),
4499 "Failed to populate and upload SCLK MCLK DPM levels!",
4500 result = tmp_result);
4501
4502 /*
4503 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
4504 * That effectively disables AVFS feature.
4505 */
4506 if (hwmgr->hardcode_pp_table != NULL)
4507 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4508
4509 tmp_result = smu7_update_avfs(hwmgr);
4510 PP_ASSERT_WITH_CODE((0 == tmp_result),
4511 "Failed to update avfs voltages!",
4512 result = tmp_result);
4513
4514 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
4515 PP_ASSERT_WITH_CODE((0 == tmp_result),
4516 "Failed to generate DPM level enabled mask!",
4517 result = tmp_result);
4518
4519 tmp_result = smum_update_sclk_threshold(hwmgr);
4520 PP_ASSERT_WITH_CODE((0 == tmp_result),
4521 "Failed to update SCLK threshold!",
4522 result = tmp_result);
4523
4524 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
4525 PP_ASSERT_WITH_CODE((0 == tmp_result),
4526 "Failed to unfreeze SCLK MCLK DPM!",
4527 result = tmp_result);
4528
4529 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
4530 PP_ASSERT_WITH_CODE((0 == tmp_result),
4531 "Failed to upload DPM level enabled mask!",
4532 result = tmp_result);
4533
4534 tmp_result = smu7_notify_smc_display(hwmgr);
4535 PP_ASSERT_WITH_CODE((0 == tmp_result),
4536 "Failed to notify smc display settings!",
4537 result = tmp_result);
4538
4539 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
4540 c: PHM_PlatformCaps_PCIEPerformanceRequest)) {
4541 tmp_result =
4542 smu7_notify_link_speed_change_after_state_change(hwmgr, input);
4543 PP_ASSERT_WITH_CODE((0 == tmp_result),
4544 "Failed to notify link speed change after state change!",
4545 result = tmp_result);
4546 }
4547 data->apply_optimized_settings = false;
4548 return result;
4549}
4550
4551static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4552{
4553 hwmgr->thermal_controller.
4554 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4555
4556 return smum_send_msg_to_smc_with_parameter(hwmgr,
4557 PPSMC_MSG_SetFanPwmMax, parameter: us_max_fan_pwm,
4558 NULL);
4559}
4560
4561static int
4562smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4563{
4564 return 0;
4565}
4566
4567/**
4568 * smu7_program_display_gap - Programs the display gap
4569 *
4570 * @hwmgr: the address of the powerplay hardware manager.
4571 * Return: always OK
4572 */
4573static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
4574{
4575 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4576 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4577 uint32_t display_gap2;
4578 uint32_t pre_vbi_time_in_us;
4579 uint32_t frame_time_in_us;
4580 uint32_t ref_clock, refresh_rate;
4581
4582 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4583 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4584
4585 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4586 refresh_rate = hwmgr->display_config->vrefresh;
4587
4588 if (0 == refresh_rate)
4589 refresh_rate = 60;
4590
4591 frame_time_in_us = 1000000 / refresh_rate;
4592
4593 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
4594
4595 data->frame_time_x2 = frame_time_in_us * 2 / 100;
4596
4597 if (data->frame_time_x2 < 280) {
4598 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
4599 data->frame_time_x2 = 280;
4600 }
4601
4602 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4603
4604 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4605
4606 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4607 data->soft_regs_start + smum_get_offsetof(hwmgr,
4608 SMU_SoftRegisters,
4609 PreVBlankGap), 0x64);
4610
4611 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4612 data->soft_regs_start + smum_get_offsetof(hwmgr,
4613 SMU_SoftRegisters,
4614 VBlankTimeout),
4615 (frame_time_in_us - pre_vbi_time_in_us));
4616
4617 return 0;
4618}
4619
4620static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4621{
4622 return smu7_program_display_gap(hwmgr);
4623}
4624
4625/**
4626 * smu7_set_max_fan_rpm_output - Set maximum target operating fan output RPM
4627 *
4628 * @hwmgr: the address of the powerplay hardware manager.
4629 * @us_max_fan_rpm: max operating fan RPM value.
4630 * Return: The response that came from the SMC.
4631 */
4632static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4633{
4634 hwmgr->thermal_controller.
4635 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4636
4637 return smum_send_msg_to_smc_with_parameter(hwmgr,
4638 PPSMC_MSG_SetFanRpmMax, parameter: us_max_fan_rpm,
4639 NULL);
4640}
4641
4642static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
4643 .process = phm_irq_process,
4644};
4645
4646static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
4647{
4648 struct amdgpu_irq_src *source =
4649 kzalloc(size: sizeof(struct amdgpu_irq_src), GFP_KERNEL);
4650
4651 if (!source)
4652 return -ENOMEM;
4653
4654 source->funcs = &smu7_irq_funcs;
4655
4656 amdgpu_irq_add_id(adev: (struct amdgpu_device *)(hwmgr->adev),
4657 AMDGPU_IRQ_CLIENTID_LEGACY,
4658 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
4659 source);
4660 amdgpu_irq_add_id(adev: (struct amdgpu_device *)(hwmgr->adev),
4661 AMDGPU_IRQ_CLIENTID_LEGACY,
4662 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
4663 source);
4664
4665 /* Register CTF(GPIO_19) interrupt */
4666 amdgpu_irq_add_id(adev: (struct amdgpu_device *)(hwmgr->adev),
4667 AMDGPU_IRQ_CLIENTID_LEGACY,
4668 VISLANDS30_IV_SRCID_GPIO_19,
4669 source);
4670
4671 return 0;
4672}
4673
4674static bool
4675smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4676{
4677 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4678 bool is_update_required = false;
4679
4680 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4681 is_update_required = true;
4682
4683 if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
4684 is_update_required = true;
4685
4686 if (hwmgr->chip_id >= CHIP_POLARIS10 &&
4687 hwmgr->chip_id <= CHIP_VEGAM &&
4688 data->last_sent_vbi_timeout != data->frame_time_x2)
4689 is_update_required = true;
4690
4691 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, c: PHM_PlatformCaps_SclkDeepSleep)) {
4692 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4693 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4694 hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4695 is_update_required = true;
4696 }
4697 return is_update_required;
4698}
4699
4700static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4701 const struct smu7_performance_level *pl2)
4702{
4703 return ((pl1->memory_clock == pl2->memory_clock) &&
4704 (pl1->engine_clock == pl2->engine_clock) &&
4705 (pl1->pcie_gen == pl2->pcie_gen) &&
4706 (pl1->pcie_lane == pl2->pcie_lane));
4707}
4708
4709static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4710 const struct pp_hw_power_state *pstate1,
4711 const struct pp_hw_power_state *pstate2, bool *equal)
4712{
4713 const struct smu7_power_state *psa;
4714 const struct smu7_power_state *psb;
4715 int i;
4716 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4717
4718 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4719 return -EINVAL;
4720
4721 psa = cast_const_phw_smu7_power_state(hw_ps: pstate1);
4722 psb = cast_const_phw_smu7_power_state(hw_ps: pstate2);
4723 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4724 if (psa->performance_level_count != psb->performance_level_count) {
4725 *equal = false;
4726 return 0;
4727 }
4728
4729 for (i = 0; i < psa->performance_level_count; i++) {
4730 if (!smu7_are_power_levels_equal(pl1: &(psa->performance_levels[i]), pl2: &(psb->performance_levels[i]))) {
4731 /* If we have found even one performance level pair that is different the states are different. */
4732 *equal = false;
4733 return 0;
4734 }
4735 }
4736
4737 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4738 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4739 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4740 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4741 /* For OD call, set value based on flag */
4742 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
4743 DPMTABLE_OD_UPDATE_MCLK |
4744 DPMTABLE_OD_UPDATE_VDDC));
4745
4746 return 0;
4747}
4748
4749static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4750{
4751 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4752
4753 uint32_t tmp;
4754
4755 /* Read MC indirect register offset 0x9F bits [3:0] to see
4756 * if VBIOS has already loaded a full version of MC ucode
4757 * or not.
4758 */
4759
4760 smu7_get_mc_microcode_version(hwmgr);
4761
4762 data->need_long_memory_training = false;
4763
4764 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4765 ixMC_IO_DEBUG_UP_13);
4766 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4767
4768 if (tmp & (1 << 23)) {
4769 data->mem_latency_high = MEM_LATENCY_HIGH;
4770 data->mem_latency_low = MEM_LATENCY_LOW;
4771 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4772 (hwmgr->chip_id == CHIP_POLARIS11) ||
4773 (hwmgr->chip_id == CHIP_POLARIS12))
4774 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL);
4775 } else {
4776 data->mem_latency_high = 330;
4777 data->mem_latency_low = 330;
4778 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4779 (hwmgr->chip_id == CHIP_POLARIS11) ||
4780 (hwmgr->chip_id == CHIP_POLARIS12))
4781 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL);
4782 }
4783
4784 return 0;
4785}
4786
4787static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4788{
4789 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4790
4791 data->clock_registers.vCG_SPLL_FUNC_CNTL =
4792 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4793 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
4794 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4795 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
4796 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4797 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
4798 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4799 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
4800 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4801 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4802 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4803 data->clock_registers.vDLL_CNTL =
4804 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4805 data->clock_registers.vMCLK_PWRMGT_CNTL =
4806 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4807 data->clock_registers.vMPLL_AD_FUNC_CNTL =
4808 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4809 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
4810 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4811 data->clock_registers.vMPLL_FUNC_CNTL =
4812 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4813 data->clock_registers.vMPLL_FUNC_CNTL_1 =
4814 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4815 data->clock_registers.vMPLL_FUNC_CNTL_2 =
4816 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4817 data->clock_registers.vMPLL_SS1 =
4818 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4819 data->clock_registers.vMPLL_SS2 =
4820 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4821 return 0;
4822
4823}
4824
4825/**
4826 * smu7_get_memory_type - Find out if memory is GDDR5.
4827 *
4828 * @hwmgr: the address of the powerplay hardware manager.
4829 * Return: always 0
4830 */
4831static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4832{
4833 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4834 struct amdgpu_device *adev = hwmgr->adev;
4835
4836 data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
4837
4838 return 0;
4839}
4840
4841/**
4842 * smu7_enable_acpi_power_management - Enables Dynamic Power Management by SMC
4843 *
4844 * @hwmgr: the address of the powerplay hardware manager.
4845 * Return: always 0
4846 */
4847static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4848{
4849 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4850 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4851
4852 return 0;
4853}
4854
4855/**
4856 * smu7_init_power_gate_state - Initialize PowerGating States for different engines
4857 *
4858 * @hwmgr: the address of the powerplay hardware manager.
4859 * Return: always 0
4860 */
4861static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4862{
4863 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4864
4865 data->uvd_power_gated = false;
4866 data->vce_power_gated = false;
4867
4868 return 0;
4869}
4870
4871static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4872{
4873 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4874
4875 data->low_sclk_interrupt_threshold = 0;
4876 return 0;
4877}
4878
4879static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4880{
4881 int tmp_result, result = 0;
4882
4883 smu7_check_mc_firmware(hwmgr);
4884
4885 tmp_result = smu7_read_clock_registers(hwmgr);
4886 PP_ASSERT_WITH_CODE((0 == tmp_result),
4887 "Failed to read clock registers!", result = tmp_result);
4888
4889 tmp_result = smu7_get_memory_type(hwmgr);
4890 PP_ASSERT_WITH_CODE((0 == tmp_result),
4891 "Failed to get memory type!", result = tmp_result);
4892
4893 tmp_result = smu7_enable_acpi_power_management(hwmgr);
4894 PP_ASSERT_WITH_CODE((0 == tmp_result),
4895 "Failed to enable ACPI power management!", result = tmp_result);
4896
4897 tmp_result = smu7_init_power_gate_state(hwmgr);
4898 PP_ASSERT_WITH_CODE((0 == tmp_result),
4899 "Failed to init power gate state!", result = tmp_result);
4900
4901 tmp_result = smu7_get_mc_microcode_version(hwmgr);
4902 PP_ASSERT_WITH_CODE((0 == tmp_result),
4903 "Failed to get MC microcode version!", result = tmp_result);
4904
4905 tmp_result = smu7_init_sclk_threshold(hwmgr);
4906 PP_ASSERT_WITH_CODE((0 == tmp_result),
4907 "Failed to init sclk threshold!", result = tmp_result);
4908
4909 return result;
4910}
4911
4912static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4913 enum pp_clock_type type, uint32_t mask)
4914{
4915 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4916
4917 if (mask == 0)
4918 return -EINVAL;
4919
4920 switch (type) {
4921 case PP_SCLK:
4922 if (!data->sclk_dpm_key_disabled)
4923 smum_send_msg_to_smc_with_parameter(hwmgr,
4924 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4925 parameter: data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask,
4926 NULL);
4927 break;
4928 case PP_MCLK:
4929 if (!data->mclk_dpm_key_disabled)
4930 smum_send_msg_to_smc_with_parameter(hwmgr,
4931 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4932 parameter: data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask,
4933 NULL);
4934 break;
4935 case PP_PCIE:
4936 {
4937 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4938
4939 if (!data->pcie_dpm_key_disabled) {
4940 if (fls(x: tmp) != ffs(tmp))
4941 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel,
4942 NULL);
4943 else
4944 smum_send_msg_to_smc_with_parameter(hwmgr,
4945 PPSMC_MSG_PCIeDPM_ForceLevel,
4946 parameter: fls(x: tmp) - 1,
4947 NULL);
4948 }
4949 break;
4950 }
4951 default:
4952 break;
4953 }
4954
4955 return 0;
4956}
4957
4958static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4959 enum pp_clock_type type, char *buf)
4960{
4961 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4962 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4963 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4964 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4965 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4966 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4967 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4968 int size = 0;
4969 uint32_t i, now, clock, pcie_speed;
4970
4971 switch (type) {
4972 case PP_SCLK:
4973 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, resp: &clock);
4974
4975 for (i = 0; i < sclk_table->count; i++) {
4976 if (clock > sclk_table->dpm_levels[i].value)
4977 continue;
4978 break;
4979 }
4980 now = i;
4981
4982 for (i = 0; i < sclk_table->count; i++)
4983 size += sprintf(buf: buf + size, fmt: "%d: %uMhz %s\n",
4984 i, sclk_table->dpm_levels[i].value / 100,
4985 (i == now) ? "*" : "");
4986 break;
4987 case PP_MCLK:
4988 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, resp: &clock);
4989
4990 for (i = 0; i < mclk_table->count; i++) {
4991 if (clock > mclk_table->dpm_levels[i].value)
4992 continue;
4993 break;
4994 }
4995 now = i;
4996
4997 for (i = 0; i < mclk_table->count; i++)
4998 size += sprintf(buf: buf + size, fmt: "%d: %uMhz %s\n",
4999 i, mclk_table->dpm_levels[i].value / 100,
5000 (i == now) ? "*" : "");
5001 break;
5002 case PP_PCIE:
5003 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
5004 for (i = 0; i < pcie_table->count; i++) {
5005 if (pcie_speed != pcie_table->dpm_levels[i].value)
5006 continue;
5007 break;
5008 }
5009 now = i;
5010
5011 for (i = 0; i < pcie_table->count; i++)
5012 size += sprintf(buf: buf + size, fmt: "%d: %s %s\n", i,
5013 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
5014 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
5015 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
5016 (i == now) ? "*" : "");
5017 break;
5018 case OD_SCLK:
5019 if (hwmgr->od_enabled) {
5020 size += sprintf(buf: buf + size, fmt: "%s:\n", "OD_SCLK");
5021 for (i = 0; i < odn_sclk_table->num_of_pl; i++)
5022 size += sprintf(buf: buf + size, fmt: "%d: %10uMHz %10umV\n",
5023 i, odn_sclk_table->entries[i].clock/100,
5024 odn_sclk_table->entries[i].vddc);
5025 }
5026 break;
5027 case OD_MCLK:
5028 if (hwmgr->od_enabled) {
5029 size += sprintf(buf: buf + size, fmt: "%s:\n", "OD_MCLK");
5030 for (i = 0; i < odn_mclk_table->num_of_pl; i++)
5031 size += sprintf(buf: buf + size, fmt: "%d: %10uMHz %10umV\n",
5032 i, odn_mclk_table->entries[i].clock/100,
5033 odn_mclk_table->entries[i].vddc);
5034 }
5035 break;
5036 case OD_RANGE:
5037 if (hwmgr->od_enabled) {
5038 size += sprintf(buf: buf + size, fmt: "%s:\n", "OD_RANGE");
5039 size += sprintf(buf: buf + size, fmt: "SCLK: %7uMHz %10uMHz\n",
5040 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
5041 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5042 size += sprintf(buf: buf + size, fmt: "MCLK: %7uMHz %10uMHz\n",
5043 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
5044 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5045 size += sprintf(buf: buf + size, fmt: "VDDC: %7umV %11umV\n",
5046 data->odn_dpm_table.min_vddc,
5047 data->odn_dpm_table.max_vddc);
5048 }
5049 break;
5050 default:
5051 break;
5052 }
5053 return size;
5054}
5055
5056static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5057{
5058 switch (mode) {
5059 case AMD_FAN_CTRL_NONE:
5060 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, speed: 255);
5061 break;
5062 case AMD_FAN_CTRL_MANUAL:
5063 if (phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps,
5064 c: PHM_PlatformCaps_MicrocodeFanControl))
5065 smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
5066 break;
5067 case AMD_FAN_CTRL_AUTO:
5068 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
5069 smu7_fan_ctrl_start_smc_fan_control(hwmgr);
5070 break;
5071 default:
5072 break;
5073 }
5074}
5075
5076static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5077{
5078 return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
5079}
5080
5081static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
5082{
5083 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5084 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5085 struct smu7_single_dpm_table *golden_sclk_table =
5086 &(data->golden_dpm_table.sclk_table);
5087 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
5088 int golden_value = golden_sclk_table->dpm_levels
5089 [golden_sclk_table->count - 1].value;
5090
5091 value -= golden_value;
5092 value = DIV_ROUND_UP(value * 100, golden_value);
5093
5094 return value;
5095}
5096
5097static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5098{
5099 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5100 struct smu7_single_dpm_table *golden_sclk_table =
5101 &(data->golden_dpm_table.sclk_table);
5102 struct pp_power_state *ps;
5103 struct smu7_power_state *smu7_ps;
5104
5105 if (value > 20)
5106 value = 20;
5107
5108 ps = hwmgr->request_ps;
5109
5110 if (ps == NULL)
5111 return -EINVAL;
5112
5113 smu7_ps = cast_phw_smu7_power_state(hw_ps: &ps->hardware);
5114
5115 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
5116 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5117 value / 100 +
5118 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5119
5120 return 0;
5121}
5122
5123static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
5124{
5125 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5126 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5127 struct smu7_single_dpm_table *golden_mclk_table =
5128 &(data->golden_dpm_table.mclk_table);
5129 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
5130 int golden_value = golden_mclk_table->dpm_levels
5131 [golden_mclk_table->count - 1].value;
5132
5133 value -= golden_value;
5134 value = DIV_ROUND_UP(value * 100, golden_value);
5135
5136 return value;
5137}
5138
5139static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5140{
5141 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5142 struct smu7_single_dpm_table *golden_mclk_table =
5143 &(data->golden_dpm_table.mclk_table);
5144 struct pp_power_state *ps;
5145 struct smu7_power_state *smu7_ps;
5146
5147 if (value > 20)
5148 value = 20;
5149
5150 ps = hwmgr->request_ps;
5151
5152 if (ps == NULL)
5153 return -EINVAL;
5154
5155 smu7_ps = cast_phw_smu7_power_state(hw_ps: &ps->hardware);
5156
5157 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
5158 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5159 value / 100 +
5160 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5161
5162 return 0;
5163}
5164
5165
5166static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
5167{
5168 struct phm_ppt_v1_information *table_info =
5169 (struct phm_ppt_v1_information *)hwmgr->pptable;
5170 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
5171 struct phm_clock_voltage_dependency_table *sclk_table;
5172 int i;
5173
5174 if (hwmgr->pp_table_version == PP_TABLE_V1) {
5175 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
5176 return -EINVAL;
5177 dep_sclk_table = table_info->vdd_dep_on_sclk;
5178 for (i = 0; i < dep_sclk_table->count; i++)
5179 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
5180 clocks->count = dep_sclk_table->count;
5181 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
5182 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
5183 for (i = 0; i < sclk_table->count; i++)
5184 clocks->clock[i] = sclk_table->entries[i].clk * 10;
5185 clocks->count = sclk_table->count;
5186 }
5187
5188 return 0;
5189}
5190
5191static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
5192{
5193 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5194
5195 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
5196 return data->mem_latency_high;
5197 else if (clk >= MEM_FREQ_HIGH_LATENCY)
5198 return data->mem_latency_low;
5199 else
5200 return MEM_LATENCY_ERR;
5201}
5202
5203static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
5204{
5205 struct phm_ppt_v1_information *table_info =
5206 (struct phm_ppt_v1_information *)hwmgr->pptable;
5207 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
5208 int i;
5209 struct phm_clock_voltage_dependency_table *mclk_table;
5210
5211 if (hwmgr->pp_table_version == PP_TABLE_V1) {
5212 if (table_info == NULL)
5213 return -EINVAL;
5214 dep_mclk_table = table_info->vdd_dep_on_mclk;
5215 for (i = 0; i < dep_mclk_table->count; i++) {
5216 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
5217 clocks->latency[i] = smu7_get_mem_latency(hwmgr,
5218 clk: dep_mclk_table->entries[i].clk);
5219 }
5220 clocks->count = dep_mclk_table->count;
5221 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
5222 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
5223 for (i = 0; i < mclk_table->count; i++)
5224 clocks->clock[i] = mclk_table->entries[i].clk * 10;
5225 clocks->count = mclk_table->count;
5226 }
5227 return 0;
5228}
5229
5230static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
5231 struct amd_pp_clocks *clocks)
5232{
5233 switch (type) {
5234 case amd_pp_sys_clock:
5235 smu7_get_sclks(hwmgr, clocks);
5236 break;
5237 case amd_pp_mem_clock:
5238 smu7_get_mclks(hwmgr, clocks);
5239 break;
5240 default:
5241 return -EINVAL;
5242 }
5243
5244 return 0;
5245}
5246
5247static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr,
5248 struct pp_clock_levels_with_latency *clocks)
5249{
5250 struct phm_ppt_v1_information *table_info =
5251 (struct phm_ppt_v1_information *)hwmgr->pptable;
5252 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
5253 table_info->vdd_dep_on_sclk;
5254 int i;
5255
5256 clocks->num_levels = 0;
5257 for (i = 0; i < dep_sclk_table->count; i++) {
5258 if (dep_sclk_table->entries[i].clk) {
5259 clocks->data[clocks->num_levels].clocks_in_khz =
5260 dep_sclk_table->entries[i].clk * 10;
5261 clocks->num_levels++;
5262 }
5263 }
5264
5265 return 0;
5266}
5267
5268static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr,
5269 struct pp_clock_levels_with_latency *clocks)
5270{
5271 struct phm_ppt_v1_information *table_info =
5272 (struct phm_ppt_v1_information *)hwmgr->pptable;
5273 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5274 table_info->vdd_dep_on_mclk;
5275 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5276 int i;
5277
5278 clocks->num_levels = 0;
5279 data->mclk_latency_table.count = 0;
5280 for (i = 0; i < dep_mclk_table->count; i++) {
5281 if (dep_mclk_table->entries[i].clk) {
5282 clocks->data[clocks->num_levels].clocks_in_khz =
5283 dep_mclk_table->entries[i].clk * 10;
5284 data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency =
5285 dep_mclk_table->entries[i].clk;
5286 clocks->data[clocks->num_levels].latency_in_us =
5287 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency =
5288 smu7_get_mem_latency(hwmgr, clk: dep_mclk_table->entries[i].clk);
5289 clocks->num_levels++;
5290 data->mclk_latency_table.count++;
5291 }
5292 }
5293
5294 return 0;
5295}
5296
5297static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
5298 enum amd_pp_clock_type type,
5299 struct pp_clock_levels_with_latency *clocks)
5300{
5301 if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
5302 hwmgr->chip_id <= CHIP_VEGAM))
5303 return -EINVAL;
5304
5305 switch (type) {
5306 case amd_pp_sys_clock:
5307 smu7_get_sclks_with_latency(hwmgr, clocks);
5308 break;
5309 case amd_pp_mem_clock:
5310 smu7_get_mclks_with_latency(hwmgr, clocks);
5311 break;
5312 default:
5313 return -EINVAL;
5314 }
5315
5316 return 0;
5317}
5318
5319static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
5320 void *clock_range)
5321{
5322 struct phm_ppt_v1_information *table_info =
5323 (struct phm_ppt_v1_information *)hwmgr->pptable;
5324 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5325 table_info->vdd_dep_on_mclk;
5326 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
5327 table_info->vdd_dep_on_sclk;
5328 struct polaris10_smumgr *smu_data =
5329 (struct polaris10_smumgr *)(hwmgr->smu_backend);
5330 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
5331 struct dm_pp_wm_sets_with_clock_ranges *watermarks =
5332 (struct dm_pp_wm_sets_with_clock_ranges *)clock_range;
5333 uint32_t i, j, k;
5334 bool valid_entry;
5335
5336 if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
5337 hwmgr->chip_id <= CHIP_VEGAM))
5338 return -EINVAL;
5339
5340 for (i = 0; i < dep_mclk_table->count; i++) {
5341 for (j = 0; j < dep_sclk_table->count; j++) {
5342 valid_entry = false;
5343 for (k = 0; k < watermarks->num_wm_sets; k++) {
5344 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 &&
5345 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 &&
5346 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 &&
5347 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) {
5348 valid_entry = true;
5349 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id;
5350 break;
5351 }
5352 }
5353 PP_ASSERT_WITH_CODE(valid_entry,
5354 "Clock is not in range of specified clock range for watermark from DAL! Using highest water mark set.",
5355 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id);
5356 }
5357 }
5358
5359 return smu7_copy_bytes_to_smc(hwmgr,
5360 smc_start_address: smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, DisplayWatermark),
5361 src: (uint8_t *)table->DisplayWatermark,
5362 byte_count: sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS,
5363 SMC_RAM_END);
5364}
5365
5366static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
5367 uint32_t virtual_addr_low,
5368 uint32_t virtual_addr_hi,
5369 uint32_t mc_addr_low,
5370 uint32_t mc_addr_hi,
5371 uint32_t size)
5372{
5373 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5374
5375 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5376 data->soft_regs_start +
5377 smum_get_offsetof(hwmgr,
5378 SMU_SoftRegisters, DRAM_LOG_ADDR_H),
5379 mc_addr_hi);
5380
5381 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5382 data->soft_regs_start +
5383 smum_get_offsetof(hwmgr,
5384 SMU_SoftRegisters, DRAM_LOG_ADDR_L),
5385 mc_addr_low);
5386
5387 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5388 data->soft_regs_start +
5389 smum_get_offsetof(hwmgr,
5390 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
5391 virtual_addr_hi);
5392
5393 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5394 data->soft_regs_start +
5395 smum_get_offsetof(hwmgr,
5396 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
5397 virtual_addr_low);
5398
5399 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5400 data->soft_regs_start +
5401 smum_get_offsetof(hwmgr,
5402 SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
5403 size);
5404 return 0;
5405}
5406
5407static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
5408 struct amd_pp_simple_clock_info *clocks)
5409{
5410 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5411 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5412 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5413
5414 if (clocks == NULL)
5415 return -EINVAL;
5416
5417 clocks->memory_max_clock = mclk_table->count > 1 ?
5418 mclk_table->dpm_levels[mclk_table->count-1].value :
5419 mclk_table->dpm_levels[0].value;
5420 clocks->engine_max_clock = sclk_table->count > 1 ?
5421 sclk_table->dpm_levels[sclk_table->count-1].value :
5422 sclk_table->dpm_levels[0].value;
5423 return 0;
5424}
5425
5426static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5427 struct PP_TemperatureRange *thermal_data)
5428{
5429 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5430 struct phm_ppt_v1_information *table_info =
5431 (struct phm_ppt_v1_information *)hwmgr->pptable;
5432
5433 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
5434
5435 if (hwmgr->pp_table_version == PP_TABLE_V1)
5436 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
5437 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5438 else if (hwmgr->pp_table_version == PP_TABLE_V0)
5439 thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
5440 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5441
5442 thermal_data->sw_ctf_threshold = thermal_data->max;
5443
5444 return 0;
5445}
5446
5447static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5448 enum PP_OD_DPM_TABLE_COMMAND type,
5449 uint32_t clk,
5450 uint32_t voltage)
5451{
5452 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5453
5454 if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) {
5455 pr_info("OD voltage is out of range [%d - %d] mV\n",
5456 data->odn_dpm_table.min_vddc,
5457 data->odn_dpm_table.max_vddc);
5458 return false;
5459 }
5460
5461 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5462 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||
5463 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5464 pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5465 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
5466 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5467 return false;
5468 }
5469 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5470 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||
5471 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5472 pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5473 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
5474 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5475 return false;
5476 }
5477 } else {
5478 return false;
5479 }
5480
5481 return true;
5482}
5483
5484static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5485 enum PP_OD_DPM_TABLE_COMMAND type,
5486 long *input, uint32_t size)
5487{
5488 uint32_t i;
5489 struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
5490 struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
5491 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5492
5493 uint32_t input_clk;
5494 uint32_t input_vol;
5495 uint32_t input_level;
5496
5497 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5498 return -EINVAL);
5499
5500 if (!hwmgr->od_enabled) {
5501 pr_info("OverDrive feature not enabled\n");
5502 return -EINVAL;
5503 }
5504
5505 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5506 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
5507 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
5508 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
5509 "Failed to get ODN SCLK and Voltage tables",
5510 return -EINVAL);
5511 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5512 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
5513 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
5514
5515 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
5516 "Failed to get ODN MCLK and Voltage tables",
5517 return -EINVAL);
5518 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5519 smu7_odn_initial_default_setting(hwmgr);
5520 return 0;
5521 } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5522 smu7_check_dpm_table_updated(hwmgr);
5523 return 0;
5524 } else {
5525 return -EINVAL;
5526 }
5527
5528 for (i = 0; i < size; i += 3) {
5529 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
5530 pr_info("invalid clock voltage input \n");
5531 return 0;
5532 }
5533 input_level = input[i];
5534 input_clk = input[i+1] * 100;
5535 input_vol = input[i+2];
5536
5537 if (smu7_check_clk_voltage_valid(hwmgr, type, clk: input_clk, voltage: input_vol)) {
5538 podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
5539 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
5540 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
5541 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
5542 podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol;
5543 } else {
5544 return -EINVAL;
5545 }
5546 }
5547
5548 return 0;
5549}
5550
5551static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5552{
5553 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5554 uint32_t i, size = 0;
5555 uint32_t len;
5556
5557 static const char *title[8] = {"NUM",
5558 "MODE_NAME",
5559 "SCLK_UP_HYST",
5560 "SCLK_DOWN_HYST",
5561 "SCLK_ACTIVE_LEVEL",
5562 "MCLK_UP_HYST",
5563 "MCLK_DOWN_HYST",
5564 "MCLK_ACTIVE_LEVEL"};
5565
5566 if (!buf)
5567 return -EINVAL;
5568
5569 phm_get_sysfs_buf(buf: &buf, offset: &size);
5570
5571 size += sysfs_emit_at(buf, at: size, fmt: "%s %16s %16s %16s %16s %16s %16s %16s\n",
5572 title[0], title[1], title[2], title[3],
5573 title[4], title[5], title[6], title[7]);
5574
5575 len = ARRAY_SIZE(smu7_profiling);
5576
5577 for (i = 0; i < len; i++) {
5578 if (i == hwmgr->power_profile_mode) {
5579 size += sysfs_emit_at(buf, at: size, fmt: "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
5580 i, amdgpu_pp_profile_name[i], "*",
5581 data->current_profile_setting.sclk_up_hyst,
5582 data->current_profile_setting.sclk_down_hyst,
5583 data->current_profile_setting.sclk_activity,
5584 data->current_profile_setting.mclk_up_hyst,
5585 data->current_profile_setting.mclk_down_hyst,
5586 data->current_profile_setting.mclk_activity);
5587 continue;
5588 }
5589 if (smu7_profiling[i].bupdate_sclk)
5590 size += sysfs_emit_at(buf, at: size, fmt: "%3d %16s: %8d %16d %16d ",
5591 i, amdgpu_pp_profile_name[i], smu7_profiling[i].sclk_up_hyst,
5592 smu7_profiling[i].sclk_down_hyst,
5593 smu7_profiling[i].sclk_activity);
5594 else
5595 size += sysfs_emit_at(buf, at: size, fmt: "%3d %16s: %8s %16s %16s ",
5596 i, amdgpu_pp_profile_name[i], "-", "-", "-");
5597
5598 if (smu7_profiling[i].bupdate_mclk)
5599 size += sysfs_emit_at(buf, at: size, fmt: "%16d %16d %16d\n",
5600 smu7_profiling[i].mclk_up_hyst,
5601 smu7_profiling[i].mclk_down_hyst,
5602 smu7_profiling[i].mclk_activity);
5603 else
5604 size += sysfs_emit_at(buf, at: size, fmt: "%16s %16s %16s\n",
5605 "-", "-", "-");
5606 }
5607
5608 return size;
5609}
5610
5611static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
5612 enum PP_SMC_POWER_PROFILE requst)
5613{
5614 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5615 uint32_t tmp, level;
5616
5617 if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
5618 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
5619 level = 0;
5620 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
5621 while (tmp >>= 1)
5622 level++;
5623 if (level > 0)
5624 smu7_force_clock_level(hwmgr, type: PP_SCLK, mask: 3 << (level-1));
5625 }
5626 } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
5627 smu7_force_clock_level(hwmgr, type: PP_SCLK, mask: data->dpm_level_enable_mask.sclk_dpm_enable_mask);
5628 }
5629}
5630
5631static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5632{
5633 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5634 struct profile_mode_setting tmp;
5635 enum PP_SMC_POWER_PROFILE mode;
5636
5637 if (input == NULL)
5638 return -EINVAL;
5639
5640 mode = input[size];
5641 switch (mode) {
5642 case PP_SMC_POWER_PROFILE_CUSTOM:
5643 if (size < 8 && size != 0)
5644 return -EINVAL;
5645 /* If only CUSTOM is passed in, use the saved values. Check
5646 * that we actually have a CUSTOM profile by ensuring that
5647 * the "use sclk" or the "use mclk" bits are set
5648 */
5649 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM];
5650 if (size == 0) {
5651 if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0)
5652 return -EINVAL;
5653 } else {
5654 tmp.bupdate_sclk = input[0];
5655 tmp.sclk_up_hyst = input[1];
5656 tmp.sclk_down_hyst = input[2];
5657 tmp.sclk_activity = input[3];
5658 tmp.bupdate_mclk = input[4];
5659 tmp.mclk_up_hyst = input[5];
5660 tmp.mclk_down_hyst = input[6];
5661 tmp.mclk_activity = input[7];
5662 smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp;
5663 }
5664 if (!smum_update_dpm_settings(hwmgr, profile_setting: &tmp)) {
5665 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
5666 hwmgr->power_profile_mode = mode;
5667 }
5668 break;
5669 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
5670 case PP_SMC_POWER_PROFILE_POWERSAVING:
5671 case PP_SMC_POWER_PROFILE_VIDEO:
5672 case PP_SMC_POWER_PROFILE_VR:
5673 case PP_SMC_POWER_PROFILE_COMPUTE:
5674 if (mode == hwmgr->power_profile_mode)
5675 return 0;
5676
5677 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
5678 if (!smum_update_dpm_settings(hwmgr, profile_setting: &tmp)) {
5679 if (tmp.bupdate_sclk) {
5680 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
5681 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
5682 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
5683 data->current_profile_setting.sclk_activity = tmp.sclk_activity;
5684 }
5685 if (tmp.bupdate_mclk) {
5686 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
5687 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
5688 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
5689 data->current_profile_setting.mclk_activity = tmp.mclk_activity;
5690 }
5691 smu7_patch_compute_profile_mode(hwmgr, requst: mode);
5692 hwmgr->power_profile_mode = mode;
5693 }
5694 break;
5695 default:
5696 return -EINVAL;
5697 }
5698
5699 return 0;
5700}
5701
5702static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5703 PHM_PerformanceLevelDesignation designation, uint32_t index,
5704 PHM_PerformanceLevel *level)
5705{
5706 const struct smu7_power_state *ps;
5707 uint32_t i;
5708
5709 if (level == NULL || hwmgr == NULL || state == NULL)
5710 return -EINVAL;
5711
5712 ps = cast_const_phw_smu7_power_state(hw_ps: state);
5713
5714 i = index > ps->performance_level_count - 1 ?
5715 ps->performance_level_count - 1 : index;
5716
5717 level->coreClock = ps->performance_levels[i].engine_clock;
5718 level->memory_clock = ps->performance_levels[i].memory_clock;
5719
5720 return 0;
5721}
5722
5723static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
5724{
5725 int result;
5726
5727 result = smu7_disable_dpm_tasks(hwmgr);
5728 PP_ASSERT_WITH_CODE((0 == result),
5729 "[disable_dpm_tasks] Failed to disable DPM!",
5730 );
5731
5732 return result;
5733}
5734
5735static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
5736 .backend_init = &smu7_hwmgr_backend_init,
5737 .backend_fini = &smu7_hwmgr_backend_fini,
5738 .asic_setup = &smu7_setup_asic_task,
5739 .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
5740 .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
5741 .force_dpm_level = &smu7_force_dpm_level,
5742 .power_state_set = smu7_set_power_state_tasks,
5743 .get_power_state_size = smu7_get_power_state_size,
5744 .get_mclk = smu7_dpm_get_mclk,
5745 .get_sclk = smu7_dpm_get_sclk,
5746 .patch_boot_state = smu7_dpm_patch_boot_state,
5747 .get_pp_table_entry = smu7_get_pp_table_entry,
5748 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
5749 .powerdown_uvd = smu7_powerdown_uvd,
5750 .powergate_uvd = smu7_powergate_uvd,
5751 .powergate_vce = smu7_powergate_vce,
5752 .disable_clock_power_gating = smu7_disable_clock_power_gating,
5753 .update_clock_gatings = smu7_update_clock_gatings,
5754 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
5755 .display_config_changed = smu7_display_configuration_changed_task,
5756 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
5757 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
5758 .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
5759 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
5760 .get_fan_speed_pwm = smu7_fan_ctrl_get_fan_speed_pwm,
5761 .set_fan_speed_pwm = smu7_fan_ctrl_set_fan_speed_pwm,
5762 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
5763 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
5764 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
5765 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
5766 .register_irq_handlers = smu7_register_irq_handlers,
5767 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
5768 .check_states_equal = smu7_check_states_equal,
5769 .set_fan_control_mode = smu7_set_fan_control_mode,
5770 .get_fan_control_mode = smu7_get_fan_control_mode,
5771 .force_clock_level = smu7_force_clock_level,
5772 .print_clock_levels = smu7_print_clock_levels,
5773 .powergate_gfx = smu7_powergate_gfx,
5774 .get_sclk_od = smu7_get_sclk_od,
5775 .set_sclk_od = smu7_set_sclk_od,
5776 .get_mclk_od = smu7_get_mclk_od,
5777 .set_mclk_od = smu7_set_mclk_od,
5778 .get_clock_by_type = smu7_get_clock_by_type,
5779 .get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency,
5780 .set_watermarks_for_clocks_ranges = smu7_set_watermarks_for_clocks_ranges,
5781 .read_sensor = smu7_read_sensor,
5782 .dynamic_state_management_disable = smu7_disable_dpm_tasks,
5783 .avfs_control = smu7_avfs_control,
5784 .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
5785 .start_thermal_controller = smu7_start_thermal_controller,
5786 .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
5787 .get_max_high_clocks = smu7_get_max_high_clocks,
5788 .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
5789 .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
5790 .set_power_limit = smu7_set_power_limit,
5791 .get_power_profile_mode = smu7_get_power_profile_mode,
5792 .set_power_profile_mode = smu7_set_power_profile_mode,
5793 .get_performance_level = smu7_get_performance_level,
5794 .get_asic_baco_capability = smu7_baco_get_capability,
5795 .get_asic_baco_state = smu7_baco_get_state,
5796 .set_asic_baco_state = smu7_baco_set_state,
5797 .power_off_asic = smu7_power_off_asic,
5798};
5799
5800uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
5801 uint32_t clock_insr)
5802{
5803 uint8_t i;
5804 uint32_t temp;
5805 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
5806
5807 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
5808 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
5809 temp = clock >> i;
5810
5811 if (temp >= min || i == 0)
5812 break;
5813 }
5814 return i;
5815}
5816
5817int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
5818{
5819 hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
5820 if (hwmgr->pp_table_version == PP_TABLE_V0)
5821 hwmgr->pptable_func = &pptable_funcs;
5822 else if (hwmgr->pp_table_version == PP_TABLE_V1)
5823 hwmgr->pptable_func = &pptable_v1_0_funcs;
5824
5825 return 0;
5826}
5827

source code of linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c